1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef __MLX5_CORE_H__
34 #define __MLX5_CORE_H__
35 
36 #include <linux/types.h>
37 #include <linux/kernel.h>
38 #include <linux/sched.h>
39 #include <linux/if_link.h>
40 #include <linux/firmware.h>
41 #include <linux/mlx5/cq.h>
42 #include <linux/mlx5/fs.h>
43 #include <linux/mlx5/driver.h>
44 
45 extern uint mlx5_core_debug_mask;
46 
47 #define mlx5_core_dbg(__dev, format, ...)				\
48 	dev_dbg((__dev)->device, "%s:%d:(pid %d): " format,		\
49 		 __func__, __LINE__, current->pid,			\
50 		 ##__VA_ARGS__)
51 
52 #define mlx5_core_dbg_once(__dev, format, ...)		\
53 	dev_dbg_once((__dev)->device,		\
54 		     "%s:%d:(pid %d): " format,		\
55 		     __func__, __LINE__, current->pid,	\
56 		     ##__VA_ARGS__)
57 
58 #define mlx5_core_dbg_mask(__dev, mask, format, ...)		\
59 do {								\
60 	if ((mask) & mlx5_core_debug_mask)			\
61 		mlx5_core_dbg(__dev, format, ##__VA_ARGS__);	\
62 } while (0)
63 
64 #define mlx5_core_err(__dev, format, ...)			\
65 	dev_err((__dev)->device, "%s:%d:(pid %d): " format,	\
66 		__func__, __LINE__, current->pid,		\
67 	       ##__VA_ARGS__)
68 
69 #define mlx5_core_err_rl(__dev, format, ...)			\
70 	dev_err_ratelimited((__dev)->device,			\
71 			    "%s:%d:(pid %d): " format,		\
72 			    __func__, __LINE__, current->pid,	\
73 			    ##__VA_ARGS__)
74 
75 #define mlx5_core_warn(__dev, format, ...)			\
76 	dev_warn((__dev)->device, "%s:%d:(pid %d): " format,	\
77 		 __func__, __LINE__, current->pid,		\
78 		 ##__VA_ARGS__)
79 
80 #define mlx5_core_warn_once(__dev, format, ...)				\
81 	dev_warn_once((__dev)->device, "%s:%d:(pid %d): " format,	\
82 		      __func__, __LINE__, current->pid,			\
83 		      ##__VA_ARGS__)
84 
85 #define mlx5_core_warn_rl(__dev, format, ...)			\
86 	dev_warn_ratelimited((__dev)->device,			\
87 			     "%s:%d:(pid %d): " format,		\
88 			     __func__, __LINE__, current->pid,	\
89 			     ##__VA_ARGS__)
90 
91 #define mlx5_core_info(__dev, format, ...)		\
92 	dev_info((__dev)->device, format, ##__VA_ARGS__)
93 
94 #define mlx5_core_info_rl(__dev, format, ...)			\
95 	dev_info_ratelimited((__dev)->device,			\
96 			     "%s:%d:(pid %d): " format,		\
97 			     __func__, __LINE__, current->pid,	\
98 			     ##__VA_ARGS__)
99 
mlx5_printk(struct mlx5_core_dev * dev,int level,const char * format,...)100 static inline void mlx5_printk(struct mlx5_core_dev *dev, int level, const char *format, ...)
101 {
102 	struct device *device = dev->device;
103 	struct va_format vaf;
104 	va_list args;
105 
106 	if (WARN_ONCE(level < LOGLEVEL_EMERG || level > LOGLEVEL_DEBUG,
107 		      "Level %d is out of range, set to default level\n", level))
108 		level = LOGLEVEL_DEFAULT;
109 
110 	va_start(args, format);
111 	vaf.fmt = format;
112 	vaf.va = &args;
113 
114 	dev_printk_emit(level, device, "%s %s: %pV", dev_driver_string(device), dev_name(device),
115 			&vaf);
116 	va_end(args);
117 }
118 
119 #define mlx5_log(__dev, level, format, ...)			\
120 	mlx5_printk(__dev, level, "%s:%d:(pid %d): " format,	\
121 		    __func__, __LINE__, current->pid,		\
122 		    ##__VA_ARGS__)
123 
mlx5_core_dma_dev(struct mlx5_core_dev * dev)124 static inline struct device *mlx5_core_dma_dev(struct mlx5_core_dev *dev)
125 {
126 	return &dev->pdev->dev;
127 }
128 
129 enum {
130 	MLX5_CMD_DATA, /* print command payload only */
131 	MLX5_CMD_TIME, /* print command execution time */
132 };
133 
134 enum {
135 	MLX5_DRIVER_STATUS_ABORTED = 0xfe,
136 	MLX5_DRIVER_SYND = 0xbadd00de,
137 };
138 
139 enum mlx5_semaphore_space_address {
140 	MLX5_SEMAPHORE_SPACE_DOMAIN     = 0xA,
141 	MLX5_SEMAPHORE_SW_RESET         = 0x20,
142 };
143 
144 #define MLX5_DEFAULT_PROF       2
145 
146 int mlx5_query_hca_caps(struct mlx5_core_dev *dev);
147 int mlx5_query_board_id(struct mlx5_core_dev *dev);
148 int mlx5_cmd_init(struct mlx5_core_dev *dev);
149 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
150 void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
151 			enum mlx5_cmdif_state cmdif_state);
152 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id);
153 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev);
154 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev);
155 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev);
156 void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force);
157 void mlx5_error_sw_reset(struct mlx5_core_dev *dev);
158 u32 mlx5_health_check_fatal_sensors(struct mlx5_core_dev *dev);
159 int mlx5_health_wait_pci_up(struct mlx5_core_dev *dev);
160 void mlx5_disable_device(struct mlx5_core_dev *dev);
161 int mlx5_recover_device(struct mlx5_core_dev *dev);
162 int mlx5_sriov_init(struct mlx5_core_dev *dev);
163 void mlx5_sriov_cleanup(struct mlx5_core_dev *dev);
164 int mlx5_sriov_attach(struct mlx5_core_dev *dev);
165 void mlx5_sriov_detach(struct mlx5_core_dev *dev);
166 int mlx5_core_sriov_configure(struct pci_dev *dev, int num_vfs);
167 void mlx5_sriov_disable(struct pci_dev *pdev);
168 int mlx5_core_sriov_set_msix_vec_count(struct pci_dev *vf, int msix_vec_count);
169 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id);
170 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id);
171 int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
172 				       void *context, u32 *element_id);
173 int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
174 				       void *context, u32 element_id,
175 				       u32 modify_bitmask);
176 int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
177 					u32 element_id);
178 int mlx5_wait_for_pages(struct mlx5_core_dev *dev, int *pages);
179 
180 void mlx5_cmd_flush(struct mlx5_core_dev *dev);
181 void mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
182 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
183 
184 int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
185 			u8 access_reg_group);
186 int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap, u8 feature_group,
187 			u8 access_reg_group);
188 int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
189 			u8 feature_group, u8 access_reg_group);
190 
191 void mlx5_lag_add_netdev(struct mlx5_core_dev *dev, struct net_device *netdev);
192 void mlx5_lag_remove_netdev(struct mlx5_core_dev *dev, struct net_device *netdev);
193 void mlx5_lag_add_mdev(struct mlx5_core_dev *dev);
194 void mlx5_lag_remove_mdev(struct mlx5_core_dev *dev);
195 void mlx5_lag_disable_change(struct mlx5_core_dev *dev);
196 void mlx5_lag_enable_change(struct mlx5_core_dev *dev);
197 
198 int mlx5_events_init(struct mlx5_core_dev *dev);
199 void mlx5_events_cleanup(struct mlx5_core_dev *dev);
200 void mlx5_events_start(struct mlx5_core_dev *dev);
201 void mlx5_events_stop(struct mlx5_core_dev *dev);
202 
203 int mlx5_adev_idx_alloc(void);
204 void mlx5_adev_idx_free(int idx);
205 void mlx5_adev_cleanup(struct mlx5_core_dev *dev);
206 int mlx5_adev_init(struct mlx5_core_dev *dev);
207 
208 int mlx5_attach_device(struct mlx5_core_dev *dev);
209 void mlx5_detach_device(struct mlx5_core_dev *dev);
210 int mlx5_register_device(struct mlx5_core_dev *dev);
211 void mlx5_unregister_device(struct mlx5_core_dev *dev);
212 struct mlx5_core_dev *mlx5_get_next_phys_dev_lag(struct mlx5_core_dev *dev);
213 void mlx5_dev_list_lock(void);
214 void mlx5_dev_list_unlock(void);
215 int mlx5_dev_list_trylock(void);
216 
217 int mlx5_query_mtpps(struct mlx5_core_dev *dev, u32 *mtpps, u32 mtpps_size);
218 int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size);
219 int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode);
220 int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode);
221 
222 struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev);
223 void mlx5_dm_cleanup(struct mlx5_core_dev *dev);
224 
225 #define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) &&		\
226 			    MLX5_CAP_GEN((mdev), pps_modify) &&		\
227 			    MLX5_CAP_MCAM_FEATURE((mdev), mtpps_fs) &&	\
228 			    MLX5_CAP_MCAM_FEATURE((mdev), mtpps_enh_out_per_adj))
229 
230 int mlx5_firmware_flash(struct mlx5_core_dev *dev, const struct firmware *fw,
231 			struct netlink_ext_ack *extack);
232 int mlx5_fw_version_query(struct mlx5_core_dev *dev,
233 			  u32 *running_ver, u32 *stored_ver);
234 
235 #ifdef CONFIG_MLX5_CORE_EN
236 int mlx5e_init(void);
237 void mlx5e_cleanup(void);
238 #else
mlx5e_init(void)239 static inline int mlx5e_init(void){ return 0; }
mlx5e_cleanup(void)240 static inline void mlx5e_cleanup(void){}
241 #endif
242 
mlx5_sriov_is_enabled(struct mlx5_core_dev * dev)243 static inline bool mlx5_sriov_is_enabled(struct mlx5_core_dev *dev)
244 {
245 	return pci_num_vf(dev->pdev) ? true : false;
246 }
247 
mlx5_lag_is_lacp_owner(struct mlx5_core_dev * dev)248 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
249 {
250 	/* LACP owner conditions:
251 	 * 1) Function is physical.
252 	 * 2) LAG is supported by FW.
253 	 * 3) LAG is managed by driver (currently the only option).
254 	 */
255 	return  MLX5_CAP_GEN(dev, vport_group_manager) &&
256 		   (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
257 		    MLX5_CAP_GEN(dev, lag_master);
258 }
259 
260 int mlx5_rescan_drivers_locked(struct mlx5_core_dev *dev);
mlx5_rescan_drivers(struct mlx5_core_dev * dev)261 static inline int mlx5_rescan_drivers(struct mlx5_core_dev *dev)
262 {
263 	int ret;
264 
265 	mlx5_dev_list_lock();
266 	ret = mlx5_rescan_drivers_locked(dev);
267 	mlx5_dev_list_unlock();
268 	return ret;
269 }
270 
271 void mlx5_lag_update(struct mlx5_core_dev *dev);
272 
273 enum {
274 	MLX5_NIC_IFC_FULL		= 0,
275 	MLX5_NIC_IFC_DISABLED		= 1,
276 	MLX5_NIC_IFC_NO_DRAM_NIC	= 2,
277 	MLX5_NIC_IFC_SW_RESET		= 7
278 };
279 
280 u8 mlx5_get_nic_state(struct mlx5_core_dev *dev);
281 void mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state);
282 
mlx5_core_is_sf(const struct mlx5_core_dev * dev)283 static inline bool mlx5_core_is_sf(const struct mlx5_core_dev *dev)
284 {
285 	return dev->coredev_type == MLX5_COREDEV_SF;
286 }
287 
288 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx);
289 void mlx5_mdev_uninit(struct mlx5_core_dev *dev);
290 int mlx5_init_one(struct mlx5_core_dev *dev);
291 void mlx5_uninit_one(struct mlx5_core_dev *dev);
292 void mlx5_unload_one(struct mlx5_core_dev *dev);
293 int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery);
294 
295 int mlx5_vport_get_other_func_cap(struct mlx5_core_dev *dev, u16 function_id, void *out);
296 
297 void mlx5_events_work_enqueue(struct mlx5_core_dev *dev, struct work_struct *work);
mlx5_sriov_get_vf_total_msix(struct pci_dev * pdev)298 static inline u32 mlx5_sriov_get_vf_total_msix(struct pci_dev *pdev)
299 {
300 	struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
301 
302 	return MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix);
303 }
304 
305 bool mlx5_eth_supported(struct mlx5_core_dev *dev);
306 bool mlx5_rdma_supported(struct mlx5_core_dev *dev);
307 bool mlx5_vnet_supported(struct mlx5_core_dev *dev);
308 bool mlx5_same_hw_devs(struct mlx5_core_dev *dev, struct mlx5_core_dev *peer_dev);
309 
310 #endif /* __MLX5_CORE_H__ */
311