1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * MIPI Display Bus Interface (DBI) LCD controller support
4  *
5  * Copyright 2016 Noralf Trønnes
6  */
7 
8 #include <linux/backlight.h>
9 #include <linux/debugfs.h>
10 #include <linux/delay.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/module.h>
13 #include <linux/regulator/consumer.h>
14 #include <linux/spi/spi.h>
15 
16 #include <drm/drm_connector.h>
17 #include <drm/drm_damage_helper.h>
18 #include <drm/drm_drv.h>
19 #include <drm/drm_file.h>
20 #include <drm/drm_format_helper.h>
21 #include <drm/drm_fourcc.h>
22 #include <drm/drm_framebuffer.h>
23 #include <drm/drm_gem.h>
24 #include <drm/drm_gem_framebuffer_helper.h>
25 #include <drm/drm_mipi_dbi.h>
26 #include <drm/drm_modes.h>
27 #include <drm/drm_probe_helper.h>
28 #include <drm/drm_rect.h>
29 #include <video/mipi_display.h>
30 
31 #define MIPI_DBI_MAX_SPI_READ_SPEED 2000000 /* 2MHz */
32 
33 #define DCS_POWER_MODE_DISPLAY			BIT(2)
34 #define DCS_POWER_MODE_DISPLAY_NORMAL_MODE	BIT(3)
35 #define DCS_POWER_MODE_SLEEP_MODE		BIT(4)
36 #define DCS_POWER_MODE_PARTIAL_MODE		BIT(5)
37 #define DCS_POWER_MODE_IDLE_MODE		BIT(6)
38 #define DCS_POWER_MODE_RESERVED_MASK		(BIT(0) | BIT(1) | BIT(7))
39 
40 /**
41  * DOC: overview
42  *
43  * This library provides helpers for MIPI Display Bus Interface (DBI)
44  * compatible display controllers.
45  *
46  * Many controllers for tiny lcd displays are MIPI compliant and can use this
47  * library. If a controller uses registers 0x2A and 0x2B to set the area to
48  * update and uses register 0x2C to write to frame memory, it is most likely
49  * MIPI compliant.
50  *
51  * Only MIPI Type 1 displays are supported since a full frame memory is needed.
52  *
53  * There are 3 MIPI DBI implementation types:
54  *
55  * A. Motorola 6800 type parallel bus
56  *
57  * B. Intel 8080 type parallel bus
58  *
59  * C. SPI type with 3 options:
60  *
61  *    1. 9-bit with the Data/Command signal as the ninth bit
62  *    2. Same as above except it's sent as 16 bits
63  *    3. 8-bit with the Data/Command signal as a separate D/CX pin
64  *
65  * Currently mipi_dbi only supports Type C options 1 and 3 with
66  * mipi_dbi_spi_init().
67  */
68 
69 #define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \
70 ({ \
71 	if (!len) \
72 		DRM_DEBUG_DRIVER("cmd=%02x\n", cmd); \
73 	else if (len <= 32) \
74 		DRM_DEBUG_DRIVER("cmd=%02x, par=%*ph\n", cmd, (int)len, data);\
75 	else \
76 		DRM_DEBUG_DRIVER("cmd=%02x, len=%zu\n", cmd, len); \
77 })
78 
79 static const u8 mipi_dbi_dcs_read_commands[] = {
80 	MIPI_DCS_GET_DISPLAY_ID,
81 	MIPI_DCS_GET_RED_CHANNEL,
82 	MIPI_DCS_GET_GREEN_CHANNEL,
83 	MIPI_DCS_GET_BLUE_CHANNEL,
84 	MIPI_DCS_GET_DISPLAY_STATUS,
85 	MIPI_DCS_GET_POWER_MODE,
86 	MIPI_DCS_GET_ADDRESS_MODE,
87 	MIPI_DCS_GET_PIXEL_FORMAT,
88 	MIPI_DCS_GET_DISPLAY_MODE,
89 	MIPI_DCS_GET_SIGNAL_MODE,
90 	MIPI_DCS_GET_DIAGNOSTIC_RESULT,
91 	MIPI_DCS_READ_MEMORY_START,
92 	MIPI_DCS_READ_MEMORY_CONTINUE,
93 	MIPI_DCS_GET_SCANLINE,
94 	MIPI_DCS_GET_DISPLAY_BRIGHTNESS,
95 	MIPI_DCS_GET_CONTROL_DISPLAY,
96 	MIPI_DCS_GET_POWER_SAVE,
97 	MIPI_DCS_GET_CABC_MIN_BRIGHTNESS,
98 	MIPI_DCS_READ_DDB_START,
99 	MIPI_DCS_READ_DDB_CONTINUE,
100 	0, /* sentinel */
101 };
102 
mipi_dbi_command_is_read(struct mipi_dbi * dbi,u8 cmd)103 static bool mipi_dbi_command_is_read(struct mipi_dbi *dbi, u8 cmd)
104 {
105 	unsigned int i;
106 
107 	if (!dbi->read_commands)
108 		return false;
109 
110 	for (i = 0; i < 0xff; i++) {
111 		if (!dbi->read_commands[i])
112 			return false;
113 		if (cmd == dbi->read_commands[i])
114 			return true;
115 	}
116 
117 	return false;
118 }
119 
120 /**
121  * mipi_dbi_command_read - MIPI DCS read command
122  * @dbi: MIPI DBI structure
123  * @cmd: Command
124  * @val: Value read
125  *
126  * Send MIPI DCS read command to the controller.
127  *
128  * Returns:
129  * Zero on success, negative error code on failure.
130  */
mipi_dbi_command_read(struct mipi_dbi * dbi,u8 cmd,u8 * val)131 int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val)
132 {
133 	if (!dbi->read_commands)
134 		return -EACCES;
135 
136 	if (!mipi_dbi_command_is_read(dbi, cmd))
137 		return -EINVAL;
138 
139 	return mipi_dbi_command_buf(dbi, cmd, val, 1);
140 }
141 EXPORT_SYMBOL(mipi_dbi_command_read);
142 
143 /**
144  * mipi_dbi_command_buf - MIPI DCS command with parameter(s) in an array
145  * @dbi: MIPI DBI structure
146  * @cmd: Command
147  * @data: Parameter buffer
148  * @len: Buffer length
149  *
150  * Returns:
151  * Zero on success, negative error code on failure.
152  */
mipi_dbi_command_buf(struct mipi_dbi * dbi,u8 cmd,u8 * data,size_t len)153 int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len)
154 {
155 	u8 *cmdbuf;
156 	int ret;
157 
158 	/* SPI requires dma-safe buffers */
159 	cmdbuf = kmemdup(&cmd, 1, GFP_KERNEL);
160 	if (!cmdbuf)
161 		return -ENOMEM;
162 
163 	mutex_lock(&dbi->cmdlock);
164 	ret = dbi->command(dbi, cmdbuf, data, len);
165 	mutex_unlock(&dbi->cmdlock);
166 
167 	kfree(cmdbuf);
168 
169 	return ret;
170 }
171 EXPORT_SYMBOL(mipi_dbi_command_buf);
172 
173 /* This should only be used by mipi_dbi_command() */
mipi_dbi_command_stackbuf(struct mipi_dbi * dbi,u8 cmd,const u8 * data,size_t len)174 int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, const u8 *data,
175 			      size_t len)
176 {
177 	u8 *buf;
178 	int ret;
179 
180 	buf = kmemdup(data, len, GFP_KERNEL);
181 	if (!buf)
182 		return -ENOMEM;
183 
184 	ret = mipi_dbi_command_buf(dbi, cmd, buf, len);
185 
186 	kfree(buf);
187 
188 	return ret;
189 }
190 EXPORT_SYMBOL(mipi_dbi_command_stackbuf);
191 
192 /**
193  * mipi_dbi_buf_copy - Copy a framebuffer, transforming it if necessary
194  * @dst: The destination buffer
195  * @fb: The source framebuffer
196  * @clip: Clipping rectangle of the area to be copied
197  * @swap: When true, swap MSB/LSB of 16-bit values
198  *
199  * Returns:
200  * Zero on success, negative error code on failure.
201  */
mipi_dbi_buf_copy(void * dst,struct drm_framebuffer * fb,struct drm_rect * clip,bool swap)202 int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb,
203 		      struct drm_rect *clip, bool swap)
204 {
205 	struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0);
206 	struct iosys_map map[DRM_FORMAT_MAX_PLANES];
207 	struct iosys_map data[DRM_FORMAT_MAX_PLANES];
208 	struct iosys_map dst_map = IOSYS_MAP_INIT_VADDR(dst);
209 	int ret;
210 
211 	ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE);
212 	if (ret)
213 		return ret;
214 
215 	ret = drm_gem_fb_vmap(fb, map, data);
216 	if (ret)
217 		goto out_drm_gem_fb_end_cpu_access;
218 
219 	switch (fb->format->format) {
220 	case DRM_FORMAT_RGB565:
221 		if (swap)
222 			drm_fb_swab(&dst_map, NULL, data, fb, clip, !gem->import_attach);
223 		else
224 			drm_fb_memcpy(&dst_map, NULL, data, fb, clip);
225 		break;
226 	case DRM_FORMAT_XRGB8888:
227 		drm_fb_xrgb8888_to_rgb565(&dst_map, NULL, data, fb, clip, swap);
228 		break;
229 	default:
230 		drm_err_once(fb->dev, "Format is not supported: %p4cc\n",
231 			     &fb->format->format);
232 		ret = -EINVAL;
233 	}
234 
235 	drm_gem_fb_vunmap(fb, map);
236 out_drm_gem_fb_end_cpu_access:
237 	drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
238 
239 	return ret;
240 }
241 EXPORT_SYMBOL(mipi_dbi_buf_copy);
242 
mipi_dbi_set_window_address(struct mipi_dbi_dev * dbidev,unsigned int xs,unsigned int xe,unsigned int ys,unsigned int ye)243 static void mipi_dbi_set_window_address(struct mipi_dbi_dev *dbidev,
244 					unsigned int xs, unsigned int xe,
245 					unsigned int ys, unsigned int ye)
246 {
247 	struct mipi_dbi *dbi = &dbidev->dbi;
248 
249 	xs += dbidev->left_offset;
250 	xe += dbidev->left_offset;
251 	ys += dbidev->top_offset;
252 	ye += dbidev->top_offset;
253 
254 	mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, (xs >> 8) & 0xff,
255 			 xs & 0xff, (xe >> 8) & 0xff, xe & 0xff);
256 	mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, (ys >> 8) & 0xff,
257 			 ys & 0xff, (ye >> 8) & 0xff, ye & 0xff);
258 }
259 
mipi_dbi_fb_dirty(struct drm_framebuffer * fb,struct drm_rect * rect)260 static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect)
261 {
262 	struct iosys_map map[DRM_FORMAT_MAX_PLANES];
263 	struct iosys_map data[DRM_FORMAT_MAX_PLANES];
264 	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev);
265 	unsigned int height = rect->y2 - rect->y1;
266 	unsigned int width = rect->x2 - rect->x1;
267 	struct mipi_dbi *dbi = &dbidev->dbi;
268 	bool swap = dbi->swap_bytes;
269 	int idx, ret = 0;
270 	bool full;
271 	void *tr;
272 
273 	if (WARN_ON(!fb))
274 		return;
275 
276 	if (!drm_dev_enter(fb->dev, &idx))
277 		return;
278 
279 	ret = drm_gem_fb_vmap(fb, map, data);
280 	if (ret)
281 		goto err_drm_dev_exit;
282 
283 	full = width == fb->width && height == fb->height;
284 
285 	DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect));
286 
287 	if (!dbi->dc || !full || swap ||
288 	    fb->format->format == DRM_FORMAT_XRGB8888) {
289 		tr = dbidev->tx_buf;
290 		ret = mipi_dbi_buf_copy(dbidev->tx_buf, fb, rect, swap);
291 		if (ret)
292 			goto err_msg;
293 	} else {
294 		tr = data[0].vaddr; /* TODO: Use mapping abstraction properly */
295 	}
296 
297 	mipi_dbi_set_window_address(dbidev, rect->x1, rect->x2 - 1, rect->y1,
298 				    rect->y2 - 1);
299 
300 	ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr,
301 				   width * height * 2);
302 err_msg:
303 	if (ret)
304 		drm_err_once(fb->dev, "Failed to update display %d\n", ret);
305 
306 	drm_gem_fb_vunmap(fb, map);
307 
308 err_drm_dev_exit:
309 	drm_dev_exit(idx);
310 }
311 
312 /**
313  * mipi_dbi_pipe_mode_valid - MIPI DBI mode-valid helper
314  * @pipe: Simple display pipe
315  * @mode: The mode to test
316  *
317  * This function validates a given display mode against the MIPI DBI's hardware
318  * display. Drivers can use this as their &drm_simple_display_pipe_funcs->mode_valid
319  * callback.
320  */
mipi_dbi_pipe_mode_valid(struct drm_simple_display_pipe * pipe,const struct drm_display_mode * mode)321 enum drm_mode_status mipi_dbi_pipe_mode_valid(struct drm_simple_display_pipe *pipe,
322 					      const struct drm_display_mode *mode)
323 {
324 	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
325 
326 	return drm_crtc_helper_mode_valid_fixed(&pipe->crtc, mode, &dbidev->mode);
327 }
328 EXPORT_SYMBOL(mipi_dbi_pipe_mode_valid);
329 
330 /**
331  * mipi_dbi_pipe_update - Display pipe update helper
332  * @pipe: Simple display pipe
333  * @old_state: Old plane state
334  *
335  * This function handles framebuffer flushing and vblank events. Drivers can use
336  * this as their &drm_simple_display_pipe_funcs->update callback.
337  */
mipi_dbi_pipe_update(struct drm_simple_display_pipe * pipe,struct drm_plane_state * old_state)338 void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe,
339 			  struct drm_plane_state *old_state)
340 {
341 	struct drm_plane_state *state = pipe->plane.state;
342 	struct drm_rect rect;
343 
344 	if (!pipe->crtc.state->active)
345 		return;
346 
347 	if (drm_atomic_helper_damage_merged(old_state, state, &rect))
348 		mipi_dbi_fb_dirty(state->fb, &rect);
349 }
350 EXPORT_SYMBOL(mipi_dbi_pipe_update);
351 
352 /**
353  * mipi_dbi_enable_flush - MIPI DBI enable helper
354  * @dbidev: MIPI DBI device structure
355  * @crtc_state: CRTC state
356  * @plane_state: Plane state
357  *
358  * Flushes the whole framebuffer and enables the backlight. Drivers can use this
359  * in their &drm_simple_display_pipe_funcs->enable callback.
360  *
361  * Note: Drivers which don't use mipi_dbi_pipe_update() because they have custom
362  * framebuffer flushing, can't use this function since they both use the same
363  * flushing code.
364  */
mipi_dbi_enable_flush(struct mipi_dbi_dev * dbidev,struct drm_crtc_state * crtc_state,struct drm_plane_state * plane_state)365 void mipi_dbi_enable_flush(struct mipi_dbi_dev *dbidev,
366 			   struct drm_crtc_state *crtc_state,
367 			   struct drm_plane_state *plane_state)
368 {
369 	struct drm_framebuffer *fb = plane_state->fb;
370 	struct drm_rect rect = {
371 		.x1 = 0,
372 		.x2 = fb->width,
373 		.y1 = 0,
374 		.y2 = fb->height,
375 	};
376 	int idx;
377 
378 	if (!drm_dev_enter(&dbidev->drm, &idx))
379 		return;
380 
381 	mipi_dbi_fb_dirty(fb, &rect);
382 	backlight_enable(dbidev->backlight);
383 
384 	drm_dev_exit(idx);
385 }
386 EXPORT_SYMBOL(mipi_dbi_enable_flush);
387 
mipi_dbi_blank(struct mipi_dbi_dev * dbidev)388 static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev)
389 {
390 	struct drm_device *drm = &dbidev->drm;
391 	u16 height = drm->mode_config.min_height;
392 	u16 width = drm->mode_config.min_width;
393 	struct mipi_dbi *dbi = &dbidev->dbi;
394 	size_t len = width * height * 2;
395 	int idx;
396 
397 	if (!drm_dev_enter(drm, &idx))
398 		return;
399 
400 	memset(dbidev->tx_buf, 0, len);
401 
402 	mipi_dbi_set_window_address(dbidev, 0, width - 1, 0, height - 1);
403 	mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START,
404 			     (u8 *)dbidev->tx_buf, len);
405 
406 	drm_dev_exit(idx);
407 }
408 
409 /**
410  * mipi_dbi_pipe_disable - MIPI DBI pipe disable helper
411  * @pipe: Display pipe
412  *
413  * This function disables backlight if present, if not the display memory is
414  * blanked. The regulator is disabled if in use. Drivers can use this as their
415  * &drm_simple_display_pipe_funcs->disable callback.
416  */
mipi_dbi_pipe_disable(struct drm_simple_display_pipe * pipe)417 void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe)
418 {
419 	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
420 
421 	DRM_DEBUG_KMS("\n");
422 
423 	if (dbidev->backlight)
424 		backlight_disable(dbidev->backlight);
425 	else
426 		mipi_dbi_blank(dbidev);
427 
428 	if (dbidev->regulator)
429 		regulator_disable(dbidev->regulator);
430 }
431 EXPORT_SYMBOL(mipi_dbi_pipe_disable);
432 
mipi_dbi_connector_get_modes(struct drm_connector * connector)433 static int mipi_dbi_connector_get_modes(struct drm_connector *connector)
434 {
435 	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(connector->dev);
436 
437 	return drm_connector_helper_get_modes_fixed(connector, &dbidev->mode);
438 }
439 
440 static const struct drm_connector_helper_funcs mipi_dbi_connector_hfuncs = {
441 	.get_modes = mipi_dbi_connector_get_modes,
442 };
443 
444 static const struct drm_connector_funcs mipi_dbi_connector_funcs = {
445 	.reset = drm_atomic_helper_connector_reset,
446 	.fill_modes = drm_helper_probe_single_connector_modes,
447 	.destroy = drm_connector_cleanup,
448 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
449 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
450 };
451 
mipi_dbi_rotate_mode(struct drm_display_mode * mode,unsigned int rotation)452 static int mipi_dbi_rotate_mode(struct drm_display_mode *mode,
453 				unsigned int rotation)
454 {
455 	if (rotation == 0 || rotation == 180) {
456 		return 0;
457 	} else if (rotation == 90 || rotation == 270) {
458 		swap(mode->hdisplay, mode->vdisplay);
459 		swap(mode->hsync_start, mode->vsync_start);
460 		swap(mode->hsync_end, mode->vsync_end);
461 		swap(mode->htotal, mode->vtotal);
462 		swap(mode->width_mm, mode->height_mm);
463 		return 0;
464 	} else {
465 		return -EINVAL;
466 	}
467 }
468 
469 static const struct drm_mode_config_funcs mipi_dbi_mode_config_funcs = {
470 	.fb_create = drm_gem_fb_create_with_dirty,
471 	.atomic_check = drm_atomic_helper_check,
472 	.atomic_commit = drm_atomic_helper_commit,
473 };
474 
475 static const uint32_t mipi_dbi_formats[] = {
476 	DRM_FORMAT_RGB565,
477 	DRM_FORMAT_XRGB8888,
478 };
479 
480 /**
481  * mipi_dbi_dev_init_with_formats - MIPI DBI device initialization with custom formats
482  * @dbidev: MIPI DBI device structure to initialize
483  * @funcs: Display pipe functions
484  * @formats: Array of supported formats (DRM_FORMAT\_\*).
485  * @format_count: Number of elements in @formats
486  * @mode: Display mode
487  * @rotation: Initial rotation in degrees Counter Clock Wise
488  * @tx_buf_size: Allocate a transmit buffer of this size.
489  *
490  * This function sets up a &drm_simple_display_pipe with a &drm_connector that
491  * has one fixed &drm_display_mode which is rotated according to @rotation.
492  * This mode is used to set the mode config min/max width/height properties.
493  *
494  * Use mipi_dbi_dev_init() if you don't need custom formats.
495  *
496  * Note:
497  * Some of the helper functions expects RGB565 to be the default format and the
498  * transmit buffer sized to fit that.
499  *
500  * Returns:
501  * Zero on success, negative error code on failure.
502  */
mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev * dbidev,const struct drm_simple_display_pipe_funcs * funcs,const uint32_t * formats,unsigned int format_count,const struct drm_display_mode * mode,unsigned int rotation,size_t tx_buf_size)503 int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev,
504 				   const struct drm_simple_display_pipe_funcs *funcs,
505 				   const uint32_t *formats, unsigned int format_count,
506 				   const struct drm_display_mode *mode,
507 				   unsigned int rotation, size_t tx_buf_size)
508 {
509 	static const uint64_t modifiers[] = {
510 		DRM_FORMAT_MOD_LINEAR,
511 		DRM_FORMAT_MOD_INVALID
512 	};
513 	struct drm_device *drm = &dbidev->drm;
514 	int ret;
515 
516 	if (!dbidev->dbi.command)
517 		return -EINVAL;
518 
519 	ret = drmm_mode_config_init(drm);
520 	if (ret)
521 		return ret;
522 
523 	dbidev->tx_buf = devm_kmalloc(drm->dev, tx_buf_size, GFP_KERNEL);
524 	if (!dbidev->tx_buf)
525 		return -ENOMEM;
526 
527 	drm_mode_copy(&dbidev->mode, mode);
528 	ret = mipi_dbi_rotate_mode(&dbidev->mode, rotation);
529 	if (ret) {
530 		DRM_ERROR("Illegal rotation value %u\n", rotation);
531 		return -EINVAL;
532 	}
533 
534 	drm_connector_helper_add(&dbidev->connector, &mipi_dbi_connector_hfuncs);
535 	ret = drm_connector_init(drm, &dbidev->connector, &mipi_dbi_connector_funcs,
536 				 DRM_MODE_CONNECTOR_SPI);
537 	if (ret)
538 		return ret;
539 
540 	ret = drm_simple_display_pipe_init(drm, &dbidev->pipe, funcs, formats, format_count,
541 					   modifiers, &dbidev->connector);
542 	if (ret)
543 		return ret;
544 
545 	drm_plane_enable_fb_damage_clips(&dbidev->pipe.plane);
546 
547 	drm->mode_config.funcs = &mipi_dbi_mode_config_funcs;
548 	drm->mode_config.min_width = dbidev->mode.hdisplay;
549 	drm->mode_config.max_width = dbidev->mode.hdisplay;
550 	drm->mode_config.min_height = dbidev->mode.vdisplay;
551 	drm->mode_config.max_height = dbidev->mode.vdisplay;
552 	dbidev->rotation = rotation;
553 
554 	DRM_DEBUG_KMS("rotation = %u\n", rotation);
555 
556 	return 0;
557 }
558 EXPORT_SYMBOL(mipi_dbi_dev_init_with_formats);
559 
560 /**
561  * mipi_dbi_dev_init - MIPI DBI device initialization
562  * @dbidev: MIPI DBI device structure to initialize
563  * @funcs: Display pipe functions
564  * @mode: Display mode
565  * @rotation: Initial rotation in degrees Counter Clock Wise
566  *
567  * This function sets up a &drm_simple_display_pipe with a &drm_connector that
568  * has one fixed &drm_display_mode which is rotated according to @rotation.
569  * This mode is used to set the mode config min/max width/height properties.
570  * Additionally &mipi_dbi.tx_buf is allocated.
571  *
572  * Supported formats: Native RGB565 and emulated XRGB8888.
573  *
574  * Returns:
575  * Zero on success, negative error code on failure.
576  */
mipi_dbi_dev_init(struct mipi_dbi_dev * dbidev,const struct drm_simple_display_pipe_funcs * funcs,const struct drm_display_mode * mode,unsigned int rotation)577 int mipi_dbi_dev_init(struct mipi_dbi_dev *dbidev,
578 		      const struct drm_simple_display_pipe_funcs *funcs,
579 		      const struct drm_display_mode *mode, unsigned int rotation)
580 {
581 	size_t bufsize = mode->vdisplay * mode->hdisplay * sizeof(u16);
582 
583 	dbidev->drm.mode_config.preferred_depth = 16;
584 
585 	return mipi_dbi_dev_init_with_formats(dbidev, funcs, mipi_dbi_formats,
586 					      ARRAY_SIZE(mipi_dbi_formats), mode,
587 					      rotation, bufsize);
588 }
589 EXPORT_SYMBOL(mipi_dbi_dev_init);
590 
591 /**
592  * mipi_dbi_hw_reset - Hardware reset of controller
593  * @dbi: MIPI DBI structure
594  *
595  * Reset controller if the &mipi_dbi->reset gpio is set.
596  */
mipi_dbi_hw_reset(struct mipi_dbi * dbi)597 void mipi_dbi_hw_reset(struct mipi_dbi *dbi)
598 {
599 	if (!dbi->reset)
600 		return;
601 
602 	gpiod_set_value_cansleep(dbi->reset, 0);
603 	usleep_range(20, 1000);
604 	gpiod_set_value_cansleep(dbi->reset, 1);
605 	msleep(120);
606 }
607 EXPORT_SYMBOL(mipi_dbi_hw_reset);
608 
609 /**
610  * mipi_dbi_display_is_on - Check if display is on
611  * @dbi: MIPI DBI structure
612  *
613  * This function checks the Power Mode register (if readable) to see if
614  * display output is turned on. This can be used to see if the bootloader
615  * has already turned on the display avoiding flicker when the pipeline is
616  * enabled.
617  *
618  * Returns:
619  * true if the display can be verified to be on, false otherwise.
620  */
mipi_dbi_display_is_on(struct mipi_dbi * dbi)621 bool mipi_dbi_display_is_on(struct mipi_dbi *dbi)
622 {
623 	u8 val;
624 
625 	if (mipi_dbi_command_read(dbi, MIPI_DCS_GET_POWER_MODE, &val))
626 		return false;
627 
628 	val &= ~DCS_POWER_MODE_RESERVED_MASK;
629 
630 	/* The poweron/reset value is 08h DCS_POWER_MODE_DISPLAY_NORMAL_MODE */
631 	if (val != (DCS_POWER_MODE_DISPLAY |
632 	    DCS_POWER_MODE_DISPLAY_NORMAL_MODE | DCS_POWER_MODE_SLEEP_MODE))
633 		return false;
634 
635 	DRM_DEBUG_DRIVER("Display is ON\n");
636 
637 	return true;
638 }
639 EXPORT_SYMBOL(mipi_dbi_display_is_on);
640 
mipi_dbi_poweron_reset_conditional(struct mipi_dbi_dev * dbidev,bool cond)641 static int mipi_dbi_poweron_reset_conditional(struct mipi_dbi_dev *dbidev, bool cond)
642 {
643 	struct device *dev = dbidev->drm.dev;
644 	struct mipi_dbi *dbi = &dbidev->dbi;
645 	int ret;
646 
647 	if (dbidev->regulator) {
648 		ret = regulator_enable(dbidev->regulator);
649 		if (ret) {
650 			DRM_DEV_ERROR(dev, "Failed to enable regulator (%d)\n", ret);
651 			return ret;
652 		}
653 	}
654 
655 	if (cond && mipi_dbi_display_is_on(dbi))
656 		return 1;
657 
658 	mipi_dbi_hw_reset(dbi);
659 	ret = mipi_dbi_command(dbi, MIPI_DCS_SOFT_RESET);
660 	if (ret) {
661 		DRM_DEV_ERROR(dev, "Failed to send reset command (%d)\n", ret);
662 		if (dbidev->regulator)
663 			regulator_disable(dbidev->regulator);
664 		return ret;
665 	}
666 
667 	/*
668 	 * If we did a hw reset, we know the controller is in Sleep mode and
669 	 * per MIPI DSC spec should wait 5ms after soft reset. If we didn't,
670 	 * we assume worst case and wait 120ms.
671 	 */
672 	if (dbi->reset)
673 		usleep_range(5000, 20000);
674 	else
675 		msleep(120);
676 
677 	return 0;
678 }
679 
680 /**
681  * mipi_dbi_poweron_reset - MIPI DBI poweron and reset
682  * @dbidev: MIPI DBI device structure
683  *
684  * This function enables the regulator if used and does a hardware and software
685  * reset.
686  *
687  * Returns:
688  * Zero on success, or a negative error code.
689  */
mipi_dbi_poweron_reset(struct mipi_dbi_dev * dbidev)690 int mipi_dbi_poweron_reset(struct mipi_dbi_dev *dbidev)
691 {
692 	return mipi_dbi_poweron_reset_conditional(dbidev, false);
693 }
694 EXPORT_SYMBOL(mipi_dbi_poweron_reset);
695 
696 /**
697  * mipi_dbi_poweron_conditional_reset - MIPI DBI poweron and conditional reset
698  * @dbidev: MIPI DBI device structure
699  *
700  * This function enables the regulator if used and if the display is off, it
701  * does a hardware and software reset. If mipi_dbi_display_is_on() determines
702  * that the display is on, no reset is performed.
703  *
704  * Returns:
705  * Zero if the controller was reset, 1 if the display was already on, or a
706  * negative error code.
707  */
mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev * dbidev)708 int mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev *dbidev)
709 {
710 	return mipi_dbi_poweron_reset_conditional(dbidev, true);
711 }
712 EXPORT_SYMBOL(mipi_dbi_poweron_conditional_reset);
713 
714 #if IS_ENABLED(CONFIG_SPI)
715 
716 /**
717  * mipi_dbi_spi_cmd_max_speed - get the maximum SPI bus speed
718  * @spi: SPI device
719  * @len: The transfer buffer length.
720  *
721  * Many controllers have a max speed of 10MHz, but can be pushed way beyond
722  * that. Increase reliability by running pixel data at max speed and the rest
723  * at 10MHz, preventing transfer glitches from messing up the init settings.
724  */
mipi_dbi_spi_cmd_max_speed(struct spi_device * spi,size_t len)725 u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len)
726 {
727 	if (len > 64)
728 		return 0; /* use default */
729 
730 	return min_t(u32, 10000000, spi->max_speed_hz);
731 }
732 EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed);
733 
mipi_dbi_machine_little_endian(void)734 static bool mipi_dbi_machine_little_endian(void)
735 {
736 #if defined(__LITTLE_ENDIAN)
737 	return true;
738 #else
739 	return false;
740 #endif
741 }
742 
743 /*
744  * MIPI DBI Type C Option 1
745  *
746  * If the SPI controller doesn't have 9 bits per word support,
747  * use blocks of 9 bytes to send 8x 9-bit words using a 8-bit SPI transfer.
748  * Pad partial blocks with MIPI_DCS_NOP (zero).
749  * This is how the D/C bit (x) is added:
750  *     x7654321
751  *     0x765432
752  *     10x76543
753  *     210x7654
754  *     3210x765
755  *     43210x76
756  *     543210x7
757  *     6543210x
758  *     76543210
759  */
760 
mipi_dbi_spi1e_transfer(struct mipi_dbi * dbi,int dc,const void * buf,size_t len,unsigned int bpw)761 static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc,
762 				   const void *buf, size_t len,
763 				   unsigned int bpw)
764 {
765 	bool swap_bytes = (bpw == 16 && mipi_dbi_machine_little_endian());
766 	size_t chunk, max_chunk = dbi->tx_buf9_len;
767 	struct spi_device *spi = dbi->spi;
768 	struct spi_transfer tr = {
769 		.tx_buf = dbi->tx_buf9,
770 		.bits_per_word = 8,
771 	};
772 	struct spi_message m;
773 	const u8 *src = buf;
774 	int i, ret;
775 	u8 *dst;
776 
777 	if (drm_debug_enabled(DRM_UT_DRIVER))
778 		pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
779 			 __func__, dc, max_chunk);
780 
781 	tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
782 	spi_message_init_with_transfers(&m, &tr, 1);
783 
784 	if (!dc) {
785 		if (WARN_ON_ONCE(len != 1))
786 			return -EINVAL;
787 
788 		/* Command: pad no-op's (zeroes) at beginning of block */
789 		dst = dbi->tx_buf9;
790 		memset(dst, 0, 9);
791 		dst[8] = *src;
792 		tr.len = 9;
793 
794 		return spi_sync(spi, &m);
795 	}
796 
797 	/* max with room for adding one bit per byte */
798 	max_chunk = max_chunk / 9 * 8;
799 	/* but no bigger than len */
800 	max_chunk = min(max_chunk, len);
801 	/* 8 byte blocks */
802 	max_chunk = max_t(size_t, 8, max_chunk & ~0x7);
803 
804 	while (len) {
805 		size_t added = 0;
806 
807 		chunk = min(len, max_chunk);
808 		len -= chunk;
809 		dst = dbi->tx_buf9;
810 
811 		if (chunk < 8) {
812 			u8 val, carry = 0;
813 
814 			/* Data: pad no-op's (zeroes) at end of block */
815 			memset(dst, 0, 9);
816 
817 			if (swap_bytes) {
818 				for (i = 1; i < (chunk + 1); i++) {
819 					val = src[1];
820 					*dst++ = carry | BIT(8 - i) | (val >> i);
821 					carry = val << (8 - i);
822 					i++;
823 					val = src[0];
824 					*dst++ = carry | BIT(8 - i) | (val >> i);
825 					carry = val << (8 - i);
826 					src += 2;
827 				}
828 				*dst++ = carry;
829 			} else {
830 				for (i = 1; i < (chunk + 1); i++) {
831 					val = *src++;
832 					*dst++ = carry | BIT(8 - i) | (val >> i);
833 					carry = val << (8 - i);
834 				}
835 				*dst++ = carry;
836 			}
837 
838 			chunk = 8;
839 			added = 1;
840 		} else {
841 			for (i = 0; i < chunk; i += 8) {
842 				if (swap_bytes) {
843 					*dst++ =                 BIT(7) | (src[1] >> 1);
844 					*dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2);
845 					*dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3);
846 					*dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4);
847 					*dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5);
848 					*dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6);
849 					*dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7);
850 					*dst++ = (src[7] << 1) | BIT(0);
851 					*dst++ = src[6];
852 				} else {
853 					*dst++ =                 BIT(7) | (src[0] >> 1);
854 					*dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2);
855 					*dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3);
856 					*dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4);
857 					*dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5);
858 					*dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6);
859 					*dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7);
860 					*dst++ = (src[6] << 1) | BIT(0);
861 					*dst++ = src[7];
862 				}
863 
864 				src += 8;
865 				added++;
866 			}
867 		}
868 
869 		tr.len = chunk + added;
870 
871 		ret = spi_sync(spi, &m);
872 		if (ret)
873 			return ret;
874 	}
875 
876 	return 0;
877 }
878 
mipi_dbi_spi1_transfer(struct mipi_dbi * dbi,int dc,const void * buf,size_t len,unsigned int bpw)879 static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc,
880 				  const void *buf, size_t len,
881 				  unsigned int bpw)
882 {
883 	struct spi_device *spi = dbi->spi;
884 	struct spi_transfer tr = {
885 		.bits_per_word = 9,
886 	};
887 	const u16 *src16 = buf;
888 	const u8 *src8 = buf;
889 	struct spi_message m;
890 	size_t max_chunk;
891 	u16 *dst16;
892 	int ret;
893 
894 	if (!spi_is_bpw_supported(spi, 9))
895 		return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw);
896 
897 	tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
898 	max_chunk = dbi->tx_buf9_len;
899 	dst16 = dbi->tx_buf9;
900 
901 	if (drm_debug_enabled(DRM_UT_DRIVER))
902 		pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
903 			 __func__, dc, max_chunk);
904 
905 	max_chunk = min(max_chunk / 2, len);
906 
907 	spi_message_init_with_transfers(&m, &tr, 1);
908 	tr.tx_buf = dst16;
909 
910 	while (len) {
911 		size_t chunk = min(len, max_chunk);
912 		unsigned int i;
913 
914 		if (bpw == 16 && mipi_dbi_machine_little_endian()) {
915 			for (i = 0; i < (chunk * 2); i += 2) {
916 				dst16[i]     = *src16 >> 8;
917 				dst16[i + 1] = *src16++ & 0xFF;
918 				if (dc) {
919 					dst16[i]     |= 0x0100;
920 					dst16[i + 1] |= 0x0100;
921 				}
922 			}
923 		} else {
924 			for (i = 0; i < chunk; i++) {
925 				dst16[i] = *src8++;
926 				if (dc)
927 					dst16[i] |= 0x0100;
928 			}
929 		}
930 
931 		tr.len = chunk * 2;
932 		len -= chunk;
933 
934 		ret = spi_sync(spi, &m);
935 		if (ret)
936 			return ret;
937 	}
938 
939 	return 0;
940 }
941 
mipi_dbi_typec1_command_read(struct mipi_dbi * dbi,u8 * cmd,u8 * data,size_t len)942 static int mipi_dbi_typec1_command_read(struct mipi_dbi *dbi, u8 *cmd,
943 					u8 *data, size_t len)
944 {
945 	struct spi_device *spi = dbi->spi;
946 	u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED,
947 			     spi->max_speed_hz / 2);
948 	struct spi_transfer tr[2] = {
949 		{
950 			.speed_hz = speed_hz,
951 			.bits_per_word = 9,
952 			.tx_buf = dbi->tx_buf9,
953 			.len = 2,
954 		}, {
955 			.speed_hz = speed_hz,
956 			.bits_per_word = 8,
957 			.len = len,
958 			.rx_buf = data,
959 		},
960 	};
961 	struct spi_message m;
962 	u16 *dst16;
963 	int ret;
964 
965 	if (!len)
966 		return -EINVAL;
967 
968 	if (!spi_is_bpw_supported(spi, 9)) {
969 		/*
970 		 * FIXME: implement something like mipi_dbi_spi1e_transfer() but
971 		 * for reads using emulation.
972 		 */
973 		dev_err(&spi->dev,
974 			"reading on host not supporting 9 bpw not yet implemented\n");
975 		return -EOPNOTSUPP;
976 	}
977 
978 	/*
979 	 * Turn the 8bit command into a 16bit version of the command in the
980 	 * buffer. Only 9 bits of this will be used when executing the actual
981 	 * transfer.
982 	 */
983 	dst16 = dbi->tx_buf9;
984 	dst16[0] = *cmd;
985 
986 	spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr));
987 	ret = spi_sync(spi, &m);
988 
989 	if (!ret)
990 		MIPI_DBI_DEBUG_COMMAND(*cmd, data, len);
991 
992 	return ret;
993 }
994 
mipi_dbi_typec1_command(struct mipi_dbi * dbi,u8 * cmd,u8 * parameters,size_t num)995 static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd,
996 				   u8 *parameters, size_t num)
997 {
998 	unsigned int bpw = (*cmd == MIPI_DCS_WRITE_MEMORY_START) ? 16 : 8;
999 	int ret;
1000 
1001 	if (mipi_dbi_command_is_read(dbi, *cmd))
1002 		return mipi_dbi_typec1_command_read(dbi, cmd, parameters, num);
1003 
1004 	MIPI_DBI_DEBUG_COMMAND(*cmd, parameters, num);
1005 
1006 	ret = mipi_dbi_spi1_transfer(dbi, 0, cmd, 1, 8);
1007 	if (ret || !num)
1008 		return ret;
1009 
1010 	return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw);
1011 }
1012 
1013 /* MIPI DBI Type C Option 3 */
1014 
mipi_dbi_typec3_command_read(struct mipi_dbi * dbi,u8 * cmd,u8 * data,size_t len)1015 static int mipi_dbi_typec3_command_read(struct mipi_dbi *dbi, u8 *cmd,
1016 					u8 *data, size_t len)
1017 {
1018 	struct spi_device *spi = dbi->spi;
1019 	u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED,
1020 			     spi->max_speed_hz / 2);
1021 	struct spi_transfer tr[2] = {
1022 		{
1023 			.speed_hz = speed_hz,
1024 			.tx_buf = cmd,
1025 			.len = 1,
1026 		}, {
1027 			.speed_hz = speed_hz,
1028 			.len = len,
1029 		},
1030 	};
1031 	struct spi_message m;
1032 	u8 *buf;
1033 	int ret;
1034 
1035 	if (!len)
1036 		return -EINVAL;
1037 
1038 	/*
1039 	 * Support non-standard 24-bit and 32-bit Nokia read commands which
1040 	 * start with a dummy clock, so we need to read an extra byte.
1041 	 */
1042 	if (*cmd == MIPI_DCS_GET_DISPLAY_ID ||
1043 	    *cmd == MIPI_DCS_GET_DISPLAY_STATUS) {
1044 		if (!(len == 3 || len == 4))
1045 			return -EINVAL;
1046 
1047 		tr[1].len = len + 1;
1048 	}
1049 
1050 	buf = kmalloc(tr[1].len, GFP_KERNEL);
1051 	if (!buf)
1052 		return -ENOMEM;
1053 
1054 	tr[1].rx_buf = buf;
1055 	gpiod_set_value_cansleep(dbi->dc, 0);
1056 
1057 	spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr));
1058 	ret = spi_sync(spi, &m);
1059 	if (ret)
1060 		goto err_free;
1061 
1062 	if (tr[1].len == len) {
1063 		memcpy(data, buf, len);
1064 	} else {
1065 		unsigned int i;
1066 
1067 		for (i = 0; i < len; i++)
1068 			data[i] = (buf[i] << 1) | (buf[i + 1] >> 7);
1069 	}
1070 
1071 	MIPI_DBI_DEBUG_COMMAND(*cmd, data, len);
1072 
1073 err_free:
1074 	kfree(buf);
1075 
1076 	return ret;
1077 }
1078 
mipi_dbi_typec3_command(struct mipi_dbi * dbi,u8 * cmd,u8 * par,size_t num)1079 static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd,
1080 				   u8 *par, size_t num)
1081 {
1082 	struct spi_device *spi = dbi->spi;
1083 	unsigned int bpw = 8;
1084 	u32 speed_hz;
1085 	int ret;
1086 
1087 	if (mipi_dbi_command_is_read(dbi, *cmd))
1088 		return mipi_dbi_typec3_command_read(dbi, cmd, par, num);
1089 
1090 	MIPI_DBI_DEBUG_COMMAND(*cmd, par, num);
1091 
1092 	gpiod_set_value_cansleep(dbi->dc, 0);
1093 	speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1);
1094 	ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, cmd, 1);
1095 	if (ret || !num)
1096 		return ret;
1097 
1098 	if (*cmd == MIPI_DCS_WRITE_MEMORY_START && !dbi->swap_bytes)
1099 		bpw = 16;
1100 
1101 	gpiod_set_value_cansleep(dbi->dc, 1);
1102 	speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num);
1103 
1104 	return mipi_dbi_spi_transfer(spi, speed_hz, bpw, par, num);
1105 }
1106 
1107 /**
1108  * mipi_dbi_spi_init - Initialize MIPI DBI SPI interface
1109  * @spi: SPI device
1110  * @dbi: MIPI DBI structure to initialize
1111  * @dc: D/C gpio (optional)
1112  *
1113  * This function sets &mipi_dbi->command, enables &mipi_dbi->read_commands for the
1114  * usual read commands. It should be followed by a call to mipi_dbi_dev_init() or
1115  * a driver-specific init.
1116  *
1117  * If @dc is set, a Type C Option 3 interface is assumed, if not
1118  * Type C Option 1.
1119  *
1120  * If the SPI master driver doesn't support the necessary bits per word,
1121  * the following transformation is used:
1122  *
1123  * - 9-bit: reorder buffer as 9x 8-bit words, padded with no-op command.
1124  * - 16-bit: if big endian send as 8-bit, if little endian swap bytes
1125  *
1126  * Returns:
1127  * Zero on success, negative error code on failure.
1128  */
mipi_dbi_spi_init(struct spi_device * spi,struct mipi_dbi * dbi,struct gpio_desc * dc)1129 int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi,
1130 		      struct gpio_desc *dc)
1131 {
1132 	struct device *dev = &spi->dev;
1133 	int ret;
1134 
1135 	/*
1136 	 * Even though it's not the SPI device that does DMA (the master does),
1137 	 * the dma mask is necessary for the dma_alloc_wc() in the GEM code
1138 	 * (e.g., drm_gem_dma_create()). The dma_addr returned will be a physical
1139 	 * address which might be different from the bus address, but this is
1140 	 * not a problem since the address will not be used.
1141 	 * The virtual address is used in the transfer and the SPI core
1142 	 * re-maps it on the SPI master device using the DMA streaming API
1143 	 * (spi_map_buf()).
1144 	 */
1145 	if (!dev->coherent_dma_mask) {
1146 		ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
1147 		if (ret) {
1148 			dev_warn(dev, "Failed to set dma mask %d\n", ret);
1149 			return ret;
1150 		}
1151 	}
1152 
1153 	dbi->spi = spi;
1154 	dbi->read_commands = mipi_dbi_dcs_read_commands;
1155 
1156 	if (dc) {
1157 		dbi->command = mipi_dbi_typec3_command;
1158 		dbi->dc = dc;
1159 		if (mipi_dbi_machine_little_endian() && !spi_is_bpw_supported(spi, 16))
1160 			dbi->swap_bytes = true;
1161 	} else {
1162 		dbi->command = mipi_dbi_typec1_command;
1163 		dbi->tx_buf9_len = SZ_16K;
1164 		dbi->tx_buf9 = devm_kmalloc(dev, dbi->tx_buf9_len, GFP_KERNEL);
1165 		if (!dbi->tx_buf9)
1166 			return -ENOMEM;
1167 	}
1168 
1169 	mutex_init(&dbi->cmdlock);
1170 
1171 	DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000);
1172 
1173 	return 0;
1174 }
1175 EXPORT_SYMBOL(mipi_dbi_spi_init);
1176 
1177 /**
1178  * mipi_dbi_spi_transfer - SPI transfer helper
1179  * @spi: SPI device
1180  * @speed_hz: Override speed (optional)
1181  * @bpw: Bits per word
1182  * @buf: Buffer to transfer
1183  * @len: Buffer length
1184  *
1185  * This SPI transfer helper breaks up the transfer of @buf into chunks which
1186  * the SPI controller driver can handle.
1187  *
1188  * Returns:
1189  * Zero on success, negative error code on failure.
1190  */
mipi_dbi_spi_transfer(struct spi_device * spi,u32 speed_hz,u8 bpw,const void * buf,size_t len)1191 int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz,
1192 			  u8 bpw, const void *buf, size_t len)
1193 {
1194 	size_t max_chunk = spi_max_transfer_size(spi);
1195 	struct spi_transfer tr = {
1196 		.bits_per_word = bpw,
1197 		.speed_hz = speed_hz,
1198 	};
1199 	struct spi_message m;
1200 	size_t chunk;
1201 	int ret;
1202 
1203 	/* In __spi_validate, there's a validation that no partial transfers
1204 	 * are accepted (xfer->len % w_size must be zero).
1205 	 * Here we align max_chunk to multiple of 2 (16bits),
1206 	 * to prevent transfers from being rejected.
1207 	 */
1208 	max_chunk = ALIGN_DOWN(max_chunk, 2);
1209 
1210 	spi_message_init_with_transfers(&m, &tr, 1);
1211 
1212 	while (len) {
1213 		chunk = min(len, max_chunk);
1214 
1215 		tr.tx_buf = buf;
1216 		tr.len = chunk;
1217 		buf += chunk;
1218 		len -= chunk;
1219 
1220 		ret = spi_sync(spi, &m);
1221 		if (ret)
1222 			return ret;
1223 	}
1224 
1225 	return 0;
1226 }
1227 EXPORT_SYMBOL(mipi_dbi_spi_transfer);
1228 
1229 #endif /* CONFIG_SPI */
1230 
1231 #ifdef CONFIG_DEBUG_FS
1232 
mipi_dbi_debugfs_command_write(struct file * file,const char __user * ubuf,size_t count,loff_t * ppos)1233 static ssize_t mipi_dbi_debugfs_command_write(struct file *file,
1234 					      const char __user *ubuf,
1235 					      size_t count, loff_t *ppos)
1236 {
1237 	struct seq_file *m = file->private_data;
1238 	struct mipi_dbi_dev *dbidev = m->private;
1239 	u8 val, cmd = 0, parameters[64];
1240 	char *buf, *pos, *token;
1241 	int i, ret, idx;
1242 
1243 	if (!drm_dev_enter(&dbidev->drm, &idx))
1244 		return -ENODEV;
1245 
1246 	buf = memdup_user_nul(ubuf, count);
1247 	if (IS_ERR(buf)) {
1248 		ret = PTR_ERR(buf);
1249 		goto err_exit;
1250 	}
1251 
1252 	/* strip trailing whitespace */
1253 	for (i = count - 1; i > 0; i--)
1254 		if (isspace(buf[i]))
1255 			buf[i] = '\0';
1256 		else
1257 			break;
1258 	i = 0;
1259 	pos = buf;
1260 	while (pos) {
1261 		token = strsep(&pos, " ");
1262 		if (!token) {
1263 			ret = -EINVAL;
1264 			goto err_free;
1265 		}
1266 
1267 		ret = kstrtou8(token, 16, &val);
1268 		if (ret < 0)
1269 			goto err_free;
1270 
1271 		if (token == buf)
1272 			cmd = val;
1273 		else
1274 			parameters[i++] = val;
1275 
1276 		if (i == 64) {
1277 			ret = -E2BIG;
1278 			goto err_free;
1279 		}
1280 	}
1281 
1282 	ret = mipi_dbi_command_buf(&dbidev->dbi, cmd, parameters, i);
1283 
1284 err_free:
1285 	kfree(buf);
1286 err_exit:
1287 	drm_dev_exit(idx);
1288 
1289 	return ret < 0 ? ret : count;
1290 }
1291 
mipi_dbi_debugfs_command_show(struct seq_file * m,void * unused)1292 static int mipi_dbi_debugfs_command_show(struct seq_file *m, void *unused)
1293 {
1294 	struct mipi_dbi_dev *dbidev = m->private;
1295 	struct mipi_dbi *dbi = &dbidev->dbi;
1296 	u8 cmd, val[4];
1297 	int ret, idx;
1298 	size_t len;
1299 
1300 	if (!drm_dev_enter(&dbidev->drm, &idx))
1301 		return -ENODEV;
1302 
1303 	for (cmd = 0; cmd < 255; cmd++) {
1304 		if (!mipi_dbi_command_is_read(dbi, cmd))
1305 			continue;
1306 
1307 		switch (cmd) {
1308 		case MIPI_DCS_READ_MEMORY_START:
1309 		case MIPI_DCS_READ_MEMORY_CONTINUE:
1310 			len = 2;
1311 			break;
1312 		case MIPI_DCS_GET_DISPLAY_ID:
1313 			len = 3;
1314 			break;
1315 		case MIPI_DCS_GET_DISPLAY_STATUS:
1316 			len = 4;
1317 			break;
1318 		default:
1319 			len = 1;
1320 			break;
1321 		}
1322 
1323 		seq_printf(m, "%02x: ", cmd);
1324 		ret = mipi_dbi_command_buf(dbi, cmd, val, len);
1325 		if (ret) {
1326 			seq_puts(m, "XX\n");
1327 			continue;
1328 		}
1329 		seq_printf(m, "%*phN\n", (int)len, val);
1330 	}
1331 
1332 	drm_dev_exit(idx);
1333 
1334 	return 0;
1335 }
1336 
mipi_dbi_debugfs_command_open(struct inode * inode,struct file * file)1337 static int mipi_dbi_debugfs_command_open(struct inode *inode,
1338 					 struct file *file)
1339 {
1340 	return single_open(file, mipi_dbi_debugfs_command_show,
1341 			   inode->i_private);
1342 }
1343 
1344 static const struct file_operations mipi_dbi_debugfs_command_fops = {
1345 	.owner = THIS_MODULE,
1346 	.open = mipi_dbi_debugfs_command_open,
1347 	.read = seq_read,
1348 	.llseek = seq_lseek,
1349 	.release = single_release,
1350 	.write = mipi_dbi_debugfs_command_write,
1351 };
1352 
1353 /**
1354  * mipi_dbi_debugfs_init - Create debugfs entries
1355  * @minor: DRM minor
1356  *
1357  * This function creates a 'command' debugfs file for sending commands to the
1358  * controller or getting the read command values.
1359  * Drivers can use this as their &drm_driver->debugfs_init callback.
1360  *
1361  */
mipi_dbi_debugfs_init(struct drm_minor * minor)1362 void mipi_dbi_debugfs_init(struct drm_minor *minor)
1363 {
1364 	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(minor->dev);
1365 	umode_t mode = S_IFREG | S_IWUSR;
1366 
1367 	if (dbidev->dbi.read_commands)
1368 		mode |= S_IRUGO;
1369 	debugfs_create_file("command", mode, minor->debugfs_root, dbidev,
1370 			    &mipi_dbi_debugfs_command_fops);
1371 }
1372 EXPORT_SYMBOL(mipi_dbi_debugfs_init);
1373 
1374 #endif
1375 
1376 MODULE_LICENSE("GPL");
1377