1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * MIPI Display Bus Interface (DBI) LCD controller support
4  *
5  * Copyright 2016 Noralf Trønnes
6  */
7 
8 #include <linux/debugfs.h>
9 #include <linux/delay.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/module.h>
12 #include <linux/regulator/consumer.h>
13 #include <linux/spi/spi.h>
14 
15 #include <drm/drm_connector.h>
16 #include <drm/drm_damage_helper.h>
17 #include <drm/drm_drv.h>
18 #include <drm/drm_file.h>
19 #include <drm/drm_format_helper.h>
20 #include <drm/drm_fourcc.h>
21 #include <drm/drm_gem.h>
22 #include <drm/drm_gem_framebuffer_helper.h>
23 #include <drm/drm_mipi_dbi.h>
24 #include <drm/drm_modes.h>
25 #include <drm/drm_probe_helper.h>
26 #include <drm/drm_rect.h>
27 #include <video/mipi_display.h>
28 
29 #define MIPI_DBI_MAX_SPI_READ_SPEED 2000000 /* 2MHz */
30 
31 #define DCS_POWER_MODE_DISPLAY			BIT(2)
32 #define DCS_POWER_MODE_DISPLAY_NORMAL_MODE	BIT(3)
33 #define DCS_POWER_MODE_SLEEP_MODE		BIT(4)
34 #define DCS_POWER_MODE_PARTIAL_MODE		BIT(5)
35 #define DCS_POWER_MODE_IDLE_MODE		BIT(6)
36 #define DCS_POWER_MODE_RESERVED_MASK		(BIT(0) | BIT(1) | BIT(7))
37 
38 /**
39  * DOC: overview
40  *
41  * This library provides helpers for MIPI Display Bus Interface (DBI)
42  * compatible display controllers.
43  *
44  * Many controllers for tiny lcd displays are MIPI compliant and can use this
45  * library. If a controller uses registers 0x2A and 0x2B to set the area to
46  * update and uses register 0x2C to write to frame memory, it is most likely
47  * MIPI compliant.
48  *
49  * Only MIPI Type 1 displays are supported since a full frame memory is needed.
50  *
51  * There are 3 MIPI DBI implementation types:
52  *
53  * A. Motorola 6800 type parallel bus
54  *
55  * B. Intel 8080 type parallel bus
56  *
57  * C. SPI type with 3 options:
58  *
59  *    1. 9-bit with the Data/Command signal as the ninth bit
60  *    2. Same as above except it's sent as 16 bits
61  *    3. 8-bit with the Data/Command signal as a separate D/CX pin
62  *
63  * Currently mipi_dbi only supports Type C options 1 and 3 with
64  * mipi_dbi_spi_init().
65  */
66 
67 #define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \
68 ({ \
69 	if (!len) \
70 		DRM_DEBUG_DRIVER("cmd=%02x\n", cmd); \
71 	else if (len <= 32) \
72 		DRM_DEBUG_DRIVER("cmd=%02x, par=%*ph\n", cmd, (int)len, data);\
73 	else \
74 		DRM_DEBUG_DRIVER("cmd=%02x, len=%zu\n", cmd, len); \
75 })
76 
77 static const u8 mipi_dbi_dcs_read_commands[] = {
78 	MIPI_DCS_GET_DISPLAY_ID,
79 	MIPI_DCS_GET_RED_CHANNEL,
80 	MIPI_DCS_GET_GREEN_CHANNEL,
81 	MIPI_DCS_GET_BLUE_CHANNEL,
82 	MIPI_DCS_GET_DISPLAY_STATUS,
83 	MIPI_DCS_GET_POWER_MODE,
84 	MIPI_DCS_GET_ADDRESS_MODE,
85 	MIPI_DCS_GET_PIXEL_FORMAT,
86 	MIPI_DCS_GET_DISPLAY_MODE,
87 	MIPI_DCS_GET_SIGNAL_MODE,
88 	MIPI_DCS_GET_DIAGNOSTIC_RESULT,
89 	MIPI_DCS_READ_MEMORY_START,
90 	MIPI_DCS_READ_MEMORY_CONTINUE,
91 	MIPI_DCS_GET_SCANLINE,
92 	MIPI_DCS_GET_DISPLAY_BRIGHTNESS,
93 	MIPI_DCS_GET_CONTROL_DISPLAY,
94 	MIPI_DCS_GET_POWER_SAVE,
95 	MIPI_DCS_GET_CABC_MIN_BRIGHTNESS,
96 	MIPI_DCS_READ_DDB_START,
97 	MIPI_DCS_READ_DDB_CONTINUE,
98 	0, /* sentinel */
99 };
100 
mipi_dbi_command_is_read(struct mipi_dbi * dbi,u8 cmd)101 static bool mipi_dbi_command_is_read(struct mipi_dbi *dbi, u8 cmd)
102 {
103 	unsigned int i;
104 
105 	if (!dbi->read_commands)
106 		return false;
107 
108 	for (i = 0; i < 0xff; i++) {
109 		if (!dbi->read_commands[i])
110 			return false;
111 		if (cmd == dbi->read_commands[i])
112 			return true;
113 	}
114 
115 	return false;
116 }
117 
118 /**
119  * mipi_dbi_command_read - MIPI DCS read command
120  * @dbi: MIPI DBI structure
121  * @cmd: Command
122  * @val: Value read
123  *
124  * Send MIPI DCS read command to the controller.
125  *
126  * Returns:
127  * Zero on success, negative error code on failure.
128  */
mipi_dbi_command_read(struct mipi_dbi * dbi,u8 cmd,u8 * val)129 int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val)
130 {
131 	if (!dbi->read_commands)
132 		return -EACCES;
133 
134 	if (!mipi_dbi_command_is_read(dbi, cmd))
135 		return -EINVAL;
136 
137 	return mipi_dbi_command_buf(dbi, cmd, val, 1);
138 }
139 EXPORT_SYMBOL(mipi_dbi_command_read);
140 
141 /**
142  * mipi_dbi_command_buf - MIPI DCS command with parameter(s) in an array
143  * @dbi: MIPI DBI structure
144  * @cmd: Command
145  * @data: Parameter buffer
146  * @len: Buffer length
147  *
148  * Returns:
149  * Zero on success, negative error code on failure.
150  */
mipi_dbi_command_buf(struct mipi_dbi * dbi,u8 cmd,u8 * data,size_t len)151 int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len)
152 {
153 	u8 *cmdbuf;
154 	int ret;
155 
156 	/* SPI requires dma-safe buffers */
157 	cmdbuf = kmemdup(&cmd, 1, GFP_KERNEL);
158 	if (!cmdbuf)
159 		return -ENOMEM;
160 
161 	mutex_lock(&dbi->cmdlock);
162 	ret = dbi->command(dbi, cmdbuf, data, len);
163 	mutex_unlock(&dbi->cmdlock);
164 
165 	kfree(cmdbuf);
166 
167 	return ret;
168 }
169 EXPORT_SYMBOL(mipi_dbi_command_buf);
170 
171 /* This should only be used by mipi_dbi_command() */
mipi_dbi_command_stackbuf(struct mipi_dbi * dbi,u8 cmd,const u8 * data,size_t len)172 int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, const u8 *data,
173 			      size_t len)
174 {
175 	u8 *buf;
176 	int ret;
177 
178 	buf = kmemdup(data, len, GFP_KERNEL);
179 	if (!buf)
180 		return -ENOMEM;
181 
182 	ret = mipi_dbi_command_buf(dbi, cmd, buf, len);
183 
184 	kfree(buf);
185 
186 	return ret;
187 }
188 EXPORT_SYMBOL(mipi_dbi_command_stackbuf);
189 
190 /**
191  * mipi_dbi_buf_copy - Copy a framebuffer, transforming it if necessary
192  * @dst: The destination buffer
193  * @fb: The source framebuffer
194  * @clip: Clipping rectangle of the area to be copied
195  * @swap: When true, swap MSB/LSB of 16-bit values
196  *
197  * Returns:
198  * Zero on success, negative error code on failure.
199  */
mipi_dbi_buf_copy(void * dst,struct drm_framebuffer * fb,struct drm_rect * clip,bool swap)200 int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb,
201 		      struct drm_rect *clip, bool swap)
202 {
203 	struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0);
204 	struct iosys_map map[DRM_FORMAT_MAX_PLANES];
205 	struct iosys_map data[DRM_FORMAT_MAX_PLANES];
206 	void *src;
207 	int ret;
208 
209 	ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE);
210 	if (ret)
211 		return ret;
212 
213 	ret = drm_gem_fb_vmap(fb, map, data);
214 	if (ret)
215 		goto out_drm_gem_fb_end_cpu_access;
216 	src = data[0].vaddr; /* TODO: Use mapping abstraction properly */
217 
218 	switch (fb->format->format) {
219 	case DRM_FORMAT_RGB565:
220 		if (swap)
221 			drm_fb_swab(dst, 0, src, fb, clip, !gem->import_attach);
222 		else
223 			drm_fb_memcpy(dst, 0, src, fb, clip);
224 		break;
225 	case DRM_FORMAT_XRGB8888:
226 		drm_fb_xrgb8888_to_rgb565(dst, 0, src, fb, clip, swap);
227 		break;
228 	default:
229 		drm_err_once(fb->dev, "Format is not supported: %p4cc\n",
230 			     &fb->format->format);
231 		ret = -EINVAL;
232 	}
233 
234 	drm_gem_fb_vunmap(fb, map);
235 out_drm_gem_fb_end_cpu_access:
236 	drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
237 
238 	return ret;
239 }
240 EXPORT_SYMBOL(mipi_dbi_buf_copy);
241 
mipi_dbi_set_window_address(struct mipi_dbi_dev * dbidev,unsigned int xs,unsigned int xe,unsigned int ys,unsigned int ye)242 static void mipi_dbi_set_window_address(struct mipi_dbi_dev *dbidev,
243 					unsigned int xs, unsigned int xe,
244 					unsigned int ys, unsigned int ye)
245 {
246 	struct mipi_dbi *dbi = &dbidev->dbi;
247 
248 	xs += dbidev->left_offset;
249 	xe += dbidev->left_offset;
250 	ys += dbidev->top_offset;
251 	ye += dbidev->top_offset;
252 
253 	mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, (xs >> 8) & 0xff,
254 			 xs & 0xff, (xe >> 8) & 0xff, xe & 0xff);
255 	mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, (ys >> 8) & 0xff,
256 			 ys & 0xff, (ye >> 8) & 0xff, ye & 0xff);
257 }
258 
mipi_dbi_fb_dirty(struct drm_framebuffer * fb,struct drm_rect * rect)259 static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect)
260 {
261 	struct iosys_map map[DRM_FORMAT_MAX_PLANES];
262 	struct iosys_map data[DRM_FORMAT_MAX_PLANES];
263 	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev);
264 	unsigned int height = rect->y2 - rect->y1;
265 	unsigned int width = rect->x2 - rect->x1;
266 	struct mipi_dbi *dbi = &dbidev->dbi;
267 	bool swap = dbi->swap_bytes;
268 	int idx, ret = 0;
269 	bool full;
270 	void *tr;
271 
272 	if (WARN_ON(!fb))
273 		return;
274 
275 	if (!drm_dev_enter(fb->dev, &idx))
276 		return;
277 
278 	ret = drm_gem_fb_vmap(fb, map, data);
279 	if (ret)
280 		goto err_drm_dev_exit;
281 
282 	full = width == fb->width && height == fb->height;
283 
284 	DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect));
285 
286 	if (!dbi->dc || !full || swap ||
287 	    fb->format->format == DRM_FORMAT_XRGB8888) {
288 		tr = dbidev->tx_buf;
289 		ret = mipi_dbi_buf_copy(dbidev->tx_buf, fb, rect, swap);
290 		if (ret)
291 			goto err_msg;
292 	} else {
293 		tr = data[0].vaddr; /* TODO: Use mapping abstraction properly */
294 	}
295 
296 	mipi_dbi_set_window_address(dbidev, rect->x1, rect->x2 - 1, rect->y1,
297 				    rect->y2 - 1);
298 
299 	ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr,
300 				   width * height * 2);
301 err_msg:
302 	if (ret)
303 		drm_err_once(fb->dev, "Failed to update display %d\n", ret);
304 
305 	drm_gem_fb_vunmap(fb, map);
306 
307 err_drm_dev_exit:
308 	drm_dev_exit(idx);
309 }
310 
311 /**
312  * mipi_dbi_pipe_update - Display pipe update helper
313  * @pipe: Simple display pipe
314  * @old_state: Old plane state
315  *
316  * This function handles framebuffer flushing and vblank events. Drivers can use
317  * this as their &drm_simple_display_pipe_funcs->update callback.
318  */
mipi_dbi_pipe_update(struct drm_simple_display_pipe * pipe,struct drm_plane_state * old_state)319 void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe,
320 			  struct drm_plane_state *old_state)
321 {
322 	struct drm_plane_state *state = pipe->plane.state;
323 	struct drm_rect rect;
324 
325 	if (!pipe->crtc.state->active)
326 		return;
327 
328 	if (drm_atomic_helper_damage_merged(old_state, state, &rect))
329 		mipi_dbi_fb_dirty(state->fb, &rect);
330 }
331 EXPORT_SYMBOL(mipi_dbi_pipe_update);
332 
333 /**
334  * mipi_dbi_enable_flush - MIPI DBI enable helper
335  * @dbidev: MIPI DBI device structure
336  * @crtc_state: CRTC state
337  * @plane_state: Plane state
338  *
339  * Flushes the whole framebuffer and enables the backlight. Drivers can use this
340  * in their &drm_simple_display_pipe_funcs->enable callback.
341  *
342  * Note: Drivers which don't use mipi_dbi_pipe_update() because they have custom
343  * framebuffer flushing, can't use this function since they both use the same
344  * flushing code.
345  */
mipi_dbi_enable_flush(struct mipi_dbi_dev * dbidev,struct drm_crtc_state * crtc_state,struct drm_plane_state * plane_state)346 void mipi_dbi_enable_flush(struct mipi_dbi_dev *dbidev,
347 			   struct drm_crtc_state *crtc_state,
348 			   struct drm_plane_state *plane_state)
349 {
350 	struct drm_framebuffer *fb = plane_state->fb;
351 	struct drm_rect rect = {
352 		.x1 = 0,
353 		.x2 = fb->width,
354 		.y1 = 0,
355 		.y2 = fb->height,
356 	};
357 	int idx;
358 
359 	if (!drm_dev_enter(&dbidev->drm, &idx))
360 		return;
361 
362 	mipi_dbi_fb_dirty(fb, &rect);
363 	backlight_enable(dbidev->backlight);
364 
365 	drm_dev_exit(idx);
366 }
367 EXPORT_SYMBOL(mipi_dbi_enable_flush);
368 
mipi_dbi_blank(struct mipi_dbi_dev * dbidev)369 static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev)
370 {
371 	struct drm_device *drm = &dbidev->drm;
372 	u16 height = drm->mode_config.min_height;
373 	u16 width = drm->mode_config.min_width;
374 	struct mipi_dbi *dbi = &dbidev->dbi;
375 	size_t len = width * height * 2;
376 	int idx;
377 
378 	if (!drm_dev_enter(drm, &idx))
379 		return;
380 
381 	memset(dbidev->tx_buf, 0, len);
382 
383 	mipi_dbi_set_window_address(dbidev, 0, width - 1, 0, height - 1);
384 	mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START,
385 			     (u8 *)dbidev->tx_buf, len);
386 
387 	drm_dev_exit(idx);
388 }
389 
390 /**
391  * mipi_dbi_pipe_disable - MIPI DBI pipe disable helper
392  * @pipe: Display pipe
393  *
394  * This function disables backlight if present, if not the display memory is
395  * blanked. The regulator is disabled if in use. Drivers can use this as their
396  * &drm_simple_display_pipe_funcs->disable callback.
397  */
mipi_dbi_pipe_disable(struct drm_simple_display_pipe * pipe)398 void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe)
399 {
400 	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
401 
402 	DRM_DEBUG_KMS("\n");
403 
404 	if (dbidev->backlight)
405 		backlight_disable(dbidev->backlight);
406 	else
407 		mipi_dbi_blank(dbidev);
408 
409 	if (dbidev->regulator)
410 		regulator_disable(dbidev->regulator);
411 }
412 EXPORT_SYMBOL(mipi_dbi_pipe_disable);
413 
mipi_dbi_connector_get_modes(struct drm_connector * connector)414 static int mipi_dbi_connector_get_modes(struct drm_connector *connector)
415 {
416 	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(connector->dev);
417 	struct drm_display_mode *mode;
418 
419 	mode = drm_mode_duplicate(connector->dev, &dbidev->mode);
420 	if (!mode) {
421 		DRM_ERROR("Failed to duplicate mode\n");
422 		return 0;
423 	}
424 
425 	if (mode->name[0] == '\0')
426 		drm_mode_set_name(mode);
427 
428 	mode->type |= DRM_MODE_TYPE_PREFERRED;
429 	drm_mode_probed_add(connector, mode);
430 
431 	if (mode->width_mm) {
432 		connector->display_info.width_mm = mode->width_mm;
433 		connector->display_info.height_mm = mode->height_mm;
434 	}
435 
436 	return 1;
437 }
438 
439 static const struct drm_connector_helper_funcs mipi_dbi_connector_hfuncs = {
440 	.get_modes = mipi_dbi_connector_get_modes,
441 };
442 
443 static const struct drm_connector_funcs mipi_dbi_connector_funcs = {
444 	.reset = drm_atomic_helper_connector_reset,
445 	.fill_modes = drm_helper_probe_single_connector_modes,
446 	.destroy = drm_connector_cleanup,
447 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
448 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
449 };
450 
mipi_dbi_rotate_mode(struct drm_display_mode * mode,unsigned int rotation)451 static int mipi_dbi_rotate_mode(struct drm_display_mode *mode,
452 				unsigned int rotation)
453 {
454 	if (rotation == 0 || rotation == 180) {
455 		return 0;
456 	} else if (rotation == 90 || rotation == 270) {
457 		swap(mode->hdisplay, mode->vdisplay);
458 		swap(mode->hsync_start, mode->vsync_start);
459 		swap(mode->hsync_end, mode->vsync_end);
460 		swap(mode->htotal, mode->vtotal);
461 		swap(mode->width_mm, mode->height_mm);
462 		return 0;
463 	} else {
464 		return -EINVAL;
465 	}
466 }
467 
468 static const struct drm_mode_config_funcs mipi_dbi_mode_config_funcs = {
469 	.fb_create = drm_gem_fb_create_with_dirty,
470 	.atomic_check = drm_atomic_helper_check,
471 	.atomic_commit = drm_atomic_helper_commit,
472 };
473 
474 static const uint32_t mipi_dbi_formats[] = {
475 	DRM_FORMAT_RGB565,
476 	DRM_FORMAT_XRGB8888,
477 };
478 
479 /**
480  * mipi_dbi_dev_init_with_formats - MIPI DBI device initialization with custom formats
481  * @dbidev: MIPI DBI device structure to initialize
482  * @funcs: Display pipe functions
483  * @formats: Array of supported formats (DRM_FORMAT\_\*).
484  * @format_count: Number of elements in @formats
485  * @mode: Display mode
486  * @rotation: Initial rotation in degrees Counter Clock Wise
487  * @tx_buf_size: Allocate a transmit buffer of this size.
488  *
489  * This function sets up a &drm_simple_display_pipe with a &drm_connector that
490  * has one fixed &drm_display_mode which is rotated according to @rotation.
491  * This mode is used to set the mode config min/max width/height properties.
492  *
493  * Use mipi_dbi_dev_init() if you don't need custom formats.
494  *
495  * Note:
496  * Some of the helper functions expects RGB565 to be the default format and the
497  * transmit buffer sized to fit that.
498  *
499  * Returns:
500  * Zero on success, negative error code on failure.
501  */
mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev * dbidev,const struct drm_simple_display_pipe_funcs * funcs,const uint32_t * formats,unsigned int format_count,const struct drm_display_mode * mode,unsigned int rotation,size_t tx_buf_size)502 int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev,
503 				   const struct drm_simple_display_pipe_funcs *funcs,
504 				   const uint32_t *formats, unsigned int format_count,
505 				   const struct drm_display_mode *mode,
506 				   unsigned int rotation, size_t tx_buf_size)
507 {
508 	static const uint64_t modifiers[] = {
509 		DRM_FORMAT_MOD_LINEAR,
510 		DRM_FORMAT_MOD_INVALID
511 	};
512 	struct drm_device *drm = &dbidev->drm;
513 	int ret;
514 
515 	if (!dbidev->dbi.command)
516 		return -EINVAL;
517 
518 	ret = drmm_mode_config_init(drm);
519 	if (ret)
520 		return ret;
521 
522 	dbidev->tx_buf = devm_kmalloc(drm->dev, tx_buf_size, GFP_KERNEL);
523 	if (!dbidev->tx_buf)
524 		return -ENOMEM;
525 
526 	drm_mode_copy(&dbidev->mode, mode);
527 	ret = mipi_dbi_rotate_mode(&dbidev->mode, rotation);
528 	if (ret) {
529 		DRM_ERROR("Illegal rotation value %u\n", rotation);
530 		return -EINVAL;
531 	}
532 
533 	drm_connector_helper_add(&dbidev->connector, &mipi_dbi_connector_hfuncs);
534 	ret = drm_connector_init(drm, &dbidev->connector, &mipi_dbi_connector_funcs,
535 				 DRM_MODE_CONNECTOR_SPI);
536 	if (ret)
537 		return ret;
538 
539 	ret = drm_simple_display_pipe_init(drm, &dbidev->pipe, funcs, formats, format_count,
540 					   modifiers, &dbidev->connector);
541 	if (ret)
542 		return ret;
543 
544 	drm_plane_enable_fb_damage_clips(&dbidev->pipe.plane);
545 
546 	drm->mode_config.funcs = &mipi_dbi_mode_config_funcs;
547 	drm->mode_config.min_width = dbidev->mode.hdisplay;
548 	drm->mode_config.max_width = dbidev->mode.hdisplay;
549 	drm->mode_config.min_height = dbidev->mode.vdisplay;
550 	drm->mode_config.max_height = dbidev->mode.vdisplay;
551 	dbidev->rotation = rotation;
552 
553 	DRM_DEBUG_KMS("rotation = %u\n", rotation);
554 
555 	return 0;
556 }
557 EXPORT_SYMBOL(mipi_dbi_dev_init_with_formats);
558 
559 /**
560  * mipi_dbi_dev_init - MIPI DBI device initialization
561  * @dbidev: MIPI DBI device structure to initialize
562  * @funcs: Display pipe functions
563  * @mode: Display mode
564  * @rotation: Initial rotation in degrees Counter Clock Wise
565  *
566  * This function sets up a &drm_simple_display_pipe with a &drm_connector that
567  * has one fixed &drm_display_mode which is rotated according to @rotation.
568  * This mode is used to set the mode config min/max width/height properties.
569  * Additionally &mipi_dbi.tx_buf is allocated.
570  *
571  * Supported formats: Native RGB565 and emulated XRGB8888.
572  *
573  * Returns:
574  * Zero on success, negative error code on failure.
575  */
mipi_dbi_dev_init(struct mipi_dbi_dev * dbidev,const struct drm_simple_display_pipe_funcs * funcs,const struct drm_display_mode * mode,unsigned int rotation)576 int mipi_dbi_dev_init(struct mipi_dbi_dev *dbidev,
577 		      const struct drm_simple_display_pipe_funcs *funcs,
578 		      const struct drm_display_mode *mode, unsigned int rotation)
579 {
580 	size_t bufsize = mode->vdisplay * mode->hdisplay * sizeof(u16);
581 
582 	dbidev->drm.mode_config.preferred_depth = 16;
583 
584 	return mipi_dbi_dev_init_with_formats(dbidev, funcs, mipi_dbi_formats,
585 					      ARRAY_SIZE(mipi_dbi_formats), mode,
586 					      rotation, bufsize);
587 }
588 EXPORT_SYMBOL(mipi_dbi_dev_init);
589 
590 /**
591  * mipi_dbi_hw_reset - Hardware reset of controller
592  * @dbi: MIPI DBI structure
593  *
594  * Reset controller if the &mipi_dbi->reset gpio is set.
595  */
mipi_dbi_hw_reset(struct mipi_dbi * dbi)596 void mipi_dbi_hw_reset(struct mipi_dbi *dbi)
597 {
598 	if (!dbi->reset)
599 		return;
600 
601 	gpiod_set_value_cansleep(dbi->reset, 0);
602 	usleep_range(20, 1000);
603 	gpiod_set_value_cansleep(dbi->reset, 1);
604 	msleep(120);
605 }
606 EXPORT_SYMBOL(mipi_dbi_hw_reset);
607 
608 /**
609  * mipi_dbi_display_is_on - Check if display is on
610  * @dbi: MIPI DBI structure
611  *
612  * This function checks the Power Mode register (if readable) to see if
613  * display output is turned on. This can be used to see if the bootloader
614  * has already turned on the display avoiding flicker when the pipeline is
615  * enabled.
616  *
617  * Returns:
618  * true if the display can be verified to be on, false otherwise.
619  */
mipi_dbi_display_is_on(struct mipi_dbi * dbi)620 bool mipi_dbi_display_is_on(struct mipi_dbi *dbi)
621 {
622 	u8 val;
623 
624 	if (mipi_dbi_command_read(dbi, MIPI_DCS_GET_POWER_MODE, &val))
625 		return false;
626 
627 	val &= ~DCS_POWER_MODE_RESERVED_MASK;
628 
629 	/* The poweron/reset value is 08h DCS_POWER_MODE_DISPLAY_NORMAL_MODE */
630 	if (val != (DCS_POWER_MODE_DISPLAY |
631 	    DCS_POWER_MODE_DISPLAY_NORMAL_MODE | DCS_POWER_MODE_SLEEP_MODE))
632 		return false;
633 
634 	DRM_DEBUG_DRIVER("Display is ON\n");
635 
636 	return true;
637 }
638 EXPORT_SYMBOL(mipi_dbi_display_is_on);
639 
mipi_dbi_poweron_reset_conditional(struct mipi_dbi_dev * dbidev,bool cond)640 static int mipi_dbi_poweron_reset_conditional(struct mipi_dbi_dev *dbidev, bool cond)
641 {
642 	struct device *dev = dbidev->drm.dev;
643 	struct mipi_dbi *dbi = &dbidev->dbi;
644 	int ret;
645 
646 	if (dbidev->regulator) {
647 		ret = regulator_enable(dbidev->regulator);
648 		if (ret) {
649 			DRM_DEV_ERROR(dev, "Failed to enable regulator (%d)\n", ret);
650 			return ret;
651 		}
652 	}
653 
654 	if (cond && mipi_dbi_display_is_on(dbi))
655 		return 1;
656 
657 	mipi_dbi_hw_reset(dbi);
658 	ret = mipi_dbi_command(dbi, MIPI_DCS_SOFT_RESET);
659 	if (ret) {
660 		DRM_DEV_ERROR(dev, "Failed to send reset command (%d)\n", ret);
661 		if (dbidev->regulator)
662 			regulator_disable(dbidev->regulator);
663 		return ret;
664 	}
665 
666 	/*
667 	 * If we did a hw reset, we know the controller is in Sleep mode and
668 	 * per MIPI DSC spec should wait 5ms after soft reset. If we didn't,
669 	 * we assume worst case and wait 120ms.
670 	 */
671 	if (dbi->reset)
672 		usleep_range(5000, 20000);
673 	else
674 		msleep(120);
675 
676 	return 0;
677 }
678 
679 /**
680  * mipi_dbi_poweron_reset - MIPI DBI poweron and reset
681  * @dbidev: MIPI DBI device structure
682  *
683  * This function enables the regulator if used and does a hardware and software
684  * reset.
685  *
686  * Returns:
687  * Zero on success, or a negative error code.
688  */
mipi_dbi_poweron_reset(struct mipi_dbi_dev * dbidev)689 int mipi_dbi_poweron_reset(struct mipi_dbi_dev *dbidev)
690 {
691 	return mipi_dbi_poweron_reset_conditional(dbidev, false);
692 }
693 EXPORT_SYMBOL(mipi_dbi_poweron_reset);
694 
695 /**
696  * mipi_dbi_poweron_conditional_reset - MIPI DBI poweron and conditional reset
697  * @dbidev: MIPI DBI device structure
698  *
699  * This function enables the regulator if used and if the display is off, it
700  * does a hardware and software reset. If mipi_dbi_display_is_on() determines
701  * that the display is on, no reset is performed.
702  *
703  * Returns:
704  * Zero if the controller was reset, 1 if the display was already on, or a
705  * negative error code.
706  */
mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev * dbidev)707 int mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev *dbidev)
708 {
709 	return mipi_dbi_poweron_reset_conditional(dbidev, true);
710 }
711 EXPORT_SYMBOL(mipi_dbi_poweron_conditional_reset);
712 
713 #if IS_ENABLED(CONFIG_SPI)
714 
715 /**
716  * mipi_dbi_spi_cmd_max_speed - get the maximum SPI bus speed
717  * @spi: SPI device
718  * @len: The transfer buffer length.
719  *
720  * Many controllers have a max speed of 10MHz, but can be pushed way beyond
721  * that. Increase reliability by running pixel data at max speed and the rest
722  * at 10MHz, preventing transfer glitches from messing up the init settings.
723  */
mipi_dbi_spi_cmd_max_speed(struct spi_device * spi,size_t len)724 u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len)
725 {
726 	if (len > 64)
727 		return 0; /* use default */
728 
729 	return min_t(u32, 10000000, spi->max_speed_hz);
730 }
731 EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed);
732 
mipi_dbi_machine_little_endian(void)733 static bool mipi_dbi_machine_little_endian(void)
734 {
735 #if defined(__LITTLE_ENDIAN)
736 	return true;
737 #else
738 	return false;
739 #endif
740 }
741 
742 /*
743  * MIPI DBI Type C Option 1
744  *
745  * If the SPI controller doesn't have 9 bits per word support,
746  * use blocks of 9 bytes to send 8x 9-bit words using a 8-bit SPI transfer.
747  * Pad partial blocks with MIPI_DCS_NOP (zero).
748  * This is how the D/C bit (x) is added:
749  *     x7654321
750  *     0x765432
751  *     10x76543
752  *     210x7654
753  *     3210x765
754  *     43210x76
755  *     543210x7
756  *     6543210x
757  *     76543210
758  */
759 
mipi_dbi_spi1e_transfer(struct mipi_dbi * dbi,int dc,const void * buf,size_t len,unsigned int bpw)760 static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc,
761 				   const void *buf, size_t len,
762 				   unsigned int bpw)
763 {
764 	bool swap_bytes = (bpw == 16 && mipi_dbi_machine_little_endian());
765 	size_t chunk, max_chunk = dbi->tx_buf9_len;
766 	struct spi_device *spi = dbi->spi;
767 	struct spi_transfer tr = {
768 		.tx_buf = dbi->tx_buf9,
769 		.bits_per_word = 8,
770 	};
771 	struct spi_message m;
772 	const u8 *src = buf;
773 	int i, ret;
774 	u8 *dst;
775 
776 	if (drm_debug_enabled(DRM_UT_DRIVER))
777 		pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
778 			 __func__, dc, max_chunk);
779 
780 	tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
781 	spi_message_init_with_transfers(&m, &tr, 1);
782 
783 	if (!dc) {
784 		if (WARN_ON_ONCE(len != 1))
785 			return -EINVAL;
786 
787 		/* Command: pad no-op's (zeroes) at beginning of block */
788 		dst = dbi->tx_buf9;
789 		memset(dst, 0, 9);
790 		dst[8] = *src;
791 		tr.len = 9;
792 
793 		return spi_sync(spi, &m);
794 	}
795 
796 	/* max with room for adding one bit per byte */
797 	max_chunk = max_chunk / 9 * 8;
798 	/* but no bigger than len */
799 	max_chunk = min(max_chunk, len);
800 	/* 8 byte blocks */
801 	max_chunk = max_t(size_t, 8, max_chunk & ~0x7);
802 
803 	while (len) {
804 		size_t added = 0;
805 
806 		chunk = min(len, max_chunk);
807 		len -= chunk;
808 		dst = dbi->tx_buf9;
809 
810 		if (chunk < 8) {
811 			u8 val, carry = 0;
812 
813 			/* Data: pad no-op's (zeroes) at end of block */
814 			memset(dst, 0, 9);
815 
816 			if (swap_bytes) {
817 				for (i = 1; i < (chunk + 1); i++) {
818 					val = src[1];
819 					*dst++ = carry | BIT(8 - i) | (val >> i);
820 					carry = val << (8 - i);
821 					i++;
822 					val = src[0];
823 					*dst++ = carry | BIT(8 - i) | (val >> i);
824 					carry = val << (8 - i);
825 					src += 2;
826 				}
827 				*dst++ = carry;
828 			} else {
829 				for (i = 1; i < (chunk + 1); i++) {
830 					val = *src++;
831 					*dst++ = carry | BIT(8 - i) | (val >> i);
832 					carry = val << (8 - i);
833 				}
834 				*dst++ = carry;
835 			}
836 
837 			chunk = 8;
838 			added = 1;
839 		} else {
840 			for (i = 0; i < chunk; i += 8) {
841 				if (swap_bytes) {
842 					*dst++ =                 BIT(7) | (src[1] >> 1);
843 					*dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2);
844 					*dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3);
845 					*dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4);
846 					*dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5);
847 					*dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6);
848 					*dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7);
849 					*dst++ = (src[7] << 1) | BIT(0);
850 					*dst++ = src[6];
851 				} else {
852 					*dst++ =                 BIT(7) | (src[0] >> 1);
853 					*dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2);
854 					*dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3);
855 					*dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4);
856 					*dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5);
857 					*dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6);
858 					*dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7);
859 					*dst++ = (src[6] << 1) | BIT(0);
860 					*dst++ = src[7];
861 				}
862 
863 				src += 8;
864 				added++;
865 			}
866 		}
867 
868 		tr.len = chunk + added;
869 
870 		ret = spi_sync(spi, &m);
871 		if (ret)
872 			return ret;
873 	}
874 
875 	return 0;
876 }
877 
mipi_dbi_spi1_transfer(struct mipi_dbi * dbi,int dc,const void * buf,size_t len,unsigned int bpw)878 static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc,
879 				  const void *buf, size_t len,
880 				  unsigned int bpw)
881 {
882 	struct spi_device *spi = dbi->spi;
883 	struct spi_transfer tr = {
884 		.bits_per_word = 9,
885 	};
886 	const u16 *src16 = buf;
887 	const u8 *src8 = buf;
888 	struct spi_message m;
889 	size_t max_chunk;
890 	u16 *dst16;
891 	int ret;
892 
893 	if (!spi_is_bpw_supported(spi, 9))
894 		return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw);
895 
896 	tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
897 	max_chunk = dbi->tx_buf9_len;
898 	dst16 = dbi->tx_buf9;
899 
900 	if (drm_debug_enabled(DRM_UT_DRIVER))
901 		pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
902 			 __func__, dc, max_chunk);
903 
904 	max_chunk = min(max_chunk / 2, len);
905 
906 	spi_message_init_with_transfers(&m, &tr, 1);
907 	tr.tx_buf = dst16;
908 
909 	while (len) {
910 		size_t chunk = min(len, max_chunk);
911 		unsigned int i;
912 
913 		if (bpw == 16 && mipi_dbi_machine_little_endian()) {
914 			for (i = 0; i < (chunk * 2); i += 2) {
915 				dst16[i]     = *src16 >> 8;
916 				dst16[i + 1] = *src16++ & 0xFF;
917 				if (dc) {
918 					dst16[i]     |= 0x0100;
919 					dst16[i + 1] |= 0x0100;
920 				}
921 			}
922 		} else {
923 			for (i = 0; i < chunk; i++) {
924 				dst16[i] = *src8++;
925 				if (dc)
926 					dst16[i] |= 0x0100;
927 			}
928 		}
929 
930 		tr.len = chunk * 2;
931 		len -= chunk;
932 
933 		ret = spi_sync(spi, &m);
934 		if (ret)
935 			return ret;
936 	}
937 
938 	return 0;
939 }
940 
mipi_dbi_typec1_command_read(struct mipi_dbi * dbi,u8 * cmd,u8 * data,size_t len)941 static int mipi_dbi_typec1_command_read(struct mipi_dbi *dbi, u8 *cmd,
942 					u8 *data, size_t len)
943 {
944 	struct spi_device *spi = dbi->spi;
945 	u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED,
946 			     spi->max_speed_hz / 2);
947 	struct spi_transfer tr[2] = {
948 		{
949 			.speed_hz = speed_hz,
950 			.bits_per_word = 9,
951 			.tx_buf = dbi->tx_buf9,
952 			.len = 2,
953 		}, {
954 			.speed_hz = speed_hz,
955 			.bits_per_word = 8,
956 			.len = len,
957 			.rx_buf = data,
958 		},
959 	};
960 	struct spi_message m;
961 	u16 *dst16;
962 	int ret;
963 
964 	if (!len)
965 		return -EINVAL;
966 
967 	if (!spi_is_bpw_supported(spi, 9)) {
968 		/*
969 		 * FIXME: implement something like mipi_dbi_spi1e_transfer() but
970 		 * for reads using emulation.
971 		 */
972 		dev_err(&spi->dev,
973 			"reading on host not supporting 9 bpw not yet implemented\n");
974 		return -EOPNOTSUPP;
975 	}
976 
977 	/*
978 	 * Turn the 8bit command into a 16bit version of the command in the
979 	 * buffer. Only 9 bits of this will be used when executing the actual
980 	 * transfer.
981 	 */
982 	dst16 = dbi->tx_buf9;
983 	dst16[0] = *cmd;
984 
985 	spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr));
986 	ret = spi_sync(spi, &m);
987 
988 	if (!ret)
989 		MIPI_DBI_DEBUG_COMMAND(*cmd, data, len);
990 
991 	return ret;
992 }
993 
mipi_dbi_typec1_command(struct mipi_dbi * dbi,u8 * cmd,u8 * parameters,size_t num)994 static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd,
995 				   u8 *parameters, size_t num)
996 {
997 	unsigned int bpw = (*cmd == MIPI_DCS_WRITE_MEMORY_START) ? 16 : 8;
998 	int ret;
999 
1000 	if (mipi_dbi_command_is_read(dbi, *cmd))
1001 		return mipi_dbi_typec1_command_read(dbi, cmd, parameters, num);
1002 
1003 	MIPI_DBI_DEBUG_COMMAND(*cmd, parameters, num);
1004 
1005 	ret = mipi_dbi_spi1_transfer(dbi, 0, cmd, 1, 8);
1006 	if (ret || !num)
1007 		return ret;
1008 
1009 	return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw);
1010 }
1011 
1012 /* MIPI DBI Type C Option 3 */
1013 
mipi_dbi_typec3_command_read(struct mipi_dbi * dbi,u8 * cmd,u8 * data,size_t len)1014 static int mipi_dbi_typec3_command_read(struct mipi_dbi *dbi, u8 *cmd,
1015 					u8 *data, size_t len)
1016 {
1017 	struct spi_device *spi = dbi->spi;
1018 	u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED,
1019 			     spi->max_speed_hz / 2);
1020 	struct spi_transfer tr[2] = {
1021 		{
1022 			.speed_hz = speed_hz,
1023 			.tx_buf = cmd,
1024 			.len = 1,
1025 		}, {
1026 			.speed_hz = speed_hz,
1027 			.len = len,
1028 		},
1029 	};
1030 	struct spi_message m;
1031 	u8 *buf;
1032 	int ret;
1033 
1034 	if (!len)
1035 		return -EINVAL;
1036 
1037 	/*
1038 	 * Support non-standard 24-bit and 32-bit Nokia read commands which
1039 	 * start with a dummy clock, so we need to read an extra byte.
1040 	 */
1041 	if (*cmd == MIPI_DCS_GET_DISPLAY_ID ||
1042 	    *cmd == MIPI_DCS_GET_DISPLAY_STATUS) {
1043 		if (!(len == 3 || len == 4))
1044 			return -EINVAL;
1045 
1046 		tr[1].len = len + 1;
1047 	}
1048 
1049 	buf = kmalloc(tr[1].len, GFP_KERNEL);
1050 	if (!buf)
1051 		return -ENOMEM;
1052 
1053 	tr[1].rx_buf = buf;
1054 	gpiod_set_value_cansleep(dbi->dc, 0);
1055 
1056 	spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr));
1057 	ret = spi_sync(spi, &m);
1058 	if (ret)
1059 		goto err_free;
1060 
1061 	if (tr[1].len == len) {
1062 		memcpy(data, buf, len);
1063 	} else {
1064 		unsigned int i;
1065 
1066 		for (i = 0; i < len; i++)
1067 			data[i] = (buf[i] << 1) | (buf[i + 1] >> 7);
1068 	}
1069 
1070 	MIPI_DBI_DEBUG_COMMAND(*cmd, data, len);
1071 
1072 err_free:
1073 	kfree(buf);
1074 
1075 	return ret;
1076 }
1077 
mipi_dbi_typec3_command(struct mipi_dbi * dbi,u8 * cmd,u8 * par,size_t num)1078 static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd,
1079 				   u8 *par, size_t num)
1080 {
1081 	struct spi_device *spi = dbi->spi;
1082 	unsigned int bpw = 8;
1083 	u32 speed_hz;
1084 	int ret;
1085 
1086 	if (mipi_dbi_command_is_read(dbi, *cmd))
1087 		return mipi_dbi_typec3_command_read(dbi, cmd, par, num);
1088 
1089 	MIPI_DBI_DEBUG_COMMAND(*cmd, par, num);
1090 
1091 	gpiod_set_value_cansleep(dbi->dc, 0);
1092 	speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1);
1093 	ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, cmd, 1);
1094 	if (ret || !num)
1095 		return ret;
1096 
1097 	if (*cmd == MIPI_DCS_WRITE_MEMORY_START && !dbi->swap_bytes)
1098 		bpw = 16;
1099 
1100 	gpiod_set_value_cansleep(dbi->dc, 1);
1101 	speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num);
1102 
1103 	return mipi_dbi_spi_transfer(spi, speed_hz, bpw, par, num);
1104 }
1105 
1106 /**
1107  * mipi_dbi_spi_init - Initialize MIPI DBI SPI interface
1108  * @spi: SPI device
1109  * @dbi: MIPI DBI structure to initialize
1110  * @dc: D/C gpio (optional)
1111  *
1112  * This function sets &mipi_dbi->command, enables &mipi_dbi->read_commands for the
1113  * usual read commands. It should be followed by a call to mipi_dbi_dev_init() or
1114  * a driver-specific init.
1115  *
1116  * If @dc is set, a Type C Option 3 interface is assumed, if not
1117  * Type C Option 1.
1118  *
1119  * If the SPI master driver doesn't support the necessary bits per word,
1120  * the following transformation is used:
1121  *
1122  * - 9-bit: reorder buffer as 9x 8-bit words, padded with no-op command.
1123  * - 16-bit: if big endian send as 8-bit, if little endian swap bytes
1124  *
1125  * Returns:
1126  * Zero on success, negative error code on failure.
1127  */
mipi_dbi_spi_init(struct spi_device * spi,struct mipi_dbi * dbi,struct gpio_desc * dc)1128 int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi,
1129 		      struct gpio_desc *dc)
1130 {
1131 	struct device *dev = &spi->dev;
1132 	int ret;
1133 
1134 	/*
1135 	 * Even though it's not the SPI device that does DMA (the master does),
1136 	 * the dma mask is necessary for the dma_alloc_wc() in the GEM code
1137 	 * (e.g., drm_gem_cma_create()). The dma_addr returned will be a physical
1138 	 * address which might be different from the bus address, but this is
1139 	 * not a problem since the address will not be used.
1140 	 * The virtual address is used in the transfer and the SPI core
1141 	 * re-maps it on the SPI master device using the DMA streaming API
1142 	 * (spi_map_buf()).
1143 	 */
1144 	if (!dev->coherent_dma_mask) {
1145 		ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
1146 		if (ret) {
1147 			dev_warn(dev, "Failed to set dma mask %d\n", ret);
1148 			return ret;
1149 		}
1150 	}
1151 
1152 	dbi->spi = spi;
1153 	dbi->read_commands = mipi_dbi_dcs_read_commands;
1154 
1155 	if (dc) {
1156 		dbi->command = mipi_dbi_typec3_command;
1157 		dbi->dc = dc;
1158 		if (mipi_dbi_machine_little_endian() && !spi_is_bpw_supported(spi, 16))
1159 			dbi->swap_bytes = true;
1160 	} else {
1161 		dbi->command = mipi_dbi_typec1_command;
1162 		dbi->tx_buf9_len = SZ_16K;
1163 		dbi->tx_buf9 = devm_kmalloc(dev, dbi->tx_buf9_len, GFP_KERNEL);
1164 		if (!dbi->tx_buf9)
1165 			return -ENOMEM;
1166 	}
1167 
1168 	mutex_init(&dbi->cmdlock);
1169 
1170 	DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000);
1171 
1172 	return 0;
1173 }
1174 EXPORT_SYMBOL(mipi_dbi_spi_init);
1175 
1176 /**
1177  * mipi_dbi_spi_transfer - SPI transfer helper
1178  * @spi: SPI device
1179  * @speed_hz: Override speed (optional)
1180  * @bpw: Bits per word
1181  * @buf: Buffer to transfer
1182  * @len: Buffer length
1183  *
1184  * This SPI transfer helper breaks up the transfer of @buf into chunks which
1185  * the SPI controller driver can handle.
1186  *
1187  * Returns:
1188  * Zero on success, negative error code on failure.
1189  */
mipi_dbi_spi_transfer(struct spi_device * spi,u32 speed_hz,u8 bpw,const void * buf,size_t len)1190 int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz,
1191 			  u8 bpw, const void *buf, size_t len)
1192 {
1193 	size_t max_chunk = spi_max_transfer_size(spi);
1194 	struct spi_transfer tr = {
1195 		.bits_per_word = bpw,
1196 		.speed_hz = speed_hz,
1197 	};
1198 	struct spi_message m;
1199 	size_t chunk;
1200 	int ret;
1201 
1202 	/* In __spi_validate, there's a validation that no partial transfers
1203 	 * are accepted (xfer->len % w_size must be zero).
1204 	 * Here we align max_chunk to multiple of 2 (16bits),
1205 	 * to prevent transfers from being rejected.
1206 	 */
1207 	max_chunk = ALIGN_DOWN(max_chunk, 2);
1208 
1209 	spi_message_init_with_transfers(&m, &tr, 1);
1210 
1211 	while (len) {
1212 		chunk = min(len, max_chunk);
1213 
1214 		tr.tx_buf = buf;
1215 		tr.len = chunk;
1216 		buf += chunk;
1217 		len -= chunk;
1218 
1219 		ret = spi_sync(spi, &m);
1220 		if (ret)
1221 			return ret;
1222 	}
1223 
1224 	return 0;
1225 }
1226 EXPORT_SYMBOL(mipi_dbi_spi_transfer);
1227 
1228 #endif /* CONFIG_SPI */
1229 
1230 #ifdef CONFIG_DEBUG_FS
1231 
mipi_dbi_debugfs_command_write(struct file * file,const char __user * ubuf,size_t count,loff_t * ppos)1232 static ssize_t mipi_dbi_debugfs_command_write(struct file *file,
1233 					      const char __user *ubuf,
1234 					      size_t count, loff_t *ppos)
1235 {
1236 	struct seq_file *m = file->private_data;
1237 	struct mipi_dbi_dev *dbidev = m->private;
1238 	u8 val, cmd = 0, parameters[64];
1239 	char *buf, *pos, *token;
1240 	int i, ret, idx;
1241 
1242 	if (!drm_dev_enter(&dbidev->drm, &idx))
1243 		return -ENODEV;
1244 
1245 	buf = memdup_user_nul(ubuf, count);
1246 	if (IS_ERR(buf)) {
1247 		ret = PTR_ERR(buf);
1248 		goto err_exit;
1249 	}
1250 
1251 	/* strip trailing whitespace */
1252 	for (i = count - 1; i > 0; i--)
1253 		if (isspace(buf[i]))
1254 			buf[i] = '\0';
1255 		else
1256 			break;
1257 	i = 0;
1258 	pos = buf;
1259 	while (pos) {
1260 		token = strsep(&pos, " ");
1261 		if (!token) {
1262 			ret = -EINVAL;
1263 			goto err_free;
1264 		}
1265 
1266 		ret = kstrtou8(token, 16, &val);
1267 		if (ret < 0)
1268 			goto err_free;
1269 
1270 		if (token == buf)
1271 			cmd = val;
1272 		else
1273 			parameters[i++] = val;
1274 
1275 		if (i == 64) {
1276 			ret = -E2BIG;
1277 			goto err_free;
1278 		}
1279 	}
1280 
1281 	ret = mipi_dbi_command_buf(&dbidev->dbi, cmd, parameters, i);
1282 
1283 err_free:
1284 	kfree(buf);
1285 err_exit:
1286 	drm_dev_exit(idx);
1287 
1288 	return ret < 0 ? ret : count;
1289 }
1290 
mipi_dbi_debugfs_command_show(struct seq_file * m,void * unused)1291 static int mipi_dbi_debugfs_command_show(struct seq_file *m, void *unused)
1292 {
1293 	struct mipi_dbi_dev *dbidev = m->private;
1294 	struct mipi_dbi *dbi = &dbidev->dbi;
1295 	u8 cmd, val[4];
1296 	int ret, idx;
1297 	size_t len;
1298 
1299 	if (!drm_dev_enter(&dbidev->drm, &idx))
1300 		return -ENODEV;
1301 
1302 	for (cmd = 0; cmd < 255; cmd++) {
1303 		if (!mipi_dbi_command_is_read(dbi, cmd))
1304 			continue;
1305 
1306 		switch (cmd) {
1307 		case MIPI_DCS_READ_MEMORY_START:
1308 		case MIPI_DCS_READ_MEMORY_CONTINUE:
1309 			len = 2;
1310 			break;
1311 		case MIPI_DCS_GET_DISPLAY_ID:
1312 			len = 3;
1313 			break;
1314 		case MIPI_DCS_GET_DISPLAY_STATUS:
1315 			len = 4;
1316 			break;
1317 		default:
1318 			len = 1;
1319 			break;
1320 		}
1321 
1322 		seq_printf(m, "%02x: ", cmd);
1323 		ret = mipi_dbi_command_buf(dbi, cmd, val, len);
1324 		if (ret) {
1325 			seq_puts(m, "XX\n");
1326 			continue;
1327 		}
1328 		seq_printf(m, "%*phN\n", (int)len, val);
1329 	}
1330 
1331 	drm_dev_exit(idx);
1332 
1333 	return 0;
1334 }
1335 
mipi_dbi_debugfs_command_open(struct inode * inode,struct file * file)1336 static int mipi_dbi_debugfs_command_open(struct inode *inode,
1337 					 struct file *file)
1338 {
1339 	return single_open(file, mipi_dbi_debugfs_command_show,
1340 			   inode->i_private);
1341 }
1342 
1343 static const struct file_operations mipi_dbi_debugfs_command_fops = {
1344 	.owner = THIS_MODULE,
1345 	.open = mipi_dbi_debugfs_command_open,
1346 	.read = seq_read,
1347 	.llseek = seq_lseek,
1348 	.release = single_release,
1349 	.write = mipi_dbi_debugfs_command_write,
1350 };
1351 
1352 /**
1353  * mipi_dbi_debugfs_init - Create debugfs entries
1354  * @minor: DRM minor
1355  *
1356  * This function creates a 'command' debugfs file for sending commands to the
1357  * controller or getting the read command values.
1358  * Drivers can use this as their &drm_driver->debugfs_init callback.
1359  *
1360  */
mipi_dbi_debugfs_init(struct drm_minor * minor)1361 void mipi_dbi_debugfs_init(struct drm_minor *minor)
1362 {
1363 	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(minor->dev);
1364 	umode_t mode = S_IFREG | S_IWUSR;
1365 
1366 	if (dbidev->dbi.read_commands)
1367 		mode |= S_IRUGO;
1368 	debugfs_create_file("command", mode, minor->debugfs_root, dbidev,
1369 			    &mipi_dbi_debugfs_command_fops);
1370 }
1371 EXPORT_SYMBOL(mipi_dbi_debugfs_init);
1372 
1373 #endif
1374 
1375 MODULE_LICENSE("GPL");
1376