1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,lpass.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 mmc1 = &sdhc_1; 54 mmc2 = &sdhc_2; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 clock-frequency = <76800000>; 77 #clock-cells = <0>; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 reserved-memory { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 92 wlan_ce_mem: memory@4cd000 { 93 no-map; 94 reg = <0x0 0x004cd000 0x0 0x1000>; 95 }; 96 97 hyp_mem: memory@80000000 { 98 reg = <0x0 0x80000000 0x0 0x600000>; 99 no-map; 100 }; 101 102 xbl_mem: memory@80600000 { 103 reg = <0x0 0x80600000 0x0 0x200000>; 104 no-map; 105 }; 106 107 aop_mem: memory@80800000 { 108 reg = <0x0 0x80800000 0x0 0x60000>; 109 no-map; 110 }; 111 112 aop_cmd_db_mem: memory@80860000 { 113 reg = <0x0 0x80860000 0x0 0x20000>; 114 compatible = "qcom,cmd-db"; 115 no-map; 116 }; 117 118 reserved_xbl_uefi_log: memory@80880000 { 119 reg = <0x0 0x80884000 0x0 0x10000>; 120 no-map; 121 }; 122 123 sec_apps_mem: memory@808ff000 { 124 reg = <0x0 0x808ff000 0x0 0x1000>; 125 no-map; 126 }; 127 128 smem_mem: memory@80900000 { 129 reg = <0x0 0x80900000 0x0 0x200000>; 130 no-map; 131 }; 132 133 cpucp_mem: memory@80b00000 { 134 no-map; 135 reg = <0x0 0x80b00000 0x0 0x100000>; 136 }; 137 138 wlan_fw_mem: memory@80c00000 { 139 reg = <0x0 0x80c00000 0x0 0xc00000>; 140 no-map; 141 }; 142 143 video_mem: memory@8b200000 { 144 reg = <0x0 0x8b200000 0x0 0x500000>; 145 no-map; 146 }; 147 148 ipa_fw_mem: memory@8b700000 { 149 reg = <0 0x8b700000 0 0x10000>; 150 no-map; 151 }; 152 153 rmtfs_mem: memory@9c900000 { 154 compatible = "qcom,rmtfs-mem"; 155 reg = <0x0 0x9c900000 0x0 0x280000>; 156 no-map; 157 158 qcom,client-id = <1>; 159 qcom,vmid = <15>; 160 }; 161 }; 162 163 cpus { 164 #address-cells = <2>; 165 #size-cells = <0>; 166 167 CPU0: cpu@0 { 168 device_type = "cpu"; 169 compatible = "arm,kryo"; 170 reg = <0x0 0x0>; 171 enable-method = "psci"; 172 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 173 &LITTLE_CPU_SLEEP_1 174 &CLUSTER_SLEEP_0>; 175 next-level-cache = <&L2_0>; 176 operating-points-v2 = <&cpu0_opp_table>; 177 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 178 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 179 qcom,freq-domain = <&cpufreq_hw 0>; 180 #cooling-cells = <2>; 181 L2_0: l2-cache { 182 compatible = "cache"; 183 next-level-cache = <&L3_0>; 184 L3_0: l3-cache { 185 compatible = "cache"; 186 }; 187 }; 188 }; 189 190 CPU1: cpu@100 { 191 device_type = "cpu"; 192 compatible = "arm,kryo"; 193 reg = <0x0 0x100>; 194 enable-method = "psci"; 195 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 196 &LITTLE_CPU_SLEEP_1 197 &CLUSTER_SLEEP_0>; 198 next-level-cache = <&L2_100>; 199 operating-points-v2 = <&cpu0_opp_table>; 200 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 201 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 202 qcom,freq-domain = <&cpufreq_hw 0>; 203 #cooling-cells = <2>; 204 L2_100: l2-cache { 205 compatible = "cache"; 206 next-level-cache = <&L3_0>; 207 }; 208 }; 209 210 CPU2: cpu@200 { 211 device_type = "cpu"; 212 compatible = "arm,kryo"; 213 reg = <0x0 0x200>; 214 enable-method = "psci"; 215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 216 &LITTLE_CPU_SLEEP_1 217 &CLUSTER_SLEEP_0>; 218 next-level-cache = <&L2_200>; 219 operating-points-v2 = <&cpu0_opp_table>; 220 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 221 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 222 qcom,freq-domain = <&cpufreq_hw 0>; 223 #cooling-cells = <2>; 224 L2_200: l2-cache { 225 compatible = "cache"; 226 next-level-cache = <&L3_0>; 227 }; 228 }; 229 230 CPU3: cpu@300 { 231 device_type = "cpu"; 232 compatible = "arm,kryo"; 233 reg = <0x0 0x300>; 234 enable-method = "psci"; 235 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 236 &LITTLE_CPU_SLEEP_1 237 &CLUSTER_SLEEP_0>; 238 next-level-cache = <&L2_300>; 239 operating-points-v2 = <&cpu0_opp_table>; 240 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 241 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 242 qcom,freq-domain = <&cpufreq_hw 0>; 243 #cooling-cells = <2>; 244 L2_300: l2-cache { 245 compatible = "cache"; 246 next-level-cache = <&L3_0>; 247 }; 248 }; 249 250 CPU4: cpu@400 { 251 device_type = "cpu"; 252 compatible = "arm,kryo"; 253 reg = <0x0 0x400>; 254 enable-method = "psci"; 255 cpu-idle-states = <&BIG_CPU_SLEEP_0 256 &BIG_CPU_SLEEP_1 257 &CLUSTER_SLEEP_0>; 258 next-level-cache = <&L2_400>; 259 operating-points-v2 = <&cpu4_opp_table>; 260 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 261 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 262 qcom,freq-domain = <&cpufreq_hw 1>; 263 #cooling-cells = <2>; 264 L2_400: l2-cache { 265 compatible = "cache"; 266 next-level-cache = <&L3_0>; 267 }; 268 }; 269 270 CPU5: cpu@500 { 271 device_type = "cpu"; 272 compatible = "arm,kryo"; 273 reg = <0x0 0x500>; 274 enable-method = "psci"; 275 cpu-idle-states = <&BIG_CPU_SLEEP_0 276 &BIG_CPU_SLEEP_1 277 &CLUSTER_SLEEP_0>; 278 next-level-cache = <&L2_500>; 279 operating-points-v2 = <&cpu4_opp_table>; 280 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 281 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 282 qcom,freq-domain = <&cpufreq_hw 1>; 283 #cooling-cells = <2>; 284 L2_500: l2-cache { 285 compatible = "cache"; 286 next-level-cache = <&L3_0>; 287 }; 288 }; 289 290 CPU6: cpu@600 { 291 device_type = "cpu"; 292 compatible = "arm,kryo"; 293 reg = <0x0 0x600>; 294 enable-method = "psci"; 295 cpu-idle-states = <&BIG_CPU_SLEEP_0 296 &BIG_CPU_SLEEP_1 297 &CLUSTER_SLEEP_0>; 298 next-level-cache = <&L2_600>; 299 operating-points-v2 = <&cpu4_opp_table>; 300 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 301 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 302 qcom,freq-domain = <&cpufreq_hw 1>; 303 #cooling-cells = <2>; 304 L2_600: l2-cache { 305 compatible = "cache"; 306 next-level-cache = <&L3_0>; 307 }; 308 }; 309 310 CPU7: cpu@700 { 311 device_type = "cpu"; 312 compatible = "arm,kryo"; 313 reg = <0x0 0x700>; 314 enable-method = "psci"; 315 cpu-idle-states = <&BIG_CPU_SLEEP_0 316 &BIG_CPU_SLEEP_1 317 &CLUSTER_SLEEP_0>; 318 next-level-cache = <&L2_700>; 319 operating-points-v2 = <&cpu7_opp_table>; 320 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 321 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 322 qcom,freq-domain = <&cpufreq_hw 2>; 323 #cooling-cells = <2>; 324 L2_700: l2-cache { 325 compatible = "cache"; 326 next-level-cache = <&L3_0>; 327 }; 328 }; 329 330 cpu-map { 331 cluster0 { 332 core0 { 333 cpu = <&CPU0>; 334 }; 335 336 core1 { 337 cpu = <&CPU1>; 338 }; 339 340 core2 { 341 cpu = <&CPU2>; 342 }; 343 344 core3 { 345 cpu = <&CPU3>; 346 }; 347 348 core4 { 349 cpu = <&CPU4>; 350 }; 351 352 core5 { 353 cpu = <&CPU5>; 354 }; 355 356 core6 { 357 cpu = <&CPU6>; 358 }; 359 360 core7 { 361 cpu = <&CPU7>; 362 }; 363 }; 364 }; 365 366 idle-states { 367 entry-method = "psci"; 368 369 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 370 compatible = "arm,idle-state"; 371 idle-state-name = "little-power-down"; 372 arm,psci-suspend-param = <0x40000003>; 373 entry-latency-us = <549>; 374 exit-latency-us = <901>; 375 min-residency-us = <1774>; 376 local-timer-stop; 377 }; 378 379 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 380 compatible = "arm,idle-state"; 381 idle-state-name = "little-rail-power-down"; 382 arm,psci-suspend-param = <0x40000004>; 383 entry-latency-us = <702>; 384 exit-latency-us = <915>; 385 min-residency-us = <4001>; 386 local-timer-stop; 387 }; 388 389 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 390 compatible = "arm,idle-state"; 391 idle-state-name = "big-power-down"; 392 arm,psci-suspend-param = <0x40000003>; 393 entry-latency-us = <523>; 394 exit-latency-us = <1244>; 395 min-residency-us = <2207>; 396 local-timer-stop; 397 }; 398 399 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 400 compatible = "arm,idle-state"; 401 idle-state-name = "big-rail-power-down"; 402 arm,psci-suspend-param = <0x40000004>; 403 entry-latency-us = <526>; 404 exit-latency-us = <1854>; 405 min-residency-us = <5555>; 406 local-timer-stop; 407 }; 408 409 CLUSTER_SLEEP_0: cluster-sleep-0 { 410 compatible = "arm,idle-state"; 411 idle-state-name = "cluster-power-down"; 412 arm,psci-suspend-param = <0x40003444>; 413 entry-latency-us = <3263>; 414 exit-latency-us = <6562>; 415 min-residency-us = <9926>; 416 local-timer-stop; 417 }; 418 }; 419 }; 420 421 cpu0_opp_table: opp-table-cpu0 { 422 compatible = "operating-points-v2"; 423 opp-shared; 424 425 cpu0_opp_300mhz: opp-300000000 { 426 opp-hz = /bits/ 64 <300000000>; 427 opp-peak-kBps = <800000 9600000>; 428 }; 429 430 cpu0_opp_691mhz: opp-691200000 { 431 opp-hz = /bits/ 64 <691200000>; 432 opp-peak-kBps = <800000 17817600>; 433 }; 434 435 cpu0_opp_806mhz: opp-806400000 { 436 opp-hz = /bits/ 64 <806400000>; 437 opp-peak-kBps = <800000 20889600>; 438 }; 439 440 cpu0_opp_941mhz: opp-940800000 { 441 opp-hz = /bits/ 64 <940800000>; 442 opp-peak-kBps = <1804000 24576000>; 443 }; 444 445 cpu0_opp_1152mhz: opp-1152000000 { 446 opp-hz = /bits/ 64 <1152000000>; 447 opp-peak-kBps = <2188000 27033600>; 448 }; 449 450 cpu0_opp_1325mhz: opp-1324800000 { 451 opp-hz = /bits/ 64 <1324800000>; 452 opp-peak-kBps = <2188000 33792000>; 453 }; 454 455 cpu0_opp_1517mhz: opp-1516800000 { 456 opp-hz = /bits/ 64 <1516800000>; 457 opp-peak-kBps = <3072000 38092800>; 458 }; 459 460 cpu0_opp_1651mhz: opp-1651200000 { 461 opp-hz = /bits/ 64 <1651200000>; 462 opp-peak-kBps = <3072000 41779200>; 463 }; 464 465 cpu0_opp_1805mhz: opp-1804800000 { 466 opp-hz = /bits/ 64 <1804800000>; 467 opp-peak-kBps = <4068000 48537600>; 468 }; 469 470 cpu0_opp_1958mhz: opp-1958400000 { 471 opp-hz = /bits/ 64 <1958400000>; 472 opp-peak-kBps = <4068000 48537600>; 473 }; 474 475 cpu0_opp_2016mhz: opp-2016000000 { 476 opp-hz = /bits/ 64 <2016000000>; 477 opp-peak-kBps = <6220000 48537600>; 478 }; 479 }; 480 481 cpu4_opp_table: opp-table-cpu4 { 482 compatible = "operating-points-v2"; 483 opp-shared; 484 485 cpu4_opp_691mhz: opp-691200000 { 486 opp-hz = /bits/ 64 <691200000>; 487 opp-peak-kBps = <1804000 9600000>; 488 }; 489 490 cpu4_opp_941mhz: opp-940800000 { 491 opp-hz = /bits/ 64 <940800000>; 492 opp-peak-kBps = <2188000 17817600>; 493 }; 494 495 cpu4_opp_1229mhz: opp-1228800000 { 496 opp-hz = /bits/ 64 <1228800000>; 497 opp-peak-kBps = <4068000 24576000>; 498 }; 499 500 cpu4_opp_1344mhz: opp-1344000000 { 501 opp-hz = /bits/ 64 <1344000000>; 502 opp-peak-kBps = <4068000 24576000>; 503 }; 504 505 cpu4_opp_1517mhz: opp-1516800000 { 506 opp-hz = /bits/ 64 <1516800000>; 507 opp-peak-kBps = <4068000 24576000>; 508 }; 509 510 cpu4_opp_1651mhz: opp-1651200000 { 511 opp-hz = /bits/ 64 <1651200000>; 512 opp-peak-kBps = <6220000 38092800>; 513 }; 514 515 cpu4_opp_1901mhz: opp-1900800000 { 516 opp-hz = /bits/ 64 <1900800000>; 517 opp-peak-kBps = <6220000 44851200>; 518 }; 519 520 cpu4_opp_2054mhz: opp-2054400000 { 521 opp-hz = /bits/ 64 <2054400000>; 522 opp-peak-kBps = <6220000 44851200>; 523 }; 524 525 cpu4_opp_2112mhz: opp-2112000000 { 526 opp-hz = /bits/ 64 <2112000000>; 527 opp-peak-kBps = <6220000 44851200>; 528 }; 529 530 cpu4_opp_2131mhz: opp-2131200000 { 531 opp-hz = /bits/ 64 <2131200000>; 532 opp-peak-kBps = <6220000 44851200>; 533 }; 534 535 cpu4_opp_2208mhz: opp-2208000000 { 536 opp-hz = /bits/ 64 <2208000000>; 537 opp-peak-kBps = <6220000 44851200>; 538 }; 539 540 cpu4_opp_2400mhz: opp-2400000000 { 541 opp-hz = /bits/ 64 <2400000000>; 542 opp-peak-kBps = <8532000 48537600>; 543 }; 544 545 cpu4_opp_2611mhz: opp-2611200000 { 546 opp-hz = /bits/ 64 <2611200000>; 547 opp-peak-kBps = <8532000 48537600>; 548 }; 549 }; 550 551 cpu7_opp_table: opp-table-cpu7 { 552 compatible = "operating-points-v2"; 553 opp-shared; 554 555 cpu7_opp_806mhz: opp-806400000 { 556 opp-hz = /bits/ 64 <806400000>; 557 opp-peak-kBps = <1804000 9600000>; 558 }; 559 560 cpu7_opp_1056mhz: opp-1056000000 { 561 opp-hz = /bits/ 64 <1056000000>; 562 opp-peak-kBps = <2188000 17817600>; 563 }; 564 565 cpu7_opp_1325mhz: opp-1324800000 { 566 opp-hz = /bits/ 64 <1324800000>; 567 opp-peak-kBps = <4068000 24576000>; 568 }; 569 570 cpu7_opp_1517mhz: opp-1516800000 { 571 opp-hz = /bits/ 64 <1516800000>; 572 opp-peak-kBps = <4068000 24576000>; 573 }; 574 575 cpu7_opp_1766mhz: opp-1766400000 { 576 opp-hz = /bits/ 64 <1766400000>; 577 opp-peak-kBps = <6220000 38092800>; 578 }; 579 580 cpu7_opp_1862mhz: opp-1862400000 { 581 opp-hz = /bits/ 64 <1862400000>; 582 opp-peak-kBps = <6220000 38092800>; 583 }; 584 585 cpu7_opp_2035mhz: opp-2035200000 { 586 opp-hz = /bits/ 64 <2035200000>; 587 opp-peak-kBps = <6220000 38092800>; 588 }; 589 590 cpu7_opp_2112mhz: opp-2112000000 { 591 opp-hz = /bits/ 64 <2112000000>; 592 opp-peak-kBps = <6220000 44851200>; 593 }; 594 595 cpu7_opp_2208mhz: opp-2208000000 { 596 opp-hz = /bits/ 64 <2208000000>; 597 opp-peak-kBps = <6220000 44851200>; 598 }; 599 600 cpu7_opp_2381mhz: opp-2380800000 { 601 opp-hz = /bits/ 64 <2380800000>; 602 opp-peak-kBps = <6832000 44851200>; 603 }; 604 605 cpu7_opp_2400mhz: opp-2400000000 { 606 opp-hz = /bits/ 64 <2400000000>; 607 opp-peak-kBps = <8532000 48537600>; 608 }; 609 610 cpu7_opp_2515mhz: opp-2515200000 { 611 opp-hz = /bits/ 64 <2515200000>; 612 opp-peak-kBps = <8532000 48537600>; 613 }; 614 615 cpu7_opp_2707mhz: opp-2707200000 { 616 opp-hz = /bits/ 64 <2707200000>; 617 opp-peak-kBps = <8532000 48537600>; 618 }; 619 620 cpu7_opp_3014mhz: opp-3014400000 { 621 opp-hz = /bits/ 64 <3014400000>; 622 opp-peak-kBps = <8532000 48537600>; 623 }; 624 }; 625 626 memory@80000000 { 627 device_type = "memory"; 628 /* We expect the bootloader to fill in the size */ 629 reg = <0 0x80000000 0 0>; 630 }; 631 632 firmware { 633 scm { 634 compatible = "qcom,scm-sc7280", "qcom,scm"; 635 }; 636 }; 637 638 clk_virt: interconnect { 639 compatible = "qcom,sc7280-clk-virt"; 640 #interconnect-cells = <2>; 641 qcom,bcm-voters = <&apps_bcm_voter>; 642 }; 643 644 smem { 645 compatible = "qcom,smem"; 646 memory-region = <&smem_mem>; 647 hwlocks = <&tcsr_mutex 3>; 648 }; 649 650 smp2p-adsp { 651 compatible = "qcom,smp2p"; 652 qcom,smem = <443>, <429>; 653 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 654 IPCC_MPROC_SIGNAL_SMP2P 655 IRQ_TYPE_EDGE_RISING>; 656 mboxes = <&ipcc IPCC_CLIENT_LPASS 657 IPCC_MPROC_SIGNAL_SMP2P>; 658 659 qcom,local-pid = <0>; 660 qcom,remote-pid = <2>; 661 662 adsp_smp2p_out: master-kernel { 663 qcom,entry-name = "master-kernel"; 664 #qcom,smem-state-cells = <1>; 665 }; 666 667 adsp_smp2p_in: slave-kernel { 668 qcom,entry-name = "slave-kernel"; 669 interrupt-controller; 670 #interrupt-cells = <2>; 671 }; 672 }; 673 674 smp2p-cdsp { 675 compatible = "qcom,smp2p"; 676 qcom,smem = <94>, <432>; 677 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 678 IPCC_MPROC_SIGNAL_SMP2P 679 IRQ_TYPE_EDGE_RISING>; 680 mboxes = <&ipcc IPCC_CLIENT_CDSP 681 IPCC_MPROC_SIGNAL_SMP2P>; 682 683 qcom,local-pid = <0>; 684 qcom,remote-pid = <5>; 685 686 cdsp_smp2p_out: master-kernel { 687 qcom,entry-name = "master-kernel"; 688 #qcom,smem-state-cells = <1>; 689 }; 690 691 cdsp_smp2p_in: slave-kernel { 692 qcom,entry-name = "slave-kernel"; 693 interrupt-controller; 694 #interrupt-cells = <2>; 695 }; 696 }; 697 698 smp2p-mpss { 699 compatible = "qcom,smp2p"; 700 qcom,smem = <435>, <428>; 701 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 702 IPCC_MPROC_SIGNAL_SMP2P 703 IRQ_TYPE_EDGE_RISING>; 704 mboxes = <&ipcc IPCC_CLIENT_MPSS 705 IPCC_MPROC_SIGNAL_SMP2P>; 706 707 qcom,local-pid = <0>; 708 qcom,remote-pid = <1>; 709 710 modem_smp2p_out: master-kernel { 711 qcom,entry-name = "master-kernel"; 712 #qcom,smem-state-cells = <1>; 713 }; 714 715 modem_smp2p_in: slave-kernel { 716 qcom,entry-name = "slave-kernel"; 717 interrupt-controller; 718 #interrupt-cells = <2>; 719 }; 720 721 ipa_smp2p_out: ipa-ap-to-modem { 722 qcom,entry-name = "ipa"; 723 #qcom,smem-state-cells = <1>; 724 }; 725 726 ipa_smp2p_in: ipa-modem-to-ap { 727 qcom,entry-name = "ipa"; 728 interrupt-controller; 729 #interrupt-cells = <2>; 730 }; 731 }; 732 733 smp2p-wpss { 734 compatible = "qcom,smp2p"; 735 qcom,smem = <617>, <616>; 736 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 737 IPCC_MPROC_SIGNAL_SMP2P 738 IRQ_TYPE_EDGE_RISING>; 739 mboxes = <&ipcc IPCC_CLIENT_WPSS 740 IPCC_MPROC_SIGNAL_SMP2P>; 741 742 qcom,local-pid = <0>; 743 qcom,remote-pid = <13>; 744 745 wpss_smp2p_out: master-kernel { 746 qcom,entry-name = "master-kernel"; 747 #qcom,smem-state-cells = <1>; 748 }; 749 750 wpss_smp2p_in: slave-kernel { 751 qcom,entry-name = "slave-kernel"; 752 interrupt-controller; 753 #interrupt-cells = <2>; 754 }; 755 }; 756 757 pmu { 758 compatible = "arm,armv8-pmuv3"; 759 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 760 }; 761 762 psci { 763 compatible = "arm,psci-1.0"; 764 method = "smc"; 765 }; 766 767 qspi_opp_table: opp-table-qspi { 768 compatible = "operating-points-v2"; 769 770 opp-75000000 { 771 opp-hz = /bits/ 64 <75000000>; 772 required-opps = <&rpmhpd_opp_low_svs>; 773 }; 774 775 opp-150000000 { 776 opp-hz = /bits/ 64 <150000000>; 777 required-opps = <&rpmhpd_opp_svs>; 778 }; 779 780 opp-200000000 { 781 opp-hz = /bits/ 64 <200000000>; 782 required-opps = <&rpmhpd_opp_svs_l1>; 783 }; 784 785 opp-300000000 { 786 opp-hz = /bits/ 64 <300000000>; 787 required-opps = <&rpmhpd_opp_nom>; 788 }; 789 }; 790 791 qup_opp_table: opp-table-qup { 792 compatible = "operating-points-v2"; 793 794 opp-75000000 { 795 opp-hz = /bits/ 64 <75000000>; 796 required-opps = <&rpmhpd_opp_low_svs>; 797 }; 798 799 opp-100000000 { 800 opp-hz = /bits/ 64 <100000000>; 801 required-opps = <&rpmhpd_opp_svs>; 802 }; 803 804 opp-128000000 { 805 opp-hz = /bits/ 64 <128000000>; 806 required-opps = <&rpmhpd_opp_nom>; 807 }; 808 }; 809 810 soc: soc@0 { 811 #address-cells = <2>; 812 #size-cells = <2>; 813 ranges = <0 0 0 0 0x10 0>; 814 dma-ranges = <0 0 0 0 0x10 0>; 815 compatible = "simple-bus"; 816 817 gcc: clock-controller@100000 { 818 compatible = "qcom,gcc-sc7280"; 819 reg = <0 0x00100000 0 0x1f0000>; 820 clocks = <&rpmhcc RPMH_CXO_CLK>, 821 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 822 <0>, <&pcie1_lane>, 823 <0>, <0>, <0>, <0>; 824 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 825 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 826 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 827 "ufs_phy_tx_symbol_0_clk", 828 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 829 #clock-cells = <1>; 830 #reset-cells = <1>; 831 #power-domain-cells = <1>; 832 power-domains = <&rpmhpd SC7280_CX>; 833 }; 834 835 ipcc: mailbox@408000 { 836 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 837 reg = <0 0x00408000 0 0x1000>; 838 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 839 interrupt-controller; 840 #interrupt-cells = <3>; 841 #mbox-cells = <2>; 842 }; 843 844 qfprom: efuse@784000 { 845 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 846 reg = <0 0x00784000 0 0xa20>, 847 <0 0x00780000 0 0xa20>, 848 <0 0x00782000 0 0x120>, 849 <0 0x00786000 0 0x1fff>; 850 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 851 clock-names = "core"; 852 power-domains = <&rpmhpd SC7280_MX>; 853 #address-cells = <1>; 854 #size-cells = <1>; 855 856 gpu_speed_bin: gpu_speed_bin@1e9 { 857 reg = <0x1e9 0x2>; 858 bits = <5 8>; 859 }; 860 }; 861 862 sdhc_1: mmc@7c4000 { 863 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 864 pinctrl-names = "default", "sleep"; 865 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 866 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 867 status = "disabled"; 868 869 reg = <0 0x007c4000 0 0x1000>, 870 <0 0x007c5000 0 0x1000>; 871 reg-names = "hc", "cqhci"; 872 873 iommus = <&apps_smmu 0xc0 0x0>; 874 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 876 interrupt-names = "hc_irq", "pwr_irq"; 877 878 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 879 <&gcc GCC_SDCC1_APPS_CLK>, 880 <&rpmhcc RPMH_CXO_CLK>; 881 clock-names = "iface", "core", "xo"; 882 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 883 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 884 interconnect-names = "sdhc-ddr","cpu-sdhc"; 885 power-domains = <&rpmhpd SC7280_CX>; 886 operating-points-v2 = <&sdhc1_opp_table>; 887 888 bus-width = <8>; 889 supports-cqe; 890 891 qcom,dll-config = <0x0007642c>; 892 qcom,ddr-config = <0x80040868>; 893 894 mmc-ddr-1_8v; 895 mmc-hs200-1_8v; 896 mmc-hs400-1_8v; 897 mmc-hs400-enhanced-strobe; 898 899 resets = <&gcc GCC_SDCC1_BCR>; 900 901 sdhc1_opp_table: opp-table { 902 compatible = "operating-points-v2"; 903 904 opp-100000000 { 905 opp-hz = /bits/ 64 <100000000>; 906 required-opps = <&rpmhpd_opp_low_svs>; 907 opp-peak-kBps = <1800000 400000>; 908 opp-avg-kBps = <100000 0>; 909 }; 910 911 opp-384000000 { 912 opp-hz = /bits/ 64 <384000000>; 913 required-opps = <&rpmhpd_opp_nom>; 914 opp-peak-kBps = <5400000 1600000>; 915 opp-avg-kBps = <390000 0>; 916 }; 917 }; 918 919 }; 920 921 gpi_dma0: dma-controller@900000 { 922 #dma-cells = <3>; 923 compatible = "qcom,sc7280-gpi-dma"; 924 reg = <0 0x00900000 0 0x60000>; 925 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 937 dma-channels = <12>; 938 dma-channel-mask = <0x7f>; 939 iommus = <&apps_smmu 0x0136 0x0>; 940 status = "disabled"; 941 }; 942 943 qupv3_id_0: geniqup@9c0000 { 944 compatible = "qcom,geni-se-qup"; 945 reg = <0 0x009c0000 0 0x2000>; 946 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 947 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 948 clock-names = "m-ahb", "s-ahb"; 949 #address-cells = <2>; 950 #size-cells = <2>; 951 ranges; 952 iommus = <&apps_smmu 0x123 0x0>; 953 status = "disabled"; 954 955 i2c0: i2c@980000 { 956 compatible = "qcom,geni-i2c"; 957 reg = <0 0x00980000 0 0x4000>; 958 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 959 clock-names = "se"; 960 pinctrl-names = "default"; 961 pinctrl-0 = <&qup_i2c0_data_clk>; 962 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 963 #address-cells = <1>; 964 #size-cells = <0>; 965 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 966 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 967 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 968 interconnect-names = "qup-core", "qup-config", 969 "qup-memory"; 970 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 971 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 972 dma-names = "tx", "rx"; 973 status = "disabled"; 974 }; 975 976 spi0: spi@980000 { 977 compatible = "qcom,geni-spi"; 978 reg = <0 0x00980000 0 0x4000>; 979 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 980 clock-names = "se"; 981 pinctrl-names = "default"; 982 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 983 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 power-domains = <&rpmhpd SC7280_CX>; 987 operating-points-v2 = <&qup_opp_table>; 988 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 989 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 990 interconnect-names = "qup-core", "qup-config"; 991 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 992 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 993 dma-names = "tx", "rx"; 994 status = "disabled"; 995 }; 996 997 uart0: serial@980000 { 998 compatible = "qcom,geni-uart"; 999 reg = <0 0x00980000 0 0x4000>; 1000 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1001 clock-names = "se"; 1002 pinctrl-names = "default"; 1003 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1004 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1005 power-domains = <&rpmhpd SC7280_CX>; 1006 operating-points-v2 = <&qup_opp_table>; 1007 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1008 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1009 interconnect-names = "qup-core", "qup-config"; 1010 status = "disabled"; 1011 }; 1012 1013 i2c1: i2c@984000 { 1014 compatible = "qcom,geni-i2c"; 1015 reg = <0 0x00984000 0 0x4000>; 1016 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1017 clock-names = "se"; 1018 pinctrl-names = "default"; 1019 pinctrl-0 = <&qup_i2c1_data_clk>; 1020 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1021 #address-cells = <1>; 1022 #size-cells = <0>; 1023 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1024 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1025 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1026 interconnect-names = "qup-core", "qup-config", 1027 "qup-memory"; 1028 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1029 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1030 dma-names = "tx", "rx"; 1031 status = "disabled"; 1032 }; 1033 1034 spi1: spi@984000 { 1035 compatible = "qcom,geni-spi"; 1036 reg = <0 0x00984000 0 0x4000>; 1037 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1038 clock-names = "se"; 1039 pinctrl-names = "default"; 1040 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1041 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 power-domains = <&rpmhpd SC7280_CX>; 1045 operating-points-v2 = <&qup_opp_table>; 1046 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1047 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1048 interconnect-names = "qup-core", "qup-config"; 1049 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1050 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1051 dma-names = "tx", "rx"; 1052 status = "disabled"; 1053 }; 1054 1055 uart1: serial@984000 { 1056 compatible = "qcom,geni-uart"; 1057 reg = <0 0x00984000 0 0x4000>; 1058 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1059 clock-names = "se"; 1060 pinctrl-names = "default"; 1061 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1062 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1063 power-domains = <&rpmhpd SC7280_CX>; 1064 operating-points-v2 = <&qup_opp_table>; 1065 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1066 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1067 interconnect-names = "qup-core", "qup-config"; 1068 status = "disabled"; 1069 }; 1070 1071 i2c2: i2c@988000 { 1072 compatible = "qcom,geni-i2c"; 1073 reg = <0 0x00988000 0 0x4000>; 1074 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1075 clock-names = "se"; 1076 pinctrl-names = "default"; 1077 pinctrl-0 = <&qup_i2c2_data_clk>; 1078 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1082 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1083 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1084 interconnect-names = "qup-core", "qup-config", 1085 "qup-memory"; 1086 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1087 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1088 dma-names = "tx", "rx"; 1089 status = "disabled"; 1090 }; 1091 1092 spi2: spi@988000 { 1093 compatible = "qcom,geni-spi"; 1094 reg = <0 0x00988000 0 0x4000>; 1095 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1096 clock-names = "se"; 1097 pinctrl-names = "default"; 1098 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1099 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1100 #address-cells = <1>; 1101 #size-cells = <0>; 1102 power-domains = <&rpmhpd SC7280_CX>; 1103 operating-points-v2 = <&qup_opp_table>; 1104 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1105 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1106 interconnect-names = "qup-core", "qup-config"; 1107 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1108 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1109 dma-names = "tx", "rx"; 1110 status = "disabled"; 1111 }; 1112 1113 uart2: serial@988000 { 1114 compatible = "qcom,geni-uart"; 1115 reg = <0 0x00988000 0 0x4000>; 1116 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1117 clock-names = "se"; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1120 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1121 power-domains = <&rpmhpd SC7280_CX>; 1122 operating-points-v2 = <&qup_opp_table>; 1123 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1124 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1125 interconnect-names = "qup-core", "qup-config"; 1126 status = "disabled"; 1127 }; 1128 1129 i2c3: i2c@98c000 { 1130 compatible = "qcom,geni-i2c"; 1131 reg = <0 0x0098c000 0 0x4000>; 1132 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1133 clock-names = "se"; 1134 pinctrl-names = "default"; 1135 pinctrl-0 = <&qup_i2c3_data_clk>; 1136 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1140 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1141 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1142 interconnect-names = "qup-core", "qup-config", 1143 "qup-memory"; 1144 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1145 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1146 dma-names = "tx", "rx"; 1147 status = "disabled"; 1148 }; 1149 1150 spi3: spi@98c000 { 1151 compatible = "qcom,geni-spi"; 1152 reg = <0 0x0098c000 0 0x4000>; 1153 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1154 clock-names = "se"; 1155 pinctrl-names = "default"; 1156 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1157 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 power-domains = <&rpmhpd SC7280_CX>; 1161 operating-points-v2 = <&qup_opp_table>; 1162 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1163 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1164 interconnect-names = "qup-core", "qup-config"; 1165 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1166 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1167 dma-names = "tx", "rx"; 1168 status = "disabled"; 1169 }; 1170 1171 uart3: serial@98c000 { 1172 compatible = "qcom,geni-uart"; 1173 reg = <0 0x0098c000 0 0x4000>; 1174 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1175 clock-names = "se"; 1176 pinctrl-names = "default"; 1177 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1178 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1179 power-domains = <&rpmhpd SC7280_CX>; 1180 operating-points-v2 = <&qup_opp_table>; 1181 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1182 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1183 interconnect-names = "qup-core", "qup-config"; 1184 status = "disabled"; 1185 }; 1186 1187 i2c4: i2c@990000 { 1188 compatible = "qcom,geni-i2c"; 1189 reg = <0 0x00990000 0 0x4000>; 1190 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1191 clock-names = "se"; 1192 pinctrl-names = "default"; 1193 pinctrl-0 = <&qup_i2c4_data_clk>; 1194 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1198 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1199 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1200 interconnect-names = "qup-core", "qup-config", 1201 "qup-memory"; 1202 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1203 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1204 dma-names = "tx", "rx"; 1205 status = "disabled"; 1206 }; 1207 1208 spi4: spi@990000 { 1209 compatible = "qcom,geni-spi"; 1210 reg = <0 0x00990000 0 0x4000>; 1211 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1212 clock-names = "se"; 1213 pinctrl-names = "default"; 1214 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1215 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1216 #address-cells = <1>; 1217 #size-cells = <0>; 1218 power-domains = <&rpmhpd SC7280_CX>; 1219 operating-points-v2 = <&qup_opp_table>; 1220 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1221 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1222 interconnect-names = "qup-core", "qup-config"; 1223 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1224 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1225 dma-names = "tx", "rx"; 1226 status = "disabled"; 1227 }; 1228 1229 uart4: serial@990000 { 1230 compatible = "qcom,geni-uart"; 1231 reg = <0 0x00990000 0 0x4000>; 1232 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1233 clock-names = "se"; 1234 pinctrl-names = "default"; 1235 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1236 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1237 power-domains = <&rpmhpd SC7280_CX>; 1238 operating-points-v2 = <&qup_opp_table>; 1239 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1240 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1241 interconnect-names = "qup-core", "qup-config"; 1242 status = "disabled"; 1243 }; 1244 1245 i2c5: i2c@994000 { 1246 compatible = "qcom,geni-i2c"; 1247 reg = <0 0x00994000 0 0x4000>; 1248 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1249 clock-names = "se"; 1250 pinctrl-names = "default"; 1251 pinctrl-0 = <&qup_i2c5_data_clk>; 1252 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1253 #address-cells = <1>; 1254 #size-cells = <0>; 1255 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1256 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1257 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1258 interconnect-names = "qup-core", "qup-config", 1259 "qup-memory"; 1260 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1261 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1262 dma-names = "tx", "rx"; 1263 status = "disabled"; 1264 }; 1265 1266 spi5: spi@994000 { 1267 compatible = "qcom,geni-spi"; 1268 reg = <0 0x00994000 0 0x4000>; 1269 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1270 clock-names = "se"; 1271 pinctrl-names = "default"; 1272 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1273 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 power-domains = <&rpmhpd SC7280_CX>; 1277 operating-points-v2 = <&qup_opp_table>; 1278 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1279 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1280 interconnect-names = "qup-core", "qup-config"; 1281 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1282 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1283 dma-names = "tx", "rx"; 1284 status = "disabled"; 1285 }; 1286 1287 uart5: serial@994000 { 1288 compatible = "qcom,geni-uart"; 1289 reg = <0 0x00994000 0 0x4000>; 1290 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1291 clock-names = "se"; 1292 pinctrl-names = "default"; 1293 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1294 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1295 power-domains = <&rpmhpd SC7280_CX>; 1296 operating-points-v2 = <&qup_opp_table>; 1297 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1298 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1299 interconnect-names = "qup-core", "qup-config"; 1300 status = "disabled"; 1301 }; 1302 1303 i2c6: i2c@998000 { 1304 compatible = "qcom,geni-i2c"; 1305 reg = <0 0x00998000 0 0x4000>; 1306 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1307 clock-names = "se"; 1308 pinctrl-names = "default"; 1309 pinctrl-0 = <&qup_i2c6_data_clk>; 1310 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1314 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1315 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1316 interconnect-names = "qup-core", "qup-config", 1317 "qup-memory"; 1318 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1319 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1320 dma-names = "tx", "rx"; 1321 status = "disabled"; 1322 }; 1323 1324 spi6: spi@998000 { 1325 compatible = "qcom,geni-spi"; 1326 reg = <0 0x00998000 0 0x4000>; 1327 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1328 clock-names = "se"; 1329 pinctrl-names = "default"; 1330 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1331 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1332 #address-cells = <1>; 1333 #size-cells = <0>; 1334 power-domains = <&rpmhpd SC7280_CX>; 1335 operating-points-v2 = <&qup_opp_table>; 1336 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1337 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1338 interconnect-names = "qup-core", "qup-config"; 1339 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1340 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1341 dma-names = "tx", "rx"; 1342 status = "disabled"; 1343 }; 1344 1345 uart6: serial@998000 { 1346 compatible = "qcom,geni-uart"; 1347 reg = <0 0x00998000 0 0x4000>; 1348 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1349 clock-names = "se"; 1350 pinctrl-names = "default"; 1351 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1352 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1353 power-domains = <&rpmhpd SC7280_CX>; 1354 operating-points-v2 = <&qup_opp_table>; 1355 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1356 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1357 interconnect-names = "qup-core", "qup-config"; 1358 status = "disabled"; 1359 }; 1360 1361 i2c7: i2c@99c000 { 1362 compatible = "qcom,geni-i2c"; 1363 reg = <0 0x0099c000 0 0x4000>; 1364 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1365 clock-names = "se"; 1366 pinctrl-names = "default"; 1367 pinctrl-0 = <&qup_i2c7_data_clk>; 1368 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1369 #address-cells = <1>; 1370 #size-cells = <0>; 1371 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1372 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1373 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1374 interconnect-names = "qup-core", "qup-config", 1375 "qup-memory"; 1376 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1377 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1378 dma-names = "tx", "rx"; 1379 status = "disabled"; 1380 }; 1381 1382 spi7: spi@99c000 { 1383 compatible = "qcom,geni-spi"; 1384 reg = <0 0x0099c000 0 0x4000>; 1385 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1386 clock-names = "se"; 1387 pinctrl-names = "default"; 1388 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1389 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1390 #address-cells = <1>; 1391 #size-cells = <0>; 1392 power-domains = <&rpmhpd SC7280_CX>; 1393 operating-points-v2 = <&qup_opp_table>; 1394 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1395 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1396 interconnect-names = "qup-core", "qup-config"; 1397 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1398 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1399 dma-names = "tx", "rx"; 1400 status = "disabled"; 1401 }; 1402 1403 uart7: serial@99c000 { 1404 compatible = "qcom,geni-uart"; 1405 reg = <0 0x0099c000 0 0x4000>; 1406 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1407 clock-names = "se"; 1408 pinctrl-names = "default"; 1409 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1410 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1411 power-domains = <&rpmhpd SC7280_CX>; 1412 operating-points-v2 = <&qup_opp_table>; 1413 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1414 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1415 interconnect-names = "qup-core", "qup-config"; 1416 status = "disabled"; 1417 }; 1418 }; 1419 1420 gpi_dma1: dma-controller@a00000 { 1421 #dma-cells = <3>; 1422 compatible = "qcom,sc7280-gpi-dma"; 1423 reg = <0 0x00a00000 0 0x60000>; 1424 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1436 dma-channels = <12>; 1437 dma-channel-mask = <0x1e>; 1438 iommus = <&apps_smmu 0x56 0x0>; 1439 status = "disabled"; 1440 }; 1441 1442 qupv3_id_1: geniqup@ac0000 { 1443 compatible = "qcom,geni-se-qup"; 1444 reg = <0 0x00ac0000 0 0x2000>; 1445 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1446 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1447 clock-names = "m-ahb", "s-ahb"; 1448 #address-cells = <2>; 1449 #size-cells = <2>; 1450 ranges; 1451 iommus = <&apps_smmu 0x43 0x0>; 1452 status = "disabled"; 1453 1454 i2c8: i2c@a80000 { 1455 compatible = "qcom,geni-i2c"; 1456 reg = <0 0x00a80000 0 0x4000>; 1457 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1458 clock-names = "se"; 1459 pinctrl-names = "default"; 1460 pinctrl-0 = <&qup_i2c8_data_clk>; 1461 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1462 #address-cells = <1>; 1463 #size-cells = <0>; 1464 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1465 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1466 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1467 interconnect-names = "qup-core", "qup-config", 1468 "qup-memory"; 1469 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1470 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1471 dma-names = "tx", "rx"; 1472 status = "disabled"; 1473 }; 1474 1475 spi8: spi@a80000 { 1476 compatible = "qcom,geni-spi"; 1477 reg = <0 0x00a80000 0 0x4000>; 1478 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1479 clock-names = "se"; 1480 pinctrl-names = "default"; 1481 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1482 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 power-domains = <&rpmhpd SC7280_CX>; 1486 operating-points-v2 = <&qup_opp_table>; 1487 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1488 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1489 interconnect-names = "qup-core", "qup-config"; 1490 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1491 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1492 dma-names = "tx", "rx"; 1493 status = "disabled"; 1494 }; 1495 1496 uart8: serial@a80000 { 1497 compatible = "qcom,geni-uart"; 1498 reg = <0 0x00a80000 0 0x4000>; 1499 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1500 clock-names = "se"; 1501 pinctrl-names = "default"; 1502 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1503 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1504 power-domains = <&rpmhpd SC7280_CX>; 1505 operating-points-v2 = <&qup_opp_table>; 1506 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1507 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1508 interconnect-names = "qup-core", "qup-config"; 1509 status = "disabled"; 1510 }; 1511 1512 i2c9: i2c@a84000 { 1513 compatible = "qcom,geni-i2c"; 1514 reg = <0 0x00a84000 0 0x4000>; 1515 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1516 clock-names = "se"; 1517 pinctrl-names = "default"; 1518 pinctrl-0 = <&qup_i2c9_data_clk>; 1519 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1520 #address-cells = <1>; 1521 #size-cells = <0>; 1522 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1523 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1524 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1525 interconnect-names = "qup-core", "qup-config", 1526 "qup-memory"; 1527 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1528 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1529 dma-names = "tx", "rx"; 1530 status = "disabled"; 1531 }; 1532 1533 spi9: spi@a84000 { 1534 compatible = "qcom,geni-spi"; 1535 reg = <0 0x00a84000 0 0x4000>; 1536 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1537 clock-names = "se"; 1538 pinctrl-names = "default"; 1539 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1540 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1541 #address-cells = <1>; 1542 #size-cells = <0>; 1543 power-domains = <&rpmhpd SC7280_CX>; 1544 operating-points-v2 = <&qup_opp_table>; 1545 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1546 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1547 interconnect-names = "qup-core", "qup-config"; 1548 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1549 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1550 dma-names = "tx", "rx"; 1551 status = "disabled"; 1552 }; 1553 1554 uart9: serial@a84000 { 1555 compatible = "qcom,geni-uart"; 1556 reg = <0 0x00a84000 0 0x4000>; 1557 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1558 clock-names = "se"; 1559 pinctrl-names = "default"; 1560 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1561 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1562 power-domains = <&rpmhpd SC7280_CX>; 1563 operating-points-v2 = <&qup_opp_table>; 1564 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1565 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1566 interconnect-names = "qup-core", "qup-config"; 1567 status = "disabled"; 1568 }; 1569 1570 i2c10: i2c@a88000 { 1571 compatible = "qcom,geni-i2c"; 1572 reg = <0 0x00a88000 0 0x4000>; 1573 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1574 clock-names = "se"; 1575 pinctrl-names = "default"; 1576 pinctrl-0 = <&qup_i2c10_data_clk>; 1577 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1578 #address-cells = <1>; 1579 #size-cells = <0>; 1580 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1581 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1582 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1583 interconnect-names = "qup-core", "qup-config", 1584 "qup-memory"; 1585 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1586 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1587 dma-names = "tx", "rx"; 1588 status = "disabled"; 1589 }; 1590 1591 spi10: spi@a88000 { 1592 compatible = "qcom,geni-spi"; 1593 reg = <0 0x00a88000 0 0x4000>; 1594 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1595 clock-names = "se"; 1596 pinctrl-names = "default"; 1597 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1598 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 power-domains = <&rpmhpd SC7280_CX>; 1602 operating-points-v2 = <&qup_opp_table>; 1603 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1604 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1605 interconnect-names = "qup-core", "qup-config"; 1606 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1607 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1608 dma-names = "tx", "rx"; 1609 status = "disabled"; 1610 }; 1611 1612 uart10: serial@a88000 { 1613 compatible = "qcom,geni-uart"; 1614 reg = <0 0x00a88000 0 0x4000>; 1615 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1616 clock-names = "se"; 1617 pinctrl-names = "default"; 1618 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1619 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1620 power-domains = <&rpmhpd SC7280_CX>; 1621 operating-points-v2 = <&qup_opp_table>; 1622 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1623 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1624 interconnect-names = "qup-core", "qup-config"; 1625 status = "disabled"; 1626 }; 1627 1628 i2c11: i2c@a8c000 { 1629 compatible = "qcom,geni-i2c"; 1630 reg = <0 0x00a8c000 0 0x4000>; 1631 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1632 clock-names = "se"; 1633 pinctrl-names = "default"; 1634 pinctrl-0 = <&qup_i2c11_data_clk>; 1635 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1636 #address-cells = <1>; 1637 #size-cells = <0>; 1638 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1639 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1640 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1641 interconnect-names = "qup-core", "qup-config", 1642 "qup-memory"; 1643 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1644 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1645 dma-names = "tx", "rx"; 1646 status = "disabled"; 1647 }; 1648 1649 spi11: spi@a8c000 { 1650 compatible = "qcom,geni-spi"; 1651 reg = <0 0x00a8c000 0 0x4000>; 1652 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1653 clock-names = "se"; 1654 pinctrl-names = "default"; 1655 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1656 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1657 #address-cells = <1>; 1658 #size-cells = <0>; 1659 power-domains = <&rpmhpd SC7280_CX>; 1660 operating-points-v2 = <&qup_opp_table>; 1661 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1662 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1663 interconnect-names = "qup-core", "qup-config"; 1664 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1665 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1666 dma-names = "tx", "rx"; 1667 status = "disabled"; 1668 }; 1669 1670 uart11: serial@a8c000 { 1671 compatible = "qcom,geni-uart"; 1672 reg = <0 0x00a8c000 0 0x4000>; 1673 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1674 clock-names = "se"; 1675 pinctrl-names = "default"; 1676 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1677 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1678 power-domains = <&rpmhpd SC7280_CX>; 1679 operating-points-v2 = <&qup_opp_table>; 1680 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1681 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1682 interconnect-names = "qup-core", "qup-config"; 1683 status = "disabled"; 1684 }; 1685 1686 i2c12: i2c@a90000 { 1687 compatible = "qcom,geni-i2c"; 1688 reg = <0 0x00a90000 0 0x4000>; 1689 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1690 clock-names = "se"; 1691 pinctrl-names = "default"; 1692 pinctrl-0 = <&qup_i2c12_data_clk>; 1693 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1694 #address-cells = <1>; 1695 #size-cells = <0>; 1696 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1697 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1698 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1699 interconnect-names = "qup-core", "qup-config", 1700 "qup-memory"; 1701 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1702 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1703 dma-names = "tx", "rx"; 1704 status = "disabled"; 1705 }; 1706 1707 spi12: spi@a90000 { 1708 compatible = "qcom,geni-spi"; 1709 reg = <0 0x00a90000 0 0x4000>; 1710 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1711 clock-names = "se"; 1712 pinctrl-names = "default"; 1713 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1714 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1715 #address-cells = <1>; 1716 #size-cells = <0>; 1717 power-domains = <&rpmhpd SC7280_CX>; 1718 operating-points-v2 = <&qup_opp_table>; 1719 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1720 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1721 interconnect-names = "qup-core", "qup-config"; 1722 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1723 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1724 dma-names = "tx", "rx"; 1725 status = "disabled"; 1726 }; 1727 1728 uart12: serial@a90000 { 1729 compatible = "qcom,geni-uart"; 1730 reg = <0 0x00a90000 0 0x4000>; 1731 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1732 clock-names = "se"; 1733 pinctrl-names = "default"; 1734 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1735 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1736 power-domains = <&rpmhpd SC7280_CX>; 1737 operating-points-v2 = <&qup_opp_table>; 1738 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1739 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1740 interconnect-names = "qup-core", "qup-config"; 1741 status = "disabled"; 1742 }; 1743 1744 i2c13: i2c@a94000 { 1745 compatible = "qcom,geni-i2c"; 1746 reg = <0 0x00a94000 0 0x4000>; 1747 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1748 clock-names = "se"; 1749 pinctrl-names = "default"; 1750 pinctrl-0 = <&qup_i2c13_data_clk>; 1751 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1752 #address-cells = <1>; 1753 #size-cells = <0>; 1754 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1755 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1756 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1757 interconnect-names = "qup-core", "qup-config", 1758 "qup-memory"; 1759 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1760 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1761 dma-names = "tx", "rx"; 1762 status = "disabled"; 1763 }; 1764 1765 spi13: spi@a94000 { 1766 compatible = "qcom,geni-spi"; 1767 reg = <0 0x00a94000 0 0x4000>; 1768 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1769 clock-names = "se"; 1770 pinctrl-names = "default"; 1771 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1772 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1773 #address-cells = <1>; 1774 #size-cells = <0>; 1775 power-domains = <&rpmhpd SC7280_CX>; 1776 operating-points-v2 = <&qup_opp_table>; 1777 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1778 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1779 interconnect-names = "qup-core", "qup-config"; 1780 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1781 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1782 dma-names = "tx", "rx"; 1783 status = "disabled"; 1784 }; 1785 1786 uart13: serial@a94000 { 1787 compatible = "qcom,geni-uart"; 1788 reg = <0 0x00a94000 0 0x4000>; 1789 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1790 clock-names = "se"; 1791 pinctrl-names = "default"; 1792 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1793 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1794 power-domains = <&rpmhpd SC7280_CX>; 1795 operating-points-v2 = <&qup_opp_table>; 1796 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1797 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1798 interconnect-names = "qup-core", "qup-config"; 1799 status = "disabled"; 1800 }; 1801 1802 i2c14: i2c@a98000 { 1803 compatible = "qcom,geni-i2c"; 1804 reg = <0 0x00a98000 0 0x4000>; 1805 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1806 clock-names = "se"; 1807 pinctrl-names = "default"; 1808 pinctrl-0 = <&qup_i2c14_data_clk>; 1809 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1810 #address-cells = <1>; 1811 #size-cells = <0>; 1812 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1813 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1814 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1815 interconnect-names = "qup-core", "qup-config", 1816 "qup-memory"; 1817 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1818 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1819 dma-names = "tx", "rx"; 1820 status = "disabled"; 1821 }; 1822 1823 spi14: spi@a98000 { 1824 compatible = "qcom,geni-spi"; 1825 reg = <0 0x00a98000 0 0x4000>; 1826 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1827 clock-names = "se"; 1828 pinctrl-names = "default"; 1829 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1830 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1831 #address-cells = <1>; 1832 #size-cells = <0>; 1833 power-domains = <&rpmhpd SC7280_CX>; 1834 operating-points-v2 = <&qup_opp_table>; 1835 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1836 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1837 interconnect-names = "qup-core", "qup-config"; 1838 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1839 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1840 dma-names = "tx", "rx"; 1841 status = "disabled"; 1842 }; 1843 1844 uart14: serial@a98000 { 1845 compatible = "qcom,geni-uart"; 1846 reg = <0 0x00a98000 0 0x4000>; 1847 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1848 clock-names = "se"; 1849 pinctrl-names = "default"; 1850 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1851 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1852 power-domains = <&rpmhpd SC7280_CX>; 1853 operating-points-v2 = <&qup_opp_table>; 1854 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1855 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1856 interconnect-names = "qup-core", "qup-config"; 1857 status = "disabled"; 1858 }; 1859 1860 i2c15: i2c@a9c000 { 1861 compatible = "qcom,geni-i2c"; 1862 reg = <0 0x00a9c000 0 0x4000>; 1863 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1864 clock-names = "se"; 1865 pinctrl-names = "default"; 1866 pinctrl-0 = <&qup_i2c15_data_clk>; 1867 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1868 #address-cells = <1>; 1869 #size-cells = <0>; 1870 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1871 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1872 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1873 interconnect-names = "qup-core", "qup-config", 1874 "qup-memory"; 1875 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1876 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1877 dma-names = "tx", "rx"; 1878 status = "disabled"; 1879 }; 1880 1881 spi15: spi@a9c000 { 1882 compatible = "qcom,geni-spi"; 1883 reg = <0 0x00a9c000 0 0x4000>; 1884 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1885 clock-names = "se"; 1886 pinctrl-names = "default"; 1887 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1888 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1889 #address-cells = <1>; 1890 #size-cells = <0>; 1891 power-domains = <&rpmhpd SC7280_CX>; 1892 operating-points-v2 = <&qup_opp_table>; 1893 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1894 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1895 interconnect-names = "qup-core", "qup-config"; 1896 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1897 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1898 dma-names = "tx", "rx"; 1899 status = "disabled"; 1900 }; 1901 1902 uart15: serial@a9c000 { 1903 compatible = "qcom,geni-uart"; 1904 reg = <0 0x00a9c000 0 0x4000>; 1905 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1906 clock-names = "se"; 1907 pinctrl-names = "default"; 1908 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1909 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1910 power-domains = <&rpmhpd SC7280_CX>; 1911 operating-points-v2 = <&qup_opp_table>; 1912 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1913 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1914 interconnect-names = "qup-core", "qup-config"; 1915 status = "disabled"; 1916 }; 1917 }; 1918 1919 cnoc2: interconnect@1500000 { 1920 reg = <0 0x01500000 0 0x1000>; 1921 compatible = "qcom,sc7280-cnoc2"; 1922 #interconnect-cells = <2>; 1923 qcom,bcm-voters = <&apps_bcm_voter>; 1924 }; 1925 1926 cnoc3: interconnect@1502000 { 1927 reg = <0 0x01502000 0 0x1000>; 1928 compatible = "qcom,sc7280-cnoc3"; 1929 #interconnect-cells = <2>; 1930 qcom,bcm-voters = <&apps_bcm_voter>; 1931 }; 1932 1933 mc_virt: interconnect@1580000 { 1934 reg = <0 0x01580000 0 0x4>; 1935 compatible = "qcom,sc7280-mc-virt"; 1936 #interconnect-cells = <2>; 1937 qcom,bcm-voters = <&apps_bcm_voter>; 1938 }; 1939 1940 system_noc: interconnect@1680000 { 1941 reg = <0 0x01680000 0 0x15480>; 1942 compatible = "qcom,sc7280-system-noc"; 1943 #interconnect-cells = <2>; 1944 qcom,bcm-voters = <&apps_bcm_voter>; 1945 }; 1946 1947 aggre1_noc: interconnect@16e0000 { 1948 compatible = "qcom,sc7280-aggre1-noc"; 1949 reg = <0 0x016e0000 0 0x1c080>; 1950 #interconnect-cells = <2>; 1951 qcom,bcm-voters = <&apps_bcm_voter>; 1952 }; 1953 1954 aggre2_noc: interconnect@1700000 { 1955 reg = <0 0x01700000 0 0x2b080>; 1956 compatible = "qcom,sc7280-aggre2-noc"; 1957 #interconnect-cells = <2>; 1958 qcom,bcm-voters = <&apps_bcm_voter>; 1959 }; 1960 1961 mmss_noc: interconnect@1740000 { 1962 reg = <0 0x01740000 0 0x1e080>; 1963 compatible = "qcom,sc7280-mmss-noc"; 1964 #interconnect-cells = <2>; 1965 qcom,bcm-voters = <&apps_bcm_voter>; 1966 }; 1967 1968 wifi: wifi@17a10040 { 1969 compatible = "qcom,wcn6750-wifi"; 1970 reg = <0 0x17a10040 0 0x0>; 1971 iommus = <&apps_smmu 0x1c00 0x1>; 1972 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 1973 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 1974 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 1975 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 1976 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 1977 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 1978 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 1979 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 1980 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 1981 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 1982 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 1983 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 1984 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 1985 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 1986 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 1987 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 1988 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 1989 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 1990 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 1991 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 1992 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 1993 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 1994 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 1995 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 1996 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 1997 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 1998 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 1999 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2000 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2001 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2002 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2003 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2004 qcom,rproc = <&remoteproc_wpss>; 2005 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2006 status = "disabled"; 2007 }; 2008 2009 pcie1: pci@1c08000 { 2010 compatible = "qcom,pcie-sc7280"; 2011 reg = <0 0x01c08000 0 0x3000>, 2012 <0 0x40000000 0 0xf1d>, 2013 <0 0x40000f20 0 0xa8>, 2014 <0 0x40001000 0 0x1000>, 2015 <0 0x40100000 0 0x100000>; 2016 2017 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2018 device_type = "pci"; 2019 linux,pci-domain = <1>; 2020 bus-range = <0x00 0xff>; 2021 num-lanes = <2>; 2022 2023 #address-cells = <3>; 2024 #size-cells = <2>; 2025 2026 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 2027 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2028 2029 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2030 interrupt-names = "msi"; 2031 #interrupt-cells = <1>; 2032 interrupt-map-mask = <0 0 0 0x7>; 2033 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2034 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2035 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2036 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2037 2038 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2039 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2040 <&pcie1_lane>, 2041 <&rpmhcc RPMH_CXO_CLK>, 2042 <&gcc GCC_PCIE_1_AUX_CLK>, 2043 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2044 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2045 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2046 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2047 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2048 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2049 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2050 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2051 2052 clock-names = "pipe", 2053 "pipe_mux", 2054 "phy_pipe", 2055 "ref", 2056 "aux", 2057 "cfg", 2058 "bus_master", 2059 "bus_slave", 2060 "slave_q2a", 2061 "tbu", 2062 "ddrss_sf_tbu", 2063 "aggre0", 2064 "aggre1"; 2065 2066 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2067 assigned-clock-rates = <19200000>; 2068 2069 resets = <&gcc GCC_PCIE_1_BCR>; 2070 reset-names = "pci"; 2071 2072 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2073 2074 phys = <&pcie1_lane>; 2075 phy-names = "pciephy"; 2076 2077 pinctrl-names = "default"; 2078 pinctrl-0 = <&pcie1_clkreq_n>; 2079 2080 iommus = <&apps_smmu 0x1c80 0x1>; 2081 2082 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2083 <0x100 &apps_smmu 0x1c81 0x1>; 2084 2085 status = "disabled"; 2086 }; 2087 2088 pcie1_phy: phy@1c0e000 { 2089 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2090 reg = <0 0x01c0e000 0 0x1c0>; 2091 #address-cells = <2>; 2092 #size-cells = <2>; 2093 ranges; 2094 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2095 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2096 <&gcc GCC_PCIE_CLKREF_EN>, 2097 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2098 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2099 2100 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2101 reset-names = "phy"; 2102 2103 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2104 assigned-clock-rates = <100000000>; 2105 2106 status = "disabled"; 2107 2108 pcie1_lane: phy@1c0e200 { 2109 reg = <0 0x01c0e200 0 0x170>, 2110 <0 0x01c0e400 0 0x200>, 2111 <0 0x01c0ea00 0 0x1f0>, 2112 <0 0x01c0e600 0 0x170>, 2113 <0 0x01c0e800 0 0x200>, 2114 <0 0x01c0ee00 0 0xf4>; 2115 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2116 clock-names = "pipe0"; 2117 2118 #phy-cells = <0>; 2119 #clock-cells = <0>; 2120 clock-output-names = "pcie_1_pipe_clk"; 2121 }; 2122 }; 2123 2124 ipa: ipa@1e40000 { 2125 compatible = "qcom,sc7280-ipa"; 2126 2127 iommus = <&apps_smmu 0x480 0x0>, 2128 <&apps_smmu 0x482 0x0>; 2129 reg = <0 0x1e40000 0 0x8000>, 2130 <0 0x1e50000 0 0x4ad0>, 2131 <0 0x1e04000 0 0x23000>; 2132 reg-names = "ipa-reg", 2133 "ipa-shared", 2134 "gsi"; 2135 2136 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2137 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2138 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2139 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2140 interrupt-names = "ipa", 2141 "gsi", 2142 "ipa-clock-query", 2143 "ipa-setup-ready"; 2144 2145 clocks = <&rpmhcc RPMH_IPA_CLK>; 2146 clock-names = "core"; 2147 2148 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2149 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2150 interconnect-names = "memory", 2151 "config"; 2152 2153 qcom,qmp = <&aoss_qmp>; 2154 2155 qcom,smem-states = <&ipa_smp2p_out 0>, 2156 <&ipa_smp2p_out 1>; 2157 qcom,smem-state-names = "ipa-clock-enabled-valid", 2158 "ipa-clock-enabled"; 2159 2160 status = "disabled"; 2161 }; 2162 2163 tcsr_mutex: hwlock@1f40000 { 2164 compatible = "qcom,tcsr-mutex"; 2165 reg = <0 0x01f40000 0 0x20000>; 2166 #hwlock-cells = <1>; 2167 }; 2168 2169 tcsr_1: syscon@1f60000 { 2170 compatible = "qcom,sc7280-tcsr", "syscon"; 2171 reg = <0 0x01f60000 0 0x20000>; 2172 }; 2173 2174 tcsr_2: syscon@1fc0000 { 2175 compatible = "qcom,sc7280-tcsr", "syscon"; 2176 reg = <0 0x01fc0000 0 0x30000>; 2177 }; 2178 2179 lpasscc: lpasscc@3000000 { 2180 compatible = "qcom,sc7280-lpasscc"; 2181 reg = <0 0x03000000 0 0x40>, 2182 <0 0x03c04000 0 0x4>; 2183 reg-names = "qdsp6ss", "top_cc"; 2184 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2185 clock-names = "iface"; 2186 #clock-cells = <1>; 2187 }; 2188 2189 lpass_rx_macro: codec@3200000 { 2190 compatible = "qcom,sc7280-lpass-rx-macro"; 2191 reg = <0 0x03200000 0 0x1000>; 2192 2193 pinctrl-names = "default"; 2194 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2195 2196 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2197 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2198 <&lpass_va_macro>; 2199 clock-names = "mclk", "npl", "fsgen"; 2200 2201 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2202 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2203 power-domain-names = "macro", "dcodec"; 2204 2205 #clock-cells = <0>; 2206 #sound-dai-cells = <1>; 2207 2208 status = "disabled"; 2209 }; 2210 2211 swr0: soundwire@3210000 { 2212 compatible = "qcom,soundwire-v1.6.0"; 2213 reg = <0 0x03210000 0 0x2000>; 2214 2215 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2216 clocks = <&lpass_rx_macro>; 2217 clock-names = "iface"; 2218 2219 qcom,din-ports = <0>; 2220 qcom,dout-ports = <5>; 2221 2222 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2223 reset-names = "swr_audio_cgcr"; 2224 2225 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2226 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2227 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2228 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2229 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2230 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2231 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2232 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2233 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2234 2235 #sound-dai-cells = <1>; 2236 #address-cells = <2>; 2237 #size-cells = <0>; 2238 2239 status = "disabled"; 2240 }; 2241 2242 lpass_tx_macro: codec@3220000 { 2243 compatible = "qcom,sc7280-lpass-tx-macro"; 2244 reg = <0 0x03220000 0 0x1000>; 2245 2246 pinctrl-names = "default"; 2247 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2248 2249 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2250 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2251 <&lpass_va_macro>; 2252 clock-names = "mclk", "npl", "fsgen"; 2253 2254 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2255 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2256 power-domain-names = "macro", "dcodec"; 2257 2258 #clock-cells = <0>; 2259 #sound-dai-cells = <1>; 2260 2261 status = "disabled"; 2262 }; 2263 2264 swr1: soundwire@3230000 { 2265 compatible = "qcom,soundwire-v1.6.0"; 2266 reg = <0 0x03230000 0 0x2000>; 2267 2268 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2269 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2270 clocks = <&lpass_tx_macro>; 2271 clock-names = "iface"; 2272 2273 qcom,din-ports = <3>; 2274 qcom,dout-ports = <0>; 2275 2276 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2277 reset-names = "swr_audio_cgcr"; 2278 2279 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2280 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2281 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2282 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2283 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2284 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2285 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2286 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2287 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2288 qcom,port-offset = <1>; 2289 2290 #sound-dai-cells = <1>; 2291 #address-cells = <2>; 2292 #size-cells = <0>; 2293 2294 status = "disabled"; 2295 }; 2296 2297 lpass_audiocc: clock-controller@3300000 { 2298 compatible = "qcom,sc7280-lpassaudiocc"; 2299 reg = <0 0x03300000 0 0x30000>, 2300 <0 0x032a9000 0 0x1000>; 2301 clocks = <&rpmhcc RPMH_CXO_CLK>, 2302 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2303 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2304 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2305 #clock-cells = <1>; 2306 #power-domain-cells = <1>; 2307 #reset-cells = <1>; 2308 }; 2309 2310 lpass_va_macro: codec@3370000 { 2311 compatible = "qcom,sc7280-lpass-va-macro"; 2312 reg = <0 0x03370000 0 0x1000>; 2313 2314 pinctrl-names = "default"; 2315 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2316 2317 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2318 clock-names = "mclk"; 2319 2320 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2321 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2322 power-domain-names = "macro", "dcodec"; 2323 2324 #clock-cells = <0>; 2325 #sound-dai-cells = <1>; 2326 2327 status = "disabled"; 2328 }; 2329 2330 lpass_aon: clock-controller@3380000 { 2331 compatible = "qcom,sc7280-lpassaoncc"; 2332 reg = <0 0x03380000 0 0x30000>; 2333 clocks = <&rpmhcc RPMH_CXO_CLK>, 2334 <&rpmhcc RPMH_CXO_CLK_A>, 2335 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2336 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2337 #clock-cells = <1>; 2338 #power-domain-cells = <1>; 2339 }; 2340 2341 lpass_core: clock-controller@3900000 { 2342 compatible = "qcom,sc7280-lpasscorecc"; 2343 reg = <0 0x03900000 0 0x50000>; 2344 clocks = <&rpmhcc RPMH_CXO_CLK>; 2345 clock-names = "bi_tcxo"; 2346 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2347 #clock-cells = <1>; 2348 #power-domain-cells = <1>; 2349 }; 2350 2351 lpass_cpu: audio@3987000 { 2352 compatible = "qcom,sc7280-lpass-cpu"; 2353 2354 reg = <0 0x03987000 0 0x68000>, 2355 <0 0x03b00000 0 0x29000>, 2356 <0 0x03260000 0 0xc000>, 2357 <0 0x03280000 0 0x29000>, 2358 <0 0x03340000 0 0x29000>, 2359 <0 0x0336c000 0 0x3000>; 2360 reg-names = "lpass-hdmiif", 2361 "lpass-lpaif", 2362 "lpass-rxtx-cdc-dma-lpm", 2363 "lpass-rxtx-lpaif", 2364 "lpass-va-lpaif", 2365 "lpass-va-cdc-dma-lpm"; 2366 2367 iommus = <&apps_smmu 0x1820 0>, 2368 <&apps_smmu 0x1821 0>, 2369 <&apps_smmu 0x1832 0>; 2370 2371 power-domains = <&rpmhpd SC7280_LCX>; 2372 power-domain-names = "lcx"; 2373 required-opps = <&rpmhpd_opp_nom>; 2374 2375 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2376 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2377 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2378 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2379 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2380 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2381 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2382 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2383 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2384 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2385 clock-names = "aon_cc_audio_hm_h", 2386 "audio_cc_ext_mclk0", 2387 "core_cc_sysnoc_mport_core", 2388 "core_cc_ext_if0_ibit", 2389 "core_cc_ext_if1_ibit", 2390 "audio_cc_codec_mem", 2391 "audio_cc_codec_mem0", 2392 "audio_cc_codec_mem1", 2393 "audio_cc_codec_mem2", 2394 "aon_cc_va_mem0"; 2395 2396 #sound-dai-cells = <1>; 2397 #address-cells = <1>; 2398 #size-cells = <0>; 2399 2400 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2401 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2402 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2403 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2404 interrupt-names = "lpass-irq-lpaif", 2405 "lpass-irq-hdmi", 2406 "lpass-irq-vaif", 2407 "lpass-irq-rxtxif"; 2408 2409 status = "disabled"; 2410 }; 2411 2412 lpass_hm: clock-controller@3c00000 { 2413 compatible = "qcom,sc7280-lpasshm"; 2414 reg = <0 0x3c00000 0 0x28>; 2415 clocks = <&rpmhcc RPMH_CXO_CLK>; 2416 clock-names = "bi_tcxo"; 2417 #clock-cells = <1>; 2418 #power-domain-cells = <1>; 2419 }; 2420 2421 lpass_ag_noc: interconnect@3c40000 { 2422 reg = <0 0x03c40000 0 0xf080>; 2423 compatible = "qcom,sc7280-lpass-ag-noc"; 2424 #interconnect-cells = <2>; 2425 qcom,bcm-voters = <&apps_bcm_voter>; 2426 }; 2427 2428 lpass_tlmm: pinctrl@33c0000 { 2429 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2430 reg = <0 0x033c0000 0x0 0x20000>, 2431 <0 0x03550000 0x0 0x10000>; 2432 qcom,adsp-bypass-mode; 2433 gpio-controller; 2434 #gpio-cells = <2>; 2435 gpio-ranges = <&lpass_tlmm 0 0 15>; 2436 2437 #clock-cells = <1>; 2438 2439 lpass_dmic01_clk: dmic01-clk { 2440 pins = "gpio6"; 2441 function = "dmic1_clk"; 2442 }; 2443 2444 lpass_dmic01_clk_sleep: dmic01-clk-sleep { 2445 pins = "gpio6"; 2446 function = "dmic1_clk"; 2447 }; 2448 2449 lpass_dmic01_data: dmic01-data { 2450 pins = "gpio7"; 2451 function = "dmic1_data"; 2452 }; 2453 2454 lpass_dmic01_data_sleep: dmic01-data-sleep { 2455 pins = "gpio7"; 2456 function = "dmic1_data"; 2457 }; 2458 2459 lpass_dmic23_clk: dmic23-clk { 2460 pins = "gpio8"; 2461 function = "dmic2_clk"; 2462 }; 2463 2464 lpass_dmic23_clk_sleep: dmic23-clk-sleep { 2465 pins = "gpio8"; 2466 function = "dmic2_clk"; 2467 }; 2468 2469 lpass_dmic23_data: dmic23-data { 2470 pins = "gpio9"; 2471 function = "dmic2_data"; 2472 }; 2473 2474 lpass_dmic23_data_sleep: dmic23-data-sleep { 2475 pins = "gpio9"; 2476 function = "dmic2_data"; 2477 }; 2478 2479 lpass_rx_swr_clk: rx-swr-clk { 2480 pins = "gpio3"; 2481 function = "swr_rx_clk"; 2482 }; 2483 2484 lpass_rx_swr_clk_sleep: rx-swr-clk-sleep { 2485 pins = "gpio3"; 2486 function = "swr_rx_clk"; 2487 }; 2488 2489 lpass_rx_swr_data: rx-swr-data { 2490 pins = "gpio4", "gpio5"; 2491 function = "swr_rx_data"; 2492 }; 2493 2494 lpass_rx_swr_data_sleep: rx-swr-data-sleep { 2495 pins = "gpio4", "gpio5"; 2496 function = "swr_rx_data"; 2497 }; 2498 2499 lpass_tx_swr_clk: tx-swr-clk { 2500 pins = "gpio0"; 2501 function = "swr_tx_clk"; 2502 }; 2503 2504 lpass_tx_swr_clk_sleep: tx-swr-clk-sleep { 2505 pins = "gpio0"; 2506 function = "swr_tx_clk"; 2507 }; 2508 2509 lpass_tx_swr_data: tx-swr-data { 2510 pins = "gpio1", "gpio2", "gpio14"; 2511 function = "swr_tx_data"; 2512 }; 2513 2514 lpass_tx_swr_data_sleep: tx-swr-data-sleep { 2515 pins = "gpio1", "gpio2", "gpio14"; 2516 function = "swr_tx_data"; 2517 }; 2518 }; 2519 2520 gpu: gpu@3d00000 { 2521 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2522 reg = <0 0x03d00000 0 0x40000>, 2523 <0 0x03d9e000 0 0x1000>, 2524 <0 0x03d61000 0 0x800>; 2525 reg-names = "kgsl_3d0_reg_memory", 2526 "cx_mem", 2527 "cx_dbgc"; 2528 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2529 iommus = <&adreno_smmu 0 0x401>; 2530 operating-points-v2 = <&gpu_opp_table>; 2531 qcom,gmu = <&gmu>; 2532 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2533 interconnect-names = "gfx-mem"; 2534 #cooling-cells = <2>; 2535 2536 nvmem-cells = <&gpu_speed_bin>; 2537 nvmem-cell-names = "speed_bin"; 2538 2539 gpu_opp_table: opp-table { 2540 compatible = "operating-points-v2"; 2541 2542 opp-315000000 { 2543 opp-hz = /bits/ 64 <315000000>; 2544 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2545 opp-peak-kBps = <1804000>; 2546 opp-supported-hw = <0x03>; 2547 }; 2548 2549 opp-450000000 { 2550 opp-hz = /bits/ 64 <450000000>; 2551 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2552 opp-peak-kBps = <4068000>; 2553 opp-supported-hw = <0x03>; 2554 }; 2555 2556 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2557 opp-550000000-0 { 2558 opp-hz = /bits/ 64 <550000000>; 2559 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2560 opp-peak-kBps = <8368000>; 2561 opp-supported-hw = <0x01>; 2562 }; 2563 2564 opp-550000000-1 { 2565 opp-hz = /bits/ 64 <550000000>; 2566 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2567 opp-peak-kBps = <6832000>; 2568 opp-supported-hw = <0x02>; 2569 }; 2570 2571 opp-608000000 { 2572 opp-hz = /bits/ 64 <608000000>; 2573 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2574 opp-peak-kBps = <8368000>; 2575 opp-supported-hw = <0x02>; 2576 }; 2577 2578 opp-700000000 { 2579 opp-hz = /bits/ 64 <700000000>; 2580 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2581 opp-peak-kBps = <8532000>; 2582 opp-supported-hw = <0x02>; 2583 }; 2584 2585 opp-812000000 { 2586 opp-hz = /bits/ 64 <812000000>; 2587 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2588 opp-peak-kBps = <8532000>; 2589 opp-supported-hw = <0x02>; 2590 }; 2591 2592 opp-840000000 { 2593 opp-hz = /bits/ 64 <840000000>; 2594 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2595 opp-peak-kBps = <8532000>; 2596 opp-supported-hw = <0x02>; 2597 }; 2598 2599 opp-900000000 { 2600 opp-hz = /bits/ 64 <900000000>; 2601 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2602 opp-peak-kBps = <8532000>; 2603 opp-supported-hw = <0x02>; 2604 }; 2605 }; 2606 }; 2607 2608 gmu: gmu@3d6a000 { 2609 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2610 reg = <0 0x03d6a000 0 0x34000>, 2611 <0 0x3de0000 0 0x10000>, 2612 <0 0x0b290000 0 0x10000>; 2613 reg-names = "gmu", "rscc", "gmu_pdc"; 2614 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2615 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2616 interrupt-names = "hfi", "gmu"; 2617 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2618 <&gpucc GPU_CC_CXO_CLK>, 2619 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2620 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2621 <&gpucc GPU_CC_AHB_CLK>, 2622 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2623 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2624 clock-names = "gmu", 2625 "cxo", 2626 "axi", 2627 "memnoc", 2628 "ahb", 2629 "hub", 2630 "smmu_vote"; 2631 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2632 <&gpucc GPU_CC_GX_GDSC>; 2633 power-domain-names = "cx", 2634 "gx"; 2635 iommus = <&adreno_smmu 5 0x400>; 2636 operating-points-v2 = <&gmu_opp_table>; 2637 2638 gmu_opp_table: opp-table { 2639 compatible = "operating-points-v2"; 2640 2641 opp-200000000 { 2642 opp-hz = /bits/ 64 <200000000>; 2643 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2644 }; 2645 }; 2646 }; 2647 2648 gpucc: clock-controller@3d90000 { 2649 compatible = "qcom,sc7280-gpucc"; 2650 reg = <0 0x03d90000 0 0x9000>; 2651 clocks = <&rpmhcc RPMH_CXO_CLK>, 2652 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2653 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2654 clock-names = "bi_tcxo", 2655 "gcc_gpu_gpll0_clk_src", 2656 "gcc_gpu_gpll0_div_clk_src"; 2657 #clock-cells = <1>; 2658 #reset-cells = <1>; 2659 #power-domain-cells = <1>; 2660 }; 2661 2662 adreno_smmu: iommu@3da0000 { 2663 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2664 reg = <0 0x03da0000 0 0x20000>; 2665 #iommu-cells = <2>; 2666 #global-interrupts = <2>; 2667 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2668 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2669 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2670 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2671 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2672 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2673 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2674 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2675 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2676 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2677 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2678 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2679 2680 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2681 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2682 <&gpucc GPU_CC_AHB_CLK>, 2683 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2684 <&gpucc GPU_CC_CX_GMU_CLK>, 2685 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2686 <&gpucc GPU_CC_HUB_AON_CLK>; 2687 clock-names = "gcc_gpu_memnoc_gfx_clk", 2688 "gcc_gpu_snoc_dvm_gfx_clk", 2689 "gpu_cc_ahb_clk", 2690 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2691 "gpu_cc_cx_gmu_clk", 2692 "gpu_cc_hub_cx_int_clk", 2693 "gpu_cc_hub_aon_clk"; 2694 2695 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2696 }; 2697 2698 remoteproc_mpss: remoteproc@4080000 { 2699 compatible = "qcom,sc7280-mpss-pas"; 2700 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2701 reg-names = "qdsp6", "rmb"; 2702 2703 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2704 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2705 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2706 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2707 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2708 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2709 interrupt-names = "wdog", "fatal", "ready", "handover", 2710 "stop-ack", "shutdown-ack"; 2711 2712 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2713 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 2714 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2715 <&rpmhcc RPMH_PKA_CLK>, 2716 <&rpmhcc RPMH_CXO_CLK>; 2717 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 2718 2719 power-domains = <&rpmhpd SC7280_CX>, 2720 <&rpmhpd SC7280_MSS>; 2721 power-domain-names = "cx", "mss"; 2722 2723 memory-region = <&mpss_mem>; 2724 2725 qcom,qmp = <&aoss_qmp>; 2726 2727 qcom,smem-states = <&modem_smp2p_out 0>; 2728 qcom,smem-state-names = "stop"; 2729 2730 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2731 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2732 reset-names = "mss_restart", "pdc_reset"; 2733 2734 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>; 2735 qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>; 2736 qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>; 2737 2738 status = "disabled"; 2739 2740 glink-edge { 2741 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2742 IPCC_MPROC_SIGNAL_GLINK_QMP 2743 IRQ_TYPE_EDGE_RISING>; 2744 mboxes = <&ipcc IPCC_CLIENT_MPSS 2745 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2746 label = "modem"; 2747 qcom,remote-pid = <1>; 2748 }; 2749 }; 2750 2751 stm@6002000 { 2752 compatible = "arm,coresight-stm", "arm,primecell"; 2753 reg = <0 0x06002000 0 0x1000>, 2754 <0 0x16280000 0 0x180000>; 2755 reg-names = "stm-base", "stm-stimulus-base"; 2756 2757 clocks = <&aoss_qmp>; 2758 clock-names = "apb_pclk"; 2759 2760 out-ports { 2761 port { 2762 stm_out: endpoint { 2763 remote-endpoint = <&funnel0_in7>; 2764 }; 2765 }; 2766 }; 2767 }; 2768 2769 funnel@6041000 { 2770 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2771 reg = <0 0x06041000 0 0x1000>; 2772 2773 clocks = <&aoss_qmp>; 2774 clock-names = "apb_pclk"; 2775 2776 out-ports { 2777 port { 2778 funnel0_out: endpoint { 2779 remote-endpoint = <&merge_funnel_in0>; 2780 }; 2781 }; 2782 }; 2783 2784 in-ports { 2785 #address-cells = <1>; 2786 #size-cells = <0>; 2787 2788 port@7 { 2789 reg = <7>; 2790 funnel0_in7: endpoint { 2791 remote-endpoint = <&stm_out>; 2792 }; 2793 }; 2794 }; 2795 }; 2796 2797 funnel@6042000 { 2798 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2799 reg = <0 0x06042000 0 0x1000>; 2800 2801 clocks = <&aoss_qmp>; 2802 clock-names = "apb_pclk"; 2803 2804 out-ports { 2805 port { 2806 funnel1_out: endpoint { 2807 remote-endpoint = <&merge_funnel_in1>; 2808 }; 2809 }; 2810 }; 2811 2812 in-ports { 2813 #address-cells = <1>; 2814 #size-cells = <0>; 2815 2816 port@4 { 2817 reg = <4>; 2818 funnel1_in4: endpoint { 2819 remote-endpoint = <&apss_merge_funnel_out>; 2820 }; 2821 }; 2822 }; 2823 }; 2824 2825 funnel@6045000 { 2826 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2827 reg = <0 0x06045000 0 0x1000>; 2828 2829 clocks = <&aoss_qmp>; 2830 clock-names = "apb_pclk"; 2831 2832 out-ports { 2833 port { 2834 merge_funnel_out: endpoint { 2835 remote-endpoint = <&swao_funnel_in>; 2836 }; 2837 }; 2838 }; 2839 2840 in-ports { 2841 #address-cells = <1>; 2842 #size-cells = <0>; 2843 2844 port@0 { 2845 reg = <0>; 2846 merge_funnel_in0: endpoint { 2847 remote-endpoint = <&funnel0_out>; 2848 }; 2849 }; 2850 2851 port@1 { 2852 reg = <1>; 2853 merge_funnel_in1: endpoint { 2854 remote-endpoint = <&funnel1_out>; 2855 }; 2856 }; 2857 }; 2858 }; 2859 2860 replicator@6046000 { 2861 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2862 reg = <0 0x06046000 0 0x1000>; 2863 2864 clocks = <&aoss_qmp>; 2865 clock-names = "apb_pclk"; 2866 2867 out-ports { 2868 port { 2869 replicator_out: endpoint { 2870 remote-endpoint = <&etr_in>; 2871 }; 2872 }; 2873 }; 2874 2875 in-ports { 2876 port { 2877 replicator_in: endpoint { 2878 remote-endpoint = <&swao_replicator_out>; 2879 }; 2880 }; 2881 }; 2882 }; 2883 2884 etr@6048000 { 2885 compatible = "arm,coresight-tmc", "arm,primecell"; 2886 reg = <0 0x06048000 0 0x1000>; 2887 iommus = <&apps_smmu 0x04c0 0>; 2888 2889 clocks = <&aoss_qmp>; 2890 clock-names = "apb_pclk"; 2891 arm,scatter-gather; 2892 2893 in-ports { 2894 port { 2895 etr_in: endpoint { 2896 remote-endpoint = <&replicator_out>; 2897 }; 2898 }; 2899 }; 2900 }; 2901 2902 funnel@6b04000 { 2903 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2904 reg = <0 0x06b04000 0 0x1000>; 2905 2906 clocks = <&aoss_qmp>; 2907 clock-names = "apb_pclk"; 2908 2909 out-ports { 2910 port { 2911 swao_funnel_out: endpoint { 2912 remote-endpoint = <&etf_in>; 2913 }; 2914 }; 2915 }; 2916 2917 in-ports { 2918 #address-cells = <1>; 2919 #size-cells = <0>; 2920 2921 port@7 { 2922 reg = <7>; 2923 swao_funnel_in: endpoint { 2924 remote-endpoint = <&merge_funnel_out>; 2925 }; 2926 }; 2927 }; 2928 }; 2929 2930 etf@6b05000 { 2931 compatible = "arm,coresight-tmc", "arm,primecell"; 2932 reg = <0 0x06b05000 0 0x1000>; 2933 2934 clocks = <&aoss_qmp>; 2935 clock-names = "apb_pclk"; 2936 2937 out-ports { 2938 port { 2939 etf_out: endpoint { 2940 remote-endpoint = <&swao_replicator_in>; 2941 }; 2942 }; 2943 }; 2944 2945 in-ports { 2946 port { 2947 etf_in: endpoint { 2948 remote-endpoint = <&swao_funnel_out>; 2949 }; 2950 }; 2951 }; 2952 }; 2953 2954 replicator@6b06000 { 2955 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2956 reg = <0 0x06b06000 0 0x1000>; 2957 2958 clocks = <&aoss_qmp>; 2959 clock-names = "apb_pclk"; 2960 qcom,replicator-loses-context; 2961 2962 out-ports { 2963 port { 2964 swao_replicator_out: endpoint { 2965 remote-endpoint = <&replicator_in>; 2966 }; 2967 }; 2968 }; 2969 2970 in-ports { 2971 port { 2972 swao_replicator_in: endpoint { 2973 remote-endpoint = <&etf_out>; 2974 }; 2975 }; 2976 }; 2977 }; 2978 2979 etm@7040000 { 2980 compatible = "arm,coresight-etm4x", "arm,primecell"; 2981 reg = <0 0x07040000 0 0x1000>; 2982 2983 cpu = <&CPU0>; 2984 2985 clocks = <&aoss_qmp>; 2986 clock-names = "apb_pclk"; 2987 arm,coresight-loses-context-with-cpu; 2988 qcom,skip-power-up; 2989 2990 out-ports { 2991 port { 2992 etm0_out: endpoint { 2993 remote-endpoint = <&apss_funnel_in0>; 2994 }; 2995 }; 2996 }; 2997 }; 2998 2999 etm@7140000 { 3000 compatible = "arm,coresight-etm4x", "arm,primecell"; 3001 reg = <0 0x07140000 0 0x1000>; 3002 3003 cpu = <&CPU1>; 3004 3005 clocks = <&aoss_qmp>; 3006 clock-names = "apb_pclk"; 3007 arm,coresight-loses-context-with-cpu; 3008 qcom,skip-power-up; 3009 3010 out-ports { 3011 port { 3012 etm1_out: endpoint { 3013 remote-endpoint = <&apss_funnel_in1>; 3014 }; 3015 }; 3016 }; 3017 }; 3018 3019 etm@7240000 { 3020 compatible = "arm,coresight-etm4x", "arm,primecell"; 3021 reg = <0 0x07240000 0 0x1000>; 3022 3023 cpu = <&CPU2>; 3024 3025 clocks = <&aoss_qmp>; 3026 clock-names = "apb_pclk"; 3027 arm,coresight-loses-context-with-cpu; 3028 qcom,skip-power-up; 3029 3030 out-ports { 3031 port { 3032 etm2_out: endpoint { 3033 remote-endpoint = <&apss_funnel_in2>; 3034 }; 3035 }; 3036 }; 3037 }; 3038 3039 etm@7340000 { 3040 compatible = "arm,coresight-etm4x", "arm,primecell"; 3041 reg = <0 0x07340000 0 0x1000>; 3042 3043 cpu = <&CPU3>; 3044 3045 clocks = <&aoss_qmp>; 3046 clock-names = "apb_pclk"; 3047 arm,coresight-loses-context-with-cpu; 3048 qcom,skip-power-up; 3049 3050 out-ports { 3051 port { 3052 etm3_out: endpoint { 3053 remote-endpoint = <&apss_funnel_in3>; 3054 }; 3055 }; 3056 }; 3057 }; 3058 3059 etm@7440000 { 3060 compatible = "arm,coresight-etm4x", "arm,primecell"; 3061 reg = <0 0x07440000 0 0x1000>; 3062 3063 cpu = <&CPU4>; 3064 3065 clocks = <&aoss_qmp>; 3066 clock-names = "apb_pclk"; 3067 arm,coresight-loses-context-with-cpu; 3068 qcom,skip-power-up; 3069 3070 out-ports { 3071 port { 3072 etm4_out: endpoint { 3073 remote-endpoint = <&apss_funnel_in4>; 3074 }; 3075 }; 3076 }; 3077 }; 3078 3079 etm@7540000 { 3080 compatible = "arm,coresight-etm4x", "arm,primecell"; 3081 reg = <0 0x07540000 0 0x1000>; 3082 3083 cpu = <&CPU5>; 3084 3085 clocks = <&aoss_qmp>; 3086 clock-names = "apb_pclk"; 3087 arm,coresight-loses-context-with-cpu; 3088 qcom,skip-power-up; 3089 3090 out-ports { 3091 port { 3092 etm5_out: endpoint { 3093 remote-endpoint = <&apss_funnel_in5>; 3094 }; 3095 }; 3096 }; 3097 }; 3098 3099 etm@7640000 { 3100 compatible = "arm,coresight-etm4x", "arm,primecell"; 3101 reg = <0 0x07640000 0 0x1000>; 3102 3103 cpu = <&CPU6>; 3104 3105 clocks = <&aoss_qmp>; 3106 clock-names = "apb_pclk"; 3107 arm,coresight-loses-context-with-cpu; 3108 qcom,skip-power-up; 3109 3110 out-ports { 3111 port { 3112 etm6_out: endpoint { 3113 remote-endpoint = <&apss_funnel_in6>; 3114 }; 3115 }; 3116 }; 3117 }; 3118 3119 etm@7740000 { 3120 compatible = "arm,coresight-etm4x", "arm,primecell"; 3121 reg = <0 0x07740000 0 0x1000>; 3122 3123 cpu = <&CPU7>; 3124 3125 clocks = <&aoss_qmp>; 3126 clock-names = "apb_pclk"; 3127 arm,coresight-loses-context-with-cpu; 3128 qcom,skip-power-up; 3129 3130 out-ports { 3131 port { 3132 etm7_out: endpoint { 3133 remote-endpoint = <&apss_funnel_in7>; 3134 }; 3135 }; 3136 }; 3137 }; 3138 3139 funnel@7800000 { /* APSS Funnel */ 3140 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3141 reg = <0 0x07800000 0 0x1000>; 3142 3143 clocks = <&aoss_qmp>; 3144 clock-names = "apb_pclk"; 3145 3146 out-ports { 3147 port { 3148 apss_funnel_out: endpoint { 3149 remote-endpoint = <&apss_merge_funnel_in>; 3150 }; 3151 }; 3152 }; 3153 3154 in-ports { 3155 #address-cells = <1>; 3156 #size-cells = <0>; 3157 3158 port@0 { 3159 reg = <0>; 3160 apss_funnel_in0: endpoint { 3161 remote-endpoint = <&etm0_out>; 3162 }; 3163 }; 3164 3165 port@1 { 3166 reg = <1>; 3167 apss_funnel_in1: endpoint { 3168 remote-endpoint = <&etm1_out>; 3169 }; 3170 }; 3171 3172 port@2 { 3173 reg = <2>; 3174 apss_funnel_in2: endpoint { 3175 remote-endpoint = <&etm2_out>; 3176 }; 3177 }; 3178 3179 port@3 { 3180 reg = <3>; 3181 apss_funnel_in3: endpoint { 3182 remote-endpoint = <&etm3_out>; 3183 }; 3184 }; 3185 3186 port@4 { 3187 reg = <4>; 3188 apss_funnel_in4: endpoint { 3189 remote-endpoint = <&etm4_out>; 3190 }; 3191 }; 3192 3193 port@5 { 3194 reg = <5>; 3195 apss_funnel_in5: endpoint { 3196 remote-endpoint = <&etm5_out>; 3197 }; 3198 }; 3199 3200 port@6 { 3201 reg = <6>; 3202 apss_funnel_in6: endpoint { 3203 remote-endpoint = <&etm6_out>; 3204 }; 3205 }; 3206 3207 port@7 { 3208 reg = <7>; 3209 apss_funnel_in7: endpoint { 3210 remote-endpoint = <&etm7_out>; 3211 }; 3212 }; 3213 }; 3214 }; 3215 3216 funnel@7810000 { 3217 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3218 reg = <0 0x07810000 0 0x1000>; 3219 3220 clocks = <&aoss_qmp>; 3221 clock-names = "apb_pclk"; 3222 3223 out-ports { 3224 port { 3225 apss_merge_funnel_out: endpoint { 3226 remote-endpoint = <&funnel1_in4>; 3227 }; 3228 }; 3229 }; 3230 3231 in-ports { 3232 port { 3233 apss_merge_funnel_in: endpoint { 3234 remote-endpoint = <&apss_funnel_out>; 3235 }; 3236 }; 3237 }; 3238 }; 3239 3240 sdhc_2: mmc@8804000 { 3241 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3242 pinctrl-names = "default", "sleep"; 3243 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3244 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3245 status = "disabled"; 3246 3247 reg = <0 0x08804000 0 0x1000>; 3248 3249 iommus = <&apps_smmu 0x100 0x0>; 3250 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3251 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3252 interrupt-names = "hc_irq", "pwr_irq"; 3253 3254 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3255 <&gcc GCC_SDCC2_APPS_CLK>, 3256 <&rpmhcc RPMH_CXO_CLK>; 3257 clock-names = "iface", "core", "xo"; 3258 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3259 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3260 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3261 power-domains = <&rpmhpd SC7280_CX>; 3262 operating-points-v2 = <&sdhc2_opp_table>; 3263 3264 bus-width = <4>; 3265 3266 qcom,dll-config = <0x0007642c>; 3267 3268 resets = <&gcc GCC_SDCC2_BCR>; 3269 3270 sdhc2_opp_table: opp-table { 3271 compatible = "operating-points-v2"; 3272 3273 opp-100000000 { 3274 opp-hz = /bits/ 64 <100000000>; 3275 required-opps = <&rpmhpd_opp_low_svs>; 3276 opp-peak-kBps = <1800000 400000>; 3277 opp-avg-kBps = <100000 0>; 3278 }; 3279 3280 opp-202000000 { 3281 opp-hz = /bits/ 64 <202000000>; 3282 required-opps = <&rpmhpd_opp_nom>; 3283 opp-peak-kBps = <5400000 1600000>; 3284 opp-avg-kBps = <200000 0>; 3285 }; 3286 }; 3287 3288 }; 3289 3290 usb_1_hsphy: phy@88e3000 { 3291 compatible = "qcom,sc7280-usb-hs-phy", 3292 "qcom,usb-snps-hs-7nm-phy"; 3293 reg = <0 0x088e3000 0 0x400>; 3294 status = "disabled"; 3295 #phy-cells = <0>; 3296 3297 clocks = <&rpmhcc RPMH_CXO_CLK>; 3298 clock-names = "ref"; 3299 3300 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3301 }; 3302 3303 usb_2_hsphy: phy@88e4000 { 3304 compatible = "qcom,sc7280-usb-hs-phy", 3305 "qcom,usb-snps-hs-7nm-phy"; 3306 reg = <0 0x088e4000 0 0x400>; 3307 status = "disabled"; 3308 #phy-cells = <0>; 3309 3310 clocks = <&rpmhcc RPMH_CXO_CLK>; 3311 clock-names = "ref"; 3312 3313 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3314 }; 3315 3316 usb_1_qmpphy: phy-wrapper@88e9000 { 3317 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3318 "qcom,sm8250-qmp-usb3-dp-phy"; 3319 reg = <0 0x088e9000 0 0x200>, 3320 <0 0x088e8000 0 0x40>, 3321 <0 0x088ea000 0 0x200>; 3322 status = "disabled"; 3323 #address-cells = <2>; 3324 #size-cells = <2>; 3325 ranges; 3326 3327 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3328 <&rpmhcc RPMH_CXO_CLK>, 3329 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3330 clock-names = "aux", "ref_clk_src", "com_aux"; 3331 3332 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3333 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3334 reset-names = "phy", "common"; 3335 3336 usb_1_ssphy: usb3-phy@88e9200 { 3337 reg = <0 0x088e9200 0 0x200>, 3338 <0 0x088e9400 0 0x200>, 3339 <0 0x088e9c00 0 0x400>, 3340 <0 0x088e9600 0 0x200>, 3341 <0 0x088e9800 0 0x200>, 3342 <0 0x088e9a00 0 0x100>; 3343 #clock-cells = <0>; 3344 #phy-cells = <0>; 3345 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3346 clock-names = "pipe0"; 3347 clock-output-names = "usb3_phy_pipe_clk_src"; 3348 }; 3349 3350 dp_phy: dp-phy@88ea200 { 3351 reg = <0 0x088ea200 0 0x200>, 3352 <0 0x088ea400 0 0x200>, 3353 <0 0x088eaa00 0 0x200>, 3354 <0 0x088ea600 0 0x200>, 3355 <0 0x088ea800 0 0x200>; 3356 #phy-cells = <0>; 3357 #clock-cells = <1>; 3358 }; 3359 }; 3360 3361 usb_2: usb@8cf8800 { 3362 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3363 reg = <0 0x08cf8800 0 0x400>; 3364 status = "disabled"; 3365 #address-cells = <2>; 3366 #size-cells = <2>; 3367 ranges; 3368 dma-ranges; 3369 3370 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3371 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3372 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3373 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3374 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3375 clock-names = "cfg_noc", 3376 "core", 3377 "iface", 3378 "sleep", 3379 "mock_utmi"; 3380 3381 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3382 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3383 assigned-clock-rates = <19200000>, <200000000>; 3384 3385 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3386 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3387 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3388 interrupt-names = "hs_phy_irq", 3389 "dp_hs_phy_irq", 3390 "dm_hs_phy_irq"; 3391 3392 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3393 required-opps = <&rpmhpd_opp_nom>; 3394 3395 resets = <&gcc GCC_USB30_SEC_BCR>; 3396 3397 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3398 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3399 interconnect-names = "usb-ddr", "apps-usb"; 3400 3401 usb_2_dwc3: usb@8c00000 { 3402 compatible = "snps,dwc3"; 3403 reg = <0 0x08c00000 0 0xe000>; 3404 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3405 iommus = <&apps_smmu 0xa0 0x0>; 3406 snps,dis_u2_susphy_quirk; 3407 snps,dis_enblslpm_quirk; 3408 phys = <&usb_2_hsphy>; 3409 phy-names = "usb2-phy"; 3410 maximum-speed = "high-speed"; 3411 usb-role-switch; 3412 port { 3413 usb2_role_switch: endpoint { 3414 remote-endpoint = <&eud_ep>; 3415 }; 3416 }; 3417 }; 3418 }; 3419 3420 qspi: spi@88dc000 { 3421 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3422 reg = <0 0x088dc000 0 0x1000>; 3423 #address-cells = <1>; 3424 #size-cells = <0>; 3425 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3426 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3427 <&gcc GCC_QSPI_CORE_CLK>; 3428 clock-names = "iface", "core"; 3429 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3430 &cnoc2 SLAVE_QSPI_0 0>; 3431 interconnect-names = "qspi-config"; 3432 power-domains = <&rpmhpd SC7280_CX>; 3433 operating-points-v2 = <&qspi_opp_table>; 3434 status = "disabled"; 3435 }; 3436 3437 remoteproc_wpss: remoteproc@8a00000 { 3438 compatible = "qcom,sc7280-wpss-pil"; 3439 reg = <0 0x08a00000 0 0x10000>; 3440 3441 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3442 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3443 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3444 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3445 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3446 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3447 interrupt-names = "wdog", "fatal", "ready", "handover", 3448 "stop-ack", "shutdown-ack"; 3449 3450 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3451 <&gcc GCC_WPSS_AHB_CLK>, 3452 <&gcc GCC_WPSS_RSCP_CLK>, 3453 <&rpmhcc RPMH_CXO_CLK>; 3454 clock-names = "ahb_bdg", "ahb", 3455 "rscp", "xo"; 3456 3457 power-domains = <&rpmhpd SC7280_CX>, 3458 <&rpmhpd SC7280_MX>; 3459 power-domain-names = "cx", "mx"; 3460 3461 memory-region = <&wpss_mem>; 3462 3463 qcom,qmp = <&aoss_qmp>; 3464 3465 qcom,smem-states = <&wpss_smp2p_out 0>; 3466 qcom,smem-state-names = "stop"; 3467 3468 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3469 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3470 reset-names = "restart", "pdc_sync"; 3471 3472 qcom,halt-regs = <&tcsr_1 0x17000>; 3473 3474 status = "disabled"; 3475 3476 glink-edge { 3477 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3478 IPCC_MPROC_SIGNAL_GLINK_QMP 3479 IRQ_TYPE_EDGE_RISING>; 3480 mboxes = <&ipcc IPCC_CLIENT_WPSS 3481 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3482 3483 label = "wpss"; 3484 qcom,remote-pid = <13>; 3485 }; 3486 }; 3487 3488 pmu@9091000 { 3489 compatible = "qcom,sc7280-llcc-bwmon"; 3490 reg = <0 0x9091000 0 0x1000>; 3491 3492 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3493 3494 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3495 3496 operating-points-v2 = <&llcc_bwmon_opp_table>; 3497 3498 llcc_bwmon_opp_table: opp-table { 3499 compatible = "operating-points-v2"; 3500 3501 opp-0 { 3502 opp-peak-kBps = <800000>; 3503 }; 3504 opp-1 { 3505 opp-peak-kBps = <1804000>; 3506 }; 3507 opp-2 { 3508 opp-peak-kBps = <2188000>; 3509 }; 3510 opp-3 { 3511 opp-peak-kBps = <3072000>; 3512 }; 3513 opp-4 { 3514 opp-peak-kBps = <4068000>; 3515 }; 3516 opp-5 { 3517 opp-peak-kBps = <6220000>; 3518 }; 3519 opp-6 { 3520 opp-peak-kBps = <6832000>; 3521 }; 3522 opp-7 { 3523 opp-peak-kBps = <8532000>; 3524 }; 3525 }; 3526 }; 3527 3528 pmu@90b6400 { 3529 compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon"; 3530 reg = <0 0x090b6400 0 0x600>; 3531 3532 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3533 3534 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3535 operating-points-v2 = <&cpu_bwmon_opp_table>; 3536 3537 cpu_bwmon_opp_table: opp-table { 3538 compatible = "operating-points-v2"; 3539 3540 opp-0 { 3541 opp-peak-kBps = <2400000>; 3542 }; 3543 opp-1 { 3544 opp-peak-kBps = <4800000>; 3545 }; 3546 opp-2 { 3547 opp-peak-kBps = <7456000>; 3548 }; 3549 opp-3 { 3550 opp-peak-kBps = <9600000>; 3551 }; 3552 opp-4 { 3553 opp-peak-kBps = <12896000>; 3554 }; 3555 opp-5 { 3556 opp-peak-kBps = <14928000>; 3557 }; 3558 opp-6 { 3559 opp-peak-kBps = <17056000>; 3560 }; 3561 }; 3562 }; 3563 3564 dc_noc: interconnect@90e0000 { 3565 reg = <0 0x090e0000 0 0x5080>; 3566 compatible = "qcom,sc7280-dc-noc"; 3567 #interconnect-cells = <2>; 3568 qcom,bcm-voters = <&apps_bcm_voter>; 3569 }; 3570 3571 gem_noc: interconnect@9100000 { 3572 reg = <0 0x9100000 0 0xe2200>; 3573 compatible = "qcom,sc7280-gem-noc"; 3574 #interconnect-cells = <2>; 3575 qcom,bcm-voters = <&apps_bcm_voter>; 3576 }; 3577 3578 system-cache-controller@9200000 { 3579 compatible = "qcom,sc7280-llcc"; 3580 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 3581 reg-names = "llcc_base", "llcc_broadcast_base"; 3582 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3583 }; 3584 3585 eud: eud@88e0000 { 3586 compatible = "qcom,sc7280-eud","qcom,eud"; 3587 reg = <0 0x88e0000 0 0x2000>, 3588 <0 0x88e2000 0 0x1000>; 3589 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3590 ports { 3591 port@0 { 3592 eud_ep: endpoint { 3593 remote-endpoint = <&usb2_role_switch>; 3594 }; 3595 }; 3596 port@1 { 3597 eud_con: endpoint { 3598 remote-endpoint = <&con_eud>; 3599 }; 3600 }; 3601 }; 3602 }; 3603 3604 eud_typec: connector { 3605 compatible = "usb-c-connector"; 3606 ports { 3607 port@0 { 3608 con_eud: endpoint { 3609 remote-endpoint = <&eud_con>; 3610 }; 3611 }; 3612 }; 3613 }; 3614 3615 nsp_noc: interconnect@a0c0000 { 3616 reg = <0 0x0a0c0000 0 0x10000>; 3617 compatible = "qcom,sc7280-nsp-noc"; 3618 #interconnect-cells = <2>; 3619 qcom,bcm-voters = <&apps_bcm_voter>; 3620 }; 3621 3622 usb_1: usb@a6f8800 { 3623 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3624 reg = <0 0x0a6f8800 0 0x400>; 3625 status = "disabled"; 3626 #address-cells = <2>; 3627 #size-cells = <2>; 3628 ranges; 3629 dma-ranges; 3630 3631 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3632 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3633 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3634 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3635 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3636 clock-names = "cfg_noc", 3637 "core", 3638 "iface", 3639 "sleep", 3640 "mock_utmi"; 3641 3642 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3643 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3644 assigned-clock-rates = <19200000>, <200000000>; 3645 3646 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3647 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3648 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3649 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3650 interrupt-names = "hs_phy_irq", 3651 "dp_hs_phy_irq", 3652 "dm_hs_phy_irq", 3653 "ss_phy_irq"; 3654 3655 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3656 required-opps = <&rpmhpd_opp_nom>; 3657 3658 resets = <&gcc GCC_USB30_PRIM_BCR>; 3659 3660 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3661 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3662 interconnect-names = "usb-ddr", "apps-usb"; 3663 3664 wakeup-source; 3665 3666 usb_1_dwc3: usb@a600000 { 3667 compatible = "snps,dwc3"; 3668 reg = <0 0x0a600000 0 0xe000>; 3669 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3670 iommus = <&apps_smmu 0xe0 0x0>; 3671 snps,dis_u2_susphy_quirk; 3672 snps,dis_enblslpm_quirk; 3673 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3674 phy-names = "usb2-phy", "usb3-phy"; 3675 maximum-speed = "super-speed"; 3676 }; 3677 }; 3678 3679 venus: video-codec@aa00000 { 3680 compatible = "qcom,sc7280-venus"; 3681 reg = <0 0x0aa00000 0 0xd0600>; 3682 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3683 3684 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3685 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3686 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3687 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3688 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3689 clock-names = "core", "bus", "iface", 3690 "vcodec_core", "vcodec_bus"; 3691 3692 power-domains = <&videocc MVSC_GDSC>, 3693 <&videocc MVS0_GDSC>, 3694 <&rpmhpd SC7280_CX>; 3695 power-domain-names = "venus", "vcodec0", "cx"; 3696 operating-points-v2 = <&venus_opp_table>; 3697 3698 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3699 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3700 interconnect-names = "cpu-cfg", "video-mem"; 3701 3702 iommus = <&apps_smmu 0x2180 0x20>, 3703 <&apps_smmu 0x2184 0x20>; 3704 memory-region = <&video_mem>; 3705 3706 video-decoder { 3707 compatible = "venus-decoder"; 3708 }; 3709 3710 video-encoder { 3711 compatible = "venus-encoder"; 3712 }; 3713 3714 video-firmware { 3715 iommus = <&apps_smmu 0x21a2 0x0>; 3716 }; 3717 3718 venus_opp_table: opp-table { 3719 compatible = "operating-points-v2"; 3720 3721 opp-133330000 { 3722 opp-hz = /bits/ 64 <133330000>; 3723 required-opps = <&rpmhpd_opp_low_svs>; 3724 }; 3725 3726 opp-240000000 { 3727 opp-hz = /bits/ 64 <240000000>; 3728 required-opps = <&rpmhpd_opp_svs>; 3729 }; 3730 3731 opp-335000000 { 3732 opp-hz = /bits/ 64 <335000000>; 3733 required-opps = <&rpmhpd_opp_svs_l1>; 3734 }; 3735 3736 opp-424000000 { 3737 opp-hz = /bits/ 64 <424000000>; 3738 required-opps = <&rpmhpd_opp_nom>; 3739 }; 3740 3741 opp-460000048 { 3742 opp-hz = /bits/ 64 <460000048>; 3743 required-opps = <&rpmhpd_opp_turbo>; 3744 }; 3745 }; 3746 3747 }; 3748 3749 videocc: clock-controller@aaf0000 { 3750 compatible = "qcom,sc7280-videocc"; 3751 reg = <0 0xaaf0000 0 0x10000>; 3752 clocks = <&rpmhcc RPMH_CXO_CLK>, 3753 <&rpmhcc RPMH_CXO_CLK_A>; 3754 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3755 #clock-cells = <1>; 3756 #reset-cells = <1>; 3757 #power-domain-cells = <1>; 3758 }; 3759 3760 camcc: clock-controller@ad00000 { 3761 compatible = "qcom,sc7280-camcc"; 3762 reg = <0 0x0ad00000 0 0x10000>; 3763 clocks = <&rpmhcc RPMH_CXO_CLK>, 3764 <&rpmhcc RPMH_CXO_CLK_A>, 3765 <&sleep_clk>; 3766 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3767 #clock-cells = <1>; 3768 #reset-cells = <1>; 3769 #power-domain-cells = <1>; 3770 }; 3771 3772 dispcc: clock-controller@af00000 { 3773 compatible = "qcom,sc7280-dispcc"; 3774 reg = <0 0xaf00000 0 0x20000>; 3775 clocks = <&rpmhcc RPMH_CXO_CLK>, 3776 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3777 <&mdss_dsi_phy 0>, 3778 <&mdss_dsi_phy 1>, 3779 <&dp_phy 0>, 3780 <&dp_phy 1>, 3781 <&mdss_edp_phy 0>, 3782 <&mdss_edp_phy 1>; 3783 clock-names = "bi_tcxo", 3784 "gcc_disp_gpll0_clk", 3785 "dsi0_phy_pll_out_byteclk", 3786 "dsi0_phy_pll_out_dsiclk", 3787 "dp_phy_pll_link_clk", 3788 "dp_phy_pll_vco_div_clk", 3789 "edp_phy_pll_link_clk", 3790 "edp_phy_pll_vco_div_clk"; 3791 #clock-cells = <1>; 3792 #reset-cells = <1>; 3793 #power-domain-cells = <1>; 3794 }; 3795 3796 mdss: display-subsystem@ae00000 { 3797 compatible = "qcom,sc7280-mdss"; 3798 reg = <0 0x0ae00000 0 0x1000>; 3799 reg-names = "mdss"; 3800 3801 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3802 3803 clocks = <&gcc GCC_DISP_AHB_CLK>, 3804 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3805 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3806 clock-names = "iface", 3807 "ahb", 3808 "core"; 3809 3810 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3811 interrupt-controller; 3812 #interrupt-cells = <1>; 3813 3814 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3815 interconnect-names = "mdp0-mem"; 3816 3817 iommus = <&apps_smmu 0x900 0x402>; 3818 3819 #address-cells = <2>; 3820 #size-cells = <2>; 3821 ranges; 3822 3823 status = "disabled"; 3824 3825 mdss_mdp: display-controller@ae01000 { 3826 compatible = "qcom,sc7280-dpu"; 3827 reg = <0 0x0ae01000 0 0x8f030>, 3828 <0 0x0aeb0000 0 0x2008>; 3829 reg-names = "mdp", "vbif"; 3830 3831 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3832 <&gcc GCC_DISP_SF_AXI_CLK>, 3833 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3834 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3835 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3836 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3837 clock-names = "bus", 3838 "nrt_bus", 3839 "iface", 3840 "lut", 3841 "core", 3842 "vsync"; 3843 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3844 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3845 assigned-clock-rates = <19200000>, 3846 <19200000>; 3847 operating-points-v2 = <&mdp_opp_table>; 3848 power-domains = <&rpmhpd SC7280_CX>; 3849 3850 interrupt-parent = <&mdss>; 3851 interrupts = <0>; 3852 3853 status = "disabled"; 3854 3855 ports { 3856 #address-cells = <1>; 3857 #size-cells = <0>; 3858 3859 port@0 { 3860 reg = <0>; 3861 dpu_intf1_out: endpoint { 3862 remote-endpoint = <&dsi0_in>; 3863 }; 3864 }; 3865 3866 port@1 { 3867 reg = <1>; 3868 dpu_intf5_out: endpoint { 3869 remote-endpoint = <&edp_in>; 3870 }; 3871 }; 3872 3873 port@2 { 3874 reg = <2>; 3875 dpu_intf0_out: endpoint { 3876 remote-endpoint = <&dp_in>; 3877 }; 3878 }; 3879 }; 3880 3881 mdp_opp_table: opp-table { 3882 compatible = "operating-points-v2"; 3883 3884 opp-200000000 { 3885 opp-hz = /bits/ 64 <200000000>; 3886 required-opps = <&rpmhpd_opp_low_svs>; 3887 }; 3888 3889 opp-300000000 { 3890 opp-hz = /bits/ 64 <300000000>; 3891 required-opps = <&rpmhpd_opp_svs>; 3892 }; 3893 3894 opp-380000000 { 3895 opp-hz = /bits/ 64 <380000000>; 3896 required-opps = <&rpmhpd_opp_svs_l1>; 3897 }; 3898 3899 opp-506666667 { 3900 opp-hz = /bits/ 64 <506666667>; 3901 required-opps = <&rpmhpd_opp_nom>; 3902 }; 3903 }; 3904 }; 3905 3906 mdss_dsi: dsi@ae94000 { 3907 compatible = "qcom,mdss-dsi-ctrl"; 3908 reg = <0 0x0ae94000 0 0x400>; 3909 reg-names = "dsi_ctrl"; 3910 3911 interrupt-parent = <&mdss>; 3912 interrupts = <4>; 3913 3914 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3915 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3916 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3917 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3918 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3919 <&gcc GCC_DISP_HF_AXI_CLK>; 3920 clock-names = "byte", 3921 "byte_intf", 3922 "pixel", 3923 "core", 3924 "iface", 3925 "bus"; 3926 3927 operating-points-v2 = <&dsi_opp_table>; 3928 power-domains = <&rpmhpd SC7280_CX>; 3929 3930 phys = <&mdss_dsi_phy>; 3931 phy-names = "dsi"; 3932 3933 #address-cells = <1>; 3934 #size-cells = <0>; 3935 3936 status = "disabled"; 3937 3938 ports { 3939 #address-cells = <1>; 3940 #size-cells = <0>; 3941 3942 port@0 { 3943 reg = <0>; 3944 dsi0_in: endpoint { 3945 remote-endpoint = <&dpu_intf1_out>; 3946 }; 3947 }; 3948 3949 port@1 { 3950 reg = <1>; 3951 dsi0_out: endpoint { 3952 }; 3953 }; 3954 }; 3955 3956 dsi_opp_table: opp-table { 3957 compatible = "operating-points-v2"; 3958 3959 opp-187500000 { 3960 opp-hz = /bits/ 64 <187500000>; 3961 required-opps = <&rpmhpd_opp_low_svs>; 3962 }; 3963 3964 opp-300000000 { 3965 opp-hz = /bits/ 64 <300000000>; 3966 required-opps = <&rpmhpd_opp_svs>; 3967 }; 3968 3969 opp-358000000 { 3970 opp-hz = /bits/ 64 <358000000>; 3971 required-opps = <&rpmhpd_opp_svs_l1>; 3972 }; 3973 }; 3974 }; 3975 3976 mdss_dsi_phy: phy@ae94400 { 3977 compatible = "qcom,sc7280-dsi-phy-7nm"; 3978 reg = <0 0x0ae94400 0 0x200>, 3979 <0 0x0ae94600 0 0x280>, 3980 <0 0x0ae94900 0 0x280>; 3981 reg-names = "dsi_phy", 3982 "dsi_phy_lane", 3983 "dsi_pll"; 3984 3985 #clock-cells = <1>; 3986 #phy-cells = <0>; 3987 3988 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3989 <&rpmhcc RPMH_CXO_CLK>; 3990 clock-names = "iface", "ref"; 3991 3992 status = "disabled"; 3993 }; 3994 3995 mdss_edp: edp@aea0000 { 3996 compatible = "qcom,sc7280-edp"; 3997 pinctrl-names = "default"; 3998 pinctrl-0 = <&edp_hot_plug_det>; 3999 4000 reg = <0 0xaea0000 0 0x200>, 4001 <0 0xaea0200 0 0x200>, 4002 <0 0xaea0400 0 0xc00>, 4003 <0 0xaea1000 0 0x400>; 4004 4005 interrupt-parent = <&mdss>; 4006 interrupts = <14>; 4007 4008 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4009 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4010 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4011 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4012 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4013 clock-names = "core_iface", 4014 "core_aux", 4015 "ctrl_link", 4016 "ctrl_link_iface", 4017 "stream_pixel"; 4018 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4019 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4020 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4021 4022 phys = <&mdss_edp_phy>; 4023 phy-names = "dp"; 4024 4025 operating-points-v2 = <&edp_opp_table>; 4026 power-domains = <&rpmhpd SC7280_CX>; 4027 4028 status = "disabled"; 4029 4030 ports { 4031 #address-cells = <1>; 4032 #size-cells = <0>; 4033 4034 port@0 { 4035 reg = <0>; 4036 edp_in: endpoint { 4037 remote-endpoint = <&dpu_intf5_out>; 4038 }; 4039 }; 4040 4041 port@1 { 4042 reg = <1>; 4043 mdss_edp_out: endpoint { }; 4044 }; 4045 }; 4046 4047 edp_opp_table: opp-table { 4048 compatible = "operating-points-v2"; 4049 4050 opp-160000000 { 4051 opp-hz = /bits/ 64 <160000000>; 4052 required-opps = <&rpmhpd_opp_low_svs>; 4053 }; 4054 4055 opp-270000000 { 4056 opp-hz = /bits/ 64 <270000000>; 4057 required-opps = <&rpmhpd_opp_svs>; 4058 }; 4059 4060 opp-540000000 { 4061 opp-hz = /bits/ 64 <540000000>; 4062 required-opps = <&rpmhpd_opp_nom>; 4063 }; 4064 4065 opp-810000000 { 4066 opp-hz = /bits/ 64 <810000000>; 4067 required-opps = <&rpmhpd_opp_nom>; 4068 }; 4069 }; 4070 }; 4071 4072 mdss_edp_phy: phy@aec2a00 { 4073 compatible = "qcom,sc7280-edp-phy"; 4074 4075 reg = <0 0xaec2a00 0 0x19c>, 4076 <0 0xaec2200 0 0xa0>, 4077 <0 0xaec2600 0 0xa0>, 4078 <0 0xaec2000 0 0x1c0>; 4079 4080 clocks = <&rpmhcc RPMH_CXO_CLK>, 4081 <&gcc GCC_EDP_CLKREF_EN>; 4082 clock-names = "aux", 4083 "cfg_ahb"; 4084 4085 #clock-cells = <1>; 4086 #phy-cells = <0>; 4087 4088 status = "disabled"; 4089 }; 4090 4091 mdss_dp: displayport-controller@ae90000 { 4092 compatible = "qcom,sc7280-dp"; 4093 4094 reg = <0 0xae90000 0 0x200>, 4095 <0 0xae90200 0 0x200>, 4096 <0 0xae90400 0 0xc00>, 4097 <0 0xae91000 0 0x400>, 4098 <0 0xae91400 0 0x400>; 4099 4100 interrupt-parent = <&mdss>; 4101 interrupts = <12>; 4102 4103 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4104 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4105 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4106 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4107 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4108 clock-names = "core_iface", 4109 "core_aux", 4110 "ctrl_link", 4111 "ctrl_link_iface", 4112 "stream_pixel"; 4113 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4114 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4115 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4116 phys = <&dp_phy>; 4117 phy-names = "dp"; 4118 4119 operating-points-v2 = <&dp_opp_table>; 4120 power-domains = <&rpmhpd SC7280_CX>; 4121 4122 #sound-dai-cells = <0>; 4123 4124 status = "disabled"; 4125 4126 ports { 4127 #address-cells = <1>; 4128 #size-cells = <0>; 4129 4130 port@0 { 4131 reg = <0>; 4132 dp_in: endpoint { 4133 remote-endpoint = <&dpu_intf0_out>; 4134 }; 4135 }; 4136 4137 port@1 { 4138 reg = <1>; 4139 dp_out: endpoint { }; 4140 }; 4141 }; 4142 4143 dp_opp_table: opp-table { 4144 compatible = "operating-points-v2"; 4145 4146 opp-160000000 { 4147 opp-hz = /bits/ 64 <160000000>; 4148 required-opps = <&rpmhpd_opp_low_svs>; 4149 }; 4150 4151 opp-270000000 { 4152 opp-hz = /bits/ 64 <270000000>; 4153 required-opps = <&rpmhpd_opp_svs>; 4154 }; 4155 4156 opp-540000000 { 4157 opp-hz = /bits/ 64 <540000000>; 4158 required-opps = <&rpmhpd_opp_svs_l1>; 4159 }; 4160 4161 opp-810000000 { 4162 opp-hz = /bits/ 64 <810000000>; 4163 required-opps = <&rpmhpd_opp_nom>; 4164 }; 4165 }; 4166 }; 4167 }; 4168 4169 pdc: interrupt-controller@b220000 { 4170 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4171 reg = <0 0x0b220000 0 0x30000>; 4172 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4173 <55 306 4>, <59 312 3>, <62 374 2>, 4174 <64 434 2>, <66 438 3>, <69 86 1>, 4175 <70 520 54>, <124 609 31>, <155 63 1>, 4176 <156 716 12>; 4177 #interrupt-cells = <2>; 4178 interrupt-parent = <&intc>; 4179 interrupt-controller; 4180 }; 4181 4182 pdc_reset: reset-controller@b5e0000 { 4183 compatible = "qcom,sc7280-pdc-global"; 4184 reg = <0 0x0b5e0000 0 0x20000>; 4185 #reset-cells = <1>; 4186 }; 4187 4188 tsens0: thermal-sensor@c263000 { 4189 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4190 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4191 <0 0x0c222000 0 0x1ff>; /* SROT */ 4192 #qcom,sensors = <15>; 4193 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4194 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4195 interrupt-names = "uplow","critical"; 4196 #thermal-sensor-cells = <1>; 4197 }; 4198 4199 tsens1: thermal-sensor@c265000 { 4200 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4201 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4202 <0 0x0c223000 0 0x1ff>; /* SROT */ 4203 #qcom,sensors = <12>; 4204 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4205 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4206 interrupt-names = "uplow","critical"; 4207 #thermal-sensor-cells = <1>; 4208 }; 4209 4210 aoss_reset: reset-controller@c2a0000 { 4211 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4212 reg = <0 0x0c2a0000 0 0x31000>; 4213 #reset-cells = <1>; 4214 }; 4215 4216 aoss_qmp: power-controller@c300000 { 4217 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4218 reg = <0 0x0c300000 0 0x400>; 4219 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4220 IPCC_MPROC_SIGNAL_GLINK_QMP 4221 IRQ_TYPE_EDGE_RISING>; 4222 mboxes = <&ipcc IPCC_CLIENT_AOP 4223 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4224 4225 #clock-cells = <0>; 4226 }; 4227 4228 sram@c3f0000 { 4229 compatible = "qcom,rpmh-stats"; 4230 reg = <0 0x0c3f0000 0 0x400>; 4231 }; 4232 4233 spmi_bus: spmi@c440000 { 4234 compatible = "qcom,spmi-pmic-arb"; 4235 reg = <0 0x0c440000 0 0x1100>, 4236 <0 0x0c600000 0 0x2000000>, 4237 <0 0x0e600000 0 0x100000>, 4238 <0 0x0e700000 0 0xa0000>, 4239 <0 0x0c40a000 0 0x26000>; 4240 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4241 interrupt-names = "periph_irq"; 4242 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4243 qcom,ee = <0>; 4244 qcom,channel = <0>; 4245 #address-cells = <1>; 4246 #size-cells = <1>; 4247 interrupt-controller; 4248 #interrupt-cells = <4>; 4249 }; 4250 4251 tlmm: pinctrl@f100000 { 4252 compatible = "qcom,sc7280-pinctrl"; 4253 reg = <0 0x0f100000 0 0x300000>; 4254 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4255 gpio-controller; 4256 #gpio-cells = <2>; 4257 interrupt-controller; 4258 #interrupt-cells = <2>; 4259 gpio-ranges = <&tlmm 0 0 175>; 4260 wakeup-parent = <&pdc>; 4261 4262 dp_hot_plug_det: dp-hot-plug-det-pins { 4263 pins = "gpio47"; 4264 function = "dp_hot"; 4265 }; 4266 4267 edp_hot_plug_det: edp-hot-plug-det-pins { 4268 pins = "gpio60"; 4269 function = "edp_hot"; 4270 }; 4271 4272 mi2s0_data0: mi2s0-data0-pins { 4273 pins = "gpio98"; 4274 function = "mi2s0_data0"; 4275 }; 4276 4277 mi2s0_data1: mi2s0-data1-pins { 4278 pins = "gpio99"; 4279 function = "mi2s0_data1"; 4280 }; 4281 4282 mi2s0_mclk: mi2s0-mclk-pins { 4283 pins = "gpio96"; 4284 function = "pri_mi2s"; 4285 }; 4286 4287 mi2s0_sclk: mi2s0-sclk-pins { 4288 pins = "gpio97"; 4289 function = "mi2s0_sck"; 4290 }; 4291 4292 mi2s0_ws: mi2s0-ws-pins { 4293 pins = "gpio100"; 4294 function = "mi2s0_ws"; 4295 }; 4296 4297 mi2s1_data0: mi2s1-data0-pins { 4298 pins = "gpio107"; 4299 function = "mi2s1_data0"; 4300 }; 4301 4302 mi2s1_sclk: mi2s1-sclk-pins { 4303 pins = "gpio106"; 4304 function = "mi2s1_sck"; 4305 }; 4306 4307 mi2s1_ws: mi2s1-ws-pins { 4308 pins = "gpio108"; 4309 function = "mi2s1_ws"; 4310 }; 4311 4312 pcie1_clkreq_n: pcie1-clkreq-n-pins { 4313 pins = "gpio79"; 4314 function = "pcie1_clkreqn"; 4315 }; 4316 4317 qspi_clk: qspi-clk-pins { 4318 pins = "gpio14"; 4319 function = "qspi_clk"; 4320 }; 4321 4322 qspi_cs0: qspi-cs0-pins { 4323 pins = "gpio15"; 4324 function = "qspi_cs"; 4325 }; 4326 4327 qspi_cs1: qspi-cs1-pins { 4328 pins = "gpio19"; 4329 function = "qspi_cs"; 4330 }; 4331 4332 qspi_data01: qspi-data01-pins { 4333 pins = "gpio12", "gpio13"; 4334 function = "qspi_data"; 4335 }; 4336 4337 qspi_data12: qspi-data12-pins { 4338 pins = "gpio16", "gpio17"; 4339 function = "qspi_data"; 4340 }; 4341 4342 qup_i2c0_data_clk: qup-i2c0-data-clk-pins { 4343 pins = "gpio0", "gpio1"; 4344 function = "qup00"; 4345 }; 4346 4347 qup_i2c1_data_clk: qup-i2c1-data-clk-pins { 4348 pins = "gpio4", "gpio5"; 4349 function = "qup01"; 4350 }; 4351 4352 qup_i2c2_data_clk: qup-i2c2-data-clk-pins { 4353 pins = "gpio8", "gpio9"; 4354 function = "qup02"; 4355 }; 4356 4357 qup_i2c3_data_clk: qup-i2c3-data-clk-pins { 4358 pins = "gpio12", "gpio13"; 4359 function = "qup03"; 4360 }; 4361 4362 qup_i2c4_data_clk: qup-i2c4-data-clk-pins { 4363 pins = "gpio16", "gpio17"; 4364 function = "qup04"; 4365 }; 4366 4367 qup_i2c5_data_clk: qup-i2c5-data-clk-pins { 4368 pins = "gpio20", "gpio21"; 4369 function = "qup05"; 4370 }; 4371 4372 qup_i2c6_data_clk: qup-i2c6-data-clk-pins { 4373 pins = "gpio24", "gpio25"; 4374 function = "qup06"; 4375 }; 4376 4377 qup_i2c7_data_clk: qup-i2c7-data-clk-pins { 4378 pins = "gpio28", "gpio29"; 4379 function = "qup07"; 4380 }; 4381 4382 qup_i2c8_data_clk: qup-i2c8-data-clk-pins { 4383 pins = "gpio32", "gpio33"; 4384 function = "qup10"; 4385 }; 4386 4387 qup_i2c9_data_clk: qup-i2c9-data-clk-pins { 4388 pins = "gpio36", "gpio37"; 4389 function = "qup11"; 4390 }; 4391 4392 qup_i2c10_data_clk: qup-i2c10-data-clk-pins { 4393 pins = "gpio40", "gpio41"; 4394 function = "qup12"; 4395 }; 4396 4397 qup_i2c11_data_clk: qup-i2c11-data-clk-pins { 4398 pins = "gpio44", "gpio45"; 4399 function = "qup13"; 4400 }; 4401 4402 qup_i2c12_data_clk: qup-i2c12-data-clk-pins { 4403 pins = "gpio48", "gpio49"; 4404 function = "qup14"; 4405 }; 4406 4407 qup_i2c13_data_clk: qup-i2c13-data-clk-pins { 4408 pins = "gpio52", "gpio53"; 4409 function = "qup15"; 4410 }; 4411 4412 qup_i2c14_data_clk: qup-i2c14-data-clk-pins { 4413 pins = "gpio56", "gpio57"; 4414 function = "qup16"; 4415 }; 4416 4417 qup_i2c15_data_clk: qup-i2c15-data-clk-pins { 4418 pins = "gpio60", "gpio61"; 4419 function = "qup17"; 4420 }; 4421 4422 qup_spi0_data_clk: qup-spi0-data-clk-pins { 4423 pins = "gpio0", "gpio1", "gpio2"; 4424 function = "qup00"; 4425 }; 4426 4427 qup_spi0_cs: qup-spi0-cs-pins { 4428 pins = "gpio3"; 4429 function = "qup00"; 4430 }; 4431 4432 qup_spi0_cs_gpio: qup-spi0-cs-gpio-pins { 4433 pins = "gpio3"; 4434 function = "gpio"; 4435 }; 4436 4437 qup_spi1_data_clk: qup-spi1-data-clk-pins { 4438 pins = "gpio4", "gpio5", "gpio6"; 4439 function = "qup01"; 4440 }; 4441 4442 qup_spi1_cs: qup-spi1-cs-pins { 4443 pins = "gpio7"; 4444 function = "qup01"; 4445 }; 4446 4447 qup_spi1_cs_gpio: qup-spi1-cs-gpio-pins { 4448 pins = "gpio7"; 4449 function = "gpio"; 4450 }; 4451 4452 qup_spi2_data_clk: qup-spi2-data-clk-pins { 4453 pins = "gpio8", "gpio9", "gpio10"; 4454 function = "qup02"; 4455 }; 4456 4457 qup_spi2_cs: qup-spi2-cs-pins { 4458 pins = "gpio11"; 4459 function = "qup02"; 4460 }; 4461 4462 qup_spi2_cs_gpio: qup-spi2-cs-gpio-pins { 4463 pins = "gpio11"; 4464 function = "gpio"; 4465 }; 4466 4467 qup_spi3_data_clk: qup-spi3-data-clk-pins { 4468 pins = "gpio12", "gpio13", "gpio14"; 4469 function = "qup03"; 4470 }; 4471 4472 qup_spi3_cs: qup-spi3-cs-pins { 4473 pins = "gpio15"; 4474 function = "qup03"; 4475 }; 4476 4477 qup_spi3_cs_gpio: qup-spi3-cs-gpio-pins { 4478 pins = "gpio15"; 4479 function = "gpio"; 4480 }; 4481 4482 qup_spi4_data_clk: qup-spi4-data-clk-pins { 4483 pins = "gpio16", "gpio17", "gpio18"; 4484 function = "qup04"; 4485 }; 4486 4487 qup_spi4_cs: qup-spi4-cs-pins { 4488 pins = "gpio19"; 4489 function = "qup04"; 4490 }; 4491 4492 qup_spi4_cs_gpio: qup-spi4-cs-gpio-pins { 4493 pins = "gpio19"; 4494 function = "gpio"; 4495 }; 4496 4497 qup_spi5_data_clk: qup-spi5-data-clk-pins { 4498 pins = "gpio20", "gpio21", "gpio22"; 4499 function = "qup05"; 4500 }; 4501 4502 qup_spi5_cs: qup-spi5-cs-pins { 4503 pins = "gpio23"; 4504 function = "qup05"; 4505 }; 4506 4507 qup_spi5_cs_gpio: qup-spi5-cs-gpio-pins { 4508 pins = "gpio23"; 4509 function = "gpio"; 4510 }; 4511 4512 qup_spi6_data_clk: qup-spi6-data-clk-pins { 4513 pins = "gpio24", "gpio25", "gpio26"; 4514 function = "qup06"; 4515 }; 4516 4517 qup_spi6_cs: qup-spi6-cs-pins { 4518 pins = "gpio27"; 4519 function = "qup06"; 4520 }; 4521 4522 qup_spi6_cs_gpio: qup-spi6-cs-gpio-pins { 4523 pins = "gpio27"; 4524 function = "gpio"; 4525 }; 4526 4527 qup_spi7_data_clk: qup-spi7-data-clk-pins { 4528 pins = "gpio28", "gpio29", "gpio30"; 4529 function = "qup07"; 4530 }; 4531 4532 qup_spi7_cs: qup-spi7-cs-pins { 4533 pins = "gpio31"; 4534 function = "qup07"; 4535 }; 4536 4537 qup_spi7_cs_gpio: qup-spi7-cs-gpio-pins { 4538 pins = "gpio31"; 4539 function = "gpio"; 4540 }; 4541 4542 qup_spi8_data_clk: qup-spi8-data-clk-pins { 4543 pins = "gpio32", "gpio33", "gpio34"; 4544 function = "qup10"; 4545 }; 4546 4547 qup_spi8_cs: qup-spi8-cs-pins { 4548 pins = "gpio35"; 4549 function = "qup10"; 4550 }; 4551 4552 qup_spi8_cs_gpio: qup-spi8-cs-gpio-pins { 4553 pins = "gpio35"; 4554 function = "gpio"; 4555 }; 4556 4557 qup_spi9_data_clk: qup-spi9-data-clk-pins { 4558 pins = "gpio36", "gpio37", "gpio38"; 4559 function = "qup11"; 4560 }; 4561 4562 qup_spi9_cs: qup-spi9-cs-pins { 4563 pins = "gpio39"; 4564 function = "qup11"; 4565 }; 4566 4567 qup_spi9_cs_gpio: qup-spi9-cs-gpio-pins { 4568 pins = "gpio39"; 4569 function = "gpio"; 4570 }; 4571 4572 qup_spi10_data_clk: qup-spi10-data-clk-pins { 4573 pins = "gpio40", "gpio41", "gpio42"; 4574 function = "qup12"; 4575 }; 4576 4577 qup_spi10_cs: qup-spi10-cs-pins { 4578 pins = "gpio43"; 4579 function = "qup12"; 4580 }; 4581 4582 qup_spi10_cs_gpio: qup-spi10-cs-gpio-pins { 4583 pins = "gpio43"; 4584 function = "gpio"; 4585 }; 4586 4587 qup_spi11_data_clk: qup-spi11-data-clk-pins { 4588 pins = "gpio44", "gpio45", "gpio46"; 4589 function = "qup13"; 4590 }; 4591 4592 qup_spi11_cs: qup-spi11-cs-pins { 4593 pins = "gpio47"; 4594 function = "qup13"; 4595 }; 4596 4597 qup_spi11_cs_gpio: qup-spi11-cs-gpio-pins { 4598 pins = "gpio47"; 4599 function = "gpio"; 4600 }; 4601 4602 qup_spi12_data_clk: qup-spi12-data-clk-pins { 4603 pins = "gpio48", "gpio49", "gpio50"; 4604 function = "qup14"; 4605 }; 4606 4607 qup_spi12_cs: qup-spi12-cs-pins { 4608 pins = "gpio51"; 4609 function = "qup14"; 4610 }; 4611 4612 qup_spi12_cs_gpio: qup-spi12-cs-gpio-pins { 4613 pins = "gpio51"; 4614 function = "gpio"; 4615 }; 4616 4617 qup_spi13_data_clk: qup-spi13-data-clk-pins { 4618 pins = "gpio52", "gpio53", "gpio54"; 4619 function = "qup15"; 4620 }; 4621 4622 qup_spi13_cs: qup-spi13-cs-pins { 4623 pins = "gpio55"; 4624 function = "qup15"; 4625 }; 4626 4627 qup_spi13_cs_gpio: qup-spi13-cs-gpio-pins { 4628 pins = "gpio55"; 4629 function = "gpio"; 4630 }; 4631 4632 qup_spi14_data_clk: qup-spi14-data-clk-pins { 4633 pins = "gpio56", "gpio57", "gpio58"; 4634 function = "qup16"; 4635 }; 4636 4637 qup_spi14_cs: qup-spi14-cs-pins { 4638 pins = "gpio59"; 4639 function = "qup16"; 4640 }; 4641 4642 qup_spi14_cs_gpio: qup-spi14-cs-gpio-pins { 4643 pins = "gpio59"; 4644 function = "gpio"; 4645 }; 4646 4647 qup_spi15_data_clk: qup-spi15-data-clk-pins { 4648 pins = "gpio60", "gpio61", "gpio62"; 4649 function = "qup17"; 4650 }; 4651 4652 qup_spi15_cs: qup-spi15-cs-pins { 4653 pins = "gpio63"; 4654 function = "qup17"; 4655 }; 4656 4657 qup_spi15_cs_gpio: qup-spi15-cs-gpio-pins { 4658 pins = "gpio63"; 4659 function = "gpio"; 4660 }; 4661 4662 qup_uart0_cts: qup-uart0-cts-pins { 4663 pins = "gpio0"; 4664 function = "qup00"; 4665 }; 4666 4667 qup_uart0_rts: qup-uart0-rts-pins { 4668 pins = "gpio1"; 4669 function = "qup00"; 4670 }; 4671 4672 qup_uart0_tx: qup-uart0-tx-pins { 4673 pins = "gpio2"; 4674 function = "qup00"; 4675 }; 4676 4677 qup_uart0_rx: qup-uart0-rx-pins { 4678 pins = "gpio3"; 4679 function = "qup00"; 4680 }; 4681 4682 qup_uart1_cts: qup-uart1-cts-pins { 4683 pins = "gpio4"; 4684 function = "qup01"; 4685 }; 4686 4687 qup_uart1_rts: qup-uart1-rts-pins { 4688 pins = "gpio5"; 4689 function = "qup01"; 4690 }; 4691 4692 qup_uart1_tx: qup-uart1-tx-pins { 4693 pins = "gpio6"; 4694 function = "qup01"; 4695 }; 4696 4697 qup_uart1_rx: qup-uart1-rx-pins { 4698 pins = "gpio7"; 4699 function = "qup01"; 4700 }; 4701 4702 qup_uart2_cts: qup-uart2-cts-pins { 4703 pins = "gpio8"; 4704 function = "qup02"; 4705 }; 4706 4707 qup_uart2_rts: qup-uart2-rts-pins { 4708 pins = "gpio9"; 4709 function = "qup02"; 4710 }; 4711 4712 qup_uart2_tx: qup-uart2-tx-pins { 4713 pins = "gpio10"; 4714 function = "qup02"; 4715 }; 4716 4717 qup_uart2_rx: qup-uart2-rx-pins { 4718 pins = "gpio11"; 4719 function = "qup02"; 4720 }; 4721 4722 qup_uart3_cts: qup-uart3-cts-pins { 4723 pins = "gpio12"; 4724 function = "qup03"; 4725 }; 4726 4727 qup_uart3_rts: qup-uart3-rts-pins { 4728 pins = "gpio13"; 4729 function = "qup03"; 4730 }; 4731 4732 qup_uart3_tx: qup-uart3-tx-pins { 4733 pins = "gpio14"; 4734 function = "qup03"; 4735 }; 4736 4737 qup_uart3_rx: qup-uart3-rx-pins { 4738 pins = "gpio15"; 4739 function = "qup03"; 4740 }; 4741 4742 qup_uart4_cts: qup-uart4-cts-pins { 4743 pins = "gpio16"; 4744 function = "qup04"; 4745 }; 4746 4747 qup_uart4_rts: qup-uart4-rts-pins { 4748 pins = "gpio17"; 4749 function = "qup04"; 4750 }; 4751 4752 qup_uart4_tx: qup-uart4-tx-pins { 4753 pins = "gpio18"; 4754 function = "qup04"; 4755 }; 4756 4757 qup_uart4_rx: qup-uart4-rx-pins { 4758 pins = "gpio19"; 4759 function = "qup04"; 4760 }; 4761 4762 qup_uart5_cts: qup-uart5-cts-pins { 4763 pins = "gpio20"; 4764 function = "qup05"; 4765 }; 4766 4767 qup_uart5_rts: qup-uart5-rts-pins { 4768 pins = "gpio21"; 4769 function = "qup05"; 4770 }; 4771 4772 qup_uart5_tx: qup-uart5-tx-pins { 4773 pins = "gpio22"; 4774 function = "qup05"; 4775 }; 4776 4777 qup_uart5_rx: qup-uart5-rx-pins { 4778 pins = "gpio23"; 4779 function = "qup05"; 4780 }; 4781 4782 qup_uart6_cts: qup-uart6-cts-pins { 4783 pins = "gpio24"; 4784 function = "qup06"; 4785 }; 4786 4787 qup_uart6_rts: qup-uart6-rts-pins { 4788 pins = "gpio25"; 4789 function = "qup06"; 4790 }; 4791 4792 qup_uart6_tx: qup-uart6-tx-pins { 4793 pins = "gpio26"; 4794 function = "qup06"; 4795 }; 4796 4797 qup_uart6_rx: qup-uart6-rx-pins { 4798 pins = "gpio27"; 4799 function = "qup06"; 4800 }; 4801 4802 qup_uart7_cts: qup-uart7-cts-pins { 4803 pins = "gpio28"; 4804 function = "qup07"; 4805 }; 4806 4807 qup_uart7_rts: qup-uart7-rts-pins { 4808 pins = "gpio29"; 4809 function = "qup07"; 4810 }; 4811 4812 qup_uart7_tx: qup-uart7-tx-pins { 4813 pins = "gpio30"; 4814 function = "qup07"; 4815 }; 4816 4817 qup_uart7_rx: qup-uart7-rx-pins { 4818 pins = "gpio31"; 4819 function = "qup07"; 4820 }; 4821 4822 qup_uart8_cts: qup-uart8-cts-pins { 4823 pins = "gpio32"; 4824 function = "qup10"; 4825 }; 4826 4827 qup_uart8_rts: qup-uart8-rts-pins { 4828 pins = "gpio33"; 4829 function = "qup10"; 4830 }; 4831 4832 qup_uart8_tx: qup-uart8-tx-pins { 4833 pins = "gpio34"; 4834 function = "qup10"; 4835 }; 4836 4837 qup_uart8_rx: qup-uart8-rx-pins { 4838 pins = "gpio35"; 4839 function = "qup10"; 4840 }; 4841 4842 qup_uart9_cts: qup-uart9-cts-pins { 4843 pins = "gpio36"; 4844 function = "qup11"; 4845 }; 4846 4847 qup_uart9_rts: qup-uart9-rts-pins { 4848 pins = "gpio37"; 4849 function = "qup11"; 4850 }; 4851 4852 qup_uart9_tx: qup-uart9-tx-pins { 4853 pins = "gpio38"; 4854 function = "qup11"; 4855 }; 4856 4857 qup_uart9_rx: qup-uart9-rx-pins { 4858 pins = "gpio39"; 4859 function = "qup11"; 4860 }; 4861 4862 qup_uart10_cts: qup-uart10-cts-pins { 4863 pins = "gpio40"; 4864 function = "qup12"; 4865 }; 4866 4867 qup_uart10_rts: qup-uart10-rts-pins { 4868 pins = "gpio41"; 4869 function = "qup12"; 4870 }; 4871 4872 qup_uart10_tx: qup-uart10-tx-pins { 4873 pins = "gpio42"; 4874 function = "qup12"; 4875 }; 4876 4877 qup_uart10_rx: qup-uart10-rx-pins { 4878 pins = "gpio43"; 4879 function = "qup12"; 4880 }; 4881 4882 qup_uart11_cts: qup-uart11-cts-pins { 4883 pins = "gpio44"; 4884 function = "qup13"; 4885 }; 4886 4887 qup_uart11_rts: qup-uart11-rts-pins { 4888 pins = "gpio45"; 4889 function = "qup13"; 4890 }; 4891 4892 qup_uart11_tx: qup-uart11-tx-pins { 4893 pins = "gpio46"; 4894 function = "qup13"; 4895 }; 4896 4897 qup_uart11_rx: qup-uart11-rx-pins { 4898 pins = "gpio47"; 4899 function = "qup13"; 4900 }; 4901 4902 qup_uart12_cts: qup-uart12-cts-pins { 4903 pins = "gpio48"; 4904 function = "qup14"; 4905 }; 4906 4907 qup_uart12_rts: qup-uart12-rts-pins { 4908 pins = "gpio49"; 4909 function = "qup14"; 4910 }; 4911 4912 qup_uart12_tx: qup-uart12-tx-pins { 4913 pins = "gpio50"; 4914 function = "qup14"; 4915 }; 4916 4917 qup_uart12_rx: qup-uart12-rx-pins { 4918 pins = "gpio51"; 4919 function = "qup14"; 4920 }; 4921 4922 qup_uart13_cts: qup-uart13-cts-pins { 4923 pins = "gpio52"; 4924 function = "qup15"; 4925 }; 4926 4927 qup_uart13_rts: qup-uart13-rts-pins { 4928 pins = "gpio53"; 4929 function = "qup15"; 4930 }; 4931 4932 qup_uart13_tx: qup-uart13-tx-pins { 4933 pins = "gpio54"; 4934 function = "qup15"; 4935 }; 4936 4937 qup_uart13_rx: qup-uart13-rx-pins { 4938 pins = "gpio55"; 4939 function = "qup15"; 4940 }; 4941 4942 qup_uart14_cts: qup-uart14-cts-pins { 4943 pins = "gpio56"; 4944 function = "qup16"; 4945 }; 4946 4947 qup_uart14_rts: qup-uart14-rts-pins { 4948 pins = "gpio57"; 4949 function = "qup16"; 4950 }; 4951 4952 qup_uart14_tx: qup-uart14-tx-pins { 4953 pins = "gpio58"; 4954 function = "qup16"; 4955 }; 4956 4957 qup_uart14_rx: qup-uart14-rx-pins { 4958 pins = "gpio59"; 4959 function = "qup16"; 4960 }; 4961 4962 qup_uart15_cts: qup-uart15-cts-pins { 4963 pins = "gpio60"; 4964 function = "qup17"; 4965 }; 4966 4967 qup_uart15_rts: qup-uart15-rts-pins { 4968 pins = "gpio61"; 4969 function = "qup17"; 4970 }; 4971 4972 qup_uart15_tx: qup-uart15-tx-pins { 4973 pins = "gpio62"; 4974 function = "qup17"; 4975 }; 4976 4977 qup_uart15_rx: qup-uart15-rx-pins { 4978 pins = "gpio63"; 4979 function = "qup17"; 4980 }; 4981 4982 sdc1_clk: sdc1-clk-pins { 4983 pins = "sdc1_clk"; 4984 }; 4985 4986 sdc1_cmd: sdc1-cmd-pins { 4987 pins = "sdc1_cmd"; 4988 }; 4989 4990 sdc1_data: sdc1-data-pins { 4991 pins = "sdc1_data"; 4992 }; 4993 4994 sdc1_rclk: sdc1-rclk-pins { 4995 pins = "sdc1_rclk"; 4996 }; 4997 4998 sdc1_clk_sleep: sdc1-clk-sleep-pins { 4999 pins = "sdc1_clk"; 5000 drive-strength = <2>; 5001 bias-bus-hold; 5002 }; 5003 5004 sdc1_cmd_sleep: sdc1-cmd-sleep-pins { 5005 pins = "sdc1_cmd"; 5006 drive-strength = <2>; 5007 bias-bus-hold; 5008 }; 5009 5010 sdc1_data_sleep: sdc1-data-sleep-pins { 5011 pins = "sdc1_data"; 5012 drive-strength = <2>; 5013 bias-bus-hold; 5014 }; 5015 5016 sdc1_rclk_sleep: sdc1-rclk-sleep-pins { 5017 pins = "sdc1_rclk"; 5018 drive-strength = <2>; 5019 bias-bus-hold; 5020 }; 5021 5022 sdc2_clk: sdc2-clk-pins { 5023 pins = "sdc2_clk"; 5024 }; 5025 5026 sdc2_cmd: sdc2-cmd-pins { 5027 pins = "sdc2_cmd"; 5028 }; 5029 5030 sdc2_data: sdc2-data-pins { 5031 pins = "sdc2_data"; 5032 }; 5033 5034 sdc2_clk_sleep: sdc2-clk-sleep-pins { 5035 pins = "sdc2_clk"; 5036 drive-strength = <2>; 5037 bias-bus-hold; 5038 }; 5039 5040 sdc2_cmd_sleep: sdc2-cmd-sleep-pins { 5041 pins = "sdc2_cmd"; 5042 drive-strength = <2>; 5043 bias-bus-hold; 5044 }; 5045 5046 sdc2_data_sleep: sdc2-data-sleep-pins { 5047 pins = "sdc2_data"; 5048 drive-strength = <2>; 5049 bias-bus-hold; 5050 }; 5051 }; 5052 5053 sram@146a5000 { 5054 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5055 reg = <0 0x146a5000 0 0x6000>; 5056 5057 #address-cells = <1>; 5058 #size-cells = <1>; 5059 5060 ranges = <0 0 0x146a5000 0x6000>; 5061 5062 pil-reloc@594c { 5063 compatible = "qcom,pil-reloc-info"; 5064 reg = <0x594c 0xc8>; 5065 }; 5066 }; 5067 5068 apps_smmu: iommu@15000000 { 5069 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5070 reg = <0 0x15000000 0 0x100000>; 5071 #iommu-cells = <2>; 5072 #global-interrupts = <1>; 5073 dma-coherent; 5074 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5075 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5076 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5077 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5078 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5079 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5080 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5081 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5082 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5083 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5084 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5085 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5086 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5087 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5088 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5089 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5090 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5091 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5092 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5093 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5094 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5095 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5096 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5097 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5098 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5099 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5100 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5101 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5102 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5155 }; 5156 5157 intc: interrupt-controller@17a00000 { 5158 compatible = "arm,gic-v3"; 5159 #address-cells = <2>; 5160 #size-cells = <2>; 5161 ranges; 5162 #interrupt-cells = <3>; 5163 interrupt-controller; 5164 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5165 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5166 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5167 5168 gic-its@17a40000 { 5169 compatible = "arm,gic-v3-its"; 5170 msi-controller; 5171 #msi-cells = <1>; 5172 reg = <0 0x17a40000 0 0x20000>; 5173 status = "disabled"; 5174 }; 5175 }; 5176 5177 watchdog@17c10000 { 5178 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5179 reg = <0 0x17c10000 0 0x1000>; 5180 clocks = <&sleep_clk>; 5181 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5182 }; 5183 5184 timer@17c20000 { 5185 #address-cells = <1>; 5186 #size-cells = <1>; 5187 ranges = <0 0 0 0x20000000>; 5188 compatible = "arm,armv7-timer-mem"; 5189 reg = <0 0x17c20000 0 0x1000>; 5190 5191 frame@17c21000 { 5192 frame-number = <0>; 5193 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5194 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5195 reg = <0x17c21000 0x1000>, 5196 <0x17c22000 0x1000>; 5197 }; 5198 5199 frame@17c23000 { 5200 frame-number = <1>; 5201 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5202 reg = <0x17c23000 0x1000>; 5203 status = "disabled"; 5204 }; 5205 5206 frame@17c25000 { 5207 frame-number = <2>; 5208 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5209 reg = <0x17c25000 0x1000>; 5210 status = "disabled"; 5211 }; 5212 5213 frame@17c27000 { 5214 frame-number = <3>; 5215 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5216 reg = <0x17c27000 0x1000>; 5217 status = "disabled"; 5218 }; 5219 5220 frame@17c29000 { 5221 frame-number = <4>; 5222 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5223 reg = <0x17c29000 0x1000>; 5224 status = "disabled"; 5225 }; 5226 5227 frame@17c2b000 { 5228 frame-number = <5>; 5229 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5230 reg = <0x17c2b000 0x1000>; 5231 status = "disabled"; 5232 }; 5233 5234 frame@17c2d000 { 5235 frame-number = <6>; 5236 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5237 reg = <0x17c2d000 0x1000>; 5238 status = "disabled"; 5239 }; 5240 }; 5241 5242 apps_rsc: rsc@18200000 { 5243 compatible = "qcom,rpmh-rsc"; 5244 reg = <0 0x18200000 0 0x10000>, 5245 <0 0x18210000 0 0x10000>, 5246 <0 0x18220000 0 0x10000>; 5247 reg-names = "drv-0", "drv-1", "drv-2"; 5248 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5249 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5250 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5251 qcom,tcs-offset = <0xd00>; 5252 qcom,drv-id = <2>; 5253 qcom,tcs-config = <ACTIVE_TCS 2>, 5254 <SLEEP_TCS 3>, 5255 <WAKE_TCS 3>, 5256 <CONTROL_TCS 1>; 5257 5258 apps_bcm_voter: bcm-voter { 5259 compatible = "qcom,bcm-voter"; 5260 }; 5261 5262 rpmhpd: power-controller { 5263 compatible = "qcom,sc7280-rpmhpd"; 5264 #power-domain-cells = <1>; 5265 operating-points-v2 = <&rpmhpd_opp_table>; 5266 5267 rpmhpd_opp_table: opp-table { 5268 compatible = "operating-points-v2"; 5269 5270 rpmhpd_opp_ret: opp1 { 5271 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5272 }; 5273 5274 rpmhpd_opp_low_svs: opp2 { 5275 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5276 }; 5277 5278 rpmhpd_opp_svs: opp3 { 5279 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5280 }; 5281 5282 rpmhpd_opp_svs_l1: opp4 { 5283 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5284 }; 5285 5286 rpmhpd_opp_svs_l2: opp5 { 5287 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5288 }; 5289 5290 rpmhpd_opp_nom: opp6 { 5291 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5292 }; 5293 5294 rpmhpd_opp_nom_l1: opp7 { 5295 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5296 }; 5297 5298 rpmhpd_opp_turbo: opp8 { 5299 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5300 }; 5301 5302 rpmhpd_opp_turbo_l1: opp9 { 5303 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5304 }; 5305 }; 5306 }; 5307 5308 rpmhcc: clock-controller { 5309 compatible = "qcom,sc7280-rpmh-clk"; 5310 clocks = <&xo_board>; 5311 clock-names = "xo"; 5312 #clock-cells = <1>; 5313 }; 5314 }; 5315 5316 epss_l3: interconnect@18590000 { 5317 compatible = "qcom,sc7280-epss-l3"; 5318 reg = <0 0x18590000 0 0x1000>; 5319 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5320 clock-names = "xo", "alternate"; 5321 #interconnect-cells = <1>; 5322 }; 5323 5324 cpufreq_hw: cpufreq@18591000 { 5325 compatible = "qcom,cpufreq-epss"; 5326 reg = <0 0x18591000 0 0x1000>, 5327 <0 0x18592000 0 0x1000>, 5328 <0 0x18593000 0 0x1000>; 5329 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5330 clock-names = "xo", "alternate"; 5331 #freq-domain-cells = <1>; 5332 }; 5333 }; 5334 5335 thermal_zones: thermal-zones { 5336 cpu0-thermal { 5337 polling-delay-passive = <250>; 5338 polling-delay = <0>; 5339 5340 thermal-sensors = <&tsens0 1>; 5341 5342 trips { 5343 cpu0_alert0: trip-point0 { 5344 temperature = <90000>; 5345 hysteresis = <2000>; 5346 type = "passive"; 5347 }; 5348 5349 cpu0_alert1: trip-point1 { 5350 temperature = <95000>; 5351 hysteresis = <2000>; 5352 type = "passive"; 5353 }; 5354 5355 cpu0_crit: cpu-crit { 5356 temperature = <110000>; 5357 hysteresis = <0>; 5358 type = "critical"; 5359 }; 5360 }; 5361 5362 cooling-maps { 5363 map0 { 5364 trip = <&cpu0_alert0>; 5365 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5366 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5367 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5368 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5369 }; 5370 map1 { 5371 trip = <&cpu0_alert1>; 5372 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5373 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5374 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5375 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5376 }; 5377 }; 5378 }; 5379 5380 cpu1-thermal { 5381 polling-delay-passive = <250>; 5382 polling-delay = <0>; 5383 5384 thermal-sensors = <&tsens0 2>; 5385 5386 trips { 5387 cpu1_alert0: trip-point0 { 5388 temperature = <90000>; 5389 hysteresis = <2000>; 5390 type = "passive"; 5391 }; 5392 5393 cpu1_alert1: trip-point1 { 5394 temperature = <95000>; 5395 hysteresis = <2000>; 5396 type = "passive"; 5397 }; 5398 5399 cpu1_crit: cpu-crit { 5400 temperature = <110000>; 5401 hysteresis = <0>; 5402 type = "critical"; 5403 }; 5404 }; 5405 5406 cooling-maps { 5407 map0 { 5408 trip = <&cpu1_alert0>; 5409 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5410 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5411 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5412 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5413 }; 5414 map1 { 5415 trip = <&cpu1_alert1>; 5416 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5417 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5418 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5419 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5420 }; 5421 }; 5422 }; 5423 5424 cpu2-thermal { 5425 polling-delay-passive = <250>; 5426 polling-delay = <0>; 5427 5428 thermal-sensors = <&tsens0 3>; 5429 5430 trips { 5431 cpu2_alert0: trip-point0 { 5432 temperature = <90000>; 5433 hysteresis = <2000>; 5434 type = "passive"; 5435 }; 5436 5437 cpu2_alert1: trip-point1 { 5438 temperature = <95000>; 5439 hysteresis = <2000>; 5440 type = "passive"; 5441 }; 5442 5443 cpu2_crit: cpu-crit { 5444 temperature = <110000>; 5445 hysteresis = <0>; 5446 type = "critical"; 5447 }; 5448 }; 5449 5450 cooling-maps { 5451 map0 { 5452 trip = <&cpu2_alert0>; 5453 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5454 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5455 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5456 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5457 }; 5458 map1 { 5459 trip = <&cpu2_alert1>; 5460 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5461 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5462 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5463 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5464 }; 5465 }; 5466 }; 5467 5468 cpu3-thermal { 5469 polling-delay-passive = <250>; 5470 polling-delay = <0>; 5471 5472 thermal-sensors = <&tsens0 4>; 5473 5474 trips { 5475 cpu3_alert0: trip-point0 { 5476 temperature = <90000>; 5477 hysteresis = <2000>; 5478 type = "passive"; 5479 }; 5480 5481 cpu3_alert1: trip-point1 { 5482 temperature = <95000>; 5483 hysteresis = <2000>; 5484 type = "passive"; 5485 }; 5486 5487 cpu3_crit: cpu-crit { 5488 temperature = <110000>; 5489 hysteresis = <0>; 5490 type = "critical"; 5491 }; 5492 }; 5493 5494 cooling-maps { 5495 map0 { 5496 trip = <&cpu3_alert0>; 5497 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5498 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5499 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5500 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5501 }; 5502 map1 { 5503 trip = <&cpu3_alert1>; 5504 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5505 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5506 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5507 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5508 }; 5509 }; 5510 }; 5511 5512 cpu4-thermal { 5513 polling-delay-passive = <250>; 5514 polling-delay = <0>; 5515 5516 thermal-sensors = <&tsens0 7>; 5517 5518 trips { 5519 cpu4_alert0: trip-point0 { 5520 temperature = <90000>; 5521 hysteresis = <2000>; 5522 type = "passive"; 5523 }; 5524 5525 cpu4_alert1: trip-point1 { 5526 temperature = <95000>; 5527 hysteresis = <2000>; 5528 type = "passive"; 5529 }; 5530 5531 cpu4_crit: cpu-crit { 5532 temperature = <110000>; 5533 hysteresis = <0>; 5534 type = "critical"; 5535 }; 5536 }; 5537 5538 cooling-maps { 5539 map0 { 5540 trip = <&cpu4_alert0>; 5541 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5542 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5543 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5544 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5545 }; 5546 map1 { 5547 trip = <&cpu4_alert1>; 5548 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5549 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5550 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5551 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5552 }; 5553 }; 5554 }; 5555 5556 cpu5-thermal { 5557 polling-delay-passive = <250>; 5558 polling-delay = <0>; 5559 5560 thermal-sensors = <&tsens0 8>; 5561 5562 trips { 5563 cpu5_alert0: trip-point0 { 5564 temperature = <90000>; 5565 hysteresis = <2000>; 5566 type = "passive"; 5567 }; 5568 5569 cpu5_alert1: trip-point1 { 5570 temperature = <95000>; 5571 hysteresis = <2000>; 5572 type = "passive"; 5573 }; 5574 5575 cpu5_crit: cpu-crit { 5576 temperature = <110000>; 5577 hysteresis = <0>; 5578 type = "critical"; 5579 }; 5580 }; 5581 5582 cooling-maps { 5583 map0 { 5584 trip = <&cpu5_alert0>; 5585 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5586 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5587 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5588 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5589 }; 5590 map1 { 5591 trip = <&cpu5_alert1>; 5592 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5593 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5594 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5595 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5596 }; 5597 }; 5598 }; 5599 5600 cpu6-thermal { 5601 polling-delay-passive = <250>; 5602 polling-delay = <0>; 5603 5604 thermal-sensors = <&tsens0 9>; 5605 5606 trips { 5607 cpu6_alert0: trip-point0 { 5608 temperature = <90000>; 5609 hysteresis = <2000>; 5610 type = "passive"; 5611 }; 5612 5613 cpu6_alert1: trip-point1 { 5614 temperature = <95000>; 5615 hysteresis = <2000>; 5616 type = "passive"; 5617 }; 5618 5619 cpu6_crit: cpu-crit { 5620 temperature = <110000>; 5621 hysteresis = <0>; 5622 type = "critical"; 5623 }; 5624 }; 5625 5626 cooling-maps { 5627 map0 { 5628 trip = <&cpu6_alert0>; 5629 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5630 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5631 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5632 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5633 }; 5634 map1 { 5635 trip = <&cpu6_alert1>; 5636 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5637 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5638 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5639 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5640 }; 5641 }; 5642 }; 5643 5644 cpu7-thermal { 5645 polling-delay-passive = <250>; 5646 polling-delay = <0>; 5647 5648 thermal-sensors = <&tsens0 10>; 5649 5650 trips { 5651 cpu7_alert0: trip-point0 { 5652 temperature = <90000>; 5653 hysteresis = <2000>; 5654 type = "passive"; 5655 }; 5656 5657 cpu7_alert1: trip-point1 { 5658 temperature = <95000>; 5659 hysteresis = <2000>; 5660 type = "passive"; 5661 }; 5662 5663 cpu7_crit: cpu-crit { 5664 temperature = <110000>; 5665 hysteresis = <0>; 5666 type = "critical"; 5667 }; 5668 }; 5669 5670 cooling-maps { 5671 map0 { 5672 trip = <&cpu7_alert0>; 5673 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5674 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5675 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5676 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5677 }; 5678 map1 { 5679 trip = <&cpu7_alert1>; 5680 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5681 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5682 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5683 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5684 }; 5685 }; 5686 }; 5687 5688 cpu8-thermal { 5689 polling-delay-passive = <250>; 5690 polling-delay = <0>; 5691 5692 thermal-sensors = <&tsens0 11>; 5693 5694 trips { 5695 cpu8_alert0: trip-point0 { 5696 temperature = <90000>; 5697 hysteresis = <2000>; 5698 type = "passive"; 5699 }; 5700 5701 cpu8_alert1: trip-point1 { 5702 temperature = <95000>; 5703 hysteresis = <2000>; 5704 type = "passive"; 5705 }; 5706 5707 cpu8_crit: cpu-crit { 5708 temperature = <110000>; 5709 hysteresis = <0>; 5710 type = "critical"; 5711 }; 5712 }; 5713 5714 cooling-maps { 5715 map0 { 5716 trip = <&cpu8_alert0>; 5717 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5718 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5719 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5720 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5721 }; 5722 map1 { 5723 trip = <&cpu8_alert1>; 5724 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5725 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5726 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5727 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5728 }; 5729 }; 5730 }; 5731 5732 cpu9-thermal { 5733 polling-delay-passive = <250>; 5734 polling-delay = <0>; 5735 5736 thermal-sensors = <&tsens0 12>; 5737 5738 trips { 5739 cpu9_alert0: trip-point0 { 5740 temperature = <90000>; 5741 hysteresis = <2000>; 5742 type = "passive"; 5743 }; 5744 5745 cpu9_alert1: trip-point1 { 5746 temperature = <95000>; 5747 hysteresis = <2000>; 5748 type = "passive"; 5749 }; 5750 5751 cpu9_crit: cpu-crit { 5752 temperature = <110000>; 5753 hysteresis = <0>; 5754 type = "critical"; 5755 }; 5756 }; 5757 5758 cooling-maps { 5759 map0 { 5760 trip = <&cpu9_alert0>; 5761 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5762 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5763 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5764 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5765 }; 5766 map1 { 5767 trip = <&cpu9_alert1>; 5768 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5769 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5770 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5771 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5772 }; 5773 }; 5774 }; 5775 5776 cpu10-thermal { 5777 polling-delay-passive = <250>; 5778 polling-delay = <0>; 5779 5780 thermal-sensors = <&tsens0 13>; 5781 5782 trips { 5783 cpu10_alert0: trip-point0 { 5784 temperature = <90000>; 5785 hysteresis = <2000>; 5786 type = "passive"; 5787 }; 5788 5789 cpu10_alert1: trip-point1 { 5790 temperature = <95000>; 5791 hysteresis = <2000>; 5792 type = "passive"; 5793 }; 5794 5795 cpu10_crit: cpu-crit { 5796 temperature = <110000>; 5797 hysteresis = <0>; 5798 type = "critical"; 5799 }; 5800 }; 5801 5802 cooling-maps { 5803 map0 { 5804 trip = <&cpu10_alert0>; 5805 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5806 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5807 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5808 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5809 }; 5810 map1 { 5811 trip = <&cpu10_alert1>; 5812 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5813 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5814 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5815 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5816 }; 5817 }; 5818 }; 5819 5820 cpu11-thermal { 5821 polling-delay-passive = <250>; 5822 polling-delay = <0>; 5823 5824 thermal-sensors = <&tsens0 14>; 5825 5826 trips { 5827 cpu11_alert0: trip-point0 { 5828 temperature = <90000>; 5829 hysteresis = <2000>; 5830 type = "passive"; 5831 }; 5832 5833 cpu11_alert1: trip-point1 { 5834 temperature = <95000>; 5835 hysteresis = <2000>; 5836 type = "passive"; 5837 }; 5838 5839 cpu11_crit: cpu-crit { 5840 temperature = <110000>; 5841 hysteresis = <0>; 5842 type = "critical"; 5843 }; 5844 }; 5845 5846 cooling-maps { 5847 map0 { 5848 trip = <&cpu11_alert0>; 5849 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5850 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5851 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5852 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5853 }; 5854 map1 { 5855 trip = <&cpu11_alert1>; 5856 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5857 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5858 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5859 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5860 }; 5861 }; 5862 }; 5863 5864 aoss0-thermal { 5865 polling-delay-passive = <0>; 5866 polling-delay = <0>; 5867 5868 thermal-sensors = <&tsens0 0>; 5869 5870 trips { 5871 aoss0_alert0: trip-point0 { 5872 temperature = <90000>; 5873 hysteresis = <2000>; 5874 type = "hot"; 5875 }; 5876 5877 aoss0_crit: aoss0-crit { 5878 temperature = <110000>; 5879 hysteresis = <0>; 5880 type = "critical"; 5881 }; 5882 }; 5883 }; 5884 5885 aoss1-thermal { 5886 polling-delay-passive = <0>; 5887 polling-delay = <0>; 5888 5889 thermal-sensors = <&tsens1 0>; 5890 5891 trips { 5892 aoss1_alert0: trip-point0 { 5893 temperature = <90000>; 5894 hysteresis = <2000>; 5895 type = "hot"; 5896 }; 5897 5898 aoss1_crit: aoss1-crit { 5899 temperature = <110000>; 5900 hysteresis = <0>; 5901 type = "critical"; 5902 }; 5903 }; 5904 }; 5905 5906 cpuss0-thermal { 5907 polling-delay-passive = <0>; 5908 polling-delay = <0>; 5909 5910 thermal-sensors = <&tsens0 5>; 5911 5912 trips { 5913 cpuss0_alert0: trip-point0 { 5914 temperature = <90000>; 5915 hysteresis = <2000>; 5916 type = "hot"; 5917 }; 5918 cpuss0_crit: cluster0-crit { 5919 temperature = <110000>; 5920 hysteresis = <0>; 5921 type = "critical"; 5922 }; 5923 }; 5924 }; 5925 5926 cpuss1-thermal { 5927 polling-delay-passive = <0>; 5928 polling-delay = <0>; 5929 5930 thermal-sensors = <&tsens0 6>; 5931 5932 trips { 5933 cpuss1_alert0: trip-point0 { 5934 temperature = <90000>; 5935 hysteresis = <2000>; 5936 type = "hot"; 5937 }; 5938 cpuss1_crit: cluster0-crit { 5939 temperature = <110000>; 5940 hysteresis = <0>; 5941 type = "critical"; 5942 }; 5943 }; 5944 }; 5945 5946 gpuss0-thermal { 5947 polling-delay-passive = <100>; 5948 polling-delay = <0>; 5949 5950 thermal-sensors = <&tsens1 1>; 5951 5952 trips { 5953 gpuss0_alert0: trip-point0 { 5954 temperature = <95000>; 5955 hysteresis = <2000>; 5956 type = "passive"; 5957 }; 5958 5959 gpuss0_crit: gpuss0-crit { 5960 temperature = <110000>; 5961 hysteresis = <0>; 5962 type = "critical"; 5963 }; 5964 }; 5965 5966 cooling-maps { 5967 map0 { 5968 trip = <&gpuss0_alert0>; 5969 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5970 }; 5971 }; 5972 }; 5973 5974 gpuss1-thermal { 5975 polling-delay-passive = <100>; 5976 polling-delay = <0>; 5977 5978 thermal-sensors = <&tsens1 2>; 5979 5980 trips { 5981 gpuss1_alert0: trip-point0 { 5982 temperature = <95000>; 5983 hysteresis = <2000>; 5984 type = "passive"; 5985 }; 5986 5987 gpuss1_crit: gpuss1-crit { 5988 temperature = <110000>; 5989 hysteresis = <0>; 5990 type = "critical"; 5991 }; 5992 }; 5993 5994 cooling-maps { 5995 map0 { 5996 trip = <&gpuss1_alert0>; 5997 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5998 }; 5999 }; 6000 }; 6001 6002 nspss0-thermal { 6003 polling-delay-passive = <0>; 6004 polling-delay = <0>; 6005 6006 thermal-sensors = <&tsens1 3>; 6007 6008 trips { 6009 nspss0_alert0: trip-point0 { 6010 temperature = <90000>; 6011 hysteresis = <2000>; 6012 type = "hot"; 6013 }; 6014 6015 nspss0_crit: nspss0-crit { 6016 temperature = <110000>; 6017 hysteresis = <0>; 6018 type = "critical"; 6019 }; 6020 }; 6021 }; 6022 6023 nspss1-thermal { 6024 polling-delay-passive = <0>; 6025 polling-delay = <0>; 6026 6027 thermal-sensors = <&tsens1 4>; 6028 6029 trips { 6030 nspss1_alert0: trip-point0 { 6031 temperature = <90000>; 6032 hysteresis = <2000>; 6033 type = "hot"; 6034 }; 6035 6036 nspss1_crit: nspss1-crit { 6037 temperature = <110000>; 6038 hysteresis = <0>; 6039 type = "critical"; 6040 }; 6041 }; 6042 }; 6043 6044 video-thermal { 6045 polling-delay-passive = <0>; 6046 polling-delay = <0>; 6047 6048 thermal-sensors = <&tsens1 5>; 6049 6050 trips { 6051 video_alert0: trip-point0 { 6052 temperature = <90000>; 6053 hysteresis = <2000>; 6054 type = "hot"; 6055 }; 6056 6057 video_crit: video-crit { 6058 temperature = <110000>; 6059 hysteresis = <0>; 6060 type = "critical"; 6061 }; 6062 }; 6063 }; 6064 6065 ddr-thermal { 6066 polling-delay-passive = <0>; 6067 polling-delay = <0>; 6068 6069 thermal-sensors = <&tsens1 6>; 6070 6071 trips { 6072 ddr_alert0: trip-point0 { 6073 temperature = <90000>; 6074 hysteresis = <2000>; 6075 type = "hot"; 6076 }; 6077 6078 ddr_crit: ddr-crit { 6079 temperature = <110000>; 6080 hysteresis = <0>; 6081 type = "critical"; 6082 }; 6083 }; 6084 }; 6085 6086 mdmss0-thermal { 6087 polling-delay-passive = <0>; 6088 polling-delay = <0>; 6089 6090 thermal-sensors = <&tsens1 7>; 6091 6092 trips { 6093 mdmss0_alert0: trip-point0 { 6094 temperature = <90000>; 6095 hysteresis = <2000>; 6096 type = "hot"; 6097 }; 6098 6099 mdmss0_crit: mdmss0-crit { 6100 temperature = <110000>; 6101 hysteresis = <0>; 6102 type = "critical"; 6103 }; 6104 }; 6105 }; 6106 6107 mdmss1-thermal { 6108 polling-delay-passive = <0>; 6109 polling-delay = <0>; 6110 6111 thermal-sensors = <&tsens1 8>; 6112 6113 trips { 6114 mdmss1_alert0: trip-point0 { 6115 temperature = <90000>; 6116 hysteresis = <2000>; 6117 type = "hot"; 6118 }; 6119 6120 mdmss1_crit: mdmss1-crit { 6121 temperature = <110000>; 6122 hysteresis = <0>; 6123 type = "critical"; 6124 }; 6125 }; 6126 }; 6127 6128 mdmss2-thermal { 6129 polling-delay-passive = <0>; 6130 polling-delay = <0>; 6131 6132 thermal-sensors = <&tsens1 9>; 6133 6134 trips { 6135 mdmss2_alert0: trip-point0 { 6136 temperature = <90000>; 6137 hysteresis = <2000>; 6138 type = "hot"; 6139 }; 6140 6141 mdmss2_crit: mdmss2-crit { 6142 temperature = <110000>; 6143 hysteresis = <0>; 6144 type = "critical"; 6145 }; 6146 }; 6147 }; 6148 6149 mdmss3-thermal { 6150 polling-delay-passive = <0>; 6151 polling-delay = <0>; 6152 6153 thermal-sensors = <&tsens1 10>; 6154 6155 trips { 6156 mdmss3_alert0: trip-point0 { 6157 temperature = <90000>; 6158 hysteresis = <2000>; 6159 type = "hot"; 6160 }; 6161 6162 mdmss3_crit: mdmss3-crit { 6163 temperature = <110000>; 6164 hysteresis = <0>; 6165 type = "critical"; 6166 }; 6167 }; 6168 }; 6169 6170 camera0-thermal { 6171 polling-delay-passive = <0>; 6172 polling-delay = <0>; 6173 6174 thermal-sensors = <&tsens1 11>; 6175 6176 trips { 6177 camera0_alert0: trip-point0 { 6178 temperature = <90000>; 6179 hysteresis = <2000>; 6180 type = "hot"; 6181 }; 6182 6183 camera0_crit: camera0-crit { 6184 temperature = <110000>; 6185 hysteresis = <0>; 6186 type = "critical"; 6187 }; 6188 }; 6189 }; 6190 }; 6191 6192 timer { 6193 compatible = "arm,armv8-timer"; 6194 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6195 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6196 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6197 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6198 }; 6199}; 6200