1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
4 *
5 */
6
7 #include <linux/delay.h>
8 #include <linux/device.h>
9 #include <linux/dma-direction.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/interrupt.h>
12 #include <linux/list.h>
13 #include <linux/mhi.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/wait.h>
17 #include "internal.h"
18
19 /*
20 * Not all MHI state transitions are synchronous. Transitions like Linkdown,
21 * SYS_ERR, and shutdown can happen anytime asynchronously. This function will
22 * transition to a new state only if we're allowed to.
23 *
24 * Priority increases as we go down. For instance, from any state in L0, the
25 * transition can be made to states in L1, L2 and L3. A notable exception to
26 * this rule is state DISABLE. From DISABLE state we can only transition to
27 * POR state. Also, while in L2 state, user cannot jump back to previous
28 * L1 or L0 states.
29 *
30 * Valid transitions:
31 * L0: DISABLE <--> POR
32 * POR <--> POR
33 * POR -> M0 -> M2 --> M0
34 * POR -> FW_DL_ERR
35 * FW_DL_ERR <--> FW_DL_ERR
36 * M0 <--> M0
37 * M0 -> FW_DL_ERR
38 * M0 -> M3_ENTER -> M3 -> M3_EXIT --> M0
39 * L1: SYS_ERR_DETECT -> SYS_ERR_PROCESS --> POR
40 * L2: SHUTDOWN_PROCESS -> LD_ERR_FATAL_DETECT
41 * SHUTDOWN_PROCESS -> DISABLE
42 * L3: LD_ERR_FATAL_DETECT <--> LD_ERR_FATAL_DETECT
43 * LD_ERR_FATAL_DETECT -> DISABLE
44 */
45 static const struct mhi_pm_transitions dev_state_transitions[] = {
46 /* L0 States */
47 {
48 MHI_PM_DISABLE,
49 MHI_PM_POR
50 },
51 {
52 MHI_PM_POR,
53 MHI_PM_POR | MHI_PM_DISABLE | MHI_PM_M0 |
54 MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
55 MHI_PM_LD_ERR_FATAL_DETECT | MHI_PM_FW_DL_ERR
56 },
57 {
58 MHI_PM_M0,
59 MHI_PM_M0 | MHI_PM_M2 | MHI_PM_M3_ENTER |
60 MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
61 MHI_PM_LD_ERR_FATAL_DETECT | MHI_PM_FW_DL_ERR
62 },
63 {
64 MHI_PM_M2,
65 MHI_PM_M0 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
66 MHI_PM_LD_ERR_FATAL_DETECT
67 },
68 {
69 MHI_PM_M3_ENTER,
70 MHI_PM_M3 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
71 MHI_PM_LD_ERR_FATAL_DETECT
72 },
73 {
74 MHI_PM_M3,
75 MHI_PM_M3_EXIT | MHI_PM_SYS_ERR_DETECT |
76 MHI_PM_LD_ERR_FATAL_DETECT
77 },
78 {
79 MHI_PM_M3_EXIT,
80 MHI_PM_M0 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
81 MHI_PM_LD_ERR_FATAL_DETECT
82 },
83 {
84 MHI_PM_FW_DL_ERR,
85 MHI_PM_FW_DL_ERR | MHI_PM_SYS_ERR_DETECT |
86 MHI_PM_SHUTDOWN_PROCESS | MHI_PM_LD_ERR_FATAL_DETECT
87 },
88 /* L1 States */
89 {
90 MHI_PM_SYS_ERR_DETECT,
91 MHI_PM_SYS_ERR_PROCESS | MHI_PM_SHUTDOWN_PROCESS |
92 MHI_PM_LD_ERR_FATAL_DETECT
93 },
94 {
95 MHI_PM_SYS_ERR_PROCESS,
96 MHI_PM_POR | MHI_PM_SHUTDOWN_PROCESS |
97 MHI_PM_LD_ERR_FATAL_DETECT
98 },
99 /* L2 States */
100 {
101 MHI_PM_SHUTDOWN_PROCESS,
102 MHI_PM_DISABLE | MHI_PM_LD_ERR_FATAL_DETECT
103 },
104 /* L3 States */
105 {
106 MHI_PM_LD_ERR_FATAL_DETECT,
107 MHI_PM_LD_ERR_FATAL_DETECT | MHI_PM_DISABLE
108 },
109 };
110
mhi_tryset_pm_state(struct mhi_controller * mhi_cntrl,enum mhi_pm_state state)111 enum mhi_pm_state __must_check mhi_tryset_pm_state(struct mhi_controller *mhi_cntrl,
112 enum mhi_pm_state state)
113 {
114 unsigned long cur_state = mhi_cntrl->pm_state;
115 int index = find_last_bit(&cur_state, 32);
116
117 if (unlikely(index >= ARRAY_SIZE(dev_state_transitions)))
118 return cur_state;
119
120 if (unlikely(dev_state_transitions[index].from_state != cur_state))
121 return cur_state;
122
123 if (unlikely(!(dev_state_transitions[index].to_states & state)))
124 return cur_state;
125
126 mhi_cntrl->pm_state = state;
127 return mhi_cntrl->pm_state;
128 }
129
mhi_set_mhi_state(struct mhi_controller * mhi_cntrl,enum mhi_state state)130 void mhi_set_mhi_state(struct mhi_controller *mhi_cntrl, enum mhi_state state)
131 {
132 struct device *dev = &mhi_cntrl->mhi_dev->dev;
133 int ret;
134
135 if (state == MHI_STATE_RESET) {
136 ret = mhi_write_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
137 MHICTRL_RESET_MASK, 1);
138 } else {
139 ret = mhi_write_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
140 MHICTRL_MHISTATE_MASK, state);
141 }
142
143 if (ret)
144 dev_err(dev, "Failed to set MHI state to: %s\n",
145 mhi_state_str(state));
146 }
147
148 /* NOP for backward compatibility, host allowed to ring DB in M2 state */
mhi_toggle_dev_wake_nop(struct mhi_controller * mhi_cntrl)149 static void mhi_toggle_dev_wake_nop(struct mhi_controller *mhi_cntrl)
150 {
151 }
152
mhi_toggle_dev_wake(struct mhi_controller * mhi_cntrl)153 static void mhi_toggle_dev_wake(struct mhi_controller *mhi_cntrl)
154 {
155 mhi_cntrl->wake_get(mhi_cntrl, false);
156 mhi_cntrl->wake_put(mhi_cntrl, true);
157 }
158
159 /* Handle device ready state transition */
mhi_ready_state_transition(struct mhi_controller * mhi_cntrl)160 int mhi_ready_state_transition(struct mhi_controller *mhi_cntrl)
161 {
162 struct mhi_event *mhi_event;
163 enum mhi_pm_state cur_state;
164 struct device *dev = &mhi_cntrl->mhi_dev->dev;
165 u32 interval_us = 25000; /* poll register field every 25 milliseconds */
166 int ret, i;
167
168 /* Check if device entered error state */
169 if (MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state)) {
170 dev_err(dev, "Device link is not accessible\n");
171 return -EIO;
172 }
173
174 /* Wait for RESET to be cleared and READY bit to be set by the device */
175 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
176 MHICTRL_RESET_MASK, 0, interval_us);
177 if (ret) {
178 dev_err(dev, "Device failed to clear MHI Reset\n");
179 return ret;
180 }
181
182 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHISTATUS,
183 MHISTATUS_READY_MASK, 1, interval_us);
184 if (ret) {
185 dev_err(dev, "Device failed to enter MHI Ready\n");
186 return ret;
187 }
188
189 dev_dbg(dev, "Device in READY State\n");
190 write_lock_irq(&mhi_cntrl->pm_lock);
191 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_POR);
192 mhi_cntrl->dev_state = MHI_STATE_READY;
193 write_unlock_irq(&mhi_cntrl->pm_lock);
194
195 if (cur_state != MHI_PM_POR) {
196 dev_err(dev, "Error moving to state %s from %s\n",
197 to_mhi_pm_state_str(MHI_PM_POR),
198 to_mhi_pm_state_str(cur_state));
199 return -EIO;
200 }
201
202 read_lock_bh(&mhi_cntrl->pm_lock);
203 if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) {
204 dev_err(dev, "Device registers not accessible\n");
205 goto error_mmio;
206 }
207
208 /* Configure MMIO registers */
209 ret = mhi_init_mmio(mhi_cntrl);
210 if (ret) {
211 dev_err(dev, "Error configuring MMIO registers\n");
212 goto error_mmio;
213 }
214
215 /* Add elements to all SW event rings */
216 mhi_event = mhi_cntrl->mhi_event;
217 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
218 struct mhi_ring *ring = &mhi_event->ring;
219
220 /* Skip if this is an offload or HW event */
221 if (mhi_event->offload_ev || mhi_event->hw_ring)
222 continue;
223
224 ring->wp = ring->base + ring->len - ring->el_size;
225 *ring->ctxt_wp = cpu_to_le64(ring->iommu_base + ring->len - ring->el_size);
226 /* Update all cores */
227 smp_wmb();
228
229 /* Ring the event ring db */
230 spin_lock_irq(&mhi_event->lock);
231 mhi_ring_er_db(mhi_event);
232 spin_unlock_irq(&mhi_event->lock);
233 }
234
235 /* Set MHI to M0 state */
236 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M0);
237 read_unlock_bh(&mhi_cntrl->pm_lock);
238
239 return 0;
240
241 error_mmio:
242 read_unlock_bh(&mhi_cntrl->pm_lock);
243
244 return -EIO;
245 }
246
mhi_pm_m0_transition(struct mhi_controller * mhi_cntrl)247 int mhi_pm_m0_transition(struct mhi_controller *mhi_cntrl)
248 {
249 enum mhi_pm_state cur_state;
250 struct mhi_chan *mhi_chan;
251 struct device *dev = &mhi_cntrl->mhi_dev->dev;
252 int i;
253
254 write_lock_irq(&mhi_cntrl->pm_lock);
255 mhi_cntrl->dev_state = MHI_STATE_M0;
256 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M0);
257 write_unlock_irq(&mhi_cntrl->pm_lock);
258 if (unlikely(cur_state != MHI_PM_M0)) {
259 dev_err(dev, "Unable to transition to M0 state\n");
260 return -EIO;
261 }
262 mhi_cntrl->M0++;
263
264 /* Wake up the device */
265 read_lock_bh(&mhi_cntrl->pm_lock);
266 mhi_cntrl->wake_get(mhi_cntrl, true);
267
268 /* Ring all event rings and CMD ring only if we're in mission mode */
269 if (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) {
270 struct mhi_event *mhi_event = mhi_cntrl->mhi_event;
271 struct mhi_cmd *mhi_cmd =
272 &mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING];
273
274 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
275 if (mhi_event->offload_ev)
276 continue;
277
278 spin_lock_irq(&mhi_event->lock);
279 mhi_ring_er_db(mhi_event);
280 spin_unlock_irq(&mhi_event->lock);
281 }
282
283 /* Only ring primary cmd ring if ring is not empty */
284 spin_lock_irq(&mhi_cmd->lock);
285 if (mhi_cmd->ring.rp != mhi_cmd->ring.wp)
286 mhi_ring_cmd_db(mhi_cntrl, mhi_cmd);
287 spin_unlock_irq(&mhi_cmd->lock);
288 }
289
290 /* Ring channel DB registers */
291 mhi_chan = mhi_cntrl->mhi_chan;
292 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) {
293 struct mhi_ring *tre_ring = &mhi_chan->tre_ring;
294
295 if (mhi_chan->db_cfg.reset_req) {
296 write_lock_irq(&mhi_chan->lock);
297 mhi_chan->db_cfg.db_mode = true;
298 write_unlock_irq(&mhi_chan->lock);
299 }
300
301 read_lock_irq(&mhi_chan->lock);
302
303 /* Only ring DB if ring is not empty */
304 if (tre_ring->base && tre_ring->wp != tre_ring->rp &&
305 mhi_chan->ch_state == MHI_CH_STATE_ENABLED)
306 mhi_ring_chan_db(mhi_cntrl, mhi_chan);
307 read_unlock_irq(&mhi_chan->lock);
308 }
309
310 mhi_cntrl->wake_put(mhi_cntrl, false);
311 read_unlock_bh(&mhi_cntrl->pm_lock);
312 wake_up_all(&mhi_cntrl->state_event);
313
314 return 0;
315 }
316
317 /*
318 * After receiving the MHI state change event from the device indicating the
319 * transition to M1 state, the host can transition the device to M2 state
320 * for keeping it in low power state.
321 */
mhi_pm_m1_transition(struct mhi_controller * mhi_cntrl)322 void mhi_pm_m1_transition(struct mhi_controller *mhi_cntrl)
323 {
324 enum mhi_pm_state state;
325 struct device *dev = &mhi_cntrl->mhi_dev->dev;
326
327 write_lock_irq(&mhi_cntrl->pm_lock);
328 state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M2);
329 if (state == MHI_PM_M2) {
330 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M2);
331 mhi_cntrl->dev_state = MHI_STATE_M2;
332
333 write_unlock_irq(&mhi_cntrl->pm_lock);
334
335 mhi_cntrl->M2++;
336 wake_up_all(&mhi_cntrl->state_event);
337
338 /* If there are any pending resources, exit M2 immediately */
339 if (unlikely(atomic_read(&mhi_cntrl->pending_pkts) ||
340 atomic_read(&mhi_cntrl->dev_wake))) {
341 dev_dbg(dev,
342 "Exiting M2, pending_pkts: %d dev_wake: %d\n",
343 atomic_read(&mhi_cntrl->pending_pkts),
344 atomic_read(&mhi_cntrl->dev_wake));
345 read_lock_bh(&mhi_cntrl->pm_lock);
346 mhi_cntrl->wake_get(mhi_cntrl, true);
347 mhi_cntrl->wake_put(mhi_cntrl, true);
348 read_unlock_bh(&mhi_cntrl->pm_lock);
349 } else {
350 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_IDLE);
351 }
352 } else {
353 write_unlock_irq(&mhi_cntrl->pm_lock);
354 }
355 }
356
357 /* MHI M3 completion handler */
mhi_pm_m3_transition(struct mhi_controller * mhi_cntrl)358 int mhi_pm_m3_transition(struct mhi_controller *mhi_cntrl)
359 {
360 enum mhi_pm_state state;
361 struct device *dev = &mhi_cntrl->mhi_dev->dev;
362
363 write_lock_irq(&mhi_cntrl->pm_lock);
364 mhi_cntrl->dev_state = MHI_STATE_M3;
365 state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3);
366 write_unlock_irq(&mhi_cntrl->pm_lock);
367 if (state != MHI_PM_M3) {
368 dev_err(dev, "Unable to transition to M3 state\n");
369 return -EIO;
370 }
371
372 mhi_cntrl->M3++;
373 wake_up_all(&mhi_cntrl->state_event);
374
375 return 0;
376 }
377
378 /* Handle device Mission Mode transition */
mhi_pm_mission_mode_transition(struct mhi_controller * mhi_cntrl)379 static int mhi_pm_mission_mode_transition(struct mhi_controller *mhi_cntrl)
380 {
381 struct mhi_event *mhi_event;
382 struct device *dev = &mhi_cntrl->mhi_dev->dev;
383 enum mhi_ee_type ee = MHI_EE_MAX, current_ee = mhi_cntrl->ee;
384 int i, ret;
385
386 dev_dbg(dev, "Processing Mission Mode transition\n");
387
388 write_lock_irq(&mhi_cntrl->pm_lock);
389 if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state))
390 ee = mhi_get_exec_env(mhi_cntrl);
391
392 if (!MHI_IN_MISSION_MODE(ee)) {
393 mhi_cntrl->pm_state = MHI_PM_LD_ERR_FATAL_DETECT;
394 write_unlock_irq(&mhi_cntrl->pm_lock);
395 wake_up_all(&mhi_cntrl->state_event);
396 return -EIO;
397 }
398 mhi_cntrl->ee = ee;
399 write_unlock_irq(&mhi_cntrl->pm_lock);
400
401 wake_up_all(&mhi_cntrl->state_event);
402
403 device_for_each_child(&mhi_cntrl->mhi_dev->dev, ¤t_ee,
404 mhi_destroy_device);
405 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_EE_MISSION_MODE);
406
407 /* Force MHI to be in M0 state before continuing */
408 ret = __mhi_device_get_sync(mhi_cntrl);
409 if (ret)
410 return ret;
411
412 read_lock_bh(&mhi_cntrl->pm_lock);
413
414 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
415 ret = -EIO;
416 goto error_mission_mode;
417 }
418
419 /* Add elements to all HW event rings */
420 mhi_event = mhi_cntrl->mhi_event;
421 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
422 struct mhi_ring *ring = &mhi_event->ring;
423
424 if (mhi_event->offload_ev || !mhi_event->hw_ring)
425 continue;
426
427 ring->wp = ring->base + ring->len - ring->el_size;
428 *ring->ctxt_wp = cpu_to_le64(ring->iommu_base + ring->len - ring->el_size);
429 /* Update to all cores */
430 smp_wmb();
431
432 spin_lock_irq(&mhi_event->lock);
433 if (MHI_DB_ACCESS_VALID(mhi_cntrl))
434 mhi_ring_er_db(mhi_event);
435 spin_unlock_irq(&mhi_event->lock);
436 }
437
438 read_unlock_bh(&mhi_cntrl->pm_lock);
439
440 /*
441 * The MHI devices are only created when the client device switches its
442 * Execution Environment (EE) to either SBL or AMSS states
443 */
444 mhi_create_devices(mhi_cntrl);
445
446 read_lock_bh(&mhi_cntrl->pm_lock);
447
448 error_mission_mode:
449 mhi_cntrl->wake_put(mhi_cntrl, false);
450 read_unlock_bh(&mhi_cntrl->pm_lock);
451
452 return ret;
453 }
454
455 /* Handle shutdown transitions */
mhi_pm_disable_transition(struct mhi_controller * mhi_cntrl)456 static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl)
457 {
458 enum mhi_pm_state cur_state;
459 struct mhi_event *mhi_event;
460 struct mhi_cmd_ctxt *cmd_ctxt;
461 struct mhi_cmd *mhi_cmd;
462 struct mhi_event_ctxt *er_ctxt;
463 struct device *dev = &mhi_cntrl->mhi_dev->dev;
464 int ret, i;
465
466 dev_dbg(dev, "Processing disable transition with PM state: %s\n",
467 to_mhi_pm_state_str(mhi_cntrl->pm_state));
468
469 mutex_lock(&mhi_cntrl->pm_mutex);
470
471 /* Trigger MHI RESET so that the device will not access host memory */
472 if (!MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state)) {
473 dev_dbg(dev, "Triggering MHI Reset in device\n");
474 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
475
476 /* Wait for the reset bit to be cleared by the device */
477 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
478 MHICTRL_RESET_MASK, 0, 25000);
479 if (ret)
480 dev_err(dev, "Device failed to clear MHI Reset\n");
481
482 /*
483 * Device will clear BHI_INTVEC as a part of RESET processing,
484 * hence re-program it
485 */
486 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
487
488 if (!MHI_IN_PBL(mhi_get_exec_env(mhi_cntrl))) {
489 /* wait for ready to be set */
490 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs,
491 MHISTATUS,
492 MHISTATUS_READY_MASK, 1, 25000);
493 if (ret)
494 dev_err(dev, "Device failed to enter READY state\n");
495 }
496 }
497
498 dev_dbg(dev,
499 "Waiting for all pending event ring processing to complete\n");
500 mhi_event = mhi_cntrl->mhi_event;
501 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
502 if (mhi_event->offload_ev)
503 continue;
504 disable_irq(mhi_cntrl->irq[mhi_event->irq]);
505 tasklet_kill(&mhi_event->task);
506 }
507
508 /* Release lock and wait for all pending threads to complete */
509 mutex_unlock(&mhi_cntrl->pm_mutex);
510 dev_dbg(dev, "Waiting for all pending threads to complete\n");
511 wake_up_all(&mhi_cntrl->state_event);
512
513 dev_dbg(dev, "Reset all active channels and remove MHI devices\n");
514 device_for_each_child(&mhi_cntrl->mhi_dev->dev, NULL, mhi_destroy_device);
515
516 mutex_lock(&mhi_cntrl->pm_mutex);
517
518 WARN_ON(atomic_read(&mhi_cntrl->dev_wake));
519 WARN_ON(atomic_read(&mhi_cntrl->pending_pkts));
520
521 /* Reset the ev rings and cmd rings */
522 dev_dbg(dev, "Resetting EV CTXT and CMD CTXT\n");
523 mhi_cmd = mhi_cntrl->mhi_cmd;
524 cmd_ctxt = mhi_cntrl->mhi_ctxt->cmd_ctxt;
525 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++, cmd_ctxt++) {
526 struct mhi_ring *ring = &mhi_cmd->ring;
527
528 ring->rp = ring->base;
529 ring->wp = ring->base;
530 cmd_ctxt->rp = cmd_ctxt->rbase;
531 cmd_ctxt->wp = cmd_ctxt->rbase;
532 }
533
534 mhi_event = mhi_cntrl->mhi_event;
535 er_ctxt = mhi_cntrl->mhi_ctxt->er_ctxt;
536 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++,
537 mhi_event++) {
538 struct mhi_ring *ring = &mhi_event->ring;
539
540 /* Skip offload events */
541 if (mhi_event->offload_ev)
542 continue;
543
544 ring->rp = ring->base;
545 ring->wp = ring->base;
546 er_ctxt->rp = er_ctxt->rbase;
547 er_ctxt->wp = er_ctxt->rbase;
548 }
549
550 /* Move to disable state */
551 write_lock_irq(&mhi_cntrl->pm_lock);
552 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_DISABLE);
553 write_unlock_irq(&mhi_cntrl->pm_lock);
554 if (unlikely(cur_state != MHI_PM_DISABLE))
555 dev_err(dev, "Error moving from PM state: %s to: %s\n",
556 to_mhi_pm_state_str(cur_state),
557 to_mhi_pm_state_str(MHI_PM_DISABLE));
558
559 dev_dbg(dev, "Exiting with PM state: %s, MHI state: %s\n",
560 to_mhi_pm_state_str(mhi_cntrl->pm_state),
561 mhi_state_str(mhi_cntrl->dev_state));
562
563 mutex_unlock(&mhi_cntrl->pm_mutex);
564 }
565
566 /* Handle system error transitions */
mhi_pm_sys_error_transition(struct mhi_controller * mhi_cntrl)567 static void mhi_pm_sys_error_transition(struct mhi_controller *mhi_cntrl)
568 {
569 enum mhi_pm_state cur_state, prev_state;
570 enum dev_st_transition next_state;
571 struct mhi_event *mhi_event;
572 struct mhi_cmd_ctxt *cmd_ctxt;
573 struct mhi_cmd *mhi_cmd;
574 struct mhi_event_ctxt *er_ctxt;
575 struct device *dev = &mhi_cntrl->mhi_dev->dev;
576 int ret, i;
577
578 dev_dbg(dev, "Transitioning from PM state: %s to: %s\n",
579 to_mhi_pm_state_str(mhi_cntrl->pm_state),
580 to_mhi_pm_state_str(MHI_PM_SYS_ERR_PROCESS));
581
582 /* We must notify MHI control driver so it can clean up first */
583 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_SYS_ERROR);
584
585 mutex_lock(&mhi_cntrl->pm_mutex);
586 write_lock_irq(&mhi_cntrl->pm_lock);
587 prev_state = mhi_cntrl->pm_state;
588 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_SYS_ERR_PROCESS);
589 write_unlock_irq(&mhi_cntrl->pm_lock);
590
591 if (cur_state != MHI_PM_SYS_ERR_PROCESS) {
592 dev_err(dev, "Failed to transition from PM state: %s to: %s\n",
593 to_mhi_pm_state_str(cur_state),
594 to_mhi_pm_state_str(MHI_PM_SYS_ERR_PROCESS));
595 goto exit_sys_error_transition;
596 }
597
598 mhi_cntrl->ee = MHI_EE_DISABLE_TRANSITION;
599 mhi_cntrl->dev_state = MHI_STATE_RESET;
600
601 /* Wake up threads waiting for state transition */
602 wake_up_all(&mhi_cntrl->state_event);
603
604 /* Trigger MHI RESET so that the device will not access host memory */
605 if (MHI_REG_ACCESS_VALID(prev_state)) {
606 u32 in_reset = -1;
607 unsigned long timeout = msecs_to_jiffies(mhi_cntrl->timeout_ms);
608
609 dev_dbg(dev, "Triggering MHI Reset in device\n");
610 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
611
612 /* Wait for the reset bit to be cleared by the device */
613 ret = wait_event_timeout(mhi_cntrl->state_event,
614 mhi_read_reg_field(mhi_cntrl,
615 mhi_cntrl->regs,
616 MHICTRL,
617 MHICTRL_RESET_MASK,
618 &in_reset) ||
619 !in_reset, timeout);
620 if (!ret || in_reset) {
621 dev_err(dev, "Device failed to exit MHI Reset state\n");
622 goto exit_sys_error_transition;
623 }
624
625 /*
626 * Device will clear BHI_INTVEC as a part of RESET processing,
627 * hence re-program it
628 */
629 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
630 }
631
632 dev_dbg(dev,
633 "Waiting for all pending event ring processing to complete\n");
634 mhi_event = mhi_cntrl->mhi_event;
635 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
636 if (mhi_event->offload_ev)
637 continue;
638 tasklet_kill(&mhi_event->task);
639 }
640
641 /* Release lock and wait for all pending threads to complete */
642 mutex_unlock(&mhi_cntrl->pm_mutex);
643 dev_dbg(dev, "Waiting for all pending threads to complete\n");
644 wake_up_all(&mhi_cntrl->state_event);
645
646 dev_dbg(dev, "Reset all active channels and remove MHI devices\n");
647 device_for_each_child(&mhi_cntrl->mhi_dev->dev, NULL, mhi_destroy_device);
648
649 mutex_lock(&mhi_cntrl->pm_mutex);
650
651 WARN_ON(atomic_read(&mhi_cntrl->dev_wake));
652 WARN_ON(atomic_read(&mhi_cntrl->pending_pkts));
653
654 /* Reset the ev rings and cmd rings */
655 dev_dbg(dev, "Resetting EV CTXT and CMD CTXT\n");
656 mhi_cmd = mhi_cntrl->mhi_cmd;
657 cmd_ctxt = mhi_cntrl->mhi_ctxt->cmd_ctxt;
658 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++, cmd_ctxt++) {
659 struct mhi_ring *ring = &mhi_cmd->ring;
660
661 ring->rp = ring->base;
662 ring->wp = ring->base;
663 cmd_ctxt->rp = cmd_ctxt->rbase;
664 cmd_ctxt->wp = cmd_ctxt->rbase;
665 }
666
667 mhi_event = mhi_cntrl->mhi_event;
668 er_ctxt = mhi_cntrl->mhi_ctxt->er_ctxt;
669 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++,
670 mhi_event++) {
671 struct mhi_ring *ring = &mhi_event->ring;
672
673 /* Skip offload events */
674 if (mhi_event->offload_ev)
675 continue;
676
677 ring->rp = ring->base;
678 ring->wp = ring->base;
679 er_ctxt->rp = er_ctxt->rbase;
680 er_ctxt->wp = er_ctxt->rbase;
681 }
682
683 /* Transition to next state */
684 if (MHI_IN_PBL(mhi_get_exec_env(mhi_cntrl))) {
685 write_lock_irq(&mhi_cntrl->pm_lock);
686 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_POR);
687 write_unlock_irq(&mhi_cntrl->pm_lock);
688 if (cur_state != MHI_PM_POR) {
689 dev_err(dev, "Error moving to state %s from %s\n",
690 to_mhi_pm_state_str(MHI_PM_POR),
691 to_mhi_pm_state_str(cur_state));
692 goto exit_sys_error_transition;
693 }
694 next_state = DEV_ST_TRANSITION_PBL;
695 } else {
696 next_state = DEV_ST_TRANSITION_READY;
697 }
698
699 mhi_queue_state_transition(mhi_cntrl, next_state);
700
701 exit_sys_error_transition:
702 dev_dbg(dev, "Exiting with PM state: %s, MHI state: %s\n",
703 to_mhi_pm_state_str(mhi_cntrl->pm_state),
704 mhi_state_str(mhi_cntrl->dev_state));
705
706 mutex_unlock(&mhi_cntrl->pm_mutex);
707 }
708
709 /* Queue a new work item and schedule work */
mhi_queue_state_transition(struct mhi_controller * mhi_cntrl,enum dev_st_transition state)710 int mhi_queue_state_transition(struct mhi_controller *mhi_cntrl,
711 enum dev_st_transition state)
712 {
713 struct state_transition *item = kmalloc(sizeof(*item), GFP_ATOMIC);
714 unsigned long flags;
715
716 if (!item)
717 return -ENOMEM;
718
719 item->state = state;
720 spin_lock_irqsave(&mhi_cntrl->transition_lock, flags);
721 list_add_tail(&item->node, &mhi_cntrl->transition_list);
722 spin_unlock_irqrestore(&mhi_cntrl->transition_lock, flags);
723
724 queue_work(mhi_cntrl->hiprio_wq, &mhi_cntrl->st_worker);
725
726 return 0;
727 }
728
729 /* SYS_ERR worker */
mhi_pm_sys_err_handler(struct mhi_controller * mhi_cntrl)730 void mhi_pm_sys_err_handler(struct mhi_controller *mhi_cntrl)
731 {
732 struct device *dev = &mhi_cntrl->mhi_dev->dev;
733
734 /* skip if controller supports RDDM */
735 if (mhi_cntrl->rddm_image) {
736 dev_dbg(dev, "Controller supports RDDM, skip SYS_ERROR\n");
737 return;
738 }
739
740 mhi_queue_state_transition(mhi_cntrl, DEV_ST_TRANSITION_SYS_ERR);
741 }
742
743 /* Device State Transition worker */
mhi_pm_st_worker(struct work_struct * work)744 void mhi_pm_st_worker(struct work_struct *work)
745 {
746 struct state_transition *itr, *tmp;
747 LIST_HEAD(head);
748 struct mhi_controller *mhi_cntrl = container_of(work,
749 struct mhi_controller,
750 st_worker);
751 struct device *dev = &mhi_cntrl->mhi_dev->dev;
752
753 spin_lock_irq(&mhi_cntrl->transition_lock);
754 list_splice_tail_init(&mhi_cntrl->transition_list, &head);
755 spin_unlock_irq(&mhi_cntrl->transition_lock);
756
757 list_for_each_entry_safe(itr, tmp, &head, node) {
758 list_del(&itr->node);
759 dev_dbg(dev, "Handling state transition: %s\n",
760 TO_DEV_STATE_TRANS_STR(itr->state));
761
762 switch (itr->state) {
763 case DEV_ST_TRANSITION_PBL:
764 write_lock_irq(&mhi_cntrl->pm_lock);
765 if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state))
766 mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl);
767 write_unlock_irq(&mhi_cntrl->pm_lock);
768 mhi_fw_load_handler(mhi_cntrl);
769 break;
770 case DEV_ST_TRANSITION_SBL:
771 write_lock_irq(&mhi_cntrl->pm_lock);
772 mhi_cntrl->ee = MHI_EE_SBL;
773 write_unlock_irq(&mhi_cntrl->pm_lock);
774 /*
775 * The MHI devices are only created when the client
776 * device switches its Execution Environment (EE) to
777 * either SBL or AMSS states
778 */
779 mhi_create_devices(mhi_cntrl);
780 if (mhi_cntrl->fbc_download)
781 mhi_download_amss_image(mhi_cntrl);
782 break;
783 case DEV_ST_TRANSITION_MISSION_MODE:
784 mhi_pm_mission_mode_transition(mhi_cntrl);
785 break;
786 case DEV_ST_TRANSITION_FP:
787 write_lock_irq(&mhi_cntrl->pm_lock);
788 mhi_cntrl->ee = MHI_EE_FP;
789 write_unlock_irq(&mhi_cntrl->pm_lock);
790 mhi_create_devices(mhi_cntrl);
791 break;
792 case DEV_ST_TRANSITION_READY:
793 mhi_ready_state_transition(mhi_cntrl);
794 break;
795 case DEV_ST_TRANSITION_SYS_ERR:
796 mhi_pm_sys_error_transition(mhi_cntrl);
797 break;
798 case DEV_ST_TRANSITION_DISABLE:
799 mhi_pm_disable_transition(mhi_cntrl);
800 break;
801 default:
802 break;
803 }
804 kfree(itr);
805 }
806 }
807
mhi_pm_suspend(struct mhi_controller * mhi_cntrl)808 int mhi_pm_suspend(struct mhi_controller *mhi_cntrl)
809 {
810 struct mhi_chan *itr, *tmp;
811 struct device *dev = &mhi_cntrl->mhi_dev->dev;
812 enum mhi_pm_state new_state;
813 int ret;
814
815 if (mhi_cntrl->pm_state == MHI_PM_DISABLE)
816 return -EINVAL;
817
818 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))
819 return -EIO;
820
821 /* Return busy if there are any pending resources */
822 if (atomic_read(&mhi_cntrl->dev_wake) ||
823 atomic_read(&mhi_cntrl->pending_pkts))
824 return -EBUSY;
825
826 /* Take MHI out of M2 state */
827 read_lock_bh(&mhi_cntrl->pm_lock);
828 mhi_cntrl->wake_get(mhi_cntrl, false);
829 read_unlock_bh(&mhi_cntrl->pm_lock);
830
831 ret = wait_event_timeout(mhi_cntrl->state_event,
832 mhi_cntrl->dev_state == MHI_STATE_M0 ||
833 mhi_cntrl->dev_state == MHI_STATE_M1 ||
834 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
835 msecs_to_jiffies(mhi_cntrl->timeout_ms));
836
837 read_lock_bh(&mhi_cntrl->pm_lock);
838 mhi_cntrl->wake_put(mhi_cntrl, false);
839 read_unlock_bh(&mhi_cntrl->pm_lock);
840
841 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
842 dev_err(dev,
843 "Could not enter M0/M1 state");
844 return -EIO;
845 }
846
847 write_lock_irq(&mhi_cntrl->pm_lock);
848
849 if (atomic_read(&mhi_cntrl->dev_wake) ||
850 atomic_read(&mhi_cntrl->pending_pkts)) {
851 write_unlock_irq(&mhi_cntrl->pm_lock);
852 return -EBUSY;
853 }
854
855 dev_dbg(dev, "Allowing M3 transition\n");
856 new_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_ENTER);
857 if (new_state != MHI_PM_M3_ENTER) {
858 write_unlock_irq(&mhi_cntrl->pm_lock);
859 dev_err(dev,
860 "Error setting to PM state: %s from: %s\n",
861 to_mhi_pm_state_str(MHI_PM_M3_ENTER),
862 to_mhi_pm_state_str(mhi_cntrl->pm_state));
863 return -EIO;
864 }
865
866 /* Set MHI to M3 and wait for completion */
867 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M3);
868 write_unlock_irq(&mhi_cntrl->pm_lock);
869 dev_dbg(dev, "Waiting for M3 completion\n");
870
871 ret = wait_event_timeout(mhi_cntrl->state_event,
872 mhi_cntrl->dev_state == MHI_STATE_M3 ||
873 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
874 msecs_to_jiffies(mhi_cntrl->timeout_ms));
875
876 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
877 dev_err(dev,
878 "Did not enter M3 state, MHI state: %s, PM state: %s\n",
879 mhi_state_str(mhi_cntrl->dev_state),
880 to_mhi_pm_state_str(mhi_cntrl->pm_state));
881 return -EIO;
882 }
883
884 /* Notify clients about entering LPM */
885 list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) {
886 mutex_lock(&itr->mutex);
887 if (itr->mhi_dev)
888 mhi_notify(itr->mhi_dev, MHI_CB_LPM_ENTER);
889 mutex_unlock(&itr->mutex);
890 }
891
892 return 0;
893 }
894 EXPORT_SYMBOL_GPL(mhi_pm_suspend);
895
__mhi_pm_resume(struct mhi_controller * mhi_cntrl,bool force)896 static int __mhi_pm_resume(struct mhi_controller *mhi_cntrl, bool force)
897 {
898 struct mhi_chan *itr, *tmp;
899 struct device *dev = &mhi_cntrl->mhi_dev->dev;
900 enum mhi_pm_state cur_state;
901 int ret;
902
903 dev_dbg(dev, "Entered with PM state: %s, MHI state: %s\n",
904 to_mhi_pm_state_str(mhi_cntrl->pm_state),
905 mhi_state_str(mhi_cntrl->dev_state));
906
907 if (mhi_cntrl->pm_state == MHI_PM_DISABLE)
908 return 0;
909
910 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))
911 return -EIO;
912
913 if (mhi_get_mhi_state(mhi_cntrl) != MHI_STATE_M3) {
914 dev_warn(dev, "Resuming from non M3 state (%s)\n",
915 mhi_state_str(mhi_get_mhi_state(mhi_cntrl)));
916 if (!force)
917 return -EINVAL;
918 }
919
920 /* Notify clients about exiting LPM */
921 list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) {
922 mutex_lock(&itr->mutex);
923 if (itr->mhi_dev)
924 mhi_notify(itr->mhi_dev, MHI_CB_LPM_EXIT);
925 mutex_unlock(&itr->mutex);
926 }
927
928 write_lock_irq(&mhi_cntrl->pm_lock);
929 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_EXIT);
930 if (cur_state != MHI_PM_M3_EXIT) {
931 write_unlock_irq(&mhi_cntrl->pm_lock);
932 dev_info(dev,
933 "Error setting to PM state: %s from: %s\n",
934 to_mhi_pm_state_str(MHI_PM_M3_EXIT),
935 to_mhi_pm_state_str(mhi_cntrl->pm_state));
936 return -EIO;
937 }
938
939 /* Set MHI to M0 and wait for completion */
940 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M0);
941 write_unlock_irq(&mhi_cntrl->pm_lock);
942
943 ret = wait_event_timeout(mhi_cntrl->state_event,
944 mhi_cntrl->dev_state == MHI_STATE_M0 ||
945 mhi_cntrl->dev_state == MHI_STATE_M2 ||
946 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
947 msecs_to_jiffies(mhi_cntrl->timeout_ms));
948
949 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
950 dev_err(dev,
951 "Did not enter M0 state, MHI state: %s, PM state: %s\n",
952 mhi_state_str(mhi_cntrl->dev_state),
953 to_mhi_pm_state_str(mhi_cntrl->pm_state));
954 return -EIO;
955 }
956
957 return 0;
958 }
959
mhi_pm_resume(struct mhi_controller * mhi_cntrl)960 int mhi_pm_resume(struct mhi_controller *mhi_cntrl)
961 {
962 return __mhi_pm_resume(mhi_cntrl, false);
963 }
964 EXPORT_SYMBOL_GPL(mhi_pm_resume);
965
mhi_pm_resume_force(struct mhi_controller * mhi_cntrl)966 int mhi_pm_resume_force(struct mhi_controller *mhi_cntrl)
967 {
968 return __mhi_pm_resume(mhi_cntrl, true);
969 }
970 EXPORT_SYMBOL_GPL(mhi_pm_resume_force);
971
__mhi_device_get_sync(struct mhi_controller * mhi_cntrl)972 int __mhi_device_get_sync(struct mhi_controller *mhi_cntrl)
973 {
974 int ret;
975
976 /* Wake up the device */
977 read_lock_bh(&mhi_cntrl->pm_lock);
978 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
979 read_unlock_bh(&mhi_cntrl->pm_lock);
980 return -EIO;
981 }
982 mhi_cntrl->wake_get(mhi_cntrl, true);
983 if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state))
984 mhi_trigger_resume(mhi_cntrl);
985 read_unlock_bh(&mhi_cntrl->pm_lock);
986
987 ret = wait_event_timeout(mhi_cntrl->state_event,
988 mhi_cntrl->pm_state == MHI_PM_M0 ||
989 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
990 msecs_to_jiffies(mhi_cntrl->timeout_ms));
991
992 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
993 read_lock_bh(&mhi_cntrl->pm_lock);
994 mhi_cntrl->wake_put(mhi_cntrl, false);
995 read_unlock_bh(&mhi_cntrl->pm_lock);
996 return -EIO;
997 }
998
999 return 0;
1000 }
1001
1002 /* Assert device wake db */
mhi_assert_dev_wake(struct mhi_controller * mhi_cntrl,bool force)1003 static void mhi_assert_dev_wake(struct mhi_controller *mhi_cntrl, bool force)
1004 {
1005 unsigned long flags;
1006
1007 /*
1008 * If force flag is set, then increment the wake count value and
1009 * ring wake db
1010 */
1011 if (unlikely(force)) {
1012 spin_lock_irqsave(&mhi_cntrl->wlock, flags);
1013 atomic_inc(&mhi_cntrl->dev_wake);
1014 if (MHI_WAKE_DB_FORCE_SET_VALID(mhi_cntrl->pm_state) &&
1015 !mhi_cntrl->wake_set) {
1016 mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 1);
1017 mhi_cntrl->wake_set = true;
1018 }
1019 spin_unlock_irqrestore(&mhi_cntrl->wlock, flags);
1020 } else {
1021 /*
1022 * If resources are already requested, then just increment
1023 * the wake count value and return
1024 */
1025 if (likely(atomic_add_unless(&mhi_cntrl->dev_wake, 1, 0)))
1026 return;
1027
1028 spin_lock_irqsave(&mhi_cntrl->wlock, flags);
1029 if ((atomic_inc_return(&mhi_cntrl->dev_wake) == 1) &&
1030 MHI_WAKE_DB_SET_VALID(mhi_cntrl->pm_state) &&
1031 !mhi_cntrl->wake_set) {
1032 mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 1);
1033 mhi_cntrl->wake_set = true;
1034 }
1035 spin_unlock_irqrestore(&mhi_cntrl->wlock, flags);
1036 }
1037 }
1038
1039 /* De-assert device wake db */
mhi_deassert_dev_wake(struct mhi_controller * mhi_cntrl,bool override)1040 static void mhi_deassert_dev_wake(struct mhi_controller *mhi_cntrl,
1041 bool override)
1042 {
1043 unsigned long flags;
1044
1045 /*
1046 * Only continue if there is a single resource, else just decrement
1047 * and return
1048 */
1049 if (likely(atomic_add_unless(&mhi_cntrl->dev_wake, -1, 1)))
1050 return;
1051
1052 spin_lock_irqsave(&mhi_cntrl->wlock, flags);
1053 if ((atomic_dec_return(&mhi_cntrl->dev_wake) == 0) &&
1054 MHI_WAKE_DB_CLEAR_VALID(mhi_cntrl->pm_state) && !override &&
1055 mhi_cntrl->wake_set) {
1056 mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 0);
1057 mhi_cntrl->wake_set = false;
1058 }
1059 spin_unlock_irqrestore(&mhi_cntrl->wlock, flags);
1060 }
1061
mhi_async_power_up(struct mhi_controller * mhi_cntrl)1062 int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
1063 {
1064 struct mhi_event *mhi_event = mhi_cntrl->mhi_event;
1065 enum mhi_state state;
1066 enum mhi_ee_type current_ee;
1067 enum dev_st_transition next_state;
1068 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1069 u32 interval_us = 25000; /* poll register field every 25 milliseconds */
1070 int ret, i;
1071
1072 dev_info(dev, "Requested to power ON\n");
1073
1074 /* Supply default wake routines if not provided by controller driver */
1075 if (!mhi_cntrl->wake_get || !mhi_cntrl->wake_put ||
1076 !mhi_cntrl->wake_toggle) {
1077 mhi_cntrl->wake_get = mhi_assert_dev_wake;
1078 mhi_cntrl->wake_put = mhi_deassert_dev_wake;
1079 mhi_cntrl->wake_toggle = (mhi_cntrl->db_access & MHI_PM_M2) ?
1080 mhi_toggle_dev_wake_nop : mhi_toggle_dev_wake;
1081 }
1082
1083 mutex_lock(&mhi_cntrl->pm_mutex);
1084 mhi_cntrl->pm_state = MHI_PM_DISABLE;
1085
1086 /* Setup BHI INTVEC */
1087 write_lock_irq(&mhi_cntrl->pm_lock);
1088 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
1089 mhi_cntrl->pm_state = MHI_PM_POR;
1090 mhi_cntrl->ee = MHI_EE_MAX;
1091 current_ee = mhi_get_exec_env(mhi_cntrl);
1092 write_unlock_irq(&mhi_cntrl->pm_lock);
1093
1094 /* Confirm that the device is in valid exec env */
1095 if (!MHI_POWER_UP_CAPABLE(current_ee)) {
1096 dev_err(dev, "%s is not a valid EE for power on\n",
1097 TO_MHI_EXEC_STR(current_ee));
1098 ret = -EIO;
1099 goto error_exit;
1100 }
1101
1102 state = mhi_get_mhi_state(mhi_cntrl);
1103 dev_dbg(dev, "Attempting power on with EE: %s, state: %s\n",
1104 TO_MHI_EXEC_STR(current_ee), mhi_state_str(state));
1105
1106 if (state == MHI_STATE_SYS_ERR) {
1107 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
1108 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
1109 MHICTRL_RESET_MASK, 0, interval_us);
1110 if (ret) {
1111 dev_info(dev, "Failed to reset MHI due to syserr state\n");
1112 goto error_exit;
1113 }
1114
1115 /*
1116 * device cleares INTVEC as part of RESET processing,
1117 * re-program it
1118 */
1119 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
1120 }
1121
1122 /* IRQs have been requested during probe, so we just need to enable them. */
1123 enable_irq(mhi_cntrl->irq[0]);
1124
1125 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
1126 if (mhi_event->offload_ev)
1127 continue;
1128
1129 enable_irq(mhi_cntrl->irq[mhi_event->irq]);
1130 }
1131
1132 /* Transition to next state */
1133 next_state = MHI_IN_PBL(current_ee) ?
1134 DEV_ST_TRANSITION_PBL : DEV_ST_TRANSITION_READY;
1135
1136 mhi_queue_state_transition(mhi_cntrl, next_state);
1137
1138 mutex_unlock(&mhi_cntrl->pm_mutex);
1139
1140 dev_info(dev, "Power on setup success\n");
1141
1142 return 0;
1143
1144 error_exit:
1145 mhi_cntrl->pm_state = MHI_PM_DISABLE;
1146 mutex_unlock(&mhi_cntrl->pm_mutex);
1147
1148 return ret;
1149 }
1150 EXPORT_SYMBOL_GPL(mhi_async_power_up);
1151
mhi_power_down(struct mhi_controller * mhi_cntrl,bool graceful)1152 void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful)
1153 {
1154 enum mhi_pm_state cur_state, transition_state;
1155 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1156
1157 mutex_lock(&mhi_cntrl->pm_mutex);
1158 write_lock_irq(&mhi_cntrl->pm_lock);
1159 cur_state = mhi_cntrl->pm_state;
1160 if (cur_state == MHI_PM_DISABLE) {
1161 write_unlock_irq(&mhi_cntrl->pm_lock);
1162 mutex_unlock(&mhi_cntrl->pm_mutex);
1163 return; /* Already powered down */
1164 }
1165
1166 /* If it's not a graceful shutdown, force MHI to linkdown state */
1167 transition_state = (graceful) ? MHI_PM_SHUTDOWN_PROCESS :
1168 MHI_PM_LD_ERR_FATAL_DETECT;
1169
1170 cur_state = mhi_tryset_pm_state(mhi_cntrl, transition_state);
1171 if (cur_state != transition_state) {
1172 dev_err(dev, "Failed to move to state: %s from: %s\n",
1173 to_mhi_pm_state_str(transition_state),
1174 to_mhi_pm_state_str(mhi_cntrl->pm_state));
1175 /* Force link down or error fatal detected state */
1176 mhi_cntrl->pm_state = MHI_PM_LD_ERR_FATAL_DETECT;
1177 }
1178
1179 /* mark device inactive to avoid any further host processing */
1180 mhi_cntrl->ee = MHI_EE_DISABLE_TRANSITION;
1181 mhi_cntrl->dev_state = MHI_STATE_RESET;
1182
1183 wake_up_all(&mhi_cntrl->state_event);
1184
1185 write_unlock_irq(&mhi_cntrl->pm_lock);
1186 mutex_unlock(&mhi_cntrl->pm_mutex);
1187
1188 mhi_queue_state_transition(mhi_cntrl, DEV_ST_TRANSITION_DISABLE);
1189
1190 /* Wait for shutdown to complete */
1191 flush_work(&mhi_cntrl->st_worker);
1192
1193 disable_irq(mhi_cntrl->irq[0]);
1194 }
1195 EXPORT_SYMBOL_GPL(mhi_power_down);
1196
mhi_sync_power_up(struct mhi_controller * mhi_cntrl)1197 int mhi_sync_power_up(struct mhi_controller *mhi_cntrl)
1198 {
1199 int ret = mhi_async_power_up(mhi_cntrl);
1200
1201 if (ret)
1202 return ret;
1203
1204 wait_event_timeout(mhi_cntrl->state_event,
1205 MHI_IN_MISSION_MODE(mhi_cntrl->ee) ||
1206 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
1207 msecs_to_jiffies(mhi_cntrl->timeout_ms));
1208
1209 ret = (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) ? 0 : -ETIMEDOUT;
1210 if (ret)
1211 mhi_power_down(mhi_cntrl, false);
1212
1213 return ret;
1214 }
1215 EXPORT_SYMBOL(mhi_sync_power_up);
1216
mhi_force_rddm_mode(struct mhi_controller * mhi_cntrl)1217 int mhi_force_rddm_mode(struct mhi_controller *mhi_cntrl)
1218 {
1219 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1220 int ret;
1221
1222 /* Check if device is already in RDDM */
1223 if (mhi_cntrl->ee == MHI_EE_RDDM)
1224 return 0;
1225
1226 dev_dbg(dev, "Triggering SYS_ERR to force RDDM state\n");
1227 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_SYS_ERR);
1228
1229 /* Wait for RDDM event */
1230 ret = wait_event_timeout(mhi_cntrl->state_event,
1231 mhi_cntrl->ee == MHI_EE_RDDM,
1232 msecs_to_jiffies(mhi_cntrl->timeout_ms));
1233 ret = ret ? 0 : -EIO;
1234
1235 return ret;
1236 }
1237 EXPORT_SYMBOL_GPL(mhi_force_rddm_mode);
1238
mhi_device_get(struct mhi_device * mhi_dev)1239 void mhi_device_get(struct mhi_device *mhi_dev)
1240 {
1241 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1242
1243 mhi_dev->dev_wake++;
1244 read_lock_bh(&mhi_cntrl->pm_lock);
1245 if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state))
1246 mhi_trigger_resume(mhi_cntrl);
1247
1248 mhi_cntrl->wake_get(mhi_cntrl, true);
1249 read_unlock_bh(&mhi_cntrl->pm_lock);
1250 }
1251 EXPORT_SYMBOL_GPL(mhi_device_get);
1252
mhi_device_get_sync(struct mhi_device * mhi_dev)1253 int mhi_device_get_sync(struct mhi_device *mhi_dev)
1254 {
1255 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1256 int ret;
1257
1258 ret = __mhi_device_get_sync(mhi_cntrl);
1259 if (!ret)
1260 mhi_dev->dev_wake++;
1261
1262 return ret;
1263 }
1264 EXPORT_SYMBOL_GPL(mhi_device_get_sync);
1265
mhi_device_put(struct mhi_device * mhi_dev)1266 void mhi_device_put(struct mhi_device *mhi_dev)
1267 {
1268 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1269
1270 mhi_dev->dev_wake--;
1271 read_lock_bh(&mhi_cntrl->pm_lock);
1272 if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state))
1273 mhi_trigger_resume(mhi_cntrl);
1274
1275 mhi_cntrl->wake_put(mhi_cntrl, false);
1276 read_unlock_bh(&mhi_cntrl->pm_lock);
1277 }
1278 EXPORT_SYMBOL_GPL(mhi_device_put);
1279