1 /* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/sched.h>
21 #include <linux/time.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/hrtimer.h>
25 #include <linux/delay.h>
26
27 #include <mach/hardware.h>
28 #include <linux/io.h>
29
30 #include <asm/system.h>
31 #include <asm/mach-types.h>
32 #include <linux/semaphore.h>
33 #include <linux/spinlock.h>
34
35 #include <linux/fb.h>
36
37 #include "mdp.h"
38 #include "msm_fb.h"
39
40 extern spinlock_t mdp_spin_lock;
41 extern uint32 mdp_intr_mask;
42
mdp_dma3_on(struct platform_device * pdev)43 int mdp_dma3_on(struct platform_device *pdev)
44 {
45 struct msm_fb_data_type *mfd;
46 struct fb_info *fbi;
47 uint8 *buf;
48 int bpp;
49 int ret = 0;
50
51 mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
52
53 if (!mfd)
54 return -ENODEV;
55
56 if (mfd->key != MFD_KEY)
57 return -EINVAL;
58
59 fbi = mfd->fbi;
60 /* MDP cmd block enable */
61 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
62
63 bpp = fbi->var.bits_per_pixel / 8;
64 buf = (uint8 *) fbi->fix.smem_start;
65 buf += fbi->var.xoffset * bpp +
66 fbi->var.yoffset * fbi->fix.line_length;
67
68 /* starting address[31..8] of Video frame buffer is CS0 */
69 MDP_OUTP(MDP_BASE + 0xC0008, (uint32) buf >> 3);
70
71 mdp_pipe_ctrl(MDP_DMA3_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
72
73 MDP_OUTP(MDP_BASE + 0xC0004, 0x4c60674); /* flicker filter enabled */
74 MDP_OUTP(MDP_BASE + 0xC0010, 0x20); /* sobel treshold */
75
76 MDP_OUTP(MDP_BASE + 0xC0018, 0xeb0010); /* Y Max, Y min */
77 MDP_OUTP(MDP_BASE + 0xC001C, 0xf00010); /* Cb Max, Cb min */
78 MDP_OUTP(MDP_BASE + 0xC0020, 0xf00010); /* Cb Max, Cb min */
79
80 MDP_OUTP(MDP_BASE + 0xC000C, 0x67686970); /* add a few chars for CC */
81 MDP_OUTP(MDP_BASE + 0xC0000, 0x1); /* MDP tv out enable */
82
83 /* MDP cmd block disable */
84 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
85
86 ret = panel_next_on(pdev);
87
88 return ret;
89 }
90
mdp_dma3_off(struct platform_device * pdev)91 int mdp_dma3_off(struct platform_device *pdev)
92 {
93 int ret = 0;
94
95 ret = panel_next_off(pdev);
96 if (ret)
97 return ret;
98
99 /* MDP cmd block enable */
100 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
101 MDP_OUTP(MDP_BASE + 0xC0000, 0x0);
102 /* MDP cmd block disable */
103 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
104
105 mdp_pipe_ctrl(MDP_DMA3_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
106
107 /* delay to make sure the last frame finishes */
108 mdelay(100);
109
110 return ret;
111 }
112
mdp_dma3_update(struct msm_fb_data_type * mfd)113 void mdp_dma3_update(struct msm_fb_data_type *mfd)
114 {
115 struct fb_info *fbi = mfd->fbi;
116 uint8 *buf;
117 int bpp;
118 unsigned long flag;
119
120 if (!mfd->panel_power_on)
121 return;
122
123 /* no need to power on cmd block since dma3 is running */
124 bpp = fbi->var.bits_per_pixel / 8;
125 buf = (uint8 *) fbi->fix.smem_start;
126 buf += fbi->var.xoffset * bpp +
127 fbi->var.yoffset * fbi->fix.line_length;
128 MDP_OUTP(MDP_BASE + 0xC0008, (uint32) buf >> 3);
129
130 spin_lock_irqsave(&mdp_spin_lock, flag);
131 mdp_enable_irq(MDP_DMA3_TERM);
132 INIT_COMPLETION(mfd->dma->comp);
133 mfd->dma->waiting = TRUE;
134
135 outp32(MDP_INTR_CLEAR, TV_OUT_DMA3_START);
136 mdp_intr_mask |= TV_OUT_DMA3_START;
137 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
138 spin_unlock_irqrestore(&mdp_spin_lock, flag);
139
140 wait_for_completion_killable(&mfd->dma->comp);
141 mdp_disable_irq(MDP_DMA3_TERM);
142 }
143