1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Ethernet driver
3  *
4  * Copyright (C) 2020 Marvell.
5  *
6  */
7 
8 #include <linux/interrupt.h>
9 #include <linux/pci.h>
10 #include <net/tso.h>
11 
12 #include "otx2_reg.h"
13 #include "otx2_common.h"
14 #include "otx2_struct.h"
15 #include "cn10k.h"
16 
otx2_nix_rq_op_stats(struct queue_stats * stats,struct otx2_nic * pfvf,int qidx)17 static void otx2_nix_rq_op_stats(struct queue_stats *stats,
18 				 struct otx2_nic *pfvf, int qidx)
19 {
20 	u64 incr = (u64)qidx << 32;
21 	u64 *ptr;
22 
23 	ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS);
24 	stats->bytes = otx2_atomic64_add(incr, ptr);
25 
26 	ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS);
27 	stats->pkts = otx2_atomic64_add(incr, ptr);
28 }
29 
otx2_nix_sq_op_stats(struct queue_stats * stats,struct otx2_nic * pfvf,int qidx)30 static void otx2_nix_sq_op_stats(struct queue_stats *stats,
31 				 struct otx2_nic *pfvf, int qidx)
32 {
33 	u64 incr = (u64)qidx << 32;
34 	u64 *ptr;
35 
36 	ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS);
37 	stats->bytes = otx2_atomic64_add(incr, ptr);
38 
39 	ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS);
40 	stats->pkts = otx2_atomic64_add(incr, ptr);
41 }
42 
otx2_update_lmac_stats(struct otx2_nic * pfvf)43 void otx2_update_lmac_stats(struct otx2_nic *pfvf)
44 {
45 	struct msg_req *req;
46 
47 	if (!netif_running(pfvf->netdev))
48 		return;
49 
50 	mutex_lock(&pfvf->mbox.lock);
51 	req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox);
52 	if (!req) {
53 		mutex_unlock(&pfvf->mbox.lock);
54 		return;
55 	}
56 
57 	otx2_sync_mbox_msg(&pfvf->mbox);
58 	mutex_unlock(&pfvf->mbox.lock);
59 }
60 
otx2_update_lmac_fec_stats(struct otx2_nic * pfvf)61 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf)
62 {
63 	struct msg_req *req;
64 
65 	if (!netif_running(pfvf->netdev))
66 		return;
67 	mutex_lock(&pfvf->mbox.lock);
68 	req = otx2_mbox_alloc_msg_cgx_fec_stats(&pfvf->mbox);
69 	if (req)
70 		otx2_sync_mbox_msg(&pfvf->mbox);
71 	mutex_unlock(&pfvf->mbox.lock);
72 }
73 
otx2_update_rq_stats(struct otx2_nic * pfvf,int qidx)74 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx)
75 {
76 	struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx];
77 
78 	if (!pfvf->qset.rq)
79 		return 0;
80 
81 	otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx);
82 	return 1;
83 }
84 
otx2_update_sq_stats(struct otx2_nic * pfvf,int qidx)85 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx)
86 {
87 	struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx];
88 
89 	if (!pfvf->qset.sq)
90 		return 0;
91 
92 	otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx);
93 	return 1;
94 }
95 
otx2_get_dev_stats(struct otx2_nic * pfvf)96 void otx2_get_dev_stats(struct otx2_nic *pfvf)
97 {
98 	struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats;
99 
100 	dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS);
101 	dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP);
102 	dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST);
103 	dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST);
104 	dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST);
105 	dev_stats->rx_frames = dev_stats->rx_bcast_frames +
106 			       dev_stats->rx_mcast_frames +
107 			       dev_stats->rx_ucast_frames;
108 
109 	dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS);
110 	dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP);
111 	dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST);
112 	dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST);
113 	dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST);
114 	dev_stats->tx_frames = dev_stats->tx_bcast_frames +
115 			       dev_stats->tx_mcast_frames +
116 			       dev_stats->tx_ucast_frames;
117 }
118 
otx2_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)119 void otx2_get_stats64(struct net_device *netdev,
120 		      struct rtnl_link_stats64 *stats)
121 {
122 	struct otx2_nic *pfvf = netdev_priv(netdev);
123 	struct otx2_dev_stats *dev_stats;
124 
125 	otx2_get_dev_stats(pfvf);
126 
127 	dev_stats = &pfvf->hw.dev_stats;
128 	stats->rx_bytes = dev_stats->rx_bytes;
129 	stats->rx_packets = dev_stats->rx_frames;
130 	stats->rx_dropped = dev_stats->rx_drops;
131 	stats->multicast = dev_stats->rx_mcast_frames;
132 
133 	stats->tx_bytes = dev_stats->tx_bytes;
134 	stats->tx_packets = dev_stats->tx_frames;
135 	stats->tx_dropped = dev_stats->tx_drops;
136 }
137 EXPORT_SYMBOL(otx2_get_stats64);
138 
139 /* Sync MAC address with RVU AF */
otx2_hw_set_mac_addr(struct otx2_nic * pfvf,u8 * mac)140 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac)
141 {
142 	struct nix_set_mac_addr *req;
143 	int err;
144 
145 	mutex_lock(&pfvf->mbox.lock);
146 	req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox);
147 	if (!req) {
148 		mutex_unlock(&pfvf->mbox.lock);
149 		return -ENOMEM;
150 	}
151 
152 	ether_addr_copy(req->mac_addr, mac);
153 
154 	err = otx2_sync_mbox_msg(&pfvf->mbox);
155 	mutex_unlock(&pfvf->mbox.lock);
156 	return err;
157 }
158 
otx2_hw_get_mac_addr(struct otx2_nic * pfvf,struct net_device * netdev)159 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf,
160 				struct net_device *netdev)
161 {
162 	struct nix_get_mac_addr_rsp *rsp;
163 	struct mbox_msghdr *msghdr;
164 	struct msg_req *req;
165 	int err;
166 
167 	mutex_lock(&pfvf->mbox.lock);
168 	req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox);
169 	if (!req) {
170 		mutex_unlock(&pfvf->mbox.lock);
171 		return -ENOMEM;
172 	}
173 
174 	err = otx2_sync_mbox_msg(&pfvf->mbox);
175 	if (err) {
176 		mutex_unlock(&pfvf->mbox.lock);
177 		return err;
178 	}
179 
180 	msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
181 	if (IS_ERR(msghdr)) {
182 		mutex_unlock(&pfvf->mbox.lock);
183 		return PTR_ERR(msghdr);
184 	}
185 	rsp = (struct nix_get_mac_addr_rsp *)msghdr;
186 	eth_hw_addr_set(netdev, rsp->mac_addr);
187 	mutex_unlock(&pfvf->mbox.lock);
188 
189 	return 0;
190 }
191 
otx2_set_mac_address(struct net_device * netdev,void * p)192 int otx2_set_mac_address(struct net_device *netdev, void *p)
193 {
194 	struct otx2_nic *pfvf = netdev_priv(netdev);
195 	struct sockaddr *addr = p;
196 
197 	if (!is_valid_ether_addr(addr->sa_data))
198 		return -EADDRNOTAVAIL;
199 
200 	if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) {
201 		eth_hw_addr_set(netdev, addr->sa_data);
202 		/* update dmac field in vlan offload rule */
203 		if (netif_running(netdev) &&
204 		    pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT)
205 			otx2_install_rxvlan_offload_flow(pfvf);
206 		/* update dmac address in ntuple and DMAC filter list */
207 		if (pfvf->flags & OTX2_FLAG_DMACFLTR_SUPPORT)
208 			otx2_dmacflt_update_pfmac_flow(pfvf);
209 	} else {
210 		return -EPERM;
211 	}
212 
213 	return 0;
214 }
215 EXPORT_SYMBOL(otx2_set_mac_address);
216 
otx2_hw_set_mtu(struct otx2_nic * pfvf,int mtu)217 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu)
218 {
219 	struct nix_frs_cfg *req;
220 	u16 maxlen;
221 	int err;
222 
223 	maxlen = otx2_get_max_mtu(pfvf) + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN;
224 
225 	mutex_lock(&pfvf->mbox.lock);
226 	req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox);
227 	if (!req) {
228 		mutex_unlock(&pfvf->mbox.lock);
229 		return -ENOMEM;
230 	}
231 
232 	req->maxlen = pfvf->netdev->mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN;
233 
234 	/* Use max receive length supported by hardware for loopback devices */
235 	if (is_otx2_lbkvf(pfvf->pdev))
236 		req->maxlen = maxlen;
237 
238 	err = otx2_sync_mbox_msg(&pfvf->mbox);
239 	mutex_unlock(&pfvf->mbox.lock);
240 	return err;
241 }
242 
otx2_config_pause_frm(struct otx2_nic * pfvf)243 int otx2_config_pause_frm(struct otx2_nic *pfvf)
244 {
245 	struct cgx_pause_frm_cfg *req;
246 	int err;
247 
248 	if (is_otx2_lbkvf(pfvf->pdev))
249 		return 0;
250 
251 	mutex_lock(&pfvf->mbox.lock);
252 	req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox);
253 	if (!req) {
254 		err = -ENOMEM;
255 		goto unlock;
256 	}
257 
258 	req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED);
259 	req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED);
260 	req->set = 1;
261 
262 	err = otx2_sync_mbox_msg(&pfvf->mbox);
263 unlock:
264 	mutex_unlock(&pfvf->mbox.lock);
265 	return err;
266 }
267 EXPORT_SYMBOL(otx2_config_pause_frm);
268 
otx2_set_flowkey_cfg(struct otx2_nic * pfvf)269 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf)
270 {
271 	struct otx2_rss_info *rss = &pfvf->hw.rss_info;
272 	struct nix_rss_flowkey_cfg_rsp *rsp;
273 	struct nix_rss_flowkey_cfg *req;
274 	int err;
275 
276 	mutex_lock(&pfvf->mbox.lock);
277 	req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox);
278 	if (!req) {
279 		mutex_unlock(&pfvf->mbox.lock);
280 		return -ENOMEM;
281 	}
282 	req->mcam_index = -1; /* Default or reserved index */
283 	req->flowkey_cfg = rss->flowkey_cfg;
284 	req->group = DEFAULT_RSS_CONTEXT_GROUP;
285 
286 	err = otx2_sync_mbox_msg(&pfvf->mbox);
287 	if (err)
288 		goto fail;
289 
290 	rsp = (struct nix_rss_flowkey_cfg_rsp *)
291 			otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
292 	if (IS_ERR(rsp)) {
293 		err = PTR_ERR(rsp);
294 		goto fail;
295 	}
296 
297 	pfvf->hw.flowkey_alg_idx = rsp->alg_idx;
298 fail:
299 	mutex_unlock(&pfvf->mbox.lock);
300 	return err;
301 }
302 
otx2_set_rss_table(struct otx2_nic * pfvf,int ctx_id)303 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id)
304 {
305 	struct otx2_rss_info *rss = &pfvf->hw.rss_info;
306 	const int index = rss->rss_size * ctx_id;
307 	struct mbox *mbox = &pfvf->mbox;
308 	struct otx2_rss_ctx *rss_ctx;
309 	struct nix_aq_enq_req *aq;
310 	int idx, err;
311 
312 	mutex_lock(&mbox->lock);
313 	rss_ctx = rss->rss_ctx[ctx_id];
314 	/* Get memory to put this msg */
315 	for (idx = 0; idx < rss->rss_size; idx++) {
316 		aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
317 		if (!aq) {
318 			/* The shared memory buffer can be full.
319 			 * Flush it and retry
320 			 */
321 			err = otx2_sync_mbox_msg(mbox);
322 			if (err) {
323 				mutex_unlock(&mbox->lock);
324 				return err;
325 			}
326 			aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
327 			if (!aq) {
328 				mutex_unlock(&mbox->lock);
329 				return -ENOMEM;
330 			}
331 		}
332 
333 		aq->rss.rq = rss_ctx->ind_tbl[idx];
334 
335 		/* Fill AQ info */
336 		aq->qidx = index + idx;
337 		aq->ctype = NIX_AQ_CTYPE_RSS;
338 		aq->op = NIX_AQ_INSTOP_INIT;
339 	}
340 	err = otx2_sync_mbox_msg(mbox);
341 	mutex_unlock(&mbox->lock);
342 	return err;
343 }
344 
otx2_set_rss_key(struct otx2_nic * pfvf)345 void otx2_set_rss_key(struct otx2_nic *pfvf)
346 {
347 	struct otx2_rss_info *rss = &pfvf->hw.rss_info;
348 	u64 *key = (u64 *)&rss->key[4];
349 	int idx;
350 
351 	/* 352bit or 44byte key needs to be configured as below
352 	 * NIX_LF_RX_SECRETX0 = key<351:288>
353 	 * NIX_LF_RX_SECRETX1 = key<287:224>
354 	 * NIX_LF_RX_SECRETX2 = key<223:160>
355 	 * NIX_LF_RX_SECRETX3 = key<159:96>
356 	 * NIX_LF_RX_SECRETX4 = key<95:32>
357 	 * NIX_LF_RX_SECRETX5<63:32> = key<31:0>
358 	 */
359 	otx2_write64(pfvf, NIX_LF_RX_SECRETX(5),
360 		     (u64)(*((u32 *)&rss->key)) << 32);
361 	idx = sizeof(rss->key) / sizeof(u64);
362 	while (idx > 0) {
363 		idx--;
364 		otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++);
365 	}
366 }
367 
otx2_rss_init(struct otx2_nic * pfvf)368 int otx2_rss_init(struct otx2_nic *pfvf)
369 {
370 	struct otx2_rss_info *rss = &pfvf->hw.rss_info;
371 	struct otx2_rss_ctx *rss_ctx;
372 	int idx, ret = 0;
373 
374 	rss->rss_size = sizeof(*rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]);
375 
376 	/* Init RSS key if it is not setup already */
377 	if (!rss->enable)
378 		netdev_rss_key_fill(rss->key, sizeof(rss->key));
379 	otx2_set_rss_key(pfvf);
380 
381 	if (!netif_is_rxfh_configured(pfvf->netdev)) {
382 		/* Set RSS group 0 as default indirection table */
383 		rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP] = kzalloc(rss->rss_size,
384 								  GFP_KERNEL);
385 		if (!rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP])
386 			return -ENOMEM;
387 
388 		rss_ctx = rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP];
389 		for (idx = 0; idx < rss->rss_size; idx++)
390 			rss_ctx->ind_tbl[idx] =
391 				ethtool_rxfh_indir_default(idx,
392 							   pfvf->hw.rx_queues);
393 	}
394 	ret = otx2_set_rss_table(pfvf, DEFAULT_RSS_CONTEXT_GROUP);
395 	if (ret)
396 		return ret;
397 
398 	/* Flowkey or hash config to be used for generating flow tag */
399 	rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg :
400 			   NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 |
401 			   NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP |
402 			   NIX_FLOW_KEY_TYPE_SCTP | NIX_FLOW_KEY_TYPE_VLAN |
403 			   NIX_FLOW_KEY_TYPE_IPV4_PROTO;
404 
405 	ret = otx2_set_flowkey_cfg(pfvf);
406 	if (ret)
407 		return ret;
408 
409 	rss->enable = true;
410 	return 0;
411 }
412 
413 /* Setup UDP segmentation algorithm in HW */
otx2_setup_udp_segmentation(struct nix_lso_format_cfg * lso,bool v4)414 static void otx2_setup_udp_segmentation(struct nix_lso_format_cfg *lso, bool v4)
415 {
416 	struct nix_lso_format *field;
417 
418 	field = (struct nix_lso_format *)&lso->fields[0];
419 	lso->field_mask = GENMASK(18, 0);
420 
421 	/* IP's Length field */
422 	field->layer = NIX_TXLAYER_OL3;
423 	/* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */
424 	field->offset = v4 ? 2 : 4;
425 	field->sizem1 = 1; /* i.e 2 bytes */
426 	field->alg = NIX_LSOALG_ADD_PAYLEN;
427 	field++;
428 
429 	/* No ID field in IPv6 header */
430 	if (v4) {
431 		/* Increment IPID */
432 		field->layer = NIX_TXLAYER_OL3;
433 		field->offset = 4;
434 		field->sizem1 = 1; /* i.e 2 bytes */
435 		field->alg = NIX_LSOALG_ADD_SEGNUM;
436 		field++;
437 	}
438 
439 	/* Update length in UDP header */
440 	field->layer = NIX_TXLAYER_OL4;
441 	field->offset = 4;
442 	field->sizem1 = 1;
443 	field->alg = NIX_LSOALG_ADD_PAYLEN;
444 }
445 
446 /* Setup segmentation algorithms in HW and retrieve algorithm index */
otx2_setup_segmentation(struct otx2_nic * pfvf)447 void otx2_setup_segmentation(struct otx2_nic *pfvf)
448 {
449 	struct nix_lso_format_cfg_rsp *rsp;
450 	struct nix_lso_format_cfg *lso;
451 	struct otx2_hw *hw = &pfvf->hw;
452 	int err;
453 
454 	mutex_lock(&pfvf->mbox.lock);
455 
456 	/* UDPv4 segmentation */
457 	lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox);
458 	if (!lso)
459 		goto fail;
460 
461 	/* Setup UDP/IP header fields that HW should update per segment */
462 	otx2_setup_udp_segmentation(lso, true);
463 
464 	err = otx2_sync_mbox_msg(&pfvf->mbox);
465 	if (err)
466 		goto fail;
467 
468 	rsp = (struct nix_lso_format_cfg_rsp *)
469 			otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr);
470 	if (IS_ERR(rsp))
471 		goto fail;
472 
473 	hw->lso_udpv4_idx = rsp->lso_format_idx;
474 
475 	/* UDPv6 segmentation */
476 	lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox);
477 	if (!lso)
478 		goto fail;
479 
480 	/* Setup UDP/IP header fields that HW should update per segment */
481 	otx2_setup_udp_segmentation(lso, false);
482 
483 	err = otx2_sync_mbox_msg(&pfvf->mbox);
484 	if (err)
485 		goto fail;
486 
487 	rsp = (struct nix_lso_format_cfg_rsp *)
488 			otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr);
489 	if (IS_ERR(rsp))
490 		goto fail;
491 
492 	hw->lso_udpv6_idx = rsp->lso_format_idx;
493 	mutex_unlock(&pfvf->mbox.lock);
494 	return;
495 fail:
496 	mutex_unlock(&pfvf->mbox.lock);
497 	netdev_info(pfvf->netdev,
498 		    "Failed to get LSO index for UDP GSO offload, disabling\n");
499 	pfvf->netdev->hw_features &= ~NETIF_F_GSO_UDP_L4;
500 }
501 
otx2_config_irq_coalescing(struct otx2_nic * pfvf,int qidx)502 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx)
503 {
504 	/* Configure CQE interrupt coalescing parameters
505 	 *
506 	 * HW triggers an irq when ECOUNT > cq_ecount_wait, hence
507 	 * set 1 less than cq_ecount_wait. And cq_time_wait is in
508 	 * usecs, convert that to 100ns count.
509 	 */
510 	otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx),
511 		     ((u64)(pfvf->hw.cq_time_wait * 10) << 48) |
512 		     ((u64)pfvf->hw.cq_qcount_wait << 32) |
513 		     (pfvf->hw.cq_ecount_wait - 1));
514 }
515 
__otx2_alloc_rbuf(struct otx2_nic * pfvf,struct otx2_pool * pool,dma_addr_t * dma)516 int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
517 		      dma_addr_t *dma)
518 {
519 	u8 *buf;
520 
521 	buf = napi_alloc_frag_align(pool->rbsize, OTX2_ALIGN);
522 	if (unlikely(!buf))
523 		return -ENOMEM;
524 
525 	*dma = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize,
526 				    DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
527 	if (unlikely(dma_mapping_error(pfvf->dev, *dma))) {
528 		page_frag_free(buf);
529 		return -ENOMEM;
530 	}
531 
532 	return 0;
533 }
534 
otx2_alloc_rbuf(struct otx2_nic * pfvf,struct otx2_pool * pool,dma_addr_t * dma)535 static int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
536 			   dma_addr_t *dma)
537 {
538 	int ret;
539 
540 	local_bh_disable();
541 	ret = __otx2_alloc_rbuf(pfvf, pool, dma);
542 	local_bh_enable();
543 	return ret;
544 }
545 
otx2_alloc_buffer(struct otx2_nic * pfvf,struct otx2_cq_queue * cq,dma_addr_t * dma)546 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq,
547 		      dma_addr_t *dma)
548 {
549 	if (unlikely(__otx2_alloc_rbuf(pfvf, cq->rbpool, dma))) {
550 		struct refill_work *work;
551 		struct delayed_work *dwork;
552 
553 		work = &pfvf->refill_wrk[cq->cq_idx];
554 		dwork = &work->pool_refill_work;
555 		/* Schedule a task if no other task is running */
556 		if (!cq->refill_task_sched) {
557 			cq->refill_task_sched = true;
558 			schedule_delayed_work(dwork,
559 					      msecs_to_jiffies(100));
560 		}
561 		return -ENOMEM;
562 	}
563 	return 0;
564 }
565 
otx2_tx_timeout(struct net_device * netdev,unsigned int txq)566 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq)
567 {
568 	struct otx2_nic *pfvf = netdev_priv(netdev);
569 
570 	schedule_work(&pfvf->reset_task);
571 }
572 EXPORT_SYMBOL(otx2_tx_timeout);
573 
otx2_get_mac_from_af(struct net_device * netdev)574 void otx2_get_mac_from_af(struct net_device *netdev)
575 {
576 	struct otx2_nic *pfvf = netdev_priv(netdev);
577 	int err;
578 
579 	err = otx2_hw_get_mac_addr(pfvf, netdev);
580 	if (err)
581 		dev_warn(pfvf->dev, "Failed to read mac from hardware\n");
582 
583 	/* If AF doesn't provide a valid MAC, generate a random one */
584 	if (!is_valid_ether_addr(netdev->dev_addr))
585 		eth_hw_addr_random(netdev);
586 }
587 EXPORT_SYMBOL(otx2_get_mac_from_af);
588 
otx2_txschq_config(struct otx2_nic * pfvf,int lvl,int prio,bool txschq_for_pfc)589 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool txschq_for_pfc)
590 {
591 	u16 (*schq_list)[MAX_TXSCHQ_PER_FUNC];
592 	struct otx2_hw *hw = &pfvf->hw;
593 	struct nix_txschq_config *req;
594 	u64 schq, parent;
595 	u64 dwrr_val;
596 
597 	dwrr_val = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen);
598 
599 	req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox);
600 	if (!req)
601 		return -ENOMEM;
602 
603 	req->lvl = lvl;
604 	req->num_regs = 1;
605 
606 	schq_list = hw->txschq_list;
607 #ifdef CONFIG_DCB
608 	if (txschq_for_pfc)
609 		schq_list = pfvf->pfc_schq_list;
610 #endif
611 
612 	schq = schq_list[lvl][prio];
613 	/* Set topology e.t.c configuration */
614 	if (lvl == NIX_TXSCH_LVL_SMQ) {
615 		req->reg[0] = NIX_AF_SMQX_CFG(schq);
616 		req->regval[0] = ((u64)pfvf->tx_max_pktlen << 8) | OTX2_MIN_MTU;
617 		req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) |
618 				  (0x2ULL << 36);
619 		req->num_regs++;
620 		/* MDQ config */
621 		parent = schq_list[NIX_TXSCH_LVL_TL4][prio];
622 		req->reg[1] = NIX_AF_MDQX_PARENT(schq);
623 		req->regval[1] = parent << 16;
624 		req->num_regs++;
625 		/* Set DWRR quantum */
626 		req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq);
627 		req->regval[2] =  dwrr_val;
628 	} else if (lvl == NIX_TXSCH_LVL_TL4) {
629 		parent = schq_list[NIX_TXSCH_LVL_TL3][prio];
630 		req->reg[0] = NIX_AF_TL4X_PARENT(schq);
631 		req->regval[0] = parent << 16;
632 		req->num_regs++;
633 		req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq);
634 		req->regval[1] = dwrr_val;
635 	} else if (lvl == NIX_TXSCH_LVL_TL3) {
636 		parent = schq_list[NIX_TXSCH_LVL_TL2][prio];
637 		req->reg[0] = NIX_AF_TL3X_PARENT(schq);
638 		req->regval[0] = parent << 16;
639 		req->num_regs++;
640 		req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq);
641 		req->regval[1] = dwrr_val;
642 		if (lvl == hw->txschq_link_cfg_lvl) {
643 			req->num_regs++;
644 			req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link);
645 			/* Enable this queue and backpressure
646 			 * and set relative channel
647 			 */
648 			req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio;
649 		}
650 	} else if (lvl == NIX_TXSCH_LVL_TL2) {
651 		parent = schq_list[NIX_TXSCH_LVL_TL1][prio];
652 		req->reg[0] = NIX_AF_TL2X_PARENT(schq);
653 		req->regval[0] = parent << 16;
654 
655 		req->num_regs++;
656 		req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq);
657 		req->regval[1] = TXSCH_TL1_DFLT_RR_PRIO << 24 | dwrr_val;
658 
659 		if (lvl == hw->txschq_link_cfg_lvl) {
660 			req->num_regs++;
661 			req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link);
662 			/* Enable this queue and backpressure
663 			 * and set relative channel
664 			 */
665 			req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio;
666 		}
667 	} else if (lvl == NIX_TXSCH_LVL_TL1) {
668 		/* Default config for TL1.
669 		 * For VF this is always ignored.
670 		 */
671 
672 		/* On CN10K, if RR_WEIGHT is greater than 16384, HW will
673 		 * clip it to 16384, so configuring a 24bit max value
674 		 * will work on both OTx2 and CN10K.
675 		 */
676 		req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq);
677 		req->regval[0] = TXSCH_TL1_DFLT_RR_QTM;
678 
679 		req->num_regs++;
680 		req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq);
681 		req->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1);
682 
683 		req->num_regs++;
684 		req->reg[2] = NIX_AF_TL1X_CIR(schq);
685 		req->regval[2] = 0;
686 	}
687 
688 	return otx2_sync_mbox_msg(&pfvf->mbox);
689 }
690 EXPORT_SYMBOL(otx2_txschq_config);
691 
otx2_smq_flush(struct otx2_nic * pfvf,int smq)692 int otx2_smq_flush(struct otx2_nic *pfvf, int smq)
693 {
694 	struct nix_txschq_config *req;
695 	int rc;
696 
697 	mutex_lock(&pfvf->mbox.lock);
698 
699 	req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox);
700 	if (!req) {
701 		mutex_unlock(&pfvf->mbox.lock);
702 		return -ENOMEM;
703 	}
704 
705 	req->lvl = NIX_TXSCH_LVL_SMQ;
706 	req->reg[0] = NIX_AF_SMQX_CFG(smq);
707 	req->regval[0] |= BIT_ULL(49);
708 	req->num_regs++;
709 
710 	rc = otx2_sync_mbox_msg(&pfvf->mbox);
711 	mutex_unlock(&pfvf->mbox.lock);
712 	return rc;
713 }
714 EXPORT_SYMBOL(otx2_smq_flush);
715 
otx2_txsch_alloc(struct otx2_nic * pfvf)716 int otx2_txsch_alloc(struct otx2_nic *pfvf)
717 {
718 	struct nix_txsch_alloc_req *req;
719 	int lvl;
720 
721 	/* Get memory to put this msg */
722 	req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox);
723 	if (!req)
724 		return -ENOMEM;
725 
726 	/* Request one schq per level */
727 	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++)
728 		req->schq[lvl] = 1;
729 
730 	return otx2_sync_mbox_msg(&pfvf->mbox);
731 }
732 
otx2_txschq_stop(struct otx2_nic * pfvf)733 int otx2_txschq_stop(struct otx2_nic *pfvf)
734 {
735 	struct nix_txsch_free_req *free_req;
736 	int lvl, schq, err;
737 
738 	mutex_lock(&pfvf->mbox.lock);
739 	/* Free the transmit schedulers */
740 	free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox);
741 	if (!free_req) {
742 		mutex_unlock(&pfvf->mbox.lock);
743 		return -ENOMEM;
744 	}
745 
746 	free_req->flags = TXSCHQ_FREE_ALL;
747 	err = otx2_sync_mbox_msg(&pfvf->mbox);
748 	mutex_unlock(&pfvf->mbox.lock);
749 
750 	/* Clear the txschq list */
751 	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
752 		for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++)
753 			pfvf->hw.txschq_list[lvl][schq] = 0;
754 	}
755 	return err;
756 }
757 
otx2_sqb_flush(struct otx2_nic * pfvf)758 void otx2_sqb_flush(struct otx2_nic *pfvf)
759 {
760 	int qidx, sqe_tail, sqe_head;
761 	u64 incr, *ptr, val;
762 	int timeout = 1000;
763 
764 	ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS);
765 	for (qidx = 0; qidx < pfvf->hw.tot_tx_queues; qidx++) {
766 		incr = (u64)qidx << 32;
767 		while (timeout) {
768 			val = otx2_atomic64_add(incr, ptr);
769 			sqe_head = (val >> 20) & 0x3F;
770 			sqe_tail = (val >> 28) & 0x3F;
771 			if (sqe_head == sqe_tail)
772 				break;
773 			usleep_range(1, 3);
774 			timeout--;
775 		}
776 	}
777 }
778 
779 /* RED and drop levels of CQ on packet reception.
780  * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty).
781  */
782 #define RQ_PASS_LVL_CQ(skid, qsize)	((((skid) + 16) * 256) / (qsize))
783 #define RQ_DROP_LVL_CQ(skid, qsize)	(((skid) * 256) / (qsize))
784 
785 /* RED and drop levels of AURA for packet reception.
786  * For AURA level is measure of fullness (0x0 = empty, 255 = full).
787  * Eg: For RQ length 1K, for pass/drop level 204/230.
788  * RED accepts pkts if free pointers > 102 & <= 205.
789  * Drops pkts if free pointers < 102.
790  */
791 #define RQ_BP_LVL_AURA   (255 - ((85 * 256) / 100)) /* BP when 85% is full */
792 #define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */
793 #define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */
794 
otx2_rq_init(struct otx2_nic * pfvf,u16 qidx,u16 lpb_aura)795 static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura)
796 {
797 	struct otx2_qset *qset = &pfvf->qset;
798 	struct nix_aq_enq_req *aq;
799 
800 	/* Get memory to put this msg */
801 	aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
802 	if (!aq)
803 		return -ENOMEM;
804 
805 	aq->rq.cq = qidx;
806 	aq->rq.ena = 1;
807 	aq->rq.pb_caching = 1;
808 	aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */
809 	aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1;
810 	aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */
811 	aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */
812 	aq->rq.qint_idx = 0;
813 	aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */
814 	aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */
815 	aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
816 	aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
817 	aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA;
818 	aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA;
819 
820 	/* Fill AQ info */
821 	aq->qidx = qidx;
822 	aq->ctype = NIX_AQ_CTYPE_RQ;
823 	aq->op = NIX_AQ_INSTOP_INIT;
824 
825 	return otx2_sync_mbox_msg(&pfvf->mbox);
826 }
827 
otx2_sq_aq_init(void * dev,u16 qidx,u16 sqb_aura)828 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura)
829 {
830 	struct otx2_nic *pfvf = dev;
831 	struct otx2_snd_queue *sq;
832 	struct nix_aq_enq_req *aq;
833 
834 	sq = &pfvf->qset.sq[qidx];
835 	sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx));
836 	/* Get memory to put this msg */
837 	aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
838 	if (!aq)
839 		return -ENOMEM;
840 
841 	aq->sq.cq = pfvf->hw.rx_queues + qidx;
842 	aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */
843 	aq->sq.cq_ena = 1;
844 	aq->sq.ena = 1;
845 	aq->sq.smq = otx2_get_smq_idx(pfvf, qidx);
846 	aq->sq.smq_rr_quantum = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen);
847 	aq->sq.default_chan = pfvf->hw.tx_chan_base;
848 	aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */
849 	aq->sq.sqb_aura = sqb_aura;
850 	aq->sq.sq_int_ena = NIX_SQINT_BITS;
851 	aq->sq.qint_idx = 0;
852 	/* Due pipelining impact minimum 2000 unused SQ CQE's
853 	 * need to maintain to avoid CQ overflow.
854 	 */
855 	aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt));
856 
857 	/* Fill AQ info */
858 	aq->qidx = qidx;
859 	aq->ctype = NIX_AQ_CTYPE_SQ;
860 	aq->op = NIX_AQ_INSTOP_INIT;
861 
862 	return otx2_sync_mbox_msg(&pfvf->mbox);
863 }
864 
otx2_sq_init(struct otx2_nic * pfvf,u16 qidx,u16 sqb_aura)865 static int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura)
866 {
867 	struct otx2_qset *qset = &pfvf->qset;
868 	struct otx2_snd_queue *sq;
869 	struct otx2_pool *pool;
870 	int err;
871 
872 	pool = &pfvf->qset.pool[sqb_aura];
873 	sq = &qset->sq[qidx];
874 	sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128;
875 	sq->sqe_cnt = qset->sqe_cnt;
876 
877 	err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size);
878 	if (err)
879 		return err;
880 
881 	if (qidx < pfvf->hw.tx_queues) {
882 		err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt,
883 				 TSO_HEADER_SIZE);
884 		if (err)
885 			return err;
886 	}
887 
888 	sq->sqe_base = sq->sqe->base;
889 	sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL);
890 	if (!sq->sg)
891 		return -ENOMEM;
892 
893 	if (pfvf->ptp && qidx < pfvf->hw.tx_queues) {
894 		err = qmem_alloc(pfvf->dev, &sq->timestamps, qset->sqe_cnt,
895 				 sizeof(*sq->timestamps));
896 		if (err)
897 			return err;
898 	}
899 
900 	sq->head = 0;
901 	sq->cons_head = 0;
902 	sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1;
903 	sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb;
904 	/* Set SQE threshold to 10% of total SQEs */
905 	sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100;
906 	sq->aura_id = sqb_aura;
907 	sq->aura_fc_addr = pool->fc_addr->base;
908 	sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0));
909 
910 	sq->stats.bytes = 0;
911 	sq->stats.pkts = 0;
912 
913 	return pfvf->hw_ops->sq_aq_init(pfvf, qidx, sqb_aura);
914 
915 }
916 
otx2_cq_init(struct otx2_nic * pfvf,u16 qidx)917 static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx)
918 {
919 	struct otx2_qset *qset = &pfvf->qset;
920 	int err, pool_id, non_xdp_queues;
921 	struct nix_aq_enq_req *aq;
922 	struct otx2_cq_queue *cq;
923 
924 	cq = &qset->cq[qidx];
925 	cq->cq_idx = qidx;
926 	non_xdp_queues = pfvf->hw.rx_queues + pfvf->hw.tx_queues;
927 	if (qidx < pfvf->hw.rx_queues) {
928 		cq->cq_type = CQ_RX;
929 		cq->cint_idx = qidx;
930 		cq->cqe_cnt = qset->rqe_cnt;
931 		if (pfvf->xdp_prog)
932 			xdp_rxq_info_reg(&cq->xdp_rxq, pfvf->netdev, qidx, 0);
933 	} else if (qidx < non_xdp_queues) {
934 		cq->cq_type = CQ_TX;
935 		cq->cint_idx = qidx - pfvf->hw.rx_queues;
936 		cq->cqe_cnt = qset->sqe_cnt;
937 	} else {
938 		cq->cq_type = CQ_XDP;
939 		cq->cint_idx = qidx - non_xdp_queues;
940 		cq->cqe_cnt = qset->sqe_cnt;
941 	}
942 	cq->cqe_size = pfvf->qset.xqe_size;
943 
944 	/* Allocate memory for CQEs */
945 	err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size);
946 	if (err)
947 		return err;
948 
949 	/* Save CQE CPU base for faster reference */
950 	cq->cqe_base = cq->cqe->base;
951 	/* In case where all RQs auras point to single pool,
952 	 * all CQs receive buffer pool also point to same pool.
953 	 */
954 	pool_id = ((cq->cq_type == CQ_RX) &&
955 		   (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx;
956 	cq->rbpool = &qset->pool[pool_id];
957 	cq->refill_task_sched = false;
958 
959 	/* Get memory to put this msg */
960 	aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
961 	if (!aq)
962 		return -ENOMEM;
963 
964 	aq->cq.ena = 1;
965 	aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4);
966 	aq->cq.caching = 1;
967 	aq->cq.base = cq->cqe->iova;
968 	aq->cq.cint_idx = cq->cint_idx;
969 	aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS;
970 	aq->cq.qint_idx = 0;
971 	aq->cq.avg_level = 255;
972 
973 	if (qidx < pfvf->hw.rx_queues) {
974 		aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt);
975 		aq->cq.drop_ena = 1;
976 
977 		if (!is_otx2_lbkvf(pfvf->pdev)) {
978 			/* Enable receive CQ backpressure */
979 			aq->cq.bp_ena = 1;
980 #ifdef CONFIG_DCB
981 			aq->cq.bpid = pfvf->bpid[pfvf->queue_to_pfc_map[qidx]];
982 #else
983 			aq->cq.bpid = pfvf->bpid[0];
984 #endif
985 
986 			/* Set backpressure level is same as cq pass level */
987 			aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
988 		}
989 	}
990 
991 	/* Fill AQ info */
992 	aq->qidx = qidx;
993 	aq->ctype = NIX_AQ_CTYPE_CQ;
994 	aq->op = NIX_AQ_INSTOP_INIT;
995 
996 	return otx2_sync_mbox_msg(&pfvf->mbox);
997 }
998 
otx2_pool_refill_task(struct work_struct * work)999 static void otx2_pool_refill_task(struct work_struct *work)
1000 {
1001 	struct otx2_cq_queue *cq;
1002 	struct otx2_pool *rbpool;
1003 	struct refill_work *wrk;
1004 	int qidx, free_ptrs = 0;
1005 	struct otx2_nic *pfvf;
1006 	dma_addr_t bufptr;
1007 
1008 	wrk = container_of(work, struct refill_work, pool_refill_work.work);
1009 	pfvf = wrk->pf;
1010 	qidx = wrk - pfvf->refill_wrk;
1011 	cq = &pfvf->qset.cq[qidx];
1012 	rbpool = cq->rbpool;
1013 	free_ptrs = cq->pool_ptrs;
1014 
1015 	while (cq->pool_ptrs) {
1016 		if (otx2_alloc_rbuf(pfvf, rbpool, &bufptr)) {
1017 			/* Schedule a WQ if we fails to free atleast half of the
1018 			 * pointers else enable napi for this RQ.
1019 			 */
1020 			if (!((free_ptrs - cq->pool_ptrs) > free_ptrs / 2)) {
1021 				struct delayed_work *dwork;
1022 
1023 				dwork = &wrk->pool_refill_work;
1024 				schedule_delayed_work(dwork,
1025 						      msecs_to_jiffies(100));
1026 			} else {
1027 				cq->refill_task_sched = false;
1028 			}
1029 			return;
1030 		}
1031 		pfvf->hw_ops->aura_freeptr(pfvf, qidx, bufptr + OTX2_HEAD_ROOM);
1032 		cq->pool_ptrs--;
1033 	}
1034 	cq->refill_task_sched = false;
1035 }
1036 
otx2_config_nix_queues(struct otx2_nic * pfvf)1037 int otx2_config_nix_queues(struct otx2_nic *pfvf)
1038 {
1039 	int qidx, err;
1040 
1041 	/* Initialize RX queues */
1042 	for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) {
1043 		u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx);
1044 
1045 		err = otx2_rq_init(pfvf, qidx, lpb_aura);
1046 		if (err)
1047 			return err;
1048 	}
1049 
1050 	/* Initialize TX queues */
1051 	for (qidx = 0; qidx < pfvf->hw.tot_tx_queues; qidx++) {
1052 		u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1053 
1054 		err = otx2_sq_init(pfvf, qidx, sqb_aura);
1055 		if (err)
1056 			return err;
1057 	}
1058 
1059 	/* Initialize completion queues */
1060 	for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) {
1061 		err = otx2_cq_init(pfvf, qidx);
1062 		if (err)
1063 			return err;
1064 	}
1065 
1066 	pfvf->cq_op_addr = (__force u64 *)otx2_get_regaddr(pfvf,
1067 							   NIX_LF_CQ_OP_STATUS);
1068 
1069 	/* Initialize work queue for receive buffer refill */
1070 	pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt,
1071 					sizeof(struct refill_work), GFP_KERNEL);
1072 	if (!pfvf->refill_wrk)
1073 		return -ENOMEM;
1074 
1075 	for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) {
1076 		pfvf->refill_wrk[qidx].pf = pfvf;
1077 		INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work,
1078 				  otx2_pool_refill_task);
1079 	}
1080 	return 0;
1081 }
1082 
otx2_config_nix(struct otx2_nic * pfvf)1083 int otx2_config_nix(struct otx2_nic *pfvf)
1084 {
1085 	struct nix_lf_alloc_req  *nixlf;
1086 	struct nix_lf_alloc_rsp *rsp;
1087 	int err;
1088 
1089 	pfvf->qset.xqe_size = pfvf->hw.xqe_size;
1090 
1091 	/* Get memory to put this msg */
1092 	nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox);
1093 	if (!nixlf)
1094 		return -ENOMEM;
1095 
1096 	/* Set RQ/SQ/CQ counts */
1097 	nixlf->rq_cnt = pfvf->hw.rx_queues;
1098 	nixlf->sq_cnt = pfvf->hw.tot_tx_queues;
1099 	nixlf->cq_cnt = pfvf->qset.cq_cnt;
1100 	nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE;
1101 	nixlf->rss_grps = MAX_RSS_GROUPS;
1102 	nixlf->xqe_sz = pfvf->hw.xqe_size == 128 ? NIX_XQESZ_W16 : NIX_XQESZ_W64;
1103 	/* We don't know absolute NPA LF idx attached.
1104 	 * AF will replace 'RVU_DEFAULT_PF_FUNC' with
1105 	 * NPA LF attached to this RVU PF/VF.
1106 	 */
1107 	nixlf->npa_func = RVU_DEFAULT_PF_FUNC;
1108 	/* Disable alignment pad, enable L2 length check,
1109 	 * enable L4 TCP/UDP checksum verification.
1110 	 */
1111 	nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37);
1112 
1113 	err = otx2_sync_mbox_msg(&pfvf->mbox);
1114 	if (err)
1115 		return err;
1116 
1117 	rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0,
1118 							   &nixlf->hdr);
1119 	if (IS_ERR(rsp))
1120 		return PTR_ERR(rsp);
1121 
1122 	if (rsp->qints < 1)
1123 		return -ENXIO;
1124 
1125 	return rsp->hdr.rc;
1126 }
1127 
otx2_sq_free_sqbs(struct otx2_nic * pfvf)1128 void otx2_sq_free_sqbs(struct otx2_nic *pfvf)
1129 {
1130 	struct otx2_qset *qset = &pfvf->qset;
1131 	struct otx2_hw *hw = &pfvf->hw;
1132 	struct otx2_snd_queue *sq;
1133 	int sqb, qidx;
1134 	u64 iova, pa;
1135 
1136 	for (qidx = 0; qidx < hw->tot_tx_queues; qidx++) {
1137 		sq = &qset->sq[qidx];
1138 		if (!sq->sqb_ptrs)
1139 			continue;
1140 		for (sqb = 0; sqb < sq->sqb_count; sqb++) {
1141 			if (!sq->sqb_ptrs[sqb])
1142 				continue;
1143 			iova = sq->sqb_ptrs[sqb];
1144 			pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
1145 			dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size,
1146 					     DMA_FROM_DEVICE,
1147 					     DMA_ATTR_SKIP_CPU_SYNC);
1148 			put_page(virt_to_page(phys_to_virt(pa)));
1149 		}
1150 		sq->sqb_count = 0;
1151 	}
1152 }
1153 
otx2_free_aura_ptr(struct otx2_nic * pfvf,int type)1154 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type)
1155 {
1156 	int pool_id, pool_start = 0, pool_end = 0, size = 0;
1157 	u64 iova, pa;
1158 
1159 	if (type == AURA_NIX_SQ) {
1160 		pool_start = otx2_get_pool_idx(pfvf, type, 0);
1161 		pool_end =  pool_start + pfvf->hw.sqpool_cnt;
1162 		size = pfvf->hw.sqb_size;
1163 	}
1164 	if (type == AURA_NIX_RQ) {
1165 		pool_start = otx2_get_pool_idx(pfvf, type, 0);
1166 		pool_end = pfvf->hw.rqpool_cnt;
1167 		size = pfvf->rbsize;
1168 	}
1169 
1170 	/* Free SQB and RQB pointers from the aura pool */
1171 	for (pool_id = pool_start; pool_id < pool_end; pool_id++) {
1172 		iova = otx2_aura_allocptr(pfvf, pool_id);
1173 		while (iova) {
1174 			if (type == AURA_NIX_RQ)
1175 				iova -= OTX2_HEAD_ROOM;
1176 
1177 			pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
1178 			dma_unmap_page_attrs(pfvf->dev, iova, size,
1179 					     DMA_FROM_DEVICE,
1180 					     DMA_ATTR_SKIP_CPU_SYNC);
1181 			put_page(virt_to_page(phys_to_virt(pa)));
1182 			iova = otx2_aura_allocptr(pfvf, pool_id);
1183 		}
1184 	}
1185 }
1186 
otx2_aura_pool_free(struct otx2_nic * pfvf)1187 void otx2_aura_pool_free(struct otx2_nic *pfvf)
1188 {
1189 	struct otx2_pool *pool;
1190 	int pool_id;
1191 
1192 	if (!pfvf->qset.pool)
1193 		return;
1194 
1195 	for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) {
1196 		pool = &pfvf->qset.pool[pool_id];
1197 		qmem_free(pfvf->dev, pool->stack);
1198 		qmem_free(pfvf->dev, pool->fc_addr);
1199 	}
1200 	devm_kfree(pfvf->dev, pfvf->qset.pool);
1201 	pfvf->qset.pool = NULL;
1202 }
1203 
otx2_aura_init(struct otx2_nic * pfvf,int aura_id,int pool_id,int numptrs)1204 static int otx2_aura_init(struct otx2_nic *pfvf, int aura_id,
1205 			  int pool_id, int numptrs)
1206 {
1207 	struct npa_aq_enq_req *aq;
1208 	struct otx2_pool *pool;
1209 	int err;
1210 
1211 	pool = &pfvf->qset.pool[pool_id];
1212 
1213 	/* Allocate memory for HW to update Aura count.
1214 	 * Alloc one cache line, so that it fits all FC_STYPE modes.
1215 	 */
1216 	if (!pool->fc_addr) {
1217 		err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN);
1218 		if (err)
1219 			return err;
1220 	}
1221 
1222 	/* Initialize this aura's context via AF */
1223 	aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1224 	if (!aq) {
1225 		/* Shared mbox memory buffer is full, flush it and retry */
1226 		err = otx2_sync_mbox_msg(&pfvf->mbox);
1227 		if (err)
1228 			return err;
1229 		aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1230 		if (!aq)
1231 			return -ENOMEM;
1232 	}
1233 
1234 	aq->aura_id = aura_id;
1235 	/* Will be filled by AF with correct pool context address */
1236 	aq->aura.pool_addr = pool_id;
1237 	aq->aura.pool_caching = 1;
1238 	aq->aura.shift = ilog2(numptrs) - 8;
1239 	aq->aura.count = numptrs;
1240 	aq->aura.limit = numptrs;
1241 	aq->aura.avg_level = 255;
1242 	aq->aura.ena = 1;
1243 	aq->aura.fc_ena = 1;
1244 	aq->aura.fc_addr = pool->fc_addr->iova;
1245 	aq->aura.fc_hyst_bits = 0; /* Store count on all updates */
1246 
1247 	/* Enable backpressure for RQ aura */
1248 	if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) {
1249 		aq->aura.bp_ena = 0;
1250 		/* If NIX1 LF is attached then specify NIX1_RX.
1251 		 *
1252 		 * Below NPA_AURA_S[BP_ENA] is set according to the
1253 		 * NPA_BPINTF_E enumeration given as:
1254 		 * 0x0 + a*0x1 where 'a' is 0 for NIX0_RX and 1 for NIX1_RX so
1255 		 * NIX0_RX is 0x0 + 0*0x1 = 0
1256 		 * NIX1_RX is 0x0 + 1*0x1 = 1
1257 		 * But in HRM it is given that
1258 		 * "NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to
1259 		 * NIX-RX based on [BP] level. One bit per NIX-RX; index
1260 		 * enumerated by NPA_BPINTF_E."
1261 		 */
1262 		if (pfvf->nix_blkaddr == BLKADDR_NIX1)
1263 			aq->aura.bp_ena = 1;
1264 #ifdef CONFIG_DCB
1265 		aq->aura.nix0_bpid = pfvf->bpid[pfvf->queue_to_pfc_map[aura_id]];
1266 #else
1267 		aq->aura.nix0_bpid = pfvf->bpid[0];
1268 #endif
1269 
1270 		/* Set backpressure level for RQ's Aura */
1271 		aq->aura.bp = RQ_BP_LVL_AURA;
1272 	}
1273 
1274 	/* Fill AQ info */
1275 	aq->ctype = NPA_AQ_CTYPE_AURA;
1276 	aq->op = NPA_AQ_INSTOP_INIT;
1277 
1278 	return 0;
1279 }
1280 
otx2_pool_init(struct otx2_nic * pfvf,u16 pool_id,int stack_pages,int numptrs,int buf_size)1281 static int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id,
1282 			  int stack_pages, int numptrs, int buf_size)
1283 {
1284 	struct npa_aq_enq_req *aq;
1285 	struct otx2_pool *pool;
1286 	int err;
1287 
1288 	pool = &pfvf->qset.pool[pool_id];
1289 	/* Alloc memory for stack which is used to store buffer pointers */
1290 	err = qmem_alloc(pfvf->dev, &pool->stack,
1291 			 stack_pages, pfvf->hw.stack_pg_bytes);
1292 	if (err)
1293 		return err;
1294 
1295 	pool->rbsize = buf_size;
1296 
1297 	/* Initialize this pool's context via AF */
1298 	aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1299 	if (!aq) {
1300 		/* Shared mbox memory buffer is full, flush it and retry */
1301 		err = otx2_sync_mbox_msg(&pfvf->mbox);
1302 		if (err) {
1303 			qmem_free(pfvf->dev, pool->stack);
1304 			return err;
1305 		}
1306 		aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1307 		if (!aq) {
1308 			qmem_free(pfvf->dev, pool->stack);
1309 			return -ENOMEM;
1310 		}
1311 	}
1312 
1313 	aq->aura_id = pool_id;
1314 	aq->pool.stack_base = pool->stack->iova;
1315 	aq->pool.stack_caching = 1;
1316 	aq->pool.ena = 1;
1317 	aq->pool.buf_size = buf_size / 128;
1318 	aq->pool.stack_max_pages = stack_pages;
1319 	aq->pool.shift = ilog2(numptrs) - 8;
1320 	aq->pool.ptr_start = 0;
1321 	aq->pool.ptr_end = ~0ULL;
1322 
1323 	/* Fill AQ info */
1324 	aq->ctype = NPA_AQ_CTYPE_POOL;
1325 	aq->op = NPA_AQ_INSTOP_INIT;
1326 
1327 	return 0;
1328 }
1329 
otx2_sq_aura_pool_init(struct otx2_nic * pfvf)1330 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf)
1331 {
1332 	int qidx, pool_id, stack_pages, num_sqbs;
1333 	struct otx2_qset *qset = &pfvf->qset;
1334 	struct otx2_hw *hw = &pfvf->hw;
1335 	struct otx2_snd_queue *sq;
1336 	struct otx2_pool *pool;
1337 	dma_addr_t bufptr;
1338 	int err, ptr;
1339 
1340 	/* Calculate number of SQBs needed.
1341 	 *
1342 	 * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB.
1343 	 * Last SQE is used for pointing to next SQB.
1344 	 */
1345 	num_sqbs = (hw->sqb_size / 128) - 1;
1346 	num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs;
1347 
1348 	/* Get no of stack pages needed */
1349 	stack_pages =
1350 		(num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs;
1351 
1352 	for (qidx = 0; qidx < hw->tot_tx_queues; qidx++) {
1353 		pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1354 		/* Initialize aura context */
1355 		err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs);
1356 		if (err)
1357 			goto fail;
1358 
1359 		/* Initialize pool context */
1360 		err = otx2_pool_init(pfvf, pool_id, stack_pages,
1361 				     num_sqbs, hw->sqb_size);
1362 		if (err)
1363 			goto fail;
1364 	}
1365 
1366 	/* Flush accumulated messages */
1367 	err = otx2_sync_mbox_msg(&pfvf->mbox);
1368 	if (err)
1369 		goto fail;
1370 
1371 	/* Allocate pointers and free them to aura/pool */
1372 	for (qidx = 0; qidx < hw->tot_tx_queues; qidx++) {
1373 		pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1374 		pool = &pfvf->qset.pool[pool_id];
1375 
1376 		sq = &qset->sq[qidx];
1377 		sq->sqb_count = 0;
1378 		sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(*sq->sqb_ptrs), GFP_KERNEL);
1379 		if (!sq->sqb_ptrs) {
1380 			err = -ENOMEM;
1381 			goto err_mem;
1382 		}
1383 
1384 		for (ptr = 0; ptr < num_sqbs; ptr++) {
1385 			err = otx2_alloc_rbuf(pfvf, pool, &bufptr);
1386 			if (err)
1387 				goto err_mem;
1388 			pfvf->hw_ops->aura_freeptr(pfvf, pool_id, bufptr);
1389 			sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr;
1390 		}
1391 	}
1392 
1393 err_mem:
1394 	return err ? -ENOMEM : 0;
1395 
1396 fail:
1397 	otx2_mbox_reset(&pfvf->mbox.mbox, 0);
1398 	otx2_aura_pool_free(pfvf);
1399 	return err;
1400 }
1401 
otx2_rq_aura_pool_init(struct otx2_nic * pfvf)1402 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf)
1403 {
1404 	struct otx2_hw *hw = &pfvf->hw;
1405 	int stack_pages, pool_id, rq;
1406 	struct otx2_pool *pool;
1407 	int err, ptr, num_ptrs;
1408 	dma_addr_t bufptr;
1409 
1410 	num_ptrs = pfvf->qset.rqe_cnt;
1411 
1412 	stack_pages =
1413 		(num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs;
1414 
1415 	for (rq = 0; rq < hw->rx_queues; rq++) {
1416 		pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq);
1417 		/* Initialize aura context */
1418 		err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs);
1419 		if (err)
1420 			goto fail;
1421 	}
1422 	for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) {
1423 		err = otx2_pool_init(pfvf, pool_id, stack_pages,
1424 				     num_ptrs, pfvf->rbsize);
1425 		if (err)
1426 			goto fail;
1427 	}
1428 
1429 	/* Flush accumulated messages */
1430 	err = otx2_sync_mbox_msg(&pfvf->mbox);
1431 	if (err)
1432 		goto fail;
1433 
1434 	/* Allocate pointers and free them to aura/pool */
1435 	for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) {
1436 		pool = &pfvf->qset.pool[pool_id];
1437 		for (ptr = 0; ptr < num_ptrs; ptr++) {
1438 			err = otx2_alloc_rbuf(pfvf, pool, &bufptr);
1439 			if (err)
1440 				return -ENOMEM;
1441 			pfvf->hw_ops->aura_freeptr(pfvf, pool_id,
1442 						   bufptr + OTX2_HEAD_ROOM);
1443 		}
1444 	}
1445 	return 0;
1446 fail:
1447 	otx2_mbox_reset(&pfvf->mbox.mbox, 0);
1448 	otx2_aura_pool_free(pfvf);
1449 	return err;
1450 }
1451 
otx2_config_npa(struct otx2_nic * pfvf)1452 int otx2_config_npa(struct otx2_nic *pfvf)
1453 {
1454 	struct otx2_qset *qset = &pfvf->qset;
1455 	struct npa_lf_alloc_req  *npalf;
1456 	struct otx2_hw *hw = &pfvf->hw;
1457 	int aura_cnt;
1458 
1459 	/* Pool - Stack of free buffer pointers
1460 	 * Aura - Alloc/frees pointers from/to pool for NIX DMA.
1461 	 */
1462 
1463 	if (!hw->pool_cnt)
1464 		return -EINVAL;
1465 
1466 	qset->pool = devm_kcalloc(pfvf->dev, hw->pool_cnt,
1467 				  sizeof(struct otx2_pool), GFP_KERNEL);
1468 	if (!qset->pool)
1469 		return -ENOMEM;
1470 
1471 	/* Get memory to put this msg */
1472 	npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox);
1473 	if (!npalf)
1474 		return -ENOMEM;
1475 
1476 	/* Set aura and pool counts */
1477 	npalf->nr_pools = hw->pool_cnt;
1478 	aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt));
1479 	npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1;
1480 
1481 	return otx2_sync_mbox_msg(&pfvf->mbox);
1482 }
1483 
otx2_detach_resources(struct mbox * mbox)1484 int otx2_detach_resources(struct mbox *mbox)
1485 {
1486 	struct rsrc_detach *detach;
1487 
1488 	mutex_lock(&mbox->lock);
1489 	detach = otx2_mbox_alloc_msg_detach_resources(mbox);
1490 	if (!detach) {
1491 		mutex_unlock(&mbox->lock);
1492 		return -ENOMEM;
1493 	}
1494 
1495 	/* detach all */
1496 	detach->partial = false;
1497 
1498 	/* Send detach request to AF */
1499 	otx2_mbox_msg_send(&mbox->mbox, 0);
1500 	mutex_unlock(&mbox->lock);
1501 	return 0;
1502 }
1503 EXPORT_SYMBOL(otx2_detach_resources);
1504 
otx2_attach_npa_nix(struct otx2_nic * pfvf)1505 int otx2_attach_npa_nix(struct otx2_nic *pfvf)
1506 {
1507 	struct rsrc_attach *attach;
1508 	struct msg_req *msix;
1509 	int err;
1510 
1511 	mutex_lock(&pfvf->mbox.lock);
1512 	/* Get memory to put this msg */
1513 	attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox);
1514 	if (!attach) {
1515 		mutex_unlock(&pfvf->mbox.lock);
1516 		return -ENOMEM;
1517 	}
1518 
1519 	attach->npalf = true;
1520 	attach->nixlf = true;
1521 
1522 	/* Send attach request to AF */
1523 	err = otx2_sync_mbox_msg(&pfvf->mbox);
1524 	if (err) {
1525 		mutex_unlock(&pfvf->mbox.lock);
1526 		return err;
1527 	}
1528 
1529 	pfvf->nix_blkaddr = BLKADDR_NIX0;
1530 
1531 	/* If the platform has two NIX blocks then LF may be
1532 	 * allocated from NIX1.
1533 	 */
1534 	if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL)
1535 		pfvf->nix_blkaddr = BLKADDR_NIX1;
1536 
1537 	/* Get NPA and NIX MSIX vector offsets */
1538 	msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox);
1539 	if (!msix) {
1540 		mutex_unlock(&pfvf->mbox.lock);
1541 		return -ENOMEM;
1542 	}
1543 
1544 	err = otx2_sync_mbox_msg(&pfvf->mbox);
1545 	if (err) {
1546 		mutex_unlock(&pfvf->mbox.lock);
1547 		return err;
1548 	}
1549 	mutex_unlock(&pfvf->mbox.lock);
1550 
1551 	if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID ||
1552 	    pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) {
1553 		dev_err(pfvf->dev,
1554 			"RVUPF: Invalid MSIX vector offset for NPA/NIX\n");
1555 		return -EINVAL;
1556 	}
1557 
1558 	return 0;
1559 }
1560 EXPORT_SYMBOL(otx2_attach_npa_nix);
1561 
otx2_ctx_disable(struct mbox * mbox,int type,bool npa)1562 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa)
1563 {
1564 	struct hwctx_disable_req *req;
1565 
1566 	mutex_lock(&mbox->lock);
1567 	/* Request AQ to disable this context */
1568 	if (npa)
1569 		req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox);
1570 	else
1571 		req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox);
1572 
1573 	if (!req) {
1574 		mutex_unlock(&mbox->lock);
1575 		return;
1576 	}
1577 
1578 	req->ctype = type;
1579 
1580 	if (otx2_sync_mbox_msg(mbox))
1581 		dev_err(mbox->pfvf->dev, "%s failed to disable context\n",
1582 			__func__);
1583 
1584 	mutex_unlock(&mbox->lock);
1585 }
1586 
otx2_nix_config_bp(struct otx2_nic * pfvf,bool enable)1587 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable)
1588 {
1589 	struct nix_bp_cfg_req *req;
1590 
1591 	if (enable)
1592 		req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox);
1593 	else
1594 		req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox);
1595 
1596 	if (!req)
1597 		return -ENOMEM;
1598 
1599 	req->chan_base = 0;
1600 #ifdef CONFIG_DCB
1601 	req->chan_cnt = pfvf->pfc_en ? IEEE_8021QAZ_MAX_TCS : 1;
1602 	req->bpid_per_chan = pfvf->pfc_en ? 1 : 0;
1603 #else
1604 	req->chan_cnt =  1;
1605 	req->bpid_per_chan = 0;
1606 #endif
1607 
1608 
1609 	return otx2_sync_mbox_msg(&pfvf->mbox);
1610 }
1611 EXPORT_SYMBOL(otx2_nix_config_bp);
1612 
1613 /* Mbox message handlers */
mbox_handler_cgx_stats(struct otx2_nic * pfvf,struct cgx_stats_rsp * rsp)1614 void mbox_handler_cgx_stats(struct otx2_nic *pfvf,
1615 			    struct cgx_stats_rsp *rsp)
1616 {
1617 	int id;
1618 
1619 	for (id = 0; id < CGX_RX_STATS_COUNT; id++)
1620 		pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id];
1621 	for (id = 0; id < CGX_TX_STATS_COUNT; id++)
1622 		pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id];
1623 }
1624 
mbox_handler_cgx_fec_stats(struct otx2_nic * pfvf,struct cgx_fec_stats_rsp * rsp)1625 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf,
1626 				struct cgx_fec_stats_rsp *rsp)
1627 {
1628 	pfvf->hw.cgx_fec_corr_blks += rsp->fec_corr_blks;
1629 	pfvf->hw.cgx_fec_uncorr_blks += rsp->fec_uncorr_blks;
1630 }
1631 
mbox_handler_nix_txsch_alloc(struct otx2_nic * pf,struct nix_txsch_alloc_rsp * rsp)1632 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf,
1633 				  struct nix_txsch_alloc_rsp *rsp)
1634 {
1635 	int lvl, schq;
1636 
1637 	/* Setup transmit scheduler list */
1638 	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++)
1639 		for (schq = 0; schq < rsp->schq[lvl]; schq++)
1640 			pf->hw.txschq_list[lvl][schq] =
1641 				rsp->schq_list[lvl][schq];
1642 
1643 	pf->hw.txschq_link_cfg_lvl = rsp->link_cfg_lvl;
1644 }
1645 EXPORT_SYMBOL(mbox_handler_nix_txsch_alloc);
1646 
mbox_handler_npa_lf_alloc(struct otx2_nic * pfvf,struct npa_lf_alloc_rsp * rsp)1647 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf,
1648 			       struct npa_lf_alloc_rsp *rsp)
1649 {
1650 	pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs;
1651 	pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes;
1652 }
1653 EXPORT_SYMBOL(mbox_handler_npa_lf_alloc);
1654 
mbox_handler_nix_lf_alloc(struct otx2_nic * pfvf,struct nix_lf_alloc_rsp * rsp)1655 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf,
1656 			       struct nix_lf_alloc_rsp *rsp)
1657 {
1658 	pfvf->hw.sqb_size = rsp->sqb_size;
1659 	pfvf->hw.rx_chan_base = rsp->rx_chan_base;
1660 	pfvf->hw.tx_chan_base = rsp->tx_chan_base;
1661 	pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx;
1662 	pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx;
1663 	pfvf->hw.cgx_links = rsp->cgx_links;
1664 	pfvf->hw.lbk_links = rsp->lbk_links;
1665 	pfvf->hw.tx_link = rsp->tx_link;
1666 }
1667 EXPORT_SYMBOL(mbox_handler_nix_lf_alloc);
1668 
mbox_handler_msix_offset(struct otx2_nic * pfvf,struct msix_offset_rsp * rsp)1669 void mbox_handler_msix_offset(struct otx2_nic *pfvf,
1670 			      struct msix_offset_rsp *rsp)
1671 {
1672 	pfvf->hw.npa_msixoff = rsp->npa_msixoff;
1673 	pfvf->hw.nix_msixoff = rsp->nix_msixoff;
1674 }
1675 EXPORT_SYMBOL(mbox_handler_msix_offset);
1676 
mbox_handler_nix_bp_enable(struct otx2_nic * pfvf,struct nix_bp_cfg_rsp * rsp)1677 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf,
1678 				struct nix_bp_cfg_rsp *rsp)
1679 {
1680 	int chan, chan_id;
1681 
1682 	for (chan = 0; chan < rsp->chan_cnt; chan++) {
1683 		chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F);
1684 		pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF;
1685 	}
1686 }
1687 EXPORT_SYMBOL(mbox_handler_nix_bp_enable);
1688 
otx2_free_cints(struct otx2_nic * pfvf,int n)1689 void otx2_free_cints(struct otx2_nic *pfvf, int n)
1690 {
1691 	struct otx2_qset *qset = &pfvf->qset;
1692 	struct otx2_hw *hw = &pfvf->hw;
1693 	int irq, qidx;
1694 
1695 	for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START;
1696 	     qidx < n;
1697 	     qidx++, irq++) {
1698 		int vector = pci_irq_vector(pfvf->pdev, irq);
1699 
1700 		irq_set_affinity_hint(vector, NULL);
1701 		free_cpumask_var(hw->affinity_mask[irq]);
1702 		free_irq(vector, &qset->napi[qidx]);
1703 	}
1704 }
1705 
otx2_set_cints_affinity(struct otx2_nic * pfvf)1706 void otx2_set_cints_affinity(struct otx2_nic *pfvf)
1707 {
1708 	struct otx2_hw *hw = &pfvf->hw;
1709 	int vec, cpu, irq, cint;
1710 
1711 	vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START;
1712 	cpu = cpumask_first(cpu_online_mask);
1713 
1714 	/* CQ interrupts */
1715 	for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) {
1716 		if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL))
1717 			return;
1718 
1719 		cpumask_set_cpu(cpu, hw->affinity_mask[vec]);
1720 
1721 		irq = pci_irq_vector(pfvf->pdev, vec);
1722 		irq_set_affinity_hint(irq, hw->affinity_mask[vec]);
1723 
1724 		cpu = cpumask_next(cpu, cpu_online_mask);
1725 		if (unlikely(cpu >= nr_cpu_ids))
1726 			cpu = 0;
1727 	}
1728 }
1729 
otx2_get_max_mtu(struct otx2_nic * pfvf)1730 u16 otx2_get_max_mtu(struct otx2_nic *pfvf)
1731 {
1732 	struct nix_hw_info *rsp;
1733 	struct msg_req *req;
1734 	u16 max_mtu;
1735 	int rc;
1736 
1737 	mutex_lock(&pfvf->mbox.lock);
1738 
1739 	req = otx2_mbox_alloc_msg_nix_get_hw_info(&pfvf->mbox);
1740 	if (!req) {
1741 		rc =  -ENOMEM;
1742 		goto out;
1743 	}
1744 
1745 	rc = otx2_sync_mbox_msg(&pfvf->mbox);
1746 	if (!rc) {
1747 		rsp = (struct nix_hw_info *)
1748 		       otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
1749 
1750 		/* HW counts VLAN insertion bytes (8 for double tag)
1751 		 * irrespective of whether SQE is requesting to insert VLAN
1752 		 * in the packet or not. Hence these 8 bytes have to be
1753 		 * discounted from max packet size otherwise HW will throw
1754 		 * SMQ errors
1755 		 */
1756 		max_mtu = rsp->max_mtu - 8 - OTX2_ETH_HLEN;
1757 
1758 		/* Also save DWRR MTU, needed for DWRR weight calculation */
1759 		pfvf->hw.dwrr_mtu = rsp->rpm_dwrr_mtu;
1760 		if (!pfvf->hw.dwrr_mtu)
1761 			pfvf->hw.dwrr_mtu = 1;
1762 	}
1763 
1764 out:
1765 	mutex_unlock(&pfvf->mbox.lock);
1766 	if (rc) {
1767 		dev_warn(pfvf->dev,
1768 			 "Failed to get MTU from hardware setting default value(1500)\n");
1769 		max_mtu = 1500;
1770 	}
1771 	return max_mtu;
1772 }
1773 EXPORT_SYMBOL(otx2_get_max_mtu);
1774 
otx2_handle_ntuple_tc_features(struct net_device * netdev,netdev_features_t features)1775 int otx2_handle_ntuple_tc_features(struct net_device *netdev, netdev_features_t features)
1776 {
1777 	netdev_features_t changed = features ^ netdev->features;
1778 	struct otx2_nic *pfvf = netdev_priv(netdev);
1779 	bool ntuple = !!(features & NETIF_F_NTUPLE);
1780 	bool tc = !!(features & NETIF_F_HW_TC);
1781 
1782 	if ((changed & NETIF_F_NTUPLE) && !ntuple)
1783 		otx2_destroy_ntuple_flows(pfvf);
1784 
1785 	if ((changed & NETIF_F_NTUPLE) && ntuple) {
1786 		if (!pfvf->flow_cfg->max_flows) {
1787 			netdev_err(netdev,
1788 				   "Can't enable NTUPLE, MCAM entries not allocated\n");
1789 			return -EINVAL;
1790 		}
1791 	}
1792 
1793 	if ((changed & NETIF_F_HW_TC) && tc) {
1794 		if (!pfvf->flow_cfg->max_flows) {
1795 			netdev_err(netdev,
1796 				   "Can't enable TC, MCAM entries not allocated\n");
1797 			return -EINVAL;
1798 		}
1799 	}
1800 
1801 	if ((changed & NETIF_F_HW_TC) && !tc &&
1802 	    pfvf->flow_cfg && pfvf->flow_cfg->nr_flows) {
1803 		netdev_err(netdev, "Can't disable TC hardware offload while flows are active\n");
1804 		return -EBUSY;
1805 	}
1806 
1807 	if ((changed & NETIF_F_NTUPLE) && ntuple &&
1808 	    (netdev->features & NETIF_F_HW_TC) && !(changed & NETIF_F_HW_TC)) {
1809 		netdev_err(netdev,
1810 			   "Can't enable NTUPLE when TC is active, disable TC and retry\n");
1811 		return -EINVAL;
1812 	}
1813 
1814 	if ((changed & NETIF_F_HW_TC) && tc &&
1815 	    (netdev->features & NETIF_F_NTUPLE) && !(changed & NETIF_F_NTUPLE)) {
1816 		netdev_err(netdev,
1817 			   "Can't enable TC when NTUPLE is active, disable NTUPLE and retry\n");
1818 		return -EINVAL;
1819 	}
1820 
1821 	return 0;
1822 }
1823 EXPORT_SYMBOL(otx2_handle_ntuple_tc_features);
1824 
1825 #define M(_name, _id, _fn_name, _req_type, _rsp_type)			\
1826 int __weak								\
1827 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf,		\
1828 				struct _req_type *req,			\
1829 				struct _rsp_type *rsp)			\
1830 {									\
1831 	/* Nothing to do here */					\
1832 	return 0;							\
1833 }									\
1834 EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name);
1835 MBOX_UP_CGX_MESSAGES
1836 MBOX_UP_MCS_MESSAGES
1837 #undef M
1838