1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_HW_CATALOG_H 8 #define _DPU_HW_CATALOG_H 9 10 #include <linux/kernel.h> 11 #include <linux/bug.h> 12 #include <linux/bitmap.h> 13 #include <linux/err.h> 14 15 /** 16 * Max hardware block count: For ex: max 12 SSPP pipes or 17 * 5 ctl paths. In all cases, it can have max 12 hardware blocks 18 * based on current design 19 */ 20 #define MAX_BLOCKS 12 21 22 #define DPU_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28) |\ 23 ((MINOR & 0xFFF) << 16) |\ 24 (STEP & 0xFFFF)) 25 26 #define DPU_HW_MAJOR(rev) ((rev) >> 28) 27 #define DPU_HW_MINOR(rev) (((rev) >> 16) & 0xFFF) 28 #define DPU_HW_STEP(rev) ((rev) & 0xFFFF) 29 #define DPU_HW_MAJOR_MINOR(rev) ((rev) >> 16) 30 31 #define IS_DPU_MAJOR_MINOR_SAME(rev1, rev2) \ 32 (DPU_HW_MAJOR_MINOR((rev1)) == DPU_HW_MAJOR_MINOR((rev2))) 33 34 #define DPU_HW_VER_170 DPU_HW_VER(1, 7, 0) /* 8996 v1.0 */ 35 #define DPU_HW_VER_171 DPU_HW_VER(1, 7, 1) /* 8996 v2.0 */ 36 #define DPU_HW_VER_172 DPU_HW_VER(1, 7, 2) /* 8996 v3.0 */ 37 #define DPU_HW_VER_300 DPU_HW_VER(3, 0, 0) /* 8998 v1.0 */ 38 #define DPU_HW_VER_301 DPU_HW_VER(3, 0, 1) /* 8998 v1.1 */ 39 #define DPU_HW_VER_400 DPU_HW_VER(4, 0, 0) /* sdm845 v1.0 */ 40 #define DPU_HW_VER_401 DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */ 41 #define DPU_HW_VER_410 DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */ 42 #define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sm8150 v1.0 */ 43 #define DPU_HW_VER_501 DPU_HW_VER(5, 0, 1) /* sm8150 v2.0 */ 44 #define DPU_HW_VER_510 DPU_HW_VER(5, 1, 1) /* sc8180 */ 45 #define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */ 46 #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ 47 #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ 48 #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ 49 50 #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) 51 #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300) 52 #define IS_SDM845_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_400) 53 #define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410) 54 #define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500) 55 #define IS_SC7180_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_620) 56 #define IS_SC7280_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_720) 57 58 #define DPU_HW_BLK_NAME_LEN 16 59 60 #define MAX_IMG_WIDTH 0x3fff 61 #define MAX_IMG_HEIGHT 0x3fff 62 63 #define CRTC_DUAL_MIXERS 2 64 65 #define MAX_XIN_COUNT 16 66 67 /** 68 * Supported UBWC feature versions 69 */ 70 enum { 71 DPU_HW_UBWC_VER_10 = 0x100, 72 DPU_HW_UBWC_VER_20 = 0x200, 73 DPU_HW_UBWC_VER_30 = 0x300, 74 DPU_HW_UBWC_VER_40 = 0x400, 75 }; 76 77 /** 78 * MDP TOP BLOCK features 79 * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe 80 * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats 81 * @DPU_MDP_BWC, MDSS HW supports Bandwidth compression. 82 * @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth 83 * compression initial revision 84 * @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5 85 * @DPU_MDP_MAX Maximum value 86 87 */ 88 enum { 89 DPU_MDP_PANIC_PER_PIPE = 0x1, 90 DPU_MDP_10BIT_SUPPORT, 91 DPU_MDP_BWC, 92 DPU_MDP_UBWC_1_0, 93 DPU_MDP_UBWC_1_5, 94 DPU_MDP_AUDIO_SELECT, 95 DPU_MDP_MAX 96 }; 97 98 /** 99 * SSPP sub-blocks/features 100 * @DPU_SSPP_SRC Src and fetch part of the pipes, 101 * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support 102 * @DPU_SSPP_SCALER_QSEED3, QSEED3 alogorithm support 103 * @DPU_SSPP_SCALER_QSEED3LITE, QSEED3 Lite alogorithm support 104 * @DPU_SSPP_SCALER_QSEED4, QSEED4 algorithm support 105 * @DPU_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes 106 * @DPU_SSPP_CSC, Support of Color space converion 107 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion 108 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer 109 * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq 110 * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control 111 * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect 112 * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support 113 * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support 114 * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper 115 * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec 116 * @DPU_SSPP_CDP Supports client driven prefetch 117 * @DPU_SSPP_INLINE_ROTATION Support inline rotation 118 * @DPU_SSPP_MAX maximum value 119 */ 120 enum { 121 DPU_SSPP_SRC = 0x1, 122 DPU_SSPP_SCALER_QSEED2, 123 DPU_SSPP_SCALER_QSEED3, 124 DPU_SSPP_SCALER_QSEED3LITE, 125 DPU_SSPP_SCALER_QSEED4, 126 DPU_SSPP_SCALER_RGB, 127 DPU_SSPP_CSC, 128 DPU_SSPP_CSC_10BIT, 129 DPU_SSPP_CURSOR, 130 DPU_SSPP_QOS, 131 DPU_SSPP_QOS_8LVL, 132 DPU_SSPP_EXCL_RECT, 133 DPU_SSPP_SMART_DMA_V1, 134 DPU_SSPP_SMART_DMA_V2, 135 DPU_SSPP_TS_PREFILL, 136 DPU_SSPP_TS_PREFILL_REC1, 137 DPU_SSPP_CDP, 138 DPU_SSPP_INLINE_ROTATION, 139 DPU_SSPP_MAX 140 }; 141 142 /* 143 * MIXER sub-blocks/features 144 * @DPU_MIXER_LAYER Layer mixer layer blend configuration, 145 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration 146 * @DPU_MIXER_GC Gamma correction block 147 * @DPU_DIM_LAYER Layer mixer supports dim layer 148 * @DPU_MIXER_MAX maximum value 149 */ 150 enum { 151 DPU_MIXER_LAYER = 0x1, 152 DPU_MIXER_SOURCESPLIT, 153 DPU_MIXER_GC, 154 DPU_DIM_LAYER, 155 DPU_MIXER_MAX 156 }; 157 158 /** 159 * DSPP sub-blocks 160 * @DPU_DSPP_PCC Panel color correction block 161 * @DPU_DSPP_GC Gamma correction block 162 */ 163 enum { 164 DPU_DSPP_PCC = 0x1, 165 DPU_DSPP_GC, 166 DPU_DSPP_MAX 167 }; 168 169 /** 170 * PINGPONG sub-blocks 171 * @DPU_PINGPONG_TE Tear check block 172 * @DPU_PINGPONG_TE2 Additional tear check block for split pipes 173 * @DPU_PINGPONG_SPLIT PP block supports split fifo 174 * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo 175 * @DPU_PINGPONG_DITHER, Dither blocks 176 * @DPU_PINGPONG_MAX 177 */ 178 enum { 179 DPU_PINGPONG_TE = 0x1, 180 DPU_PINGPONG_TE2, 181 DPU_PINGPONG_SPLIT, 182 DPU_PINGPONG_SLAVE, 183 DPU_PINGPONG_DITHER, 184 DPU_PINGPONG_MAX 185 }; 186 187 /** 188 * CTL sub-blocks 189 * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display 190 * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs) 191 * @DPU_CTL_VM_CFG: CTL config to support multiple VMs 192 * @DPU_CTL_MAX 193 */ 194 enum { 195 DPU_CTL_SPLIT_DISPLAY = 0x1, 196 DPU_CTL_ACTIVE_CFG, 197 DPU_CTL_FETCH_ACTIVE, 198 DPU_CTL_VM_CFG, 199 DPU_CTL_MAX 200 }; 201 202 /** 203 * INTF sub-blocks 204 * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which 205 * pixel data arrives to this INTF 206 * @DPU_INTF_TE INTF block has TE configuration support 207 * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate 208 than video timing 209 * @DPU_INTF_MAX 210 */ 211 enum { 212 DPU_INTF_INPUT_CTRL = 0x1, 213 DPU_INTF_TE, 214 DPU_DATA_HCTL_EN, 215 DPU_INTF_MAX 216 }; 217 218 /** 219 * WB sub-blocks and features 220 * @DPU_WB_LINE_MODE Writeback module supports line/linear mode 221 * @DPU_WB_BLOCK_MODE Writeback module supports block mode read 222 * @DPU_WB_CHROMA_DOWN, Writeback chroma down block, 223 * @DPU_WB_DOWNSCALE, Writeback integer downscaler, 224 * @DPU_WB_DITHER, Dither block 225 * @DPU_WB_TRAFFIC_SHAPER, Writeback traffic shaper bloc 226 * @DPU_WB_UBWC, Writeback Universal bandwidth compression 227 * @DPU_WB_YUV_CONFIG Writeback supports output of YUV colorspace 228 * @DPU_WB_PIPE_ALPHA Writeback supports pipe alpha 229 * @DPU_WB_XY_ROI_OFFSET Writeback supports x/y-offset of out ROI in 230 * the destination image 231 * @DPU_WB_QOS, Writeback supports QoS control, danger/safe/creq 232 * @DPU_WB_QOS_8LVL, Writeback supports 8-level QoS control 233 * @DPU_WB_CDP Writeback supports client driven prefetch 234 * @DPU_WB_INPUT_CTRL Writeback supports from which pp block input pixel 235 * data arrives. 236 * @DPU_WB_CROP CWB supports cropping 237 * @DPU_WB_MAX maximum value 238 */ 239 enum { 240 DPU_WB_LINE_MODE = 0x1, 241 DPU_WB_BLOCK_MODE, 242 DPU_WB_UBWC, 243 DPU_WB_YUV_CONFIG, 244 DPU_WB_PIPE_ALPHA, 245 DPU_WB_XY_ROI_OFFSET, 246 DPU_WB_QOS, 247 DPU_WB_QOS_8LVL, 248 DPU_WB_CDP, 249 DPU_WB_INPUT_CTRL, 250 DPU_WB_CROP, 251 DPU_WB_MAX 252 }; 253 254 /** 255 * VBIF sub-blocks and features 256 * @DPU_VBIF_QOS_OTLIM VBIF supports OT Limit 257 * @DPU_VBIF_QOS_REMAP VBIF supports QoS priority remap 258 * @DPU_VBIF_MAX maximum value 259 */ 260 enum { 261 DPU_VBIF_QOS_OTLIM = 0x1, 262 DPU_VBIF_QOS_REMAP, 263 DPU_VBIF_MAX 264 }; 265 266 /** 267 * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU 268 * @name: string name for debug purposes 269 * @id: enum identifying this block 270 * @base: register base offset to mdss 271 * @len: length of hardware block 272 * @features bit mask identifying sub-blocks/features 273 */ 274 #define DPU_HW_BLK_INFO \ 275 char name[DPU_HW_BLK_NAME_LEN]; \ 276 u32 id; \ 277 u32 base; \ 278 u32 len; \ 279 unsigned long features 280 281 /** 282 * MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU 283 * @name: string name for debug purposes 284 * @id: enum identifying this sub-block 285 * @base: offset of this sub-block relative to the block 286 * offset 287 * @len register block length of this sub-block 288 */ 289 #define DPU_HW_SUBBLK_INFO \ 290 char name[DPU_HW_BLK_NAME_LEN]; \ 291 u32 id; \ 292 u32 base; \ 293 u32 len 294 295 /** 296 * struct dpu_src_blk: SSPP part of the source pipes 297 * @info: HW register and features supported by this sub-blk 298 */ 299 struct dpu_src_blk { 300 DPU_HW_SUBBLK_INFO; 301 }; 302 303 /** 304 * struct dpu_scaler_blk: Scaler information 305 * @info: HW register and features supported by this sub-blk 306 * @version: qseed block revision 307 */ 308 struct dpu_scaler_blk { 309 DPU_HW_SUBBLK_INFO; 310 u32 version; 311 }; 312 313 struct dpu_csc_blk { 314 DPU_HW_SUBBLK_INFO; 315 }; 316 317 /** 318 * struct dpu_pp_blk : Pixel processing sub-blk information 319 * @info: HW register and features supported by this sub-blk 320 * @version: HW Algorithm version 321 */ 322 struct dpu_pp_blk { 323 DPU_HW_SUBBLK_INFO; 324 u32 version; 325 }; 326 327 /** 328 * enum dpu_qos_lut_usage - define QoS LUT use cases 329 */ 330 enum dpu_qos_lut_usage { 331 DPU_QOS_LUT_USAGE_LINEAR, 332 DPU_QOS_LUT_USAGE_MACROTILE, 333 DPU_QOS_LUT_USAGE_NRT, 334 DPU_QOS_LUT_USAGE_MAX, 335 }; 336 337 /** 338 * struct dpu_qos_lut_entry - define QoS LUT table entry 339 * @fl: fill level, or zero on last entry to indicate default lut 340 * @lut: lut to use if equal to or less than fill level 341 */ 342 struct dpu_qos_lut_entry { 343 u32 fl; 344 u64 lut; 345 }; 346 347 /** 348 * struct dpu_qos_lut_tbl - define QoS LUT table 349 * @nentry: number of entry in this table 350 * @entries: Pointer to table entries 351 */ 352 struct dpu_qos_lut_tbl { 353 u32 nentry; 354 const struct dpu_qos_lut_entry *entries; 355 }; 356 357 /** 358 * struct dpu_rotation_cfg - define inline rotation config 359 * @rot_maxheight: max pre rotated height allowed for rotation 360 * @rot_num_formats: number of elements in @rot_format_list 361 * @rot_format_list: list of supported rotator formats 362 */ 363 struct dpu_rotation_cfg { 364 u32 rot_maxheight; 365 size_t rot_num_formats; 366 const u32 *rot_format_list; 367 }; 368 369 /** 370 * struct dpu_caps - define DPU capabilities 371 * @max_mixer_width max layer mixer line width support. 372 * @max_mixer_blendstages max layer mixer blend stages or 373 * supported z order 374 * @qseed_type qseed2 or qseed3 support. 375 * @smart_dma_rev Supported version of SmartDMA feature. 376 * @ubwc_version UBWC feature version (0x0 for not supported) 377 * @has_src_split source split feature status 378 * @has_dim_layer dim layer feature status 379 * @has_idle_pc indicate if idle power collapse feature is supported 380 * @has_3d_merge indicate if 3D merge is supported 381 * @max_linewidth max linewidth for sspp 382 * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes 383 * @max_hdeci_exp max horizontal decimation supported (max is 2^value) 384 * @max_vdeci_exp max vertical decimation supported (max is 2^value) 385 */ 386 struct dpu_caps { 387 u32 max_mixer_width; 388 u32 max_mixer_blendstages; 389 u32 qseed_type; 390 u32 smart_dma_rev; 391 u32 ubwc_version; 392 bool has_src_split; 393 bool has_dim_layer; 394 bool has_idle_pc; 395 bool has_3d_merge; 396 /* SSPP limits */ 397 u32 max_linewidth; 398 u32 pixel_ram_size; 399 u32 max_hdeci_exp; 400 u32 max_vdeci_exp; 401 }; 402 403 /** 404 * struct dpu_sspp_sub_blks : SSPP sub-blocks 405 * common: Pointer to common configurations shared by sub blocks 406 * @creq_vblank: creq priority during vertical blanking 407 * @danger_vblank: danger priority during vertical blanking 408 * @maxdwnscale: max downscale ratio supported(without DECIMATION) 409 * @maxupscale: maxupscale ratio supported 410 * @smart_dma_priority: hw priority of rect1 of multirect pipe 411 * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps 412 * @qseed_ver: qseed version 413 * @src_blk: 414 * @scaler_blk: 415 * @csc_blk: 416 * @hsic: 417 * @memcolor: 418 * @pcc_blk: 419 * @igc_blk: 420 * @format_list: Pointer to list of supported formats 421 * @num_formats: Number of supported formats 422 * @virt_format_list: Pointer to list of supported formats for virtual planes 423 * @virt_num_formats: Number of supported formats for virtual planes 424 * @dpu_rotation_cfg: inline rotation configuration 425 */ 426 struct dpu_sspp_sub_blks { 427 u32 creq_vblank; 428 u32 danger_vblank; 429 u32 maxdwnscale; 430 u32 maxupscale; 431 u32 smart_dma_priority; 432 u32 max_per_pipe_bw; 433 u32 qseed_ver; 434 struct dpu_src_blk src_blk; 435 struct dpu_scaler_blk scaler_blk; 436 struct dpu_pp_blk csc_blk; 437 struct dpu_pp_blk hsic_blk; 438 struct dpu_pp_blk memcolor_blk; 439 struct dpu_pp_blk pcc_blk; 440 struct dpu_pp_blk igc_blk; 441 442 const u32 *format_list; 443 u32 num_formats; 444 const u32 *virt_format_list; 445 u32 virt_num_formats; 446 const struct dpu_rotation_cfg *rotation_cfg; 447 }; 448 449 /** 450 * struct dpu_lm_sub_blks: information of mixer block 451 * @maxwidth: Max pixel width supported by this mixer 452 * @maxblendstages: Max number of blend-stages supported 453 * @blendstage_base: Blend-stage register base offset 454 * @gc: gamma correction block 455 */ 456 struct dpu_lm_sub_blks { 457 u32 maxwidth; 458 u32 maxblendstages; 459 u32 blendstage_base[MAX_BLOCKS]; 460 struct dpu_pp_blk gc; 461 }; 462 463 /** 464 * struct dpu_dspp_sub_blks: Information of DSPP block 465 * @gc : gamma correction block 466 * @pcc: pixel color correction block 467 */ 468 struct dpu_dspp_sub_blks { 469 struct dpu_pp_blk gc; 470 struct dpu_pp_blk pcc; 471 }; 472 473 struct dpu_pingpong_sub_blks { 474 struct dpu_pp_blk te; 475 struct dpu_pp_blk te2; 476 struct dpu_pp_blk dither; 477 }; 478 479 /** 480 * dpu_clk_ctrl_type - Defines top level clock control signals 481 */ 482 enum dpu_clk_ctrl_type { 483 DPU_CLK_CTRL_NONE, 484 DPU_CLK_CTRL_VIG0, 485 DPU_CLK_CTRL_VIG1, 486 DPU_CLK_CTRL_VIG2, 487 DPU_CLK_CTRL_VIG3, 488 DPU_CLK_CTRL_VIG4, 489 DPU_CLK_CTRL_RGB0, 490 DPU_CLK_CTRL_RGB1, 491 DPU_CLK_CTRL_RGB2, 492 DPU_CLK_CTRL_RGB3, 493 DPU_CLK_CTRL_DMA0, 494 DPU_CLK_CTRL_DMA1, 495 DPU_CLK_CTRL_DMA2, 496 DPU_CLK_CTRL_DMA3, 497 DPU_CLK_CTRL_CURSOR0, 498 DPU_CLK_CTRL_CURSOR1, 499 DPU_CLK_CTRL_INLINE_ROT0_SSPP, 500 DPU_CLK_CTRL_REG_DMA, 501 DPU_CLK_CTRL_WB2, 502 DPU_CLK_CTRL_MAX, 503 }; 504 505 /* struct dpu_clk_ctrl_reg : Clock control register 506 * @reg_off: register offset 507 * @bit_off: bit offset 508 */ 509 struct dpu_clk_ctrl_reg { 510 u32 reg_off; 511 u32 bit_off; 512 }; 513 514 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info 515 * @id: index identifying this block 516 * @base: register base offset to mdss 517 * @features bit mask identifying sub-blocks/features 518 * @highest_bank_bit: UBWC parameter 519 * @ubwc_static: ubwc static configuration 520 * @ubwc_swizzle: ubwc default swizzle setting 521 * @clk_ctrls clock control register definition 522 */ 523 struct dpu_mdp_cfg { 524 DPU_HW_BLK_INFO; 525 u32 highest_bank_bit; 526 u32 ubwc_swizzle; 527 struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; 528 }; 529 530 /* struct dpu_ctl_cfg : MDP CTL instance info 531 * @id: index identifying this block 532 * @base: register base offset to mdss 533 * @features bit mask identifying sub-blocks/features 534 * @intr_start: interrupt index for CTL_START 535 */ 536 struct dpu_ctl_cfg { 537 DPU_HW_BLK_INFO; 538 s32 intr_start; 539 }; 540 541 /** 542 * struct dpu_sspp_cfg - information of source pipes 543 * @id: index identifying this block 544 * @base register offset of this block 545 * @features bit mask identifying sub-blocks/features 546 * @sblk: SSPP sub-blocks information 547 * @xin_id: bus client identifier 548 * @clk_ctrl clock control identifier 549 * @type sspp type identifier 550 */ 551 struct dpu_sspp_cfg { 552 DPU_HW_BLK_INFO; 553 const struct dpu_sspp_sub_blks *sblk; 554 u32 xin_id; 555 enum dpu_clk_ctrl_type clk_ctrl; 556 u32 type; 557 }; 558 559 /** 560 * struct dpu_lm_cfg - information of layer mixer blocks 561 * @id: index identifying this block 562 * @base register offset of this block 563 * @features bit mask identifying sub-blocks/features 564 * @sblk: LM Sub-blocks information 565 * @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported 566 * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL 567 */ 568 struct dpu_lm_cfg { 569 DPU_HW_BLK_INFO; 570 const struct dpu_lm_sub_blks *sblk; 571 u32 pingpong; 572 u32 dspp; 573 unsigned long lm_pair_mask; 574 }; 575 576 /** 577 * struct dpu_dspp_cfg - information of DSPP blocks 578 * @id enum identifying this block 579 * @base register offset of this block 580 * @features bit mask identifying sub-blocks/features 581 * supported by this block 582 * @sblk sub-blocks information 583 */ 584 struct dpu_dspp_cfg { 585 DPU_HW_BLK_INFO; 586 const struct dpu_dspp_sub_blks *sblk; 587 }; 588 589 /** 590 * struct dpu_pingpong_cfg - information of PING-PONG blocks 591 * @id enum identifying this block 592 * @base register offset of this block 593 * @features bit mask identifying sub-blocks/features 594 * @intr_done: index for PINGPONG done interrupt 595 * @intr_rdptr: index for PINGPONG readpointer done interrupt 596 * @sblk sub-blocks information 597 */ 598 struct dpu_pingpong_cfg { 599 DPU_HW_BLK_INFO; 600 u32 merge_3d; 601 s32 intr_done; 602 s32 intr_rdptr; 603 const struct dpu_pingpong_sub_blks *sblk; 604 }; 605 606 /** 607 * struct dpu_merge_3d_cfg - information of DSPP blocks 608 * @id enum identifying this block 609 * @base register offset of this block 610 * @features bit mask identifying sub-blocks/features 611 * supported by this block 612 * @sblk sub-blocks information 613 */ 614 struct dpu_merge_3d_cfg { 615 DPU_HW_BLK_INFO; 616 const struct dpu_merge_3d_sub_blks *sblk; 617 }; 618 619 /** 620 * struct dpu_dsc_cfg - information of DSC blocks 621 * @id enum identifying this block 622 * @base register offset of this block 623 * @features bit mask identifying sub-blocks/features 624 */ 625 struct dpu_dsc_cfg { 626 DPU_HW_BLK_INFO; 627 }; 628 629 /** 630 * struct dpu_intf_cfg - information of timing engine blocks 631 * @id enum identifying this block 632 * @base register offset of this block 633 * @features bit mask identifying sub-blocks/features 634 * @type: Interface type(DSI, DP, HDMI) 635 * @controller_id: Controller Instance ID in case of multiple of intf type 636 * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch 637 * @intr_underrun: index for INTF underrun interrupt 638 * @intr_vsync: index for INTF VSYNC interrupt 639 */ 640 struct dpu_intf_cfg { 641 DPU_HW_BLK_INFO; 642 u32 type; /* interface type*/ 643 u32 controller_id; 644 u32 prog_fetch_lines_worst_case; 645 s32 intr_underrun; 646 s32 intr_vsync; 647 }; 648 649 /** 650 * struct dpu_wb_cfg - information of writeback blocks 651 * @DPU_HW_BLK_INFO: refer to the description above for DPU_HW_BLK_INFO 652 * @vbif_idx: vbif client index 653 * @maxlinewidth: max line width supported by writeback block 654 * @xin_id: bus client identifier 655 * @intr_wb_done: interrupt index for WB_DONE 656 * @format_list: list of formats supported by this writeback block 657 * @num_formats: number of formats supported by this writeback block 658 * @clk_ctrl: clock control identifier 659 */ 660 struct dpu_wb_cfg { 661 DPU_HW_BLK_INFO; 662 u8 vbif_idx; 663 u32 maxlinewidth; 664 u32 xin_id; 665 s32 intr_wb_done; 666 const u32 *format_list; 667 u32 num_formats; 668 enum dpu_clk_ctrl_type clk_ctrl; 669 }; 670 671 /** 672 * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting 673 * @pps pixel per seconds 674 * @ot_limit OT limit to use up to specified pixel per second 675 */ 676 struct dpu_vbif_dynamic_ot_cfg { 677 u64 pps; 678 u32 ot_limit; 679 }; 680 681 /** 682 * struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table 683 * @count length of cfg 684 * @cfg pointer to array of configuration settings with 685 * ascending requirements 686 */ 687 struct dpu_vbif_dynamic_ot_tbl { 688 u32 count; 689 const struct dpu_vbif_dynamic_ot_cfg *cfg; 690 }; 691 692 /** 693 * struct dpu_vbif_qos_tbl - QoS priority table 694 * @npriority_lvl num of priority level 695 * @priority_lvl pointer to array of priority level in ascending order 696 */ 697 struct dpu_vbif_qos_tbl { 698 u32 npriority_lvl; 699 const u32 *priority_lvl; 700 }; 701 702 /** 703 * struct dpu_vbif_cfg - information of VBIF blocks 704 * @id enum identifying this block 705 * @base register offset of this block 706 * @features bit mask identifying sub-blocks/features 707 * @ot_rd_limit default OT read limit 708 * @ot_wr_limit default OT write limit 709 * @xin_halt_timeout maximum time (in usec) for xin to halt 710 * @dynamic_ot_rd_tbl dynamic OT read configuration table 711 * @dynamic_ot_wr_tbl dynamic OT write configuration table 712 * @qos_rt_tbl real-time QoS priority table 713 * @qos_nrt_tbl non-real-time QoS priority table 714 * @memtype_count number of defined memtypes 715 * @memtype array of xin memtype definitions 716 */ 717 struct dpu_vbif_cfg { 718 DPU_HW_BLK_INFO; 719 u32 default_ot_rd_limit; 720 u32 default_ot_wr_limit; 721 u32 xin_halt_timeout; 722 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl; 723 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl; 724 struct dpu_vbif_qos_tbl qos_rt_tbl; 725 struct dpu_vbif_qos_tbl qos_nrt_tbl; 726 u32 memtype_count; 727 u32 memtype[MAX_XIN_COUNT]; 728 }; 729 /** 730 * struct dpu_reg_dma_cfg - information of lut dma blocks 731 * @id enum identifying this block 732 * @base register offset of this block 733 * @features bit mask identifying sub-blocks/features 734 * @version version of lutdma hw block 735 * @trigger_sel_off offset to trigger select registers of lutdma 736 */ 737 struct dpu_reg_dma_cfg { 738 DPU_HW_BLK_INFO; 739 u32 version; 740 u32 trigger_sel_off; 741 u32 xin_id; 742 enum dpu_clk_ctrl_type clk_ctrl; 743 }; 744 745 /** 746 * Define CDP use cases 747 * @DPU_PERF_CDP_UDAGE_RT: real-time use cases 748 * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD 749 */ 750 enum { 751 DPU_PERF_CDP_USAGE_RT, 752 DPU_PERF_CDP_USAGE_NRT, 753 DPU_PERF_CDP_USAGE_MAX 754 }; 755 756 /** 757 * struct dpu_perf_cdp_cfg - define CDP use case configuration 758 * @rd_enable: true if read pipe CDP is enabled 759 * @wr_enable: true if write pipe CDP is enabled 760 */ 761 struct dpu_perf_cdp_cfg { 762 bool rd_enable; 763 bool wr_enable; 764 }; 765 766 /** 767 * struct dpu_perf_cfg - performance control settings 768 * @max_bw_low low threshold of maximum bandwidth (kbps) 769 * @max_bw_high high threshold of maximum bandwidth (kbps) 770 * @min_core_ib minimum bandwidth for core (kbps) 771 * @min_core_ib minimum mnoc ib vote in kbps 772 * @min_llcc_ib minimum llcc ib vote in kbps 773 * @min_dram_ib minimum dram ib vote in kbps 774 * @undersized_prefill_lines undersized prefill in lines 775 * @xtra_prefill_lines extra prefill latency in lines 776 * @dest_scale_prefill_lines destination scaler latency in lines 777 * @macrotile_perfill_lines macrotile latency in lines 778 * @yuv_nv12_prefill_lines yuv_nv12 latency in lines 779 * @linear_prefill_lines linear latency in lines 780 * @downscaling_prefill_lines downscaling latency in lines 781 * @amortizable_theshold minimum y position for traffic shaping prefill 782 * @min_prefill_lines minimum pipeline latency in lines 783 * @clk_inefficiency_factor DPU src clock inefficiency factor 784 * @bw_inefficiency_factor DPU axi bus bw inefficiency factor 785 * @safe_lut_tbl: LUT tables for safe signals 786 * @danger_lut_tbl: LUT tables for danger signals 787 * @qos_lut_tbl: LUT tables for QoS signals 788 * @cdp_cfg cdp use case configurations 789 */ 790 struct dpu_perf_cfg { 791 u32 max_bw_low; 792 u32 max_bw_high; 793 u32 min_core_ib; 794 u32 min_llcc_ib; 795 u32 min_dram_ib; 796 u32 undersized_prefill_lines; 797 u32 xtra_prefill_lines; 798 u32 dest_scale_prefill_lines; 799 u32 macrotile_prefill_lines; 800 u32 yuv_nv12_prefill_lines; 801 u32 linear_prefill_lines; 802 u32 downscaling_prefill_lines; 803 u32 amortizable_threshold; 804 u32 min_prefill_lines; 805 u32 clk_inefficiency_factor; 806 u32 bw_inefficiency_factor; 807 u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 808 u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 809 struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 810 struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX]; 811 }; 812 813 /** 814 * struct dpu_mdss_cfg - information of MDSS HW 815 * This is the main catalog data structure representing 816 * this HW version. Contains number of instances, 817 * register offsets, capabilities of the all MDSS HW sub-blocks. 818 * 819 * @dma_formats Supported formats for dma pipe 820 * @cursor_formats Supported formats for cursor pipe 821 * @vig_formats Supported formats for vig pipe 822 * @mdss_irqs: Bitmap with the irqs supported by the target 823 */ 824 struct dpu_mdss_cfg { 825 u32 hwversion; 826 827 const struct dpu_caps *caps; 828 829 u32 mdp_count; 830 const struct dpu_mdp_cfg *mdp; 831 832 u32 ctl_count; 833 const struct dpu_ctl_cfg *ctl; 834 835 u32 sspp_count; 836 const struct dpu_sspp_cfg *sspp; 837 838 u32 mixer_count; 839 const struct dpu_lm_cfg *mixer; 840 841 u32 pingpong_count; 842 const struct dpu_pingpong_cfg *pingpong; 843 844 u32 merge_3d_count; 845 const struct dpu_merge_3d_cfg *merge_3d; 846 847 u32 dsc_count; 848 struct dpu_dsc_cfg *dsc; 849 850 u32 intf_count; 851 const struct dpu_intf_cfg *intf; 852 853 u32 vbif_count; 854 const struct dpu_vbif_cfg *vbif; 855 856 u32 wb_count; 857 const struct dpu_wb_cfg *wb; 858 859 u32 reg_dma_count; 860 struct dpu_reg_dma_cfg dma_cfg; 861 862 u32 ad_count; 863 864 u32 dspp_count; 865 const struct dpu_dspp_cfg *dspp; 866 867 /* Add additional block data structures here */ 868 869 struct dpu_perf_cfg perf; 870 const struct dpu_format_extended *dma_formats; 871 const struct dpu_format_extended *cursor_formats; 872 const struct dpu_format_extended *vig_formats; 873 874 unsigned long mdss_irqs; 875 }; 876 877 struct dpu_mdss_hw_cfg_handler { 878 u32 hw_rev; 879 void (*cfg_init)(struct dpu_mdss_cfg *dpu_cfg); 880 }; 881 882 /** 883 * dpu_hw_catalog_init - dpu hardware catalog init API retrieves 884 * hardcoded target specific catalog information in config structure 885 * @hw_rev: caller needs provide the hardware revision. 886 * 887 * Return: dpu config structure 888 */ 889 struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev); 890 891 /** 892 * dpu_hw_catalog_deinit - dpu hardware catalog cleanup 893 * @dpu_cfg: pointer returned from init function 894 */ 895 void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg); 896 897 #endif /* _DPU_HW_CATALOG_H */ 898