1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Resource Director Technology(RDT)
4 * - Cache Allocation code.
5 *
6 * Copyright (C) 2016 Intel Corporation
7 *
8 * Authors:
9 * Fenghua Yu <fenghua.yu@intel.com>
10 * Tony Luck <tony.luck@intel.com>
11 * Vikas Shivappa <vikas.shivappa@intel.com>
12 *
13 * More information about RDT be found in the Intel (R) x86 Architecture
14 * Software Developer Manual June 2016, volume 3, section 17.17.
15 */
16
17 #define pr_fmt(fmt) "resctrl: " fmt
18
19 #include <linux/slab.h>
20 #include <linux/err.h>
21 #include <linux/cacheinfo.h>
22 #include <linux/cpuhotplug.h>
23
24 #include <asm/intel-family.h>
25 #include <asm/resctrl.h>
26 #include "internal.h"
27
28 /* Mutex to protect rdtgroup access. */
29 DEFINE_MUTEX(rdtgroup_mutex);
30
31 /*
32 * The cached resctrl_pqr_state is strictly per CPU and can never be
33 * updated from a remote CPU. Functions which modify the state
34 * are called with interrupts disabled and no preemption, which
35 * is sufficient for the protection.
36 */
37 DEFINE_PER_CPU(struct resctrl_pqr_state, pqr_state);
38
39 /*
40 * Used to store the max resource name width and max resource data width
41 * to display the schemata in a tabular format
42 */
43 int max_name_width, max_data_width;
44
45 /*
46 * Global boolean for rdt_alloc which is true if any
47 * resource allocation is enabled.
48 */
49 bool rdt_alloc_capable;
50
51 static void
52 mba_wrmsr_intel(struct rdt_domain *d, struct msr_param *m,
53 struct rdt_resource *r);
54 static void
55 cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r);
56 static void
57 mba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m,
58 struct rdt_resource *r);
59
60 #define domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.domains)
61
62 struct rdt_hw_resource rdt_resources_all[] = {
63 [RDT_RESOURCE_L3] =
64 {
65 .r_resctrl = {
66 .rid = RDT_RESOURCE_L3,
67 .name = "L3",
68 .cache_level = 3,
69 .domains = domain_init(RDT_RESOURCE_L3),
70 .parse_ctrlval = parse_cbm,
71 .format_str = "%d=%0*x",
72 .fflags = RFTYPE_RES_CACHE,
73 },
74 .msr_base = MSR_IA32_L3_CBM_BASE,
75 .msr_update = cat_wrmsr,
76 },
77 [RDT_RESOURCE_L2] =
78 {
79 .r_resctrl = {
80 .rid = RDT_RESOURCE_L2,
81 .name = "L2",
82 .cache_level = 2,
83 .domains = domain_init(RDT_RESOURCE_L2),
84 .parse_ctrlval = parse_cbm,
85 .format_str = "%d=%0*x",
86 .fflags = RFTYPE_RES_CACHE,
87 },
88 .msr_base = MSR_IA32_L2_CBM_BASE,
89 .msr_update = cat_wrmsr,
90 },
91 [RDT_RESOURCE_MBA] =
92 {
93 .r_resctrl = {
94 .rid = RDT_RESOURCE_MBA,
95 .name = "MB",
96 .cache_level = 3,
97 .domains = domain_init(RDT_RESOURCE_MBA),
98 .parse_ctrlval = parse_bw,
99 .format_str = "%d=%*u",
100 .fflags = RFTYPE_RES_MB,
101 },
102 },
103 [RDT_RESOURCE_SMBA] =
104 {
105 .r_resctrl = {
106 .rid = RDT_RESOURCE_SMBA,
107 .name = "SMBA",
108 .cache_level = 3,
109 .domains = domain_init(RDT_RESOURCE_SMBA),
110 .parse_ctrlval = parse_bw,
111 .format_str = "%d=%*u",
112 .fflags = RFTYPE_RES_MB,
113 },
114 },
115 };
116
117 /*
118 * cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs
119 * as they do not have CPUID enumeration support for Cache allocation.
120 * The check for Vendor/Family/Model is not enough to guarantee that
121 * the MSRs won't #GP fault because only the following SKUs support
122 * CAT:
123 * Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz
124 * Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz
125 * Intel(R) Xeon(R) CPU E5-2628L v3 @ 2.00GHz
126 * Intel(R) Xeon(R) CPU E5-2618L v3 @ 2.30GHz
127 * Intel(R) Xeon(R) CPU E5-2608L v3 @ 2.00GHz
128 * Intel(R) Xeon(R) CPU E5-2658A v3 @ 2.20GHz
129 *
130 * Probe by trying to write the first of the L3 cache mask registers
131 * and checking that the bits stick. Max CLOSids is always 4 and max cbm length
132 * is always 20 on hsw server parts. The minimum cache bitmask length
133 * allowed for HSW server is always 2 bits. Hardcode all of them.
134 */
cache_alloc_hsw_probe(void)135 static inline void cache_alloc_hsw_probe(void)
136 {
137 struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_L3];
138 struct rdt_resource *r = &hw_res->r_resctrl;
139 u32 l, h, max_cbm = BIT_MASK(20) - 1;
140
141 if (wrmsr_safe(MSR_IA32_L3_CBM_BASE, max_cbm, 0))
142 return;
143
144 rdmsr(MSR_IA32_L3_CBM_BASE, l, h);
145
146 /* If all the bits were set in MSR, return success */
147 if (l != max_cbm)
148 return;
149
150 hw_res->num_closid = 4;
151 r->default_ctrl = max_cbm;
152 r->cache.cbm_len = 20;
153 r->cache.shareable_bits = 0xc0000;
154 r->cache.min_cbm_bits = 2;
155 r->alloc_capable = true;
156
157 rdt_alloc_capable = true;
158 }
159
is_mba_sc(struct rdt_resource * r)160 bool is_mba_sc(struct rdt_resource *r)
161 {
162 if (!r)
163 return rdt_resources_all[RDT_RESOURCE_MBA].r_resctrl.membw.mba_sc;
164
165 /*
166 * The software controller support is only applicable to MBA resource.
167 * Make sure to check for resource type.
168 */
169 if (r->rid != RDT_RESOURCE_MBA)
170 return false;
171
172 return r->membw.mba_sc;
173 }
174
175 /*
176 * rdt_get_mb_table() - get a mapping of bandwidth(b/w) percentage values
177 * exposed to user interface and the h/w understandable delay values.
178 *
179 * The non-linear delay values have the granularity of power of two
180 * and also the h/w does not guarantee a curve for configured delay
181 * values vs. actual b/w enforced.
182 * Hence we need a mapping that is pre calibrated so the user can
183 * express the memory b/w as a percentage value.
184 */
rdt_get_mb_table(struct rdt_resource * r)185 static inline bool rdt_get_mb_table(struct rdt_resource *r)
186 {
187 /*
188 * There are no Intel SKUs as of now to support non-linear delay.
189 */
190 pr_info("MBA b/w map not implemented for cpu:%d, model:%d",
191 boot_cpu_data.x86, boot_cpu_data.x86_model);
192
193 return false;
194 }
195
__get_mem_config_intel(struct rdt_resource * r)196 static bool __get_mem_config_intel(struct rdt_resource *r)
197 {
198 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
199 union cpuid_0x10_3_eax eax;
200 union cpuid_0x10_x_edx edx;
201 u32 ebx, ecx, max_delay;
202
203 cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full);
204 hw_res->num_closid = edx.split.cos_max + 1;
205 max_delay = eax.split.max_delay + 1;
206 r->default_ctrl = MAX_MBA_BW;
207 r->membw.arch_needs_linear = true;
208 if (ecx & MBA_IS_LINEAR) {
209 r->membw.delay_linear = true;
210 r->membw.min_bw = MAX_MBA_BW - max_delay;
211 r->membw.bw_gran = MAX_MBA_BW - max_delay;
212 } else {
213 if (!rdt_get_mb_table(r))
214 return false;
215 r->membw.arch_needs_linear = false;
216 }
217 r->data_width = 3;
218
219 if (boot_cpu_has(X86_FEATURE_PER_THREAD_MBA))
220 r->membw.throttle_mode = THREAD_THROTTLE_PER_THREAD;
221 else
222 r->membw.throttle_mode = THREAD_THROTTLE_MAX;
223 thread_throttle_mode_init();
224
225 r->alloc_capable = true;
226
227 return true;
228 }
229
__rdt_get_mem_config_amd(struct rdt_resource * r)230 static bool __rdt_get_mem_config_amd(struct rdt_resource *r)
231 {
232 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
233 union cpuid_0x10_3_eax eax;
234 union cpuid_0x10_x_edx edx;
235 u32 ebx, ecx, subleaf;
236
237 /*
238 * Query CPUID_Fn80000020_EDX_x01 for MBA and
239 * CPUID_Fn80000020_EDX_x02 for SMBA
240 */
241 subleaf = (r->rid == RDT_RESOURCE_SMBA) ? 2 : 1;
242
243 cpuid_count(0x80000020, subleaf, &eax.full, &ebx, &ecx, &edx.full);
244 hw_res->num_closid = edx.split.cos_max + 1;
245 r->default_ctrl = MAX_MBA_BW_AMD;
246
247 /* AMD does not use delay */
248 r->membw.delay_linear = false;
249 r->membw.arch_needs_linear = false;
250
251 /*
252 * AMD does not use memory delay throttle model to control
253 * the allocation like Intel does.
254 */
255 r->membw.throttle_mode = THREAD_THROTTLE_UNDEFINED;
256 r->membw.min_bw = 0;
257 r->membw.bw_gran = 1;
258 /* Max value is 2048, Data width should be 4 in decimal */
259 r->data_width = 4;
260
261 r->alloc_capable = true;
262
263 return true;
264 }
265
rdt_get_cache_alloc_cfg(int idx,struct rdt_resource * r)266 static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r)
267 {
268 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
269 union cpuid_0x10_1_eax eax;
270 union cpuid_0x10_x_edx edx;
271 u32 ebx, ecx;
272
273 cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx, &edx.full);
274 hw_res->num_closid = edx.split.cos_max + 1;
275 r->cache.cbm_len = eax.split.cbm_len + 1;
276 r->default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1;
277 r->cache.shareable_bits = ebx & r->default_ctrl;
278 r->data_width = (r->cache.cbm_len + 3) / 4;
279 r->alloc_capable = true;
280 }
281
rdt_get_cdp_config(int level)282 static void rdt_get_cdp_config(int level)
283 {
284 /*
285 * By default, CDP is disabled. CDP can be enabled by mount parameter
286 * "cdp" during resctrl file system mount time.
287 */
288 rdt_resources_all[level].cdp_enabled = false;
289 rdt_resources_all[level].r_resctrl.cdp_capable = true;
290 }
291
rdt_get_cdp_l3_config(void)292 static void rdt_get_cdp_l3_config(void)
293 {
294 rdt_get_cdp_config(RDT_RESOURCE_L3);
295 }
296
rdt_get_cdp_l2_config(void)297 static void rdt_get_cdp_l2_config(void)
298 {
299 rdt_get_cdp_config(RDT_RESOURCE_L2);
300 }
301
302 static void
mba_wrmsr_amd(struct rdt_domain * d,struct msr_param * m,struct rdt_resource * r)303 mba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r)
304 {
305 unsigned int i;
306 struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d);
307 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
308
309 for (i = m->low; i < m->high; i++)
310 wrmsrl(hw_res->msr_base + i, hw_dom->ctrl_val[i]);
311 }
312
313 /*
314 * Map the memory b/w percentage value to delay values
315 * that can be written to QOS_MSRs.
316 * There are currently no SKUs which support non linear delay values.
317 */
delay_bw_map(unsigned long bw,struct rdt_resource * r)318 static u32 delay_bw_map(unsigned long bw, struct rdt_resource *r)
319 {
320 if (r->membw.delay_linear)
321 return MAX_MBA_BW - bw;
322
323 pr_warn_once("Non Linear delay-bw map not supported but queried\n");
324 return r->default_ctrl;
325 }
326
327 static void
mba_wrmsr_intel(struct rdt_domain * d,struct msr_param * m,struct rdt_resource * r)328 mba_wrmsr_intel(struct rdt_domain *d, struct msr_param *m,
329 struct rdt_resource *r)
330 {
331 unsigned int i;
332 struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d);
333 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
334
335 /* Write the delay values for mba. */
336 for (i = m->low; i < m->high; i++)
337 wrmsrl(hw_res->msr_base + i, delay_bw_map(hw_dom->ctrl_val[i], r));
338 }
339
340 static void
cat_wrmsr(struct rdt_domain * d,struct msr_param * m,struct rdt_resource * r)341 cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r)
342 {
343 unsigned int i;
344 struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d);
345 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
346
347 for (i = m->low; i < m->high; i++)
348 wrmsrl(hw_res->msr_base + i, hw_dom->ctrl_val[i]);
349 }
350
get_domain_from_cpu(int cpu,struct rdt_resource * r)351 struct rdt_domain *get_domain_from_cpu(int cpu, struct rdt_resource *r)
352 {
353 struct rdt_domain *d;
354
355 list_for_each_entry(d, &r->domains, list) {
356 /* Find the domain that contains this CPU */
357 if (cpumask_test_cpu(cpu, &d->cpu_mask))
358 return d;
359 }
360
361 return NULL;
362 }
363
resctrl_arch_get_num_closid(struct rdt_resource * r)364 u32 resctrl_arch_get_num_closid(struct rdt_resource *r)
365 {
366 return resctrl_to_arch_res(r)->num_closid;
367 }
368
rdt_ctrl_update(void * arg)369 void rdt_ctrl_update(void *arg)
370 {
371 struct msr_param *m = arg;
372 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res);
373 struct rdt_resource *r = m->res;
374 int cpu = smp_processor_id();
375 struct rdt_domain *d;
376
377 d = get_domain_from_cpu(cpu, r);
378 if (d) {
379 hw_res->msr_update(d, m, r);
380 return;
381 }
382 pr_warn_once("cpu %d not found in any domain for resource %s\n",
383 cpu, r->name);
384 }
385
386 /*
387 * rdt_find_domain - Find a domain in a resource that matches input resource id
388 *
389 * Search resource r's domain list to find the resource id. If the resource
390 * id is found in a domain, return the domain. Otherwise, if requested by
391 * caller, return the first domain whose id is bigger than the input id.
392 * The domain list is sorted by id in ascending order.
393 */
rdt_find_domain(struct rdt_resource * r,int id,struct list_head ** pos)394 struct rdt_domain *rdt_find_domain(struct rdt_resource *r, int id,
395 struct list_head **pos)
396 {
397 struct rdt_domain *d;
398 struct list_head *l;
399
400 if (id < 0)
401 return ERR_PTR(-ENODEV);
402
403 list_for_each(l, &r->domains) {
404 d = list_entry(l, struct rdt_domain, list);
405 /* When id is found, return its domain. */
406 if (id == d->id)
407 return d;
408 /* Stop searching when finding id's position in sorted list. */
409 if (id < d->id)
410 break;
411 }
412
413 if (pos)
414 *pos = l;
415
416 return NULL;
417 }
418
setup_default_ctrlval(struct rdt_resource * r,u32 * dc)419 static void setup_default_ctrlval(struct rdt_resource *r, u32 *dc)
420 {
421 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
422 int i;
423
424 /*
425 * Initialize the Control MSRs to having no control.
426 * For Cache Allocation: Set all bits in cbm
427 * For Memory Allocation: Set b/w requested to 100%
428 */
429 for (i = 0; i < hw_res->num_closid; i++, dc++)
430 *dc = r->default_ctrl;
431 }
432
domain_free(struct rdt_hw_domain * hw_dom)433 static void domain_free(struct rdt_hw_domain *hw_dom)
434 {
435 kfree(hw_dom->arch_mbm_total);
436 kfree(hw_dom->arch_mbm_local);
437 kfree(hw_dom->ctrl_val);
438 kfree(hw_dom);
439 }
440
domain_setup_ctrlval(struct rdt_resource * r,struct rdt_domain * d)441 static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_domain *d)
442 {
443 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
444 struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d);
445 struct msr_param m;
446 u32 *dc;
447
448 dc = kmalloc_array(hw_res->num_closid, sizeof(*hw_dom->ctrl_val),
449 GFP_KERNEL);
450 if (!dc)
451 return -ENOMEM;
452
453 hw_dom->ctrl_val = dc;
454 setup_default_ctrlval(r, dc);
455
456 m.low = 0;
457 m.high = hw_res->num_closid;
458 hw_res->msr_update(d, &m, r);
459 return 0;
460 }
461
462 /**
463 * arch_domain_mbm_alloc() - Allocate arch private storage for the MBM counters
464 * @num_rmid: The size of the MBM counter array
465 * @hw_dom: The domain that owns the allocated arrays
466 */
arch_domain_mbm_alloc(u32 num_rmid,struct rdt_hw_domain * hw_dom)467 static int arch_domain_mbm_alloc(u32 num_rmid, struct rdt_hw_domain *hw_dom)
468 {
469 size_t tsize;
470
471 if (is_mbm_total_enabled()) {
472 tsize = sizeof(*hw_dom->arch_mbm_total);
473 hw_dom->arch_mbm_total = kcalloc(num_rmid, tsize, GFP_KERNEL);
474 if (!hw_dom->arch_mbm_total)
475 return -ENOMEM;
476 }
477 if (is_mbm_local_enabled()) {
478 tsize = sizeof(*hw_dom->arch_mbm_local);
479 hw_dom->arch_mbm_local = kcalloc(num_rmid, tsize, GFP_KERNEL);
480 if (!hw_dom->arch_mbm_local) {
481 kfree(hw_dom->arch_mbm_total);
482 hw_dom->arch_mbm_total = NULL;
483 return -ENOMEM;
484 }
485 }
486
487 return 0;
488 }
489
490 /*
491 * domain_add_cpu - Add a cpu to a resource's domain list.
492 *
493 * If an existing domain in the resource r's domain list matches the cpu's
494 * resource id, add the cpu in the domain.
495 *
496 * Otherwise, a new domain is allocated and inserted into the right position
497 * in the domain list sorted by id in ascending order.
498 *
499 * The order in the domain list is visible to users when we print entries
500 * in the schemata file and schemata input is validated to have the same order
501 * as this list.
502 */
domain_add_cpu(int cpu,struct rdt_resource * r)503 static void domain_add_cpu(int cpu, struct rdt_resource *r)
504 {
505 int id = get_cpu_cacheinfo_id(cpu, r->cache_level);
506 struct list_head *add_pos = NULL;
507 struct rdt_hw_domain *hw_dom;
508 struct rdt_domain *d;
509 int err;
510
511 d = rdt_find_domain(r, id, &add_pos);
512 if (IS_ERR(d)) {
513 pr_warn("Couldn't find cache id for CPU %d\n", cpu);
514 return;
515 }
516
517 if (d) {
518 cpumask_set_cpu(cpu, &d->cpu_mask);
519 if (r->cache.arch_has_per_cpu_cfg)
520 rdt_domain_reconfigure_cdp(r);
521 return;
522 }
523
524 hw_dom = kzalloc_node(sizeof(*hw_dom), GFP_KERNEL, cpu_to_node(cpu));
525 if (!hw_dom)
526 return;
527
528 d = &hw_dom->d_resctrl;
529 d->id = id;
530 cpumask_set_cpu(cpu, &d->cpu_mask);
531
532 rdt_domain_reconfigure_cdp(r);
533
534 if (r->alloc_capable && domain_setup_ctrlval(r, d)) {
535 domain_free(hw_dom);
536 return;
537 }
538
539 if (r->mon_capable && arch_domain_mbm_alloc(r->num_rmid, hw_dom)) {
540 domain_free(hw_dom);
541 return;
542 }
543
544 list_add_tail(&d->list, add_pos);
545
546 err = resctrl_online_domain(r, d);
547 if (err) {
548 list_del(&d->list);
549 domain_free(hw_dom);
550 }
551 }
552
domain_remove_cpu(int cpu,struct rdt_resource * r)553 static void domain_remove_cpu(int cpu, struct rdt_resource *r)
554 {
555 int id = get_cpu_cacheinfo_id(cpu, r->cache_level);
556 struct rdt_hw_domain *hw_dom;
557 struct rdt_domain *d;
558
559 d = rdt_find_domain(r, id, NULL);
560 if (IS_ERR_OR_NULL(d)) {
561 pr_warn("Couldn't find cache id for CPU %d\n", cpu);
562 return;
563 }
564 hw_dom = resctrl_to_arch_dom(d);
565
566 cpumask_clear_cpu(cpu, &d->cpu_mask);
567 if (cpumask_empty(&d->cpu_mask)) {
568 resctrl_offline_domain(r, d);
569 list_del(&d->list);
570
571 /*
572 * rdt_domain "d" is going to be freed below, so clear
573 * its pointer from pseudo_lock_region struct.
574 */
575 if (d->plr)
576 d->plr->d = NULL;
577 domain_free(hw_dom);
578
579 return;
580 }
581
582 if (r == &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl) {
583 if (is_mbm_enabled() && cpu == d->mbm_work_cpu) {
584 cancel_delayed_work(&d->mbm_over);
585 mbm_setup_overflow_handler(d, 0);
586 }
587 if (is_llc_occupancy_enabled() && cpu == d->cqm_work_cpu &&
588 has_busy_rmid(r, d)) {
589 cancel_delayed_work(&d->cqm_limbo);
590 cqm_setup_limbo_handler(d, 0);
591 }
592 }
593 }
594
clear_closid_rmid(int cpu)595 static void clear_closid_rmid(int cpu)
596 {
597 struct resctrl_pqr_state *state = this_cpu_ptr(&pqr_state);
598
599 state->default_closid = 0;
600 state->default_rmid = 0;
601 state->cur_closid = 0;
602 state->cur_rmid = 0;
603 wrmsr(MSR_IA32_PQR_ASSOC, 0, 0);
604 }
605
resctrl_online_cpu(unsigned int cpu)606 static int resctrl_online_cpu(unsigned int cpu)
607 {
608 struct rdt_resource *r;
609
610 mutex_lock(&rdtgroup_mutex);
611 for_each_capable_rdt_resource(r)
612 domain_add_cpu(cpu, r);
613 /* The cpu is set in default rdtgroup after online. */
614 cpumask_set_cpu(cpu, &rdtgroup_default.cpu_mask);
615 clear_closid_rmid(cpu);
616 mutex_unlock(&rdtgroup_mutex);
617
618 return 0;
619 }
620
clear_childcpus(struct rdtgroup * r,unsigned int cpu)621 static void clear_childcpus(struct rdtgroup *r, unsigned int cpu)
622 {
623 struct rdtgroup *cr;
624
625 list_for_each_entry(cr, &r->mon.crdtgrp_list, mon.crdtgrp_list) {
626 if (cpumask_test_and_clear_cpu(cpu, &cr->cpu_mask)) {
627 break;
628 }
629 }
630 }
631
resctrl_offline_cpu(unsigned int cpu)632 static int resctrl_offline_cpu(unsigned int cpu)
633 {
634 struct rdtgroup *rdtgrp;
635 struct rdt_resource *r;
636
637 mutex_lock(&rdtgroup_mutex);
638 for_each_capable_rdt_resource(r)
639 domain_remove_cpu(cpu, r);
640 list_for_each_entry(rdtgrp, &rdt_all_groups, rdtgroup_list) {
641 if (cpumask_test_and_clear_cpu(cpu, &rdtgrp->cpu_mask)) {
642 clear_childcpus(rdtgrp, cpu);
643 break;
644 }
645 }
646 clear_closid_rmid(cpu);
647 mutex_unlock(&rdtgroup_mutex);
648
649 return 0;
650 }
651
652 /*
653 * Choose a width for the resource name and resource data based on the
654 * resource that has widest name and cbm.
655 */
rdt_init_padding(void)656 static __init void rdt_init_padding(void)
657 {
658 struct rdt_resource *r;
659
660 for_each_alloc_capable_rdt_resource(r) {
661 if (r->data_width > max_data_width)
662 max_data_width = r->data_width;
663 }
664 }
665
666 enum {
667 RDT_FLAG_CMT,
668 RDT_FLAG_MBM_TOTAL,
669 RDT_FLAG_MBM_LOCAL,
670 RDT_FLAG_L3_CAT,
671 RDT_FLAG_L3_CDP,
672 RDT_FLAG_L2_CAT,
673 RDT_FLAG_L2_CDP,
674 RDT_FLAG_MBA,
675 RDT_FLAG_SMBA,
676 RDT_FLAG_BMEC,
677 };
678
679 #define RDT_OPT(idx, n, f) \
680 [idx] = { \
681 .name = n, \
682 .flag = f \
683 }
684
685 struct rdt_options {
686 char *name;
687 int flag;
688 bool force_off, force_on;
689 };
690
691 static struct rdt_options rdt_options[] __initdata = {
692 RDT_OPT(RDT_FLAG_CMT, "cmt", X86_FEATURE_CQM_OCCUP_LLC),
693 RDT_OPT(RDT_FLAG_MBM_TOTAL, "mbmtotal", X86_FEATURE_CQM_MBM_TOTAL),
694 RDT_OPT(RDT_FLAG_MBM_LOCAL, "mbmlocal", X86_FEATURE_CQM_MBM_LOCAL),
695 RDT_OPT(RDT_FLAG_L3_CAT, "l3cat", X86_FEATURE_CAT_L3),
696 RDT_OPT(RDT_FLAG_L3_CDP, "l3cdp", X86_FEATURE_CDP_L3),
697 RDT_OPT(RDT_FLAG_L2_CAT, "l2cat", X86_FEATURE_CAT_L2),
698 RDT_OPT(RDT_FLAG_L2_CDP, "l2cdp", X86_FEATURE_CDP_L2),
699 RDT_OPT(RDT_FLAG_MBA, "mba", X86_FEATURE_MBA),
700 RDT_OPT(RDT_FLAG_SMBA, "smba", X86_FEATURE_SMBA),
701 RDT_OPT(RDT_FLAG_BMEC, "bmec", X86_FEATURE_BMEC),
702 };
703 #define NUM_RDT_OPTIONS ARRAY_SIZE(rdt_options)
704
set_rdt_options(char * str)705 static int __init set_rdt_options(char *str)
706 {
707 struct rdt_options *o;
708 bool force_off;
709 char *tok;
710
711 if (*str == '=')
712 str++;
713 while ((tok = strsep(&str, ",")) != NULL) {
714 force_off = *tok == '!';
715 if (force_off)
716 tok++;
717 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) {
718 if (strcmp(tok, o->name) == 0) {
719 if (force_off)
720 o->force_off = true;
721 else
722 o->force_on = true;
723 break;
724 }
725 }
726 }
727 return 1;
728 }
729 __setup("rdt", set_rdt_options);
730
rdt_cpu_has(int flag)731 bool __init rdt_cpu_has(int flag)
732 {
733 bool ret = boot_cpu_has(flag);
734 struct rdt_options *o;
735
736 if (!ret)
737 return ret;
738
739 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) {
740 if (flag == o->flag) {
741 if (o->force_off)
742 ret = false;
743 if (o->force_on)
744 ret = true;
745 break;
746 }
747 }
748 return ret;
749 }
750
get_mem_config(void)751 static __init bool get_mem_config(void)
752 {
753 struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_MBA];
754
755 if (!rdt_cpu_has(X86_FEATURE_MBA))
756 return false;
757
758 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
759 return __get_mem_config_intel(&hw_res->r_resctrl);
760 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
761 return __rdt_get_mem_config_amd(&hw_res->r_resctrl);
762
763 return false;
764 }
765
get_slow_mem_config(void)766 static __init bool get_slow_mem_config(void)
767 {
768 struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_SMBA];
769
770 if (!rdt_cpu_has(X86_FEATURE_SMBA))
771 return false;
772
773 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
774 return __rdt_get_mem_config_amd(&hw_res->r_resctrl);
775
776 return false;
777 }
778
get_rdt_alloc_resources(void)779 static __init bool get_rdt_alloc_resources(void)
780 {
781 struct rdt_resource *r;
782 bool ret = false;
783
784 if (rdt_alloc_capable)
785 return true;
786
787 if (!boot_cpu_has(X86_FEATURE_RDT_A))
788 return false;
789
790 if (rdt_cpu_has(X86_FEATURE_CAT_L3)) {
791 r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl;
792 rdt_get_cache_alloc_cfg(1, r);
793 if (rdt_cpu_has(X86_FEATURE_CDP_L3))
794 rdt_get_cdp_l3_config();
795 ret = true;
796 }
797 if (rdt_cpu_has(X86_FEATURE_CAT_L2)) {
798 /* CPUID 0x10.2 fields are same format at 0x10.1 */
799 r = &rdt_resources_all[RDT_RESOURCE_L2].r_resctrl;
800 rdt_get_cache_alloc_cfg(2, r);
801 if (rdt_cpu_has(X86_FEATURE_CDP_L2))
802 rdt_get_cdp_l2_config();
803 ret = true;
804 }
805
806 if (get_mem_config())
807 ret = true;
808
809 if (get_slow_mem_config())
810 ret = true;
811
812 return ret;
813 }
814
get_rdt_mon_resources(void)815 static __init bool get_rdt_mon_resources(void)
816 {
817 struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl;
818
819 if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC))
820 rdt_mon_features |= (1 << QOS_L3_OCCUP_EVENT_ID);
821 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL))
822 rdt_mon_features |= (1 << QOS_L3_MBM_TOTAL_EVENT_ID);
823 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL))
824 rdt_mon_features |= (1 << QOS_L3_MBM_LOCAL_EVENT_ID);
825
826 if (!rdt_mon_features)
827 return false;
828
829 return !rdt_get_mon_l3_config(r);
830 }
831
__check_quirks_intel(void)832 static __init void __check_quirks_intel(void)
833 {
834 switch (boot_cpu_data.x86_model) {
835 case INTEL_FAM6_HASWELL_X:
836 if (!rdt_options[RDT_FLAG_L3_CAT].force_off)
837 cache_alloc_hsw_probe();
838 break;
839 case INTEL_FAM6_SKYLAKE_X:
840 if (boot_cpu_data.x86_stepping <= 4)
841 set_rdt_options("!cmt,!mbmtotal,!mbmlocal,!l3cat");
842 else
843 set_rdt_options("!l3cat");
844 fallthrough;
845 case INTEL_FAM6_BROADWELL_X:
846 intel_rdt_mbm_apply_quirk();
847 break;
848 }
849 }
850
check_quirks(void)851 static __init void check_quirks(void)
852 {
853 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
854 __check_quirks_intel();
855 }
856
get_rdt_resources(void)857 static __init bool get_rdt_resources(void)
858 {
859 rdt_alloc_capable = get_rdt_alloc_resources();
860 rdt_mon_capable = get_rdt_mon_resources();
861
862 return (rdt_mon_capable || rdt_alloc_capable);
863 }
864
rdt_init_res_defs_intel(void)865 static __init void rdt_init_res_defs_intel(void)
866 {
867 struct rdt_hw_resource *hw_res;
868 struct rdt_resource *r;
869
870 for_each_rdt_resource(r) {
871 hw_res = resctrl_to_arch_res(r);
872
873 if (r->rid == RDT_RESOURCE_L3 ||
874 r->rid == RDT_RESOURCE_L2) {
875 r->cache.arch_has_sparse_bitmaps = false;
876 r->cache.arch_has_per_cpu_cfg = false;
877 r->cache.min_cbm_bits = 1;
878 } else if (r->rid == RDT_RESOURCE_MBA) {
879 hw_res->msr_base = MSR_IA32_MBA_THRTL_BASE;
880 hw_res->msr_update = mba_wrmsr_intel;
881 }
882 }
883 }
884
rdt_init_res_defs_amd(void)885 static __init void rdt_init_res_defs_amd(void)
886 {
887 struct rdt_hw_resource *hw_res;
888 struct rdt_resource *r;
889
890 for_each_rdt_resource(r) {
891 hw_res = resctrl_to_arch_res(r);
892
893 if (r->rid == RDT_RESOURCE_L3 ||
894 r->rid == RDT_RESOURCE_L2) {
895 r->cache.arch_has_sparse_bitmaps = true;
896 r->cache.arch_has_per_cpu_cfg = true;
897 r->cache.min_cbm_bits = 0;
898 } else if (r->rid == RDT_RESOURCE_MBA) {
899 hw_res->msr_base = MSR_IA32_MBA_BW_BASE;
900 hw_res->msr_update = mba_wrmsr_amd;
901 } else if (r->rid == RDT_RESOURCE_SMBA) {
902 hw_res->msr_base = MSR_IA32_SMBA_BW_BASE;
903 hw_res->msr_update = mba_wrmsr_amd;
904 }
905 }
906 }
907
rdt_init_res_defs(void)908 static __init void rdt_init_res_defs(void)
909 {
910 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
911 rdt_init_res_defs_intel();
912 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
913 rdt_init_res_defs_amd();
914 }
915
916 static enum cpuhp_state rdt_online;
917
918 /* Runs once on the BSP during boot. */
resctrl_cpu_detect(struct cpuinfo_x86 * c)919 void resctrl_cpu_detect(struct cpuinfo_x86 *c)
920 {
921 if (!cpu_has(c, X86_FEATURE_CQM_LLC)) {
922 c->x86_cache_max_rmid = -1;
923 c->x86_cache_occ_scale = -1;
924 c->x86_cache_mbm_width_offset = -1;
925 return;
926 }
927
928 /* will be overridden if occupancy monitoring exists */
929 c->x86_cache_max_rmid = cpuid_ebx(0xf);
930
931 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) ||
932 cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) ||
933 cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) {
934 u32 eax, ebx, ecx, edx;
935
936 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
937 cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx);
938
939 c->x86_cache_max_rmid = ecx;
940 c->x86_cache_occ_scale = ebx;
941 c->x86_cache_mbm_width_offset = eax & 0xff;
942
943 if (c->x86_vendor == X86_VENDOR_AMD && !c->x86_cache_mbm_width_offset)
944 c->x86_cache_mbm_width_offset = MBM_CNTR_WIDTH_OFFSET_AMD;
945 }
946 }
947
resctrl_late_init(void)948 static int __init resctrl_late_init(void)
949 {
950 struct rdt_resource *r;
951 int state, ret;
952
953 /*
954 * Initialize functions(or definitions) that are different
955 * between vendors here.
956 */
957 rdt_init_res_defs();
958
959 check_quirks();
960
961 if (!get_rdt_resources())
962 return -ENODEV;
963
964 rdt_init_padding();
965
966 state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
967 "x86/resctrl/cat:online:",
968 resctrl_online_cpu, resctrl_offline_cpu);
969 if (state < 0)
970 return state;
971
972 ret = rdtgroup_init();
973 if (ret) {
974 cpuhp_remove_state(state);
975 return ret;
976 }
977 rdt_online = state;
978
979 for_each_alloc_capable_rdt_resource(r)
980 pr_info("%s allocation detected\n", r->name);
981
982 for_each_mon_capable_rdt_resource(r)
983 pr_info("%s monitoring detected\n", r->name);
984
985 return 0;
986 }
987
988 late_initcall(resctrl_late_init);
989
resctrl_exit(void)990 static void __exit resctrl_exit(void)
991 {
992 cpuhp_remove_state(rdt_online);
993 rdtgroup_exit();
994 }
995
996 __exitcall(resctrl_exit);
997