1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef __AMDGPU_DPM_H__
24 #define __AMDGPU_DPM_H__
25 
26 /* Argument for PPSMC_MSG_GpuChangeState */
27 enum gfx_change_state {
28 	sGpuChangeState_D0Entry = 1,
29 	sGpuChangeState_D3Entry,
30 };
31 
32 enum amdgpu_int_thermal_type {
33 	THERMAL_TYPE_NONE,
34 	THERMAL_TYPE_EXTERNAL,
35 	THERMAL_TYPE_EXTERNAL_GPIO,
36 	THERMAL_TYPE_RV6XX,
37 	THERMAL_TYPE_RV770,
38 	THERMAL_TYPE_ADT7473_WITH_INTERNAL,
39 	THERMAL_TYPE_EVERGREEN,
40 	THERMAL_TYPE_SUMO,
41 	THERMAL_TYPE_NI,
42 	THERMAL_TYPE_SI,
43 	THERMAL_TYPE_EMC2103_WITH_INTERNAL,
44 	THERMAL_TYPE_CI,
45 	THERMAL_TYPE_KV,
46 };
47 
48 enum amdgpu_runpm_mode {
49 	AMDGPU_RUNPM_NONE,
50 	AMDGPU_RUNPM_PX,
51 	AMDGPU_RUNPM_BOCO,
52 	AMDGPU_RUNPM_BACO,
53 };
54 
55 struct amdgpu_ps {
56 	u32 caps; /* vbios flags */
57 	u32 class; /* vbios flags */
58 	u32 class2; /* vbios flags */
59 	/* UVD clocks */
60 	u32 vclk;
61 	u32 dclk;
62 	/* VCE clocks */
63 	u32 evclk;
64 	u32 ecclk;
65 	bool vce_active;
66 	enum amd_vce_level vce_level;
67 	/* asic priv */
68 	void *ps_priv;
69 };
70 
71 struct amdgpu_dpm_thermal {
72 	/* thermal interrupt work */
73 	struct work_struct work;
74 	/* low temperature threshold */
75 	int                min_temp;
76 	/* high temperature threshold */
77 	int                max_temp;
78 	/* edge max emergency(shutdown) temp */
79 	int                max_edge_emergency_temp;
80 	/* hotspot low temperature threshold */
81 	int                min_hotspot_temp;
82 	/* hotspot high temperature critical threshold */
83 	int                max_hotspot_crit_temp;
84 	/* hotspot max emergency(shutdown) temp */
85 	int                max_hotspot_emergency_temp;
86 	/* memory low temperature threshold */
87 	int                min_mem_temp;
88 	/* memory high temperature critical threshold */
89 	int                max_mem_crit_temp;
90 	/* memory max emergency(shutdown) temp */
91 	int                max_mem_emergency_temp;
92 	/* SWCTF threshold */
93 	int                sw_ctf_threshold;
94 	/* was last interrupt low to high or high to low */
95 	bool               high_to_low;
96 	/* interrupt source */
97 	struct amdgpu_irq_src	irq;
98 };
99 
100 struct amdgpu_clock_and_voltage_limits {
101 	u32 sclk;
102 	u32 mclk;
103 	u16 vddc;
104 	u16 vddci;
105 };
106 
107 struct amdgpu_clock_array {
108 	u32 count;
109 	u32 *values;
110 };
111 
112 struct amdgpu_clock_voltage_dependency_entry {
113 	u32 clk;
114 	u16 v;
115 };
116 
117 struct amdgpu_clock_voltage_dependency_table {
118 	u32 count;
119 	struct amdgpu_clock_voltage_dependency_entry *entries;
120 };
121 
122 union amdgpu_cac_leakage_entry {
123 	struct {
124 		u16 vddc;
125 		u32 leakage;
126 	};
127 	struct {
128 		u16 vddc1;
129 		u16 vddc2;
130 		u16 vddc3;
131 	};
132 };
133 
134 struct amdgpu_cac_leakage_table {
135 	u32 count;
136 	union amdgpu_cac_leakage_entry *entries;
137 };
138 
139 struct amdgpu_phase_shedding_limits_entry {
140 	u16 voltage;
141 	u32 sclk;
142 	u32 mclk;
143 };
144 
145 struct amdgpu_phase_shedding_limits_table {
146 	u32 count;
147 	struct amdgpu_phase_shedding_limits_entry *entries;
148 };
149 
150 struct amdgpu_uvd_clock_voltage_dependency_entry {
151 	u32 vclk;
152 	u32 dclk;
153 	u16 v;
154 };
155 
156 struct amdgpu_uvd_clock_voltage_dependency_table {
157 	u8 count;
158 	struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
159 };
160 
161 struct amdgpu_vce_clock_voltage_dependency_entry {
162 	u32 ecclk;
163 	u32 evclk;
164 	u16 v;
165 };
166 
167 struct amdgpu_vce_clock_voltage_dependency_table {
168 	u8 count;
169 	struct amdgpu_vce_clock_voltage_dependency_entry *entries;
170 };
171 
172 struct amdgpu_ppm_table {
173 	u8 ppm_design;
174 	u16 cpu_core_number;
175 	u32 platform_tdp;
176 	u32 small_ac_platform_tdp;
177 	u32 platform_tdc;
178 	u32 small_ac_platform_tdc;
179 	u32 apu_tdp;
180 	u32 dgpu_tdp;
181 	u32 dgpu_ulv_power;
182 	u32 tj_max;
183 };
184 
185 struct amdgpu_cac_tdp_table {
186 	u16 tdp;
187 	u16 configurable_tdp;
188 	u16 tdc;
189 	u16 battery_power_limit;
190 	u16 small_power_limit;
191 	u16 low_cac_leakage;
192 	u16 high_cac_leakage;
193 	u16 maximum_power_delivery_limit;
194 };
195 
196 struct amdgpu_dpm_dynamic_state {
197 	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
198 	struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
199 	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
200 	struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
201 	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
202 	struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
203 	struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
204 	struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
205 	struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
206 	struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
207 	struct amdgpu_clock_array valid_sclk_values;
208 	struct amdgpu_clock_array valid_mclk_values;
209 	struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
210 	struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
211 	u32 mclk_sclk_ratio;
212 	u32 sclk_mclk_delta;
213 	u16 vddc_vddci_delta;
214 	u16 min_vddc_for_pcie_gen2;
215 	struct amdgpu_cac_leakage_table cac_leakage_table;
216 	struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
217 	struct amdgpu_ppm_table *ppm_table;
218 	struct amdgpu_cac_tdp_table *cac_tdp_table;
219 };
220 
221 struct amdgpu_dpm_fan {
222 	u16 t_min;
223 	u16 t_med;
224 	u16 t_high;
225 	u16 pwm_min;
226 	u16 pwm_med;
227 	u16 pwm_high;
228 	u8 t_hyst;
229 	u32 cycle_delay;
230 	u16 t_max;
231 	u8 control_mode;
232 	u16 default_max_fan_pwm;
233 	u16 default_fan_output_sensitivity;
234 	u16 fan_output_sensitivity;
235 	bool ucode_fan_control;
236 };
237 
238 struct amdgpu_dpm {
239 	struct amdgpu_ps        *ps;
240 	/* number of valid power states */
241 	int                     num_ps;
242 	/* current power state that is active */
243 	struct amdgpu_ps        *current_ps;
244 	/* requested power state */
245 	struct amdgpu_ps        *requested_ps;
246 	/* boot up power state */
247 	struct amdgpu_ps        *boot_ps;
248 	/* default uvd power state */
249 	struct amdgpu_ps        *uvd_ps;
250 	/* vce requirements */
251 	u32                  num_of_vce_states;
252 	struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
253 	enum amd_vce_level vce_level;
254 	enum amd_pm_state_type state;
255 	enum amd_pm_state_type user_state;
256 	enum amd_pm_state_type last_state;
257 	enum amd_pm_state_type last_user_state;
258 	u32                     platform_caps;
259 	u32                     voltage_response_time;
260 	u32                     backbias_response_time;
261 	void                    *priv;
262 	u32			new_active_crtcs;
263 	int			new_active_crtc_count;
264 	u32			current_active_crtcs;
265 	int			current_active_crtc_count;
266 	struct amdgpu_dpm_dynamic_state dyn_state;
267 	struct amdgpu_dpm_fan fan;
268 	u32 tdp_limit;
269 	u32 near_tdp_limit;
270 	u32 near_tdp_limit_adjusted;
271 	u32 sq_ramping_threshold;
272 	u32 cac_leakage;
273 	u16 tdp_od_limit;
274 	u32 tdp_adjustment;
275 	u16 load_line_slope;
276 	bool power_control;
277 	/* special states active */
278 	bool                    thermal_active;
279 	bool                    uvd_active;
280 	bool                    vce_active;
281 	/* thermal handling */
282 	struct amdgpu_dpm_thermal thermal;
283 	/* forced levels */
284 	enum amd_dpm_forced_level forced_level;
285 };
286 
287 enum ip_power_state {
288 	POWER_STATE_UNKNOWN,
289 	POWER_STATE_ON,
290 	POWER_STATE_OFF,
291 };
292 
293 /* Used to mask smu debug modes */
294 #define SMU_DEBUG_HALT_ON_ERROR		0x1
295 
296 #define MAX_SMU_I2C_BUSES       2
297 
298 struct amdgpu_smu_i2c_bus {
299 	struct i2c_adapter adapter;
300 	struct amdgpu_device *adev;
301 	int port;
302 	struct mutex mutex;
303 };
304 
305 struct config_table_setting
306 {
307 	uint16_t gfxclk_average_tau;
308 	uint16_t socclk_average_tau;
309 	uint16_t uclk_average_tau;
310 	uint16_t gfx_activity_average_tau;
311 	uint16_t mem_activity_average_tau;
312 	uint16_t socket_power_average_tau;
313 	uint16_t apu_socket_power_average_tau;
314 	uint16_t fclk_average_tau;
315 };
316 
317 struct amdgpu_pm {
318 	struct mutex		mutex;
319 	u32                     current_sclk;
320 	u32                     current_mclk;
321 	u32                     default_sclk;
322 	u32                     default_mclk;
323 	struct amdgpu_i2c_chan *i2c_bus;
324 	bool                    bus_locked;
325 	/* internal thermal controller on rv6xx+ */
326 	enum amdgpu_int_thermal_type int_thermal_type;
327 	struct device	        *int_hwmon_dev;
328 	/* fan control parameters */
329 	bool                    no_fan;
330 	u8                      fan_pulses_per_revolution;
331 	u8                      fan_min_rpm;
332 	u8                      fan_max_rpm;
333 	/* dpm */
334 	bool                    dpm_enabled;
335 	bool                    sysfs_initialized;
336 	struct amdgpu_dpm       dpm;
337 	const struct firmware	*fw;	/* SMC firmware */
338 	uint32_t                fw_version;
339 	uint32_t                pcie_gen_mask;
340 	uint32_t                pcie_mlw_mask;
341 	struct amd_pp_display_configuration pm_display_cfg;/* set by dc */
342 	uint32_t                smu_prv_buffer_size;
343 	struct amdgpu_bo        *smu_prv_buffer;
344 	bool ac_power;
345 	/* powerplay feature */
346 	uint32_t pp_feature;
347 
348 	/* Used for I2C access to various EEPROMs on relevant ASICs */
349 	struct amdgpu_smu_i2c_bus smu_i2c[MAX_SMU_I2C_BUSES];
350 	struct i2c_adapter     *ras_eeprom_i2c_bus;
351 	struct i2c_adapter     *fru_eeprom_i2c_bus;
352 	struct list_head	pm_attr_list;
353 
354 	atomic_t		pwr_state[AMD_IP_BLOCK_TYPE_NUM];
355 
356 	/*
357 	 * 0 = disabled (default), otherwise enable corresponding debug mode
358 	 */
359 	uint32_t		smu_debug_mask;
360 
361 	bool			pp_force_state_enabled;
362 
363 	struct mutex            stable_pstate_ctx_lock;
364 	struct amdgpu_ctx       *stable_pstate_ctx;
365 
366 	struct config_table_setting config_table;
367 	/* runtime mode */
368 	enum amdgpu_runpm_mode rpm_mode;
369 };
370 
371 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
372 			   void *data, uint32_t *size);
373 
374 int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit);
375 int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit);
376 
377 int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev,
378 				      uint32_t block_type, bool gate);
379 
380 extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low);
381 
382 extern int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low);
383 
384 int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev,
385 			       uint32_t pstate);
386 
387 int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev,
388 				    enum PP_SMC_POWER_PROFILE type,
389 				    bool en);
390 
391 int amdgpu_dpm_baco_reset(struct amdgpu_device *adev);
392 
393 int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev);
394 int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev);
395 
396 bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev);
397 
398 bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev);
399 int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev);
400 
401 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev,
402 			     enum pp_mp1_state mp1_state);
403 
404 int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev);
405 
406 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev);
407 
408 int amdgpu_dpm_baco_enter(struct amdgpu_device *adev);
409 
410 int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev,
411 			     uint32_t cstate);
412 
413 int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device *adev, bool en);
414 
415 int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev);
416 
417 int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev,
418 				      uint32_t msg_id);
419 
420 int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev,
421 				  bool acquire);
422 
423 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev);
424 
425 void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev);
426 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
427 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable);
428 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable);
429 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version);
430 int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable);
431 int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size);
432 int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size);
433 int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev,
434 				       enum pp_clock_type type,
435 				       uint32_t *min,
436 				       uint32_t *max);
437 int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev,
438 				        enum pp_clock_type type,
439 				        uint32_t min,
440 				        uint32_t max);
441 int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev);
442 int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event,
443 		       uint64_t event_arg);
444 int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value);
445 int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value);
446 int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value);
447 int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value);
448 uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev);
449 void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev,
450 				 enum gfx_change_state state);
451 int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev,
452 			    void *umc_ecc);
453 struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev,
454 						     uint32_t idx);
455 void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, enum amd_pm_state_type *state);
456 void amdgpu_dpm_set_power_state(struct amdgpu_device *adev,
457 				enum amd_pm_state_type state);
458 enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev);
459 int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev,
460 				       enum amd_dpm_forced_level level);
461 int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev,
462 				 struct pp_states_info *states);
463 int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev,
464 			      enum amd_pp_task task_id,
465 			      enum amd_pm_state_type *user_state);
466 int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table);
467 int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev,
468 				      uint32_t type,
469 				      long *input,
470 				      uint32_t size);
471 int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev,
472 				  uint32_t type,
473 				  long *input,
474 				  uint32_t size);
475 int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev,
476 				  enum pp_clock_type type,
477 				  char *buf);
478 int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev,
479 				  enum pp_clock_type type,
480 				  char *buf,
481 				  int *offset);
482 int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev,
483 				    uint64_t ppfeature_masks);
484 int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf);
485 int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev,
486 				 enum pp_clock_type type,
487 				 uint32_t mask);
488 int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev);
489 int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value);
490 int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev);
491 int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value);
492 int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev,
493 				      char *buf);
494 int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev,
495 				      long *input, uint32_t size);
496 int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table);
497 int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev,
498 				    uint32_t *fan_mode);
499 int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev,
500 				 uint32_t speed);
501 int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev,
502 				 uint32_t *speed);
503 int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev,
504 				 uint32_t *speed);
505 int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev,
506 				 uint32_t speed);
507 int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev,
508 				    uint32_t mode);
509 int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev,
510 			       uint32_t *limit,
511 			       enum pp_power_limit_level pp_limit_level,
512 			       enum pp_power_type power_type);
513 int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev,
514 			       uint32_t limit);
515 int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev);
516 int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
517 						       struct seq_file *m);
518 int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev,
519 				       void **addr,
520 				       size_t *size);
521 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev);
522 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev,
523 			    const char *buf,
524 			    size_t size);
525 int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev);
526 void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev);
527 int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev,
528 					    const struct amd_pp_display_configuration *input);
529 int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev,
530 				 enum amd_pp_clock_type type,
531 				 struct amd_pp_clocks *clocks);
532 int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev,
533 						struct amd_pp_simple_clock_info *clocks);
534 int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev,
535 					      enum amd_pp_clock_type type,
536 					      struct pp_clock_levels_with_latency *clocks);
537 int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev,
538 					      enum amd_pp_clock_type type,
539 					      struct pp_clock_levels_with_voltage *clocks);
540 int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev,
541 					       void *clock_ranges);
542 int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev,
543 					     struct pp_display_clock_request *clock);
544 int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev,
545 				  struct amd_pp_clock_info *clocks);
546 void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev);
547 int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev,
548 					uint32_t count);
549 int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev,
550 					  uint32_t clock);
551 void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev,
552 					     uint32_t clock);
553 void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev,
554 					  uint32_t clock);
555 int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev,
556 						   bool disable_memory_clock_switch);
557 int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev,
558 						struct pp_smu_nv_clock_table *max_clocks);
559 enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev,
560 						  unsigned int *clock_values_in_khz,
561 						  unsigned int *num_states);
562 int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev,
563 				   struct dpm_clocks *clock_table);
564 #endif
565