1 #ifndef CCISS_H
2 #define CCISS_H
3
4 #include <linux/genhd.h>
5 #include <linux/mutex.h>
6
7 #include "cciss_cmd.h"
8
9
10 #define NWD_SHIFT 4
11 #define MAX_PART (1 << NWD_SHIFT)
12
13 #define IO_OK 0
14 #define IO_ERROR 1
15 #define IO_NEEDS_RETRY 3
16
17 #define VENDOR_LEN 8
18 #define MODEL_LEN 16
19 #define REV_LEN 4
20
21 struct ctlr_info;
22 typedef struct ctlr_info ctlr_info_t;
23
24 struct access_method {
25 void (*submit_command)(ctlr_info_t *h, CommandList_struct *c);
26 void (*set_intr_mask)(ctlr_info_t *h, unsigned long val);
27 unsigned long (*fifo_full)(ctlr_info_t *h);
28 bool (*intr_pending)(ctlr_info_t *h);
29 unsigned long (*command_completed)(ctlr_info_t *h);
30 };
31 typedef struct _drive_info_struct
32 {
33 unsigned char LunID[8];
34 int usage_count;
35 struct request_queue *queue;
36 sector_t nr_blocks;
37 int block_size;
38 int heads;
39 int sectors;
40 int cylinders;
41 int raid_level; /* set to -1 to indicate that
42 * the drive is not in use/configured
43 */
44 int busy_configuring; /* This is set when a drive is being removed
45 * to prevent it from being opened or it's
46 * queue from being started.
47 */
48 struct device dev;
49 __u8 serial_no[16]; /* from inquiry page 0x83,
50 * not necc. null terminated.
51 */
52 char vendor[VENDOR_LEN + 1]; /* SCSI vendor string */
53 char model[MODEL_LEN + 1]; /* SCSI model string */
54 char rev[REV_LEN + 1]; /* SCSI revision string */
55 char device_initialized; /* indicates whether dev is initialized */
56 } drive_info_struct;
57
58 struct ctlr_info
59 {
60 int ctlr;
61 char devname[8];
62 char *product_name;
63 char firm_ver[4]; /* Firmware version */
64 struct pci_dev *pdev;
65 __u32 board_id;
66 void __iomem *vaddr;
67 unsigned long paddr;
68 int nr_cmds; /* Number of commands allowed on this controller */
69 CfgTable_struct __iomem *cfgtable;
70 int interrupts_enabled;
71 int major;
72 int max_commands;
73 int commands_outstanding;
74 int max_outstanding; /* Debug */
75 int num_luns;
76 int highest_lun;
77 int usage_count; /* number of opens all all minor devices */
78 /* Need space for temp sg list
79 * number of scatter/gathers supported
80 * number of scatter/gathers in chained block
81 */
82 struct scatterlist **scatter_list;
83 int maxsgentries;
84 int chainsize;
85 int max_cmd_sgentries;
86 SGDescriptor_struct **cmd_sg_list;
87
88 # define PERF_MODE_INT 0
89 # define DOORBELL_INT 1
90 # define SIMPLE_MODE_INT 2
91 # define MEMQ_MODE_INT 3
92 unsigned int intr[4];
93 unsigned int msix_vector;
94 unsigned int msi_vector;
95 int cciss_max_sectors;
96 BYTE cciss_read;
97 BYTE cciss_write;
98 BYTE cciss_read_capacity;
99
100 /* information about each logical volume */
101 drive_info_struct *drv[CISS_MAX_LUN];
102
103 struct access_method access;
104
105 /* queue and queue Info */
106 struct list_head reqQ;
107 struct list_head cmpQ;
108 unsigned int Qdepth;
109 unsigned int maxQsinceinit;
110 unsigned int maxSG;
111 spinlock_t lock;
112
113 /* pointers to command and error info pool */
114 CommandList_struct *cmd_pool;
115 dma_addr_t cmd_pool_dhandle;
116 ErrorInfo_struct *errinfo_pool;
117 dma_addr_t errinfo_pool_dhandle;
118 unsigned long *cmd_pool_bits;
119 int nr_allocs;
120 int nr_frees;
121 int busy_configuring;
122 int busy_initializing;
123 int busy_scanning;
124 struct mutex busy_shutting_down;
125
126 /* This element holds the zero based queue number of the last
127 * queue to be started. It is used for fairness.
128 */
129 int next_to_run;
130
131 /* Disk structures we need to pass back */
132 struct gendisk *gendisk[CISS_MAX_LUN];
133 #ifdef CONFIG_CISS_SCSI_TAPE
134 struct cciss_scsi_adapter_data_t *scsi_ctlr;
135 #endif
136 unsigned char alive;
137 struct list_head scan_list;
138 struct completion scan_wait;
139 struct device dev;
140 /*
141 * Performant mode tables.
142 */
143 u32 trans_support;
144 u32 trans_offset;
145 struct TransTable_struct *transtable;
146 unsigned long transMethod;
147
148 /*
149 * Performant mode completion buffer
150 */
151 u64 *reply_pool;
152 dma_addr_t reply_pool_dhandle;
153 u64 *reply_pool_head;
154 size_t reply_pool_size;
155 unsigned char reply_pool_wraparound;
156 u32 *blockFetchTable;
157 };
158
159 /* Defining the diffent access_methods
160 *
161 * Memory mapped FIFO interface (SMART 53xx cards)
162 */
163 #define SA5_DOORBELL 0x20
164 #define SA5_REQUEST_PORT_OFFSET 0x40
165 #define SA5_REPLY_INTR_MASK_OFFSET 0x34
166 #define SA5_REPLY_PORT_OFFSET 0x44
167 #define SA5_INTR_STATUS 0x30
168 #define SA5_SCRATCHPAD_OFFSET 0xB0
169
170 #define SA5_CTCFG_OFFSET 0xB4
171 #define SA5_CTMEM_OFFSET 0xB8
172
173 #define SA5_INTR_OFF 0x08
174 #define SA5B_INTR_OFF 0x04
175 #define SA5_INTR_PENDING 0x08
176 #define SA5B_INTR_PENDING 0x04
177 #define FIFO_EMPTY 0xffffffff
178 #define CCISS_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
179 /* Perf. mode flags */
180 #define SA5_PERF_INTR_PENDING 0x04
181 #define SA5_PERF_INTR_OFF 0x05
182 #define SA5_OUTDB_STATUS_PERF_BIT 0x01
183 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
184 #define SA5_OUTDB_CLEAR 0xA0
185 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
186 #define SA5_OUTDB_STATUS 0x9C
187
188
189 #define CISS_ERROR_BIT 0x02
190
191 #define CCISS_INTR_ON 1
192 #define CCISS_INTR_OFF 0
193
194
195 /* CCISS_BOARD_READY_WAIT_SECS is how long to wait for a board
196 * to become ready, in seconds, before giving up on it.
197 * CCISS_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
198 * between polling the board to see if it is ready, in
199 * milliseconds. CCISS_BOARD_READY_ITERATIONS is derived
200 * the above.
201 */
202 #define CCISS_BOARD_READY_WAIT_SECS (120)
203 #define CCISS_BOARD_NOT_READY_WAIT_SECS (10)
204 #define CCISS_BOARD_READY_POLL_INTERVAL_MSECS (100)
205 #define CCISS_BOARD_READY_ITERATIONS \
206 ((CCISS_BOARD_READY_WAIT_SECS * 1000) / \
207 CCISS_BOARD_READY_POLL_INTERVAL_MSECS)
208 #define CCISS_BOARD_NOT_READY_ITERATIONS \
209 ((CCISS_BOARD_NOT_READY_WAIT_SECS * 1000) / \
210 CCISS_BOARD_READY_POLL_INTERVAL_MSECS)
211 #define CCISS_POST_RESET_PAUSE_MSECS (3000)
212 #define CCISS_POST_RESET_NOOP_INTERVAL_MSECS (1000)
213 #define CCISS_POST_RESET_NOOP_RETRIES (12)
214
215 /*
216 Send the command to the hardware
217 */
SA5_submit_command(ctlr_info_t * h,CommandList_struct * c)218 static void SA5_submit_command( ctlr_info_t *h, CommandList_struct *c)
219 {
220 #ifdef CCISS_DEBUG
221 printk(KERN_WARNING "cciss%d: Sending %08x - down to controller\n",
222 h->ctlr, c->busaddr);
223 #endif /* CCISS_DEBUG */
224 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
225 readl(h->vaddr + SA5_REQUEST_PORT_OFFSET);
226 h->commands_outstanding++;
227 if ( h->commands_outstanding > h->max_outstanding)
228 h->max_outstanding = h->commands_outstanding;
229 }
230
231 /*
232 * This card is the opposite of the other cards.
233 * 0 turns interrupts on...
234 * 0x08 turns them off...
235 */
SA5_intr_mask(ctlr_info_t * h,unsigned long val)236 static void SA5_intr_mask(ctlr_info_t *h, unsigned long val)
237 {
238 if (val)
239 { /* Turn interrupts on */
240 h->interrupts_enabled = 1;
241 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
242 } else /* Turn them off */
243 {
244 h->interrupts_enabled = 0;
245 writel( SA5_INTR_OFF,
246 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
247 }
248 }
249 /*
250 * This card is the opposite of the other cards.
251 * 0 turns interrupts on...
252 * 0x04 turns them off...
253 */
SA5B_intr_mask(ctlr_info_t * h,unsigned long val)254 static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val)
255 {
256 if (val)
257 { /* Turn interrupts on */
258 h->interrupts_enabled = 1;
259 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
260 } else /* Turn them off */
261 {
262 h->interrupts_enabled = 0;
263 writel( SA5B_INTR_OFF,
264 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
265 }
266 }
267
268 /* Performant mode intr_mask */
SA5_performant_intr_mask(ctlr_info_t * h,unsigned long val)269 static void SA5_performant_intr_mask(ctlr_info_t *h, unsigned long val)
270 {
271 if (val) { /* turn on interrupts */
272 h->interrupts_enabled = 1;
273 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
274 } else {
275 h->interrupts_enabled = 0;
276 writel(SA5_PERF_INTR_OFF,
277 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
278 }
279 }
280
281 /*
282 * Returns true if fifo is full.
283 *
284 */
SA5_fifo_full(ctlr_info_t * h)285 static unsigned long SA5_fifo_full(ctlr_info_t *h)
286 {
287 if( h->commands_outstanding >= h->max_commands)
288 return(1);
289 else
290 return(0);
291
292 }
293 /*
294 * returns value read from hardware.
295 * returns FIFO_EMPTY if there is nothing to read
296 */
SA5_completed(ctlr_info_t * h)297 static unsigned long SA5_completed(ctlr_info_t *h)
298 {
299 unsigned long register_value
300 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
301 if(register_value != FIFO_EMPTY)
302 {
303 h->commands_outstanding--;
304 #ifdef CCISS_DEBUG
305 printk("cciss: Read %lx back from board\n", register_value);
306 #endif /* CCISS_DEBUG */
307 }
308 #ifdef CCISS_DEBUG
309 else
310 {
311 printk("cciss: FIFO Empty read\n");
312 }
313 #endif
314 return ( register_value);
315
316 }
317
318 /* Performant mode command completed */
SA5_performant_completed(ctlr_info_t * h)319 static unsigned long SA5_performant_completed(ctlr_info_t *h)
320 {
321 unsigned long register_value = FIFO_EMPTY;
322
323 /* flush the controller write of the reply queue by reading
324 * outbound doorbell status register.
325 */
326 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
327 /* msi auto clears the interrupt pending bit. */
328 if (!(h->msi_vector || h->msix_vector)) {
329 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
330 /* Do a read in order to flush the write to the controller
331 * (as per spec.)
332 */
333 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
334 }
335
336 if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
337 register_value = *(h->reply_pool_head);
338 (h->reply_pool_head)++;
339 h->commands_outstanding--;
340 } else {
341 register_value = FIFO_EMPTY;
342 }
343 /* Check for wraparound */
344 if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
345 h->reply_pool_head = h->reply_pool;
346 h->reply_pool_wraparound ^= 1;
347 }
348
349 return register_value;
350 }
351 /*
352 * Returns true if an interrupt is pending..
353 */
SA5_intr_pending(ctlr_info_t * h)354 static bool SA5_intr_pending(ctlr_info_t *h)
355 {
356 unsigned long register_value =
357 readl(h->vaddr + SA5_INTR_STATUS);
358 #ifdef CCISS_DEBUG
359 printk("cciss: intr_pending %lx\n", register_value);
360 #endif /* CCISS_DEBUG */
361 if( register_value & SA5_INTR_PENDING)
362 return 1;
363 return 0 ;
364 }
365
366 /*
367 * Returns true if an interrupt is pending..
368 */
SA5B_intr_pending(ctlr_info_t * h)369 static bool SA5B_intr_pending(ctlr_info_t *h)
370 {
371 unsigned long register_value =
372 readl(h->vaddr + SA5_INTR_STATUS);
373 #ifdef CCISS_DEBUG
374 printk("cciss: intr_pending %lx\n", register_value);
375 #endif /* CCISS_DEBUG */
376 if( register_value & SA5B_INTR_PENDING)
377 return 1;
378 return 0 ;
379 }
380
SA5_performant_intr_pending(ctlr_info_t * h)381 static bool SA5_performant_intr_pending(ctlr_info_t *h)
382 {
383 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
384
385 if (!register_value)
386 return false;
387
388 if (h->msi_vector || h->msix_vector)
389 return true;
390
391 /* Read outbound doorbell to flush */
392 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
393 return register_value & SA5_OUTDB_STATUS_PERF_BIT;
394 }
395
396 static struct access_method SA5_access = {
397 SA5_submit_command,
398 SA5_intr_mask,
399 SA5_fifo_full,
400 SA5_intr_pending,
401 SA5_completed,
402 };
403
404 static struct access_method SA5B_access = {
405 SA5_submit_command,
406 SA5B_intr_mask,
407 SA5_fifo_full,
408 SA5B_intr_pending,
409 SA5_completed,
410 };
411
412 static struct access_method SA5_performant_access = {
413 SA5_submit_command,
414 SA5_performant_intr_mask,
415 SA5_fifo_full,
416 SA5_performant_intr_pending,
417 SA5_performant_completed,
418 };
419
420 struct board_type {
421 __u32 board_id;
422 char *product_name;
423 struct access_method *access;
424 int nr_cmds; /* Max cmds this kind of ctlr can handle. */
425 };
426
427 #endif /* CCISS_H */
428