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Searched defs:mask1 (Results 1 – 25 of 58) sorted by relevance

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/linux-6.6.21/tools/testing/selftests/bpf/progs/
Dcpumask_success.c27 struct bpf_cpumask *mask1, *mask2, *mask3, *mask4; in create_cpumask_set() local
181 struct bpf_cpumask *mask1, *mask2; in BPF_PROG() local
245 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; in BPF_PROG() local
292 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; in BPF_PROG() local
334 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; in BPF_PROG() local
467 struct bpf_cpumask *mask1, *mask2; in BPF_PROG() local
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/
Ddc_helper.c110 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in set_reg_field_values()
225 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in generic_reg_update_ex()
253 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in generic_reg_set_ex()
289 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get2()
299 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get3()
311 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get4()
325 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get5()
341 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get6()
359 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get7()
379 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get8()
[all …]
/linux-6.6.21/drivers/gpu/drm/amd/display/dmub/src/
Ddmub_reg.c45 uint32_t mask1, uint32_t field_value1, in set_reg_field_values()
73 uint32_t mask1, uint32_t field_value1, ...) in dmub_reg_update()
90 uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) in dmub_reg_set()
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/irq/dcn21/
Dirq_service_dcn21.c215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/irq/dcn30/
Dirq_service_dcn30.c220 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
234 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/irq/dcn302/
Dirq_service_dcn302.c195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
213 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/irq/dcn31/
Dirq_service_dcn31.c208 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
222 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/irq/dcn314/
Dirq_service_dcn314.c210 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
224 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/irq/dcn32/
Dirq_service_dcn32.c209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
223 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/irq/dcn315/
Dirq_service_dcn315.c215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/linux-6.6.21/arch/parisc/kernel/
Dsys_parisc32.c28 compat_uint_t mask0, compat_uint_t mask1, compat_int_t dfd, in sys32_fanotify_mark()
/linux-6.6.21/drivers/net/hamradio/
Dhdlcdrv.c159 unsigned int mask1, mask2, mask3, mask4, mask5, mask6, word; in hdlcdrv_receiver() local
255 unsigned int mask1, mask2, mask3; in hdlcdrv_transmitter() local
/linux-6.6.21/arch/mips/sgi-ip27/
Dip27-nmi.c134 u64 mask0, mask1, pend0, pend1; in nmi_dump_hub_irq() local
/linux-6.6.21/lib/
Dcpumask_kunit.c26 #define EXPECT_FOR_EACH_CPU_OP_EQ(test, op, mask1, mask2) \ argument
/linux-6.6.21/include/linux/
Dcpumask.h332 #define for_each_cpu_and(cpu, mask1, mask2) \ argument
350 #define for_each_cpu_andnot(cpu, mask1, mask2) \ argument
367 #define for_each_cpu_or(cpu, mask1, mask2) \ argument
758 #define cpumask_any_and(mask1, mask2) cpumask_first_and((mask1), (mask2)) argument
/linux-6.6.21/arch/alpha/kernel/
Dsys_rawhide.c102 unsigned int mask, mask1, hose; in rawhide_mask_and_ack_irq() local
Dsys_titan.c69 unsigned long mask0, mask1, mask2, mask3, dummy; in titan_update_irq_hw() local
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/irq/dce120/
Dirq_service_dce120.c103 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/irq/dcn10/
Dirq_service_dcn10.c200 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/irq/dcn20/
Dirq_service_dcn20.c205 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/irq/dcn303/
Dirq_service_dcn303.c119 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/irq/dcn201/
Dirq_service_dcn201.c152 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
/linux-6.6.21/drivers/media/test-drivers/vidtv/
Dvidtv_pes.c88 u64 mask1; in vidtv_pes_write_pts_dts() local
/linux-6.6.21/drivers/soc/fsl/qe/
Dgpio.c241 u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1)); in qe_pin_set_dedicated() local
/linux-6.6.21/sound/soc/codecs/
Dcs35l56-shared.c335 unsigned int mask1, mask8, mask20; in cs35l56_irq() local

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