1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright (c) 2021, Microsoft Corporation. */
3 
4 #include <linux/module.h>
5 #include <linux/pci.h>
6 #include <linux/utsname.h>
7 #include <linux/version.h>
8 
9 #include "mana.h"
10 
mana_gd_r32(struct gdma_context * g,u64 offset)11 static u32 mana_gd_r32(struct gdma_context *g, u64 offset)
12 {
13 	return readl(g->bar0_va + offset);
14 }
15 
mana_gd_r64(struct gdma_context * g,u64 offset)16 static u64 mana_gd_r64(struct gdma_context *g, u64 offset)
17 {
18 	return readq(g->bar0_va + offset);
19 }
20 
mana_gd_init_pf_regs(struct pci_dev * pdev)21 static void mana_gd_init_pf_regs(struct pci_dev *pdev)
22 {
23 	struct gdma_context *gc = pci_get_drvdata(pdev);
24 	void __iomem *sriov_base_va;
25 	u64 sriov_base_off;
26 
27 	gc->db_page_size = mana_gd_r32(gc, GDMA_PF_REG_DB_PAGE_SIZE) & 0xFFFF;
28 	gc->db_page_base = gc->bar0_va +
29 				mana_gd_r64(gc, GDMA_PF_REG_DB_PAGE_OFF);
30 
31 	sriov_base_off = mana_gd_r64(gc, GDMA_SRIOV_REG_CFG_BASE_OFF);
32 
33 	sriov_base_va = gc->bar0_va + sriov_base_off;
34 	gc->shm_base = sriov_base_va +
35 			mana_gd_r64(gc, sriov_base_off + GDMA_PF_REG_SHM_OFF);
36 }
37 
mana_gd_init_vf_regs(struct pci_dev * pdev)38 static void mana_gd_init_vf_regs(struct pci_dev *pdev)
39 {
40 	struct gdma_context *gc = pci_get_drvdata(pdev);
41 
42 	gc->db_page_size = mana_gd_r32(gc, GDMA_REG_DB_PAGE_SIZE) & 0xFFFF;
43 
44 	gc->db_page_base = gc->bar0_va +
45 				mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET);
46 
47 	gc->shm_base = gc->bar0_va + mana_gd_r64(gc, GDMA_REG_SHM_OFFSET);
48 }
49 
mana_gd_init_registers(struct pci_dev * pdev)50 static void mana_gd_init_registers(struct pci_dev *pdev)
51 {
52 	struct gdma_context *gc = pci_get_drvdata(pdev);
53 
54 	if (gc->is_pf)
55 		mana_gd_init_pf_regs(pdev);
56 	else
57 		mana_gd_init_vf_regs(pdev);
58 }
59 
mana_gd_query_max_resources(struct pci_dev * pdev)60 static int mana_gd_query_max_resources(struct pci_dev *pdev)
61 {
62 	struct gdma_context *gc = pci_get_drvdata(pdev);
63 	struct gdma_query_max_resources_resp resp = {};
64 	struct gdma_general_req req = {};
65 	int err;
66 
67 	mana_gd_init_req_hdr(&req.hdr, GDMA_QUERY_MAX_RESOURCES,
68 			     sizeof(req), sizeof(resp));
69 
70 	err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
71 	if (err || resp.hdr.status) {
72 		dev_err(gc->dev, "Failed to query resource info: %d, 0x%x\n",
73 			err, resp.hdr.status);
74 		return err ? err : -EPROTO;
75 	}
76 
77 	if (gc->num_msix_usable > resp.max_msix)
78 		gc->num_msix_usable = resp.max_msix;
79 
80 	if (gc->num_msix_usable <= 1)
81 		return -ENOSPC;
82 
83 	gc->max_num_queues = num_online_cpus();
84 	if (gc->max_num_queues > MANA_MAX_NUM_QUEUES)
85 		gc->max_num_queues = MANA_MAX_NUM_QUEUES;
86 
87 	if (gc->max_num_queues > resp.max_eq)
88 		gc->max_num_queues = resp.max_eq;
89 
90 	if (gc->max_num_queues > resp.max_cq)
91 		gc->max_num_queues = resp.max_cq;
92 
93 	if (gc->max_num_queues > resp.max_sq)
94 		gc->max_num_queues = resp.max_sq;
95 
96 	if (gc->max_num_queues > resp.max_rq)
97 		gc->max_num_queues = resp.max_rq;
98 
99 	/* The Hardware Channel (HWC) used 1 MSI-X */
100 	if (gc->max_num_queues > gc->num_msix_usable - 1)
101 		gc->max_num_queues = gc->num_msix_usable - 1;
102 
103 	return 0;
104 }
105 
mana_gd_detect_devices(struct pci_dev * pdev)106 static int mana_gd_detect_devices(struct pci_dev *pdev)
107 {
108 	struct gdma_context *gc = pci_get_drvdata(pdev);
109 	struct gdma_list_devices_resp resp = {};
110 	struct gdma_general_req req = {};
111 	struct gdma_dev_id dev;
112 	u32 i, max_num_devs;
113 	u16 dev_type;
114 	int err;
115 
116 	mana_gd_init_req_hdr(&req.hdr, GDMA_LIST_DEVICES, sizeof(req),
117 			     sizeof(resp));
118 
119 	err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
120 	if (err || resp.hdr.status) {
121 		dev_err(gc->dev, "Failed to detect devices: %d, 0x%x\n", err,
122 			resp.hdr.status);
123 		return err ? err : -EPROTO;
124 	}
125 
126 	max_num_devs = min_t(u32, MAX_NUM_GDMA_DEVICES, resp.num_of_devs);
127 
128 	for (i = 0; i < max_num_devs; i++) {
129 		dev = resp.devs[i];
130 		dev_type = dev.type;
131 
132 		/* HWC is already detected in mana_hwc_create_channel(). */
133 		if (dev_type == GDMA_DEVICE_HWC)
134 			continue;
135 
136 		if (dev_type == GDMA_DEVICE_MANA) {
137 			gc->mana.gdma_context = gc;
138 			gc->mana.dev_id = dev;
139 		}
140 	}
141 
142 	return gc->mana.dev_id.type == 0 ? -ENODEV : 0;
143 }
144 
mana_gd_send_request(struct gdma_context * gc,u32 req_len,const void * req,u32 resp_len,void * resp)145 int mana_gd_send_request(struct gdma_context *gc, u32 req_len, const void *req,
146 			 u32 resp_len, void *resp)
147 {
148 	struct hw_channel_context *hwc = gc->hwc.driver_data;
149 
150 	return mana_hwc_send_request(hwc, req_len, req, resp_len, resp);
151 }
152 
mana_gd_alloc_memory(struct gdma_context * gc,unsigned int length,struct gdma_mem_info * gmi)153 int mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length,
154 			 struct gdma_mem_info *gmi)
155 {
156 	dma_addr_t dma_handle;
157 	void *buf;
158 
159 	if (length < PAGE_SIZE || !is_power_of_2(length))
160 		return -EINVAL;
161 
162 	gmi->dev = gc->dev;
163 	buf = dma_alloc_coherent(gmi->dev, length, &dma_handle, GFP_KERNEL);
164 	if (!buf)
165 		return -ENOMEM;
166 
167 	gmi->dma_handle = dma_handle;
168 	gmi->virt_addr = buf;
169 	gmi->length = length;
170 
171 	return 0;
172 }
173 
mana_gd_free_memory(struct gdma_mem_info * gmi)174 void mana_gd_free_memory(struct gdma_mem_info *gmi)
175 {
176 	dma_free_coherent(gmi->dev, gmi->length, gmi->virt_addr,
177 			  gmi->dma_handle);
178 }
179 
mana_gd_create_hw_eq(struct gdma_context * gc,struct gdma_queue * queue)180 static int mana_gd_create_hw_eq(struct gdma_context *gc,
181 				struct gdma_queue *queue)
182 {
183 	struct gdma_create_queue_resp resp = {};
184 	struct gdma_create_queue_req req = {};
185 	int err;
186 
187 	if (queue->type != GDMA_EQ)
188 		return -EINVAL;
189 
190 	mana_gd_init_req_hdr(&req.hdr, GDMA_CREATE_QUEUE,
191 			     sizeof(req), sizeof(resp));
192 
193 	req.hdr.dev_id = queue->gdma_dev->dev_id;
194 	req.type = queue->type;
195 	req.pdid = queue->gdma_dev->pdid;
196 	req.doolbell_id = queue->gdma_dev->doorbell;
197 	req.gdma_region = queue->mem_info.gdma_region;
198 	req.queue_size = queue->queue_size;
199 	req.log2_throttle_limit = queue->eq.log2_throttle_limit;
200 	req.eq_pci_msix_index = queue->eq.msix_index;
201 
202 	err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
203 	if (err || resp.hdr.status) {
204 		dev_err(gc->dev, "Failed to create queue: %d, 0x%x\n", err,
205 			resp.hdr.status);
206 		return err ? err : -EPROTO;
207 	}
208 
209 	queue->id = resp.queue_index;
210 	queue->eq.disable_needed = true;
211 	queue->mem_info.gdma_region = GDMA_INVALID_DMA_REGION;
212 	return 0;
213 }
214 
mana_gd_disable_queue(struct gdma_queue * queue)215 static int mana_gd_disable_queue(struct gdma_queue *queue)
216 {
217 	struct gdma_context *gc = queue->gdma_dev->gdma_context;
218 	struct gdma_disable_queue_req req = {};
219 	struct gdma_general_resp resp = {};
220 	int err;
221 
222 	WARN_ON(queue->type != GDMA_EQ);
223 
224 	mana_gd_init_req_hdr(&req.hdr, GDMA_DISABLE_QUEUE,
225 			     sizeof(req), sizeof(resp));
226 
227 	req.hdr.dev_id = queue->gdma_dev->dev_id;
228 	req.type = queue->type;
229 	req.queue_index =  queue->id;
230 	req.alloc_res_id_on_creation = 1;
231 
232 	err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
233 	if (err || resp.hdr.status) {
234 		dev_err(gc->dev, "Failed to disable queue: %d, 0x%x\n", err,
235 			resp.hdr.status);
236 		return err ? err : -EPROTO;
237 	}
238 
239 	return 0;
240 }
241 
242 #define DOORBELL_OFFSET_SQ	0x0
243 #define DOORBELL_OFFSET_RQ	0x400
244 #define DOORBELL_OFFSET_CQ	0x800
245 #define DOORBELL_OFFSET_EQ	0xFF8
246 
mana_gd_ring_doorbell(struct gdma_context * gc,u32 db_index,enum gdma_queue_type q_type,u32 qid,u32 tail_ptr,u8 num_req)247 static void mana_gd_ring_doorbell(struct gdma_context *gc, u32 db_index,
248 				  enum gdma_queue_type q_type, u32 qid,
249 				  u32 tail_ptr, u8 num_req)
250 {
251 	void __iomem *addr = gc->db_page_base + gc->db_page_size * db_index;
252 	union gdma_doorbell_entry e = {};
253 
254 	switch (q_type) {
255 	case GDMA_EQ:
256 		e.eq.id = qid;
257 		e.eq.tail_ptr = tail_ptr;
258 		e.eq.arm = num_req;
259 
260 		addr += DOORBELL_OFFSET_EQ;
261 		break;
262 
263 	case GDMA_CQ:
264 		e.cq.id = qid;
265 		e.cq.tail_ptr = tail_ptr;
266 		e.cq.arm = num_req;
267 
268 		addr += DOORBELL_OFFSET_CQ;
269 		break;
270 
271 	case GDMA_RQ:
272 		e.rq.id = qid;
273 		e.rq.tail_ptr = tail_ptr;
274 		e.rq.wqe_cnt = num_req;
275 
276 		addr += DOORBELL_OFFSET_RQ;
277 		break;
278 
279 	case GDMA_SQ:
280 		e.sq.id = qid;
281 		e.sq.tail_ptr = tail_ptr;
282 
283 		addr += DOORBELL_OFFSET_SQ;
284 		break;
285 
286 	default:
287 		WARN_ON(1);
288 		return;
289 	}
290 
291 	/* Ensure all writes are done before ring doorbell */
292 	wmb();
293 
294 	writeq(e.as_uint64, addr);
295 }
296 
mana_gd_wq_ring_doorbell(struct gdma_context * gc,struct gdma_queue * queue)297 void mana_gd_wq_ring_doorbell(struct gdma_context *gc, struct gdma_queue *queue)
298 {
299 	mana_gd_ring_doorbell(gc, queue->gdma_dev->doorbell, queue->type,
300 			      queue->id, queue->head * GDMA_WQE_BU_SIZE, 1);
301 }
302 
mana_gd_ring_cq(struct gdma_queue * cq,u8 arm_bit)303 void mana_gd_ring_cq(struct gdma_queue *cq, u8 arm_bit)
304 {
305 	struct gdma_context *gc = cq->gdma_dev->gdma_context;
306 
307 	u32 num_cqe = cq->queue_size / GDMA_CQE_SIZE;
308 
309 	u32 head = cq->head % (num_cqe << GDMA_CQE_OWNER_BITS);
310 
311 	mana_gd_ring_doorbell(gc, cq->gdma_dev->doorbell, cq->type, cq->id,
312 			      head, arm_bit);
313 }
314 
mana_gd_process_eqe(struct gdma_queue * eq)315 static void mana_gd_process_eqe(struct gdma_queue *eq)
316 {
317 	u32 head = eq->head % (eq->queue_size / GDMA_EQE_SIZE);
318 	struct gdma_context *gc = eq->gdma_dev->gdma_context;
319 	struct gdma_eqe *eq_eqe_ptr = eq->queue_mem_ptr;
320 	union gdma_eqe_info eqe_info;
321 	enum gdma_eqe_type type;
322 	struct gdma_event event;
323 	struct gdma_queue *cq;
324 	struct gdma_eqe *eqe;
325 	u32 cq_id;
326 
327 	eqe = &eq_eqe_ptr[head];
328 	eqe_info.as_uint32 = eqe->eqe_info;
329 	type = eqe_info.type;
330 
331 	switch (type) {
332 	case GDMA_EQE_COMPLETION:
333 		cq_id = eqe->details[0] & 0xFFFFFF;
334 		if (WARN_ON_ONCE(cq_id >= gc->max_num_cqs))
335 			break;
336 
337 		cq = gc->cq_table[cq_id];
338 		if (WARN_ON_ONCE(!cq || cq->type != GDMA_CQ || cq->id != cq_id))
339 			break;
340 
341 		if (cq->cq.callback)
342 			cq->cq.callback(cq->cq.context, cq);
343 
344 		break;
345 
346 	case GDMA_EQE_TEST_EVENT:
347 		gc->test_event_eq_id = eq->id;
348 		complete(&gc->eq_test_event);
349 		break;
350 
351 	case GDMA_EQE_HWC_INIT_EQ_ID_DB:
352 	case GDMA_EQE_HWC_INIT_DATA:
353 	case GDMA_EQE_HWC_INIT_DONE:
354 		if (!eq->eq.callback)
355 			break;
356 
357 		event.type = type;
358 		memcpy(&event.details, &eqe->details, GDMA_EVENT_DATA_SIZE);
359 		eq->eq.callback(eq->eq.context, eq, &event);
360 		break;
361 
362 	default:
363 		break;
364 	}
365 }
366 
mana_gd_process_eq_events(void * arg)367 static void mana_gd_process_eq_events(void *arg)
368 {
369 	u32 owner_bits, new_bits, old_bits;
370 	union gdma_eqe_info eqe_info;
371 	struct gdma_eqe *eq_eqe_ptr;
372 	struct gdma_queue *eq = arg;
373 	struct gdma_context *gc;
374 	struct gdma_eqe *eqe;
375 	u32 head, num_eqe;
376 	int i;
377 
378 	gc = eq->gdma_dev->gdma_context;
379 
380 	num_eqe = eq->queue_size / GDMA_EQE_SIZE;
381 	eq_eqe_ptr = eq->queue_mem_ptr;
382 
383 	/* Process up to 5 EQEs at a time, and update the HW head. */
384 	for (i = 0; i < 5; i++) {
385 		eqe = &eq_eqe_ptr[eq->head % num_eqe];
386 		eqe_info.as_uint32 = eqe->eqe_info;
387 		owner_bits = eqe_info.owner_bits;
388 
389 		old_bits = (eq->head / num_eqe - 1) & GDMA_EQE_OWNER_MASK;
390 		/* No more entries */
391 		if (owner_bits == old_bits)
392 			break;
393 
394 		new_bits = (eq->head / num_eqe) & GDMA_EQE_OWNER_MASK;
395 		if (owner_bits != new_bits) {
396 			dev_err(gc->dev, "EQ %d: overflow detected\n", eq->id);
397 			break;
398 		}
399 
400 		/* Per GDMA spec, rmb is necessary after checking owner_bits, before
401 		 * reading eqe.
402 		 */
403 		rmb();
404 
405 		mana_gd_process_eqe(eq);
406 
407 		eq->head++;
408 	}
409 
410 	head = eq->head % (num_eqe << GDMA_EQE_OWNER_BITS);
411 
412 	mana_gd_ring_doorbell(gc, eq->gdma_dev->doorbell, eq->type, eq->id,
413 			      head, SET_ARM_BIT);
414 }
415 
mana_gd_register_irq(struct gdma_queue * queue,const struct gdma_queue_spec * spec)416 static int mana_gd_register_irq(struct gdma_queue *queue,
417 				const struct gdma_queue_spec *spec)
418 {
419 	struct gdma_dev *gd = queue->gdma_dev;
420 	struct gdma_irq_context *gic;
421 	struct gdma_context *gc;
422 	struct gdma_resource *r;
423 	unsigned int msi_index;
424 	unsigned long flags;
425 	struct device *dev;
426 	int err = 0;
427 
428 	gc = gd->gdma_context;
429 	r = &gc->msix_resource;
430 	dev = gc->dev;
431 
432 	spin_lock_irqsave(&r->lock, flags);
433 
434 	msi_index = find_first_zero_bit(r->map, r->size);
435 	if (msi_index >= r->size || msi_index >= gc->num_msix_usable) {
436 		err = -ENOSPC;
437 	} else {
438 		bitmap_set(r->map, msi_index, 1);
439 		queue->eq.msix_index = msi_index;
440 	}
441 
442 	spin_unlock_irqrestore(&r->lock, flags);
443 
444 	if (err) {
445 		dev_err(dev, "Register IRQ err:%d, msi:%u rsize:%u, nMSI:%u",
446 			err, msi_index, r->size, gc->num_msix_usable);
447 
448 		return err;
449 	}
450 
451 	gic = &gc->irq_contexts[msi_index];
452 
453 	WARN_ON(gic->handler || gic->arg);
454 
455 	gic->arg = queue;
456 
457 	gic->handler = mana_gd_process_eq_events;
458 
459 	return 0;
460 }
461 
mana_gd_deregiser_irq(struct gdma_queue * queue)462 static void mana_gd_deregiser_irq(struct gdma_queue *queue)
463 {
464 	struct gdma_dev *gd = queue->gdma_dev;
465 	struct gdma_irq_context *gic;
466 	struct gdma_context *gc;
467 	struct gdma_resource *r;
468 	unsigned int msix_index;
469 	unsigned long flags;
470 
471 	gc = gd->gdma_context;
472 	r = &gc->msix_resource;
473 
474 	/* At most num_online_cpus() + 1 interrupts are used. */
475 	msix_index = queue->eq.msix_index;
476 	if (WARN_ON(msix_index >= gc->num_msix_usable))
477 		return;
478 
479 	gic = &gc->irq_contexts[msix_index];
480 	gic->handler = NULL;
481 	gic->arg = NULL;
482 
483 	spin_lock_irqsave(&r->lock, flags);
484 	bitmap_clear(r->map, msix_index, 1);
485 	spin_unlock_irqrestore(&r->lock, flags);
486 
487 	queue->eq.msix_index = INVALID_PCI_MSIX_INDEX;
488 }
489 
mana_gd_test_eq(struct gdma_context * gc,struct gdma_queue * eq)490 int mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq)
491 {
492 	struct gdma_generate_test_event_req req = {};
493 	struct gdma_general_resp resp = {};
494 	struct device *dev = gc->dev;
495 	int err;
496 
497 	mutex_lock(&gc->eq_test_event_mutex);
498 
499 	init_completion(&gc->eq_test_event);
500 	gc->test_event_eq_id = INVALID_QUEUE_ID;
501 
502 	mana_gd_init_req_hdr(&req.hdr, GDMA_GENERATE_TEST_EQE,
503 			     sizeof(req), sizeof(resp));
504 
505 	req.hdr.dev_id = eq->gdma_dev->dev_id;
506 	req.queue_index = eq->id;
507 
508 	err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
509 	if (err) {
510 		dev_err(dev, "test_eq failed: %d\n", err);
511 		goto out;
512 	}
513 
514 	err = -EPROTO;
515 
516 	if (resp.hdr.status) {
517 		dev_err(dev, "test_eq failed: 0x%x\n", resp.hdr.status);
518 		goto out;
519 	}
520 
521 	if (!wait_for_completion_timeout(&gc->eq_test_event, 30 * HZ)) {
522 		dev_err(dev, "test_eq timed out on queue %d\n", eq->id);
523 		goto out;
524 	}
525 
526 	if (eq->id != gc->test_event_eq_id) {
527 		dev_err(dev, "test_eq got an event on wrong queue %d (%d)\n",
528 			gc->test_event_eq_id, eq->id);
529 		goto out;
530 	}
531 
532 	err = 0;
533 out:
534 	mutex_unlock(&gc->eq_test_event_mutex);
535 	return err;
536 }
537 
mana_gd_destroy_eq(struct gdma_context * gc,bool flush_evenets,struct gdma_queue * queue)538 static void mana_gd_destroy_eq(struct gdma_context *gc, bool flush_evenets,
539 			       struct gdma_queue *queue)
540 {
541 	int err;
542 
543 	if (flush_evenets) {
544 		err = mana_gd_test_eq(gc, queue);
545 		if (err)
546 			dev_warn(gc->dev, "Failed to flush EQ: %d\n", err);
547 	}
548 
549 	mana_gd_deregiser_irq(queue);
550 
551 	if (queue->eq.disable_needed)
552 		mana_gd_disable_queue(queue);
553 }
554 
mana_gd_create_eq(struct gdma_dev * gd,const struct gdma_queue_spec * spec,bool create_hwq,struct gdma_queue * queue)555 static int mana_gd_create_eq(struct gdma_dev *gd,
556 			     const struct gdma_queue_spec *spec,
557 			     bool create_hwq, struct gdma_queue *queue)
558 {
559 	struct gdma_context *gc = gd->gdma_context;
560 	struct device *dev = gc->dev;
561 	u32 log2_num_entries;
562 	int err;
563 
564 	queue->eq.msix_index = INVALID_PCI_MSIX_INDEX;
565 
566 	log2_num_entries = ilog2(queue->queue_size / GDMA_EQE_SIZE);
567 
568 	if (spec->eq.log2_throttle_limit > log2_num_entries) {
569 		dev_err(dev, "EQ throttling limit (%lu) > maximum EQE (%u)\n",
570 			spec->eq.log2_throttle_limit, log2_num_entries);
571 		return -EINVAL;
572 	}
573 
574 	err = mana_gd_register_irq(queue, spec);
575 	if (err) {
576 		dev_err(dev, "Failed to register irq: %d\n", err);
577 		return err;
578 	}
579 
580 	queue->eq.callback = spec->eq.callback;
581 	queue->eq.context = spec->eq.context;
582 	queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries);
583 	queue->eq.log2_throttle_limit = spec->eq.log2_throttle_limit ?: 1;
584 
585 	if (create_hwq) {
586 		err = mana_gd_create_hw_eq(gc, queue);
587 		if (err)
588 			goto out;
589 
590 		err = mana_gd_test_eq(gc, queue);
591 		if (err)
592 			goto out;
593 	}
594 
595 	return 0;
596 out:
597 	dev_err(dev, "Failed to create EQ: %d\n", err);
598 	mana_gd_destroy_eq(gc, false, queue);
599 	return err;
600 }
601 
mana_gd_create_cq(const struct gdma_queue_spec * spec,struct gdma_queue * queue)602 static void mana_gd_create_cq(const struct gdma_queue_spec *spec,
603 			      struct gdma_queue *queue)
604 {
605 	u32 log2_num_entries = ilog2(spec->queue_size / GDMA_CQE_SIZE);
606 
607 	queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries);
608 	queue->cq.parent = spec->cq.parent_eq;
609 	queue->cq.context = spec->cq.context;
610 	queue->cq.callback = spec->cq.callback;
611 }
612 
mana_gd_destroy_cq(struct gdma_context * gc,struct gdma_queue * queue)613 static void mana_gd_destroy_cq(struct gdma_context *gc,
614 			       struct gdma_queue *queue)
615 {
616 	u32 id = queue->id;
617 
618 	if (id >= gc->max_num_cqs)
619 		return;
620 
621 	if (!gc->cq_table[id])
622 		return;
623 
624 	gc->cq_table[id] = NULL;
625 }
626 
mana_gd_create_hwc_queue(struct gdma_dev * gd,const struct gdma_queue_spec * spec,struct gdma_queue ** queue_ptr)627 int mana_gd_create_hwc_queue(struct gdma_dev *gd,
628 			     const struct gdma_queue_spec *spec,
629 			     struct gdma_queue **queue_ptr)
630 {
631 	struct gdma_context *gc = gd->gdma_context;
632 	struct gdma_mem_info *gmi;
633 	struct gdma_queue *queue;
634 	int err;
635 
636 	queue = kzalloc(sizeof(*queue), GFP_KERNEL);
637 	if (!queue)
638 		return -ENOMEM;
639 
640 	gmi = &queue->mem_info;
641 	err = mana_gd_alloc_memory(gc, spec->queue_size, gmi);
642 	if (err)
643 		goto free_q;
644 
645 	queue->head = 0;
646 	queue->tail = 0;
647 	queue->queue_mem_ptr = gmi->virt_addr;
648 	queue->queue_size = spec->queue_size;
649 	queue->monitor_avl_buf = spec->monitor_avl_buf;
650 	queue->type = spec->type;
651 	queue->gdma_dev = gd;
652 
653 	if (spec->type == GDMA_EQ)
654 		err = mana_gd_create_eq(gd, spec, false, queue);
655 	else if (spec->type == GDMA_CQ)
656 		mana_gd_create_cq(spec, queue);
657 
658 	if (err)
659 		goto out;
660 
661 	*queue_ptr = queue;
662 	return 0;
663 out:
664 	mana_gd_free_memory(gmi);
665 free_q:
666 	kfree(queue);
667 	return err;
668 }
669 
mana_gd_destroy_dma_region(struct gdma_context * gc,u64 gdma_region)670 static void mana_gd_destroy_dma_region(struct gdma_context *gc, u64 gdma_region)
671 {
672 	struct gdma_destroy_dma_region_req req = {};
673 	struct gdma_general_resp resp = {};
674 	int err;
675 
676 	if (gdma_region == GDMA_INVALID_DMA_REGION)
677 		return;
678 
679 	mana_gd_init_req_hdr(&req.hdr, GDMA_DESTROY_DMA_REGION, sizeof(req),
680 			     sizeof(resp));
681 	req.gdma_region = gdma_region;
682 
683 	err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
684 	if (err || resp.hdr.status)
685 		dev_err(gc->dev, "Failed to destroy DMA region: %d, 0x%x\n",
686 			err, resp.hdr.status);
687 }
688 
mana_gd_create_dma_region(struct gdma_dev * gd,struct gdma_mem_info * gmi)689 static int mana_gd_create_dma_region(struct gdma_dev *gd,
690 				     struct gdma_mem_info *gmi)
691 {
692 	unsigned int num_page = gmi->length / PAGE_SIZE;
693 	struct gdma_create_dma_region_req *req = NULL;
694 	struct gdma_create_dma_region_resp resp = {};
695 	struct gdma_context *gc = gd->gdma_context;
696 	struct hw_channel_context *hwc;
697 	u32 length = gmi->length;
698 	size_t req_msg_size;
699 	int err;
700 	int i;
701 
702 	if (length < PAGE_SIZE || !is_power_of_2(length))
703 		return -EINVAL;
704 
705 	if (offset_in_page(gmi->virt_addr) != 0)
706 		return -EINVAL;
707 
708 	hwc = gc->hwc.driver_data;
709 	req_msg_size = struct_size(req, page_addr_list, num_page);
710 	if (req_msg_size > hwc->max_req_msg_size)
711 		return -EINVAL;
712 
713 	req = kzalloc(req_msg_size, GFP_KERNEL);
714 	if (!req)
715 		return -ENOMEM;
716 
717 	mana_gd_init_req_hdr(&req->hdr, GDMA_CREATE_DMA_REGION,
718 			     req_msg_size, sizeof(resp));
719 	req->length = length;
720 	req->offset_in_page = 0;
721 	req->gdma_page_type = GDMA_PAGE_TYPE_4K;
722 	req->page_count = num_page;
723 	req->page_addr_list_len = num_page;
724 
725 	for (i = 0; i < num_page; i++)
726 		req->page_addr_list[i] = gmi->dma_handle +  i * PAGE_SIZE;
727 
728 	err = mana_gd_send_request(gc, req_msg_size, req, sizeof(resp), &resp);
729 	if (err)
730 		goto out;
731 
732 	if (resp.hdr.status || resp.gdma_region == GDMA_INVALID_DMA_REGION) {
733 		dev_err(gc->dev, "Failed to create DMA region: 0x%x\n",
734 			resp.hdr.status);
735 		err = -EPROTO;
736 		goto out;
737 	}
738 
739 	gmi->gdma_region = resp.gdma_region;
740 out:
741 	kfree(req);
742 	return err;
743 }
744 
mana_gd_create_mana_eq(struct gdma_dev * gd,const struct gdma_queue_spec * spec,struct gdma_queue ** queue_ptr)745 int mana_gd_create_mana_eq(struct gdma_dev *gd,
746 			   const struct gdma_queue_spec *spec,
747 			   struct gdma_queue **queue_ptr)
748 {
749 	struct gdma_context *gc = gd->gdma_context;
750 	struct gdma_mem_info *gmi;
751 	struct gdma_queue *queue;
752 	int err;
753 
754 	if (spec->type != GDMA_EQ)
755 		return -EINVAL;
756 
757 	queue = kzalloc(sizeof(*queue), GFP_KERNEL);
758 	if (!queue)
759 		return -ENOMEM;
760 
761 	gmi = &queue->mem_info;
762 	err = mana_gd_alloc_memory(gc, spec->queue_size, gmi);
763 	if (err)
764 		goto free_q;
765 
766 	err = mana_gd_create_dma_region(gd, gmi);
767 	if (err)
768 		goto out;
769 
770 	queue->head = 0;
771 	queue->tail = 0;
772 	queue->queue_mem_ptr = gmi->virt_addr;
773 	queue->queue_size = spec->queue_size;
774 	queue->monitor_avl_buf = spec->monitor_avl_buf;
775 	queue->type = spec->type;
776 	queue->gdma_dev = gd;
777 
778 	err = mana_gd_create_eq(gd, spec, true, queue);
779 	if (err)
780 		goto out;
781 
782 	*queue_ptr = queue;
783 	return 0;
784 out:
785 	mana_gd_free_memory(gmi);
786 free_q:
787 	kfree(queue);
788 	return err;
789 }
790 
mana_gd_create_mana_wq_cq(struct gdma_dev * gd,const struct gdma_queue_spec * spec,struct gdma_queue ** queue_ptr)791 int mana_gd_create_mana_wq_cq(struct gdma_dev *gd,
792 			      const struct gdma_queue_spec *spec,
793 			      struct gdma_queue **queue_ptr)
794 {
795 	struct gdma_context *gc = gd->gdma_context;
796 	struct gdma_mem_info *gmi;
797 	struct gdma_queue *queue;
798 	int err;
799 
800 	if (spec->type != GDMA_CQ && spec->type != GDMA_SQ &&
801 	    spec->type != GDMA_RQ)
802 		return -EINVAL;
803 
804 	queue = kzalloc(sizeof(*queue), GFP_KERNEL);
805 	if (!queue)
806 		return -ENOMEM;
807 
808 	gmi = &queue->mem_info;
809 	err = mana_gd_alloc_memory(gc, spec->queue_size, gmi);
810 	if (err)
811 		goto free_q;
812 
813 	err = mana_gd_create_dma_region(gd, gmi);
814 	if (err)
815 		goto out;
816 
817 	queue->head = 0;
818 	queue->tail = 0;
819 	queue->queue_mem_ptr = gmi->virt_addr;
820 	queue->queue_size = spec->queue_size;
821 	queue->monitor_avl_buf = spec->monitor_avl_buf;
822 	queue->type = spec->type;
823 	queue->gdma_dev = gd;
824 
825 	if (spec->type == GDMA_CQ)
826 		mana_gd_create_cq(spec, queue);
827 
828 	*queue_ptr = queue;
829 	return 0;
830 out:
831 	mana_gd_free_memory(gmi);
832 free_q:
833 	kfree(queue);
834 	return err;
835 }
836 
mana_gd_destroy_queue(struct gdma_context * gc,struct gdma_queue * queue)837 void mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue)
838 {
839 	struct gdma_mem_info *gmi = &queue->mem_info;
840 
841 	switch (queue->type) {
842 	case GDMA_EQ:
843 		mana_gd_destroy_eq(gc, queue->eq.disable_needed, queue);
844 		break;
845 
846 	case GDMA_CQ:
847 		mana_gd_destroy_cq(gc, queue);
848 		break;
849 
850 	case GDMA_RQ:
851 		break;
852 
853 	case GDMA_SQ:
854 		break;
855 
856 	default:
857 		dev_err(gc->dev, "Can't destroy unknown queue: type=%d\n",
858 			queue->type);
859 		return;
860 	}
861 
862 	mana_gd_destroy_dma_region(gc, gmi->gdma_region);
863 	mana_gd_free_memory(gmi);
864 	kfree(queue);
865 }
866 
mana_gd_verify_vf_version(struct pci_dev * pdev)867 int mana_gd_verify_vf_version(struct pci_dev *pdev)
868 {
869 	struct gdma_context *gc = pci_get_drvdata(pdev);
870 	struct gdma_verify_ver_resp resp = {};
871 	struct gdma_verify_ver_req req = {};
872 	int err;
873 
874 	mana_gd_init_req_hdr(&req.hdr, GDMA_VERIFY_VF_DRIVER_VERSION,
875 			     sizeof(req), sizeof(resp));
876 
877 	req.protocol_ver_min = GDMA_PROTOCOL_FIRST;
878 	req.protocol_ver_max = GDMA_PROTOCOL_LAST;
879 
880 	req.gd_drv_cap_flags1 = GDMA_DRV_CAP_FLAGS1;
881 	req.gd_drv_cap_flags2 = GDMA_DRV_CAP_FLAGS2;
882 	req.gd_drv_cap_flags3 = GDMA_DRV_CAP_FLAGS3;
883 	req.gd_drv_cap_flags4 = GDMA_DRV_CAP_FLAGS4;
884 
885 	req.drv_ver = 0;	/* Unused*/
886 	req.os_type = 0x10;	/* Linux */
887 	req.os_ver_major = LINUX_VERSION_MAJOR;
888 	req.os_ver_minor = LINUX_VERSION_PATCHLEVEL;
889 	req.os_ver_build = LINUX_VERSION_SUBLEVEL;
890 	strscpy(req.os_ver_str1, utsname()->sysname, sizeof(req.os_ver_str1));
891 	strscpy(req.os_ver_str2, utsname()->release, sizeof(req.os_ver_str2));
892 	strscpy(req.os_ver_str3, utsname()->version, sizeof(req.os_ver_str3));
893 
894 	err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
895 	if (err || resp.hdr.status) {
896 		dev_err(gc->dev, "VfVerifyVersionOutput: %d, status=0x%x\n",
897 			err, resp.hdr.status);
898 		return err ? err : -EPROTO;
899 	}
900 
901 	return 0;
902 }
903 
mana_gd_register_device(struct gdma_dev * gd)904 int mana_gd_register_device(struct gdma_dev *gd)
905 {
906 	struct gdma_context *gc = gd->gdma_context;
907 	struct gdma_register_device_resp resp = {};
908 	struct gdma_general_req req = {};
909 	int err;
910 
911 	gd->pdid = INVALID_PDID;
912 	gd->doorbell = INVALID_DOORBELL;
913 	gd->gpa_mkey = INVALID_MEM_KEY;
914 
915 	mana_gd_init_req_hdr(&req.hdr, GDMA_REGISTER_DEVICE, sizeof(req),
916 			     sizeof(resp));
917 
918 	req.hdr.dev_id = gd->dev_id;
919 
920 	err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
921 	if (err || resp.hdr.status) {
922 		dev_err(gc->dev, "gdma_register_device_resp failed: %d, 0x%x\n",
923 			err, resp.hdr.status);
924 		return err ? err : -EPROTO;
925 	}
926 
927 	gd->pdid = resp.pdid;
928 	gd->gpa_mkey = resp.gpa_mkey;
929 	gd->doorbell = resp.db_id;
930 
931 	return 0;
932 }
933 
mana_gd_deregister_device(struct gdma_dev * gd)934 int mana_gd_deregister_device(struct gdma_dev *gd)
935 {
936 	struct gdma_context *gc = gd->gdma_context;
937 	struct gdma_general_resp resp = {};
938 	struct gdma_general_req req = {};
939 	int err;
940 
941 	if (gd->pdid == INVALID_PDID)
942 		return -EINVAL;
943 
944 	mana_gd_init_req_hdr(&req.hdr, GDMA_DEREGISTER_DEVICE, sizeof(req),
945 			     sizeof(resp));
946 
947 	req.hdr.dev_id = gd->dev_id;
948 
949 	err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
950 	if (err || resp.hdr.status) {
951 		dev_err(gc->dev, "Failed to deregister device: %d, 0x%x\n",
952 			err, resp.hdr.status);
953 		if (!err)
954 			err = -EPROTO;
955 	}
956 
957 	gd->pdid = INVALID_PDID;
958 	gd->doorbell = INVALID_DOORBELL;
959 	gd->gpa_mkey = INVALID_MEM_KEY;
960 
961 	return err;
962 }
963 
mana_gd_wq_avail_space(struct gdma_queue * wq)964 u32 mana_gd_wq_avail_space(struct gdma_queue *wq)
965 {
966 	u32 used_space = (wq->head - wq->tail) * GDMA_WQE_BU_SIZE;
967 	u32 wq_size = wq->queue_size;
968 
969 	WARN_ON_ONCE(used_space > wq_size);
970 
971 	return wq_size - used_space;
972 }
973 
mana_gd_get_wqe_ptr(const struct gdma_queue * wq,u32 wqe_offset)974 u8 *mana_gd_get_wqe_ptr(const struct gdma_queue *wq, u32 wqe_offset)
975 {
976 	u32 offset = (wqe_offset * GDMA_WQE_BU_SIZE) & (wq->queue_size - 1);
977 
978 	WARN_ON_ONCE((offset + GDMA_WQE_BU_SIZE) > wq->queue_size);
979 
980 	return wq->queue_mem_ptr + offset;
981 }
982 
mana_gd_write_client_oob(const struct gdma_wqe_request * wqe_req,enum gdma_queue_type q_type,u32 client_oob_size,u32 sgl_data_size,u8 * wqe_ptr)983 static u32 mana_gd_write_client_oob(const struct gdma_wqe_request *wqe_req,
984 				    enum gdma_queue_type q_type,
985 				    u32 client_oob_size, u32 sgl_data_size,
986 				    u8 *wqe_ptr)
987 {
988 	bool oob_in_sgl = !!(wqe_req->flags & GDMA_WR_OOB_IN_SGL);
989 	bool pad_data = !!(wqe_req->flags & GDMA_WR_PAD_BY_SGE0);
990 	struct gdma_wqe *header = (struct gdma_wqe *)wqe_ptr;
991 	u8 *ptr;
992 
993 	memset(header, 0, sizeof(struct gdma_wqe));
994 	header->num_sge = wqe_req->num_sge;
995 	header->inline_oob_size_div4 = client_oob_size / sizeof(u32);
996 
997 	if (oob_in_sgl) {
998 		WARN_ON_ONCE(!pad_data || wqe_req->num_sge < 2);
999 
1000 		header->client_oob_in_sgl = 1;
1001 
1002 		if (pad_data)
1003 			header->last_vbytes = wqe_req->sgl[0].size;
1004 	}
1005 
1006 	if (q_type == GDMA_SQ)
1007 		header->client_data_unit = wqe_req->client_data_unit;
1008 
1009 	/* The size of gdma_wqe + client_oob_size must be less than or equal
1010 	 * to one Basic Unit (i.e. 32 bytes), so the pointer can't go beyond
1011 	 * the queue memory buffer boundary.
1012 	 */
1013 	ptr = wqe_ptr + sizeof(header);
1014 
1015 	if (wqe_req->inline_oob_data && wqe_req->inline_oob_size > 0) {
1016 		memcpy(ptr, wqe_req->inline_oob_data, wqe_req->inline_oob_size);
1017 
1018 		if (client_oob_size > wqe_req->inline_oob_size)
1019 			memset(ptr + wqe_req->inline_oob_size, 0,
1020 			       client_oob_size - wqe_req->inline_oob_size);
1021 	}
1022 
1023 	return sizeof(header) + client_oob_size;
1024 }
1025 
mana_gd_write_sgl(struct gdma_queue * wq,u8 * wqe_ptr,const struct gdma_wqe_request * wqe_req)1026 static void mana_gd_write_sgl(struct gdma_queue *wq, u8 *wqe_ptr,
1027 			      const struct gdma_wqe_request *wqe_req)
1028 {
1029 	u32 sgl_size = sizeof(struct gdma_sge) * wqe_req->num_sge;
1030 	const u8 *address = (u8 *)wqe_req->sgl;
1031 	u8 *base_ptr, *end_ptr;
1032 	u32 size_to_end;
1033 
1034 	base_ptr = wq->queue_mem_ptr;
1035 	end_ptr = base_ptr + wq->queue_size;
1036 	size_to_end = (u32)(end_ptr - wqe_ptr);
1037 
1038 	if (size_to_end < sgl_size) {
1039 		memcpy(wqe_ptr, address, size_to_end);
1040 
1041 		wqe_ptr = base_ptr;
1042 		address += size_to_end;
1043 		sgl_size -= size_to_end;
1044 	}
1045 
1046 	memcpy(wqe_ptr, address, sgl_size);
1047 }
1048 
mana_gd_post_work_request(struct gdma_queue * wq,const struct gdma_wqe_request * wqe_req,struct gdma_posted_wqe_info * wqe_info)1049 int mana_gd_post_work_request(struct gdma_queue *wq,
1050 			      const struct gdma_wqe_request *wqe_req,
1051 			      struct gdma_posted_wqe_info *wqe_info)
1052 {
1053 	u32 client_oob_size = wqe_req->inline_oob_size;
1054 	struct gdma_context *gc;
1055 	u32 sgl_data_size;
1056 	u32 max_wqe_size;
1057 	u32 wqe_size;
1058 	u8 *wqe_ptr;
1059 
1060 	if (wqe_req->num_sge == 0)
1061 		return -EINVAL;
1062 
1063 	if (wq->type == GDMA_RQ) {
1064 		if (client_oob_size != 0)
1065 			return -EINVAL;
1066 
1067 		client_oob_size = INLINE_OOB_SMALL_SIZE;
1068 
1069 		max_wqe_size = GDMA_MAX_RQE_SIZE;
1070 	} else {
1071 		if (client_oob_size != INLINE_OOB_SMALL_SIZE &&
1072 		    client_oob_size != INLINE_OOB_LARGE_SIZE)
1073 			return -EINVAL;
1074 
1075 		max_wqe_size = GDMA_MAX_SQE_SIZE;
1076 	}
1077 
1078 	sgl_data_size = sizeof(struct gdma_sge) * wqe_req->num_sge;
1079 	wqe_size = ALIGN(sizeof(struct gdma_wqe) + client_oob_size +
1080 			 sgl_data_size, GDMA_WQE_BU_SIZE);
1081 	if (wqe_size > max_wqe_size)
1082 		return -EINVAL;
1083 
1084 	if (wq->monitor_avl_buf && wqe_size > mana_gd_wq_avail_space(wq)) {
1085 		gc = wq->gdma_dev->gdma_context;
1086 		dev_err(gc->dev, "unsuccessful flow control!\n");
1087 		return -ENOSPC;
1088 	}
1089 
1090 	if (wqe_info)
1091 		wqe_info->wqe_size_in_bu = wqe_size / GDMA_WQE_BU_SIZE;
1092 
1093 	wqe_ptr = mana_gd_get_wqe_ptr(wq, wq->head);
1094 	wqe_ptr += mana_gd_write_client_oob(wqe_req, wq->type, client_oob_size,
1095 					    sgl_data_size, wqe_ptr);
1096 	if (wqe_ptr >= (u8 *)wq->queue_mem_ptr + wq->queue_size)
1097 		wqe_ptr -= wq->queue_size;
1098 
1099 	mana_gd_write_sgl(wq, wqe_ptr, wqe_req);
1100 
1101 	wq->head += wqe_size / GDMA_WQE_BU_SIZE;
1102 
1103 	return 0;
1104 }
1105 
mana_gd_post_and_ring(struct gdma_queue * queue,const struct gdma_wqe_request * wqe_req,struct gdma_posted_wqe_info * wqe_info)1106 int mana_gd_post_and_ring(struct gdma_queue *queue,
1107 			  const struct gdma_wqe_request *wqe_req,
1108 			  struct gdma_posted_wqe_info *wqe_info)
1109 {
1110 	struct gdma_context *gc = queue->gdma_dev->gdma_context;
1111 	int err;
1112 
1113 	err = mana_gd_post_work_request(queue, wqe_req, wqe_info);
1114 	if (err)
1115 		return err;
1116 
1117 	mana_gd_wq_ring_doorbell(gc, queue);
1118 
1119 	return 0;
1120 }
1121 
mana_gd_read_cqe(struct gdma_queue * cq,struct gdma_comp * comp)1122 static int mana_gd_read_cqe(struct gdma_queue *cq, struct gdma_comp *comp)
1123 {
1124 	unsigned int num_cqe = cq->queue_size / sizeof(struct gdma_cqe);
1125 	struct gdma_cqe *cq_cqe = cq->queue_mem_ptr;
1126 	u32 owner_bits, new_bits, old_bits;
1127 	struct gdma_cqe *cqe;
1128 
1129 	cqe = &cq_cqe[cq->head % num_cqe];
1130 	owner_bits = cqe->cqe_info.owner_bits;
1131 
1132 	old_bits = (cq->head / num_cqe - 1) & GDMA_CQE_OWNER_MASK;
1133 	/* Return 0 if no more entries. */
1134 	if (owner_bits == old_bits)
1135 		return 0;
1136 
1137 	new_bits = (cq->head / num_cqe) & GDMA_CQE_OWNER_MASK;
1138 	/* Return -1 if overflow detected. */
1139 	if (WARN_ON_ONCE(owner_bits != new_bits))
1140 		return -1;
1141 
1142 	/* Per GDMA spec, rmb is necessary after checking owner_bits, before
1143 	 * reading completion info
1144 	 */
1145 	rmb();
1146 
1147 	comp->wq_num = cqe->cqe_info.wq_num;
1148 	comp->is_sq = cqe->cqe_info.is_sq;
1149 	memcpy(comp->cqe_data, cqe->cqe_data, GDMA_COMP_DATA_SIZE);
1150 
1151 	return 1;
1152 }
1153 
mana_gd_poll_cq(struct gdma_queue * cq,struct gdma_comp * comp,int num_cqe)1154 int mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe)
1155 {
1156 	int cqe_idx;
1157 	int ret;
1158 
1159 	for (cqe_idx = 0; cqe_idx < num_cqe; cqe_idx++) {
1160 		ret = mana_gd_read_cqe(cq, &comp[cqe_idx]);
1161 
1162 		if (ret < 0) {
1163 			cq->head -= cqe_idx;
1164 			return ret;
1165 		}
1166 
1167 		if (ret == 0)
1168 			break;
1169 
1170 		cq->head++;
1171 	}
1172 
1173 	return cqe_idx;
1174 }
1175 
mana_gd_intr(int irq,void * arg)1176 static irqreturn_t mana_gd_intr(int irq, void *arg)
1177 {
1178 	struct gdma_irq_context *gic = arg;
1179 
1180 	if (gic->handler)
1181 		gic->handler(gic->arg);
1182 
1183 	return IRQ_HANDLED;
1184 }
1185 
mana_gd_alloc_res_map(u32 res_avail,struct gdma_resource * r)1186 int mana_gd_alloc_res_map(u32 res_avail, struct gdma_resource *r)
1187 {
1188 	r->map = bitmap_zalloc(res_avail, GFP_KERNEL);
1189 	if (!r->map)
1190 		return -ENOMEM;
1191 
1192 	r->size = res_avail;
1193 	spin_lock_init(&r->lock);
1194 
1195 	return 0;
1196 }
1197 
mana_gd_free_res_map(struct gdma_resource * r)1198 void mana_gd_free_res_map(struct gdma_resource *r)
1199 {
1200 	bitmap_free(r->map);
1201 	r->map = NULL;
1202 	r->size = 0;
1203 }
1204 
mana_gd_setup_irqs(struct pci_dev * pdev)1205 static int mana_gd_setup_irqs(struct pci_dev *pdev)
1206 {
1207 	unsigned int max_queues_per_port = num_online_cpus();
1208 	struct gdma_context *gc = pci_get_drvdata(pdev);
1209 	struct gdma_irq_context *gic;
1210 	unsigned int max_irqs;
1211 	int nvec, irq;
1212 	int err, i, j;
1213 
1214 	if (max_queues_per_port > MANA_MAX_NUM_QUEUES)
1215 		max_queues_per_port = MANA_MAX_NUM_QUEUES;
1216 
1217 	/* Need 1 interrupt for the Hardware communication Channel (HWC) */
1218 	max_irqs = max_queues_per_port + 1;
1219 
1220 	nvec = pci_alloc_irq_vectors(pdev, 2, max_irqs, PCI_IRQ_MSIX);
1221 	if (nvec < 0)
1222 		return nvec;
1223 
1224 	gc->irq_contexts = kcalloc(nvec, sizeof(struct gdma_irq_context),
1225 				   GFP_KERNEL);
1226 	if (!gc->irq_contexts) {
1227 		err = -ENOMEM;
1228 		goto free_irq_vector;
1229 	}
1230 
1231 	for (i = 0; i < nvec; i++) {
1232 		gic = &gc->irq_contexts[i];
1233 		gic->handler = NULL;
1234 		gic->arg = NULL;
1235 
1236 		if (!i)
1237 			snprintf(gic->name, MANA_IRQ_NAME_SZ, "mana_hwc@pci:%s",
1238 				 pci_name(pdev));
1239 		else
1240 			snprintf(gic->name, MANA_IRQ_NAME_SZ, "mana_q%d@pci:%s",
1241 				 i - 1, pci_name(pdev));
1242 
1243 		irq = pci_irq_vector(pdev, i);
1244 		if (irq < 0) {
1245 			err = irq;
1246 			goto free_irq;
1247 		}
1248 
1249 		err = request_irq(irq, mana_gd_intr, 0, gic->name, gic);
1250 		if (err)
1251 			goto free_irq;
1252 	}
1253 
1254 	err = mana_gd_alloc_res_map(nvec, &gc->msix_resource);
1255 	if (err)
1256 		goto free_irq;
1257 
1258 	gc->max_num_msix = nvec;
1259 	gc->num_msix_usable = nvec;
1260 
1261 	return 0;
1262 
1263 free_irq:
1264 	for (j = i - 1; j >= 0; j--) {
1265 		irq = pci_irq_vector(pdev, j);
1266 		gic = &gc->irq_contexts[j];
1267 		free_irq(irq, gic);
1268 	}
1269 
1270 	kfree(gc->irq_contexts);
1271 	gc->irq_contexts = NULL;
1272 free_irq_vector:
1273 	pci_free_irq_vectors(pdev);
1274 	return err;
1275 }
1276 
mana_gd_remove_irqs(struct pci_dev * pdev)1277 static void mana_gd_remove_irqs(struct pci_dev *pdev)
1278 {
1279 	struct gdma_context *gc = pci_get_drvdata(pdev);
1280 	struct gdma_irq_context *gic;
1281 	int irq, i;
1282 
1283 	if (gc->max_num_msix < 1)
1284 		return;
1285 
1286 	mana_gd_free_res_map(&gc->msix_resource);
1287 
1288 	for (i = 0; i < gc->max_num_msix; i++) {
1289 		irq = pci_irq_vector(pdev, i);
1290 		if (irq < 0)
1291 			continue;
1292 
1293 		gic = &gc->irq_contexts[i];
1294 		free_irq(irq, gic);
1295 	}
1296 
1297 	pci_free_irq_vectors(pdev);
1298 
1299 	gc->max_num_msix = 0;
1300 	gc->num_msix_usable = 0;
1301 	kfree(gc->irq_contexts);
1302 	gc->irq_contexts = NULL;
1303 }
1304 
mana_gd_setup(struct pci_dev * pdev)1305 static int mana_gd_setup(struct pci_dev *pdev)
1306 {
1307 	struct gdma_context *gc = pci_get_drvdata(pdev);
1308 	int err;
1309 
1310 	mana_gd_init_registers(pdev);
1311 	mana_smc_init(&gc->shm_channel, gc->dev, gc->shm_base);
1312 
1313 	err = mana_gd_setup_irqs(pdev);
1314 	if (err)
1315 		return err;
1316 
1317 	err = mana_hwc_create_channel(gc);
1318 	if (err)
1319 		goto remove_irq;
1320 
1321 	err = mana_gd_verify_vf_version(pdev);
1322 	if (err)
1323 		goto destroy_hwc;
1324 
1325 	err = mana_gd_query_max_resources(pdev);
1326 	if (err)
1327 		goto destroy_hwc;
1328 
1329 	err = mana_gd_detect_devices(pdev);
1330 	if (err)
1331 		goto destroy_hwc;
1332 
1333 	return 0;
1334 
1335 destroy_hwc:
1336 	mana_hwc_destroy_channel(gc);
1337 remove_irq:
1338 	mana_gd_remove_irqs(pdev);
1339 	return err;
1340 }
1341 
mana_gd_cleanup(struct pci_dev * pdev)1342 static void mana_gd_cleanup(struct pci_dev *pdev)
1343 {
1344 	struct gdma_context *gc = pci_get_drvdata(pdev);
1345 
1346 	mana_hwc_destroy_channel(gc);
1347 
1348 	mana_gd_remove_irqs(pdev);
1349 }
1350 
mana_is_pf(unsigned short dev_id)1351 static bool mana_is_pf(unsigned short dev_id)
1352 {
1353 	return dev_id == MANA_PF_DEVICE_ID;
1354 }
1355 
mana_gd_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1356 static int mana_gd_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1357 {
1358 	struct gdma_context *gc;
1359 	void __iomem *bar0_va;
1360 	int bar = 0;
1361 	int err;
1362 
1363 	/* Each port has 2 CQs, each CQ has at most 1 EQE at a time */
1364 	BUILD_BUG_ON(2 * MAX_PORTS_IN_MANA_DEV * GDMA_EQE_SIZE > EQ_SIZE);
1365 
1366 	err = pci_enable_device(pdev);
1367 	if (err)
1368 		return -ENXIO;
1369 
1370 	pci_set_master(pdev);
1371 
1372 	err = pci_request_regions(pdev, "mana");
1373 	if (err)
1374 		goto disable_dev;
1375 
1376 	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1377 	if (err)
1378 		goto release_region;
1379 
1380 	err = -ENOMEM;
1381 	gc = vzalloc(sizeof(*gc));
1382 	if (!gc)
1383 		goto release_region;
1384 
1385 	mutex_init(&gc->eq_test_event_mutex);
1386 	pci_set_drvdata(pdev, gc);
1387 
1388 	bar0_va = pci_iomap(pdev, bar, 0);
1389 	if (!bar0_va)
1390 		goto free_gc;
1391 
1392 	gc->is_pf = mana_is_pf(pdev->device);
1393 	gc->bar0_va = bar0_va;
1394 	gc->dev = &pdev->dev;
1395 
1396 	err = mana_gd_setup(pdev);
1397 	if (err)
1398 		goto unmap_bar;
1399 
1400 	err = mana_probe(&gc->mana, false);
1401 	if (err)
1402 		goto cleanup_gd;
1403 
1404 	return 0;
1405 
1406 cleanup_gd:
1407 	mana_gd_cleanup(pdev);
1408 unmap_bar:
1409 	pci_iounmap(pdev, bar0_va);
1410 free_gc:
1411 	pci_set_drvdata(pdev, NULL);
1412 	vfree(gc);
1413 release_region:
1414 	pci_release_regions(pdev);
1415 disable_dev:
1416 	pci_clear_master(pdev);
1417 	pci_disable_device(pdev);
1418 	dev_err(&pdev->dev, "gdma probe failed: err = %d\n", err);
1419 	return err;
1420 }
1421 
mana_gd_remove(struct pci_dev * pdev)1422 static void mana_gd_remove(struct pci_dev *pdev)
1423 {
1424 	struct gdma_context *gc = pci_get_drvdata(pdev);
1425 
1426 	mana_remove(&gc->mana, false);
1427 
1428 	mana_gd_cleanup(pdev);
1429 
1430 	pci_iounmap(pdev, gc->bar0_va);
1431 
1432 	vfree(gc);
1433 
1434 	pci_release_regions(pdev);
1435 	pci_clear_master(pdev);
1436 	pci_disable_device(pdev);
1437 }
1438 
1439 /* The 'state' parameter is not used. */
mana_gd_suspend(struct pci_dev * pdev,pm_message_t state)1440 static int mana_gd_suspend(struct pci_dev *pdev, pm_message_t state)
1441 {
1442 	struct gdma_context *gc = pci_get_drvdata(pdev);
1443 
1444 	mana_remove(&gc->mana, true);
1445 
1446 	mana_gd_cleanup(pdev);
1447 
1448 	return 0;
1449 }
1450 
1451 /* In case the NIC hardware stops working, the suspend and resume callbacks will
1452  * fail -- if this happens, it's safer to just report an error than try to undo
1453  * what has been done.
1454  */
mana_gd_resume(struct pci_dev * pdev)1455 static int mana_gd_resume(struct pci_dev *pdev)
1456 {
1457 	struct gdma_context *gc = pci_get_drvdata(pdev);
1458 	int err;
1459 
1460 	err = mana_gd_setup(pdev);
1461 	if (err)
1462 		return err;
1463 
1464 	err = mana_probe(&gc->mana, true);
1465 	if (err)
1466 		return err;
1467 
1468 	return 0;
1469 }
1470 
1471 /* Quiesce the device for kexec. This is also called upon reboot/shutdown. */
mana_gd_shutdown(struct pci_dev * pdev)1472 static void mana_gd_shutdown(struct pci_dev *pdev)
1473 {
1474 	struct gdma_context *gc = pci_get_drvdata(pdev);
1475 
1476 	dev_info(&pdev->dev, "Shutdown was called\n");
1477 
1478 	mana_remove(&gc->mana, true);
1479 
1480 	mana_gd_cleanup(pdev);
1481 
1482 	pci_disable_device(pdev);
1483 }
1484 
1485 static const struct pci_device_id mana_id_table[] = {
1486 	{ PCI_DEVICE(PCI_VENDOR_ID_MICROSOFT, MANA_PF_DEVICE_ID) },
1487 	{ PCI_DEVICE(PCI_VENDOR_ID_MICROSOFT, MANA_VF_DEVICE_ID) },
1488 	{ }
1489 };
1490 
1491 static struct pci_driver mana_driver = {
1492 	.name		= "mana",
1493 	.id_table	= mana_id_table,
1494 	.probe		= mana_gd_probe,
1495 	.remove		= mana_gd_remove,
1496 	.suspend	= mana_gd_suspend,
1497 	.resume		= mana_gd_resume,
1498 	.shutdown	= mana_gd_shutdown,
1499 };
1500 
1501 module_pci_driver(mana_driver);
1502 
1503 MODULE_DEVICE_TABLE(pci, mana_id_table);
1504 
1505 MODULE_LICENSE("Dual BSD/GPL");
1506 MODULE_DESCRIPTION("Microsoft Azure Network Adapter driver");
1507