1/*
2 * Kernel execution entry point code.
3 *
4 *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
5 *	Initial PowerPC version.
6 *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
7 *	Rewritten for PReP
8 *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
9 *	Low-level exception handers, MMU support, and rewrite.
10 *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
11 *	PowerPC 8xx modifications.
12 *    Copyright (c) 1998-1999 TiVo, Inc.
13 *	PowerPC 403GCX modifications.
14 *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
15 *	PowerPC 403GCX/405GP modifications.
16 *    Copyright 2000 MontaVista Software Inc.
17 *	PPC405 modifications
18 *	PowerPC 403GCX/405GP modifications.
19 *	Author: MontaVista Software, Inc.
20 *		frank_rowand@mvista.com or source@mvista.com
21 *		debbie_chu@mvista.com
22 *    Copyright 2002-2004 MontaVista Software, Inc.
23 *	PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
24 *    Copyright 2004 Freescale Semiconductor, Inc
25 *	PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
26 *
27 * This program is free software; you can redistribute  it and/or modify it
28 * under  the terms of  the GNU General  Public License as published by the
29 * Free Software Foundation;  either version 2 of the  License, or (at your
30 * option) any later version.
31 */
32
33#include <linux/init.h>
34#include <linux/threads.h>
35#include <asm/processor.h>
36#include <asm/page.h>
37#include <asm/mmu.h>
38#include <asm/pgtable.h>
39#include <asm/cputable.h>
40#include <asm/thread_info.h>
41#include <asm/ppc_asm.h>
42#include <asm/asm-offsets.h>
43#include <asm/cache.h>
44#include <asm/ptrace.h>
45#include "head_booke.h"
46
47/* As with the other PowerPC ports, it is expected that when code
48 * execution begins here, the following registers contain valid, yet
49 * optional, information:
50 *
51 *   r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
52 *   r4 - Starting address of the init RAM disk
53 *   r5 - Ending address of the init RAM disk
54 *   r6 - Start of kernel command line string (e.g. "mem=128")
55 *   r7 - End of kernel command line string
56 *
57 */
58	__HEAD
59_ENTRY(_stext);
60_ENTRY(_start);
61	/*
62	 * Reserve a word at a fixed location to store the address
63	 * of abatron_pteptrs
64	 */
65	nop
66/*
67 * Save parameters we are passed
68 */
69	mr	r31,r3
70	mr	r30,r4
71	mr	r29,r5
72	mr	r28,r6
73	mr	r27,r7
74	li	r25,0		/* phys kernel start (low) */
75	li	r24,0		/* CPU number */
76	li	r23,0		/* phys kernel start (high) */
77
78/* We try to not make any assumptions about how the boot loader
79 * setup or used the TLBs.  We invalidate all mappings from the
80 * boot loader and load a single entry in TLB1[0] to map the
81 * first 64M of kernel memory.  Any boot info passed from the
82 * bootloader needs to live in this first 64M.
83 *
84 * Requirement on bootloader:
85 *  - The page we're executing in needs to reside in TLB1 and
86 *    have IPROT=1.  If not an invalidate broadcast could
87 *    evict the entry we're currently executing in.
88 *
89 *  r3 = Index of TLB1 were executing in
90 *  r4 = Current MSR[IS]
91 *  r5 = Index of TLB1 temp mapping
92 *
93 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
94 * if needed
95 */
96
97_ENTRY(__early_start)
98
99#define ENTRY_MAPPING_BOOT_SETUP
100#include "fsl_booke_entry_mapping.S"
101#undef ENTRY_MAPPING_BOOT_SETUP
102
103	/* Establish the interrupt vector offsets */
104	SET_IVOR(0,  CriticalInput);
105	SET_IVOR(1,  MachineCheck);
106	SET_IVOR(2,  DataStorage);
107	SET_IVOR(3,  InstructionStorage);
108	SET_IVOR(4,  ExternalInput);
109	SET_IVOR(5,  Alignment);
110	SET_IVOR(6,  Program);
111	SET_IVOR(7,  FloatingPointUnavailable);
112	SET_IVOR(8,  SystemCall);
113	SET_IVOR(9,  AuxillaryProcessorUnavailable);
114	SET_IVOR(10, Decrementer);
115	SET_IVOR(11, FixedIntervalTimer);
116	SET_IVOR(12, WatchdogTimer);
117	SET_IVOR(13, DataTLBError);
118	SET_IVOR(14, InstructionTLBError);
119	SET_IVOR(15, DebugCrit);
120
121	/* Establish the interrupt vector base */
122	lis	r4,interrupt_base@h	/* IVPR only uses the high 16-bits */
123	mtspr	SPRN_IVPR,r4
124
125	/* Setup the defaults for TLB entries */
126	li	r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
127#ifdef CONFIG_E200
128	oris	r2,r2,MAS4_TLBSELD(1)@h
129#endif
130	mtspr	SPRN_MAS4, r2
131
132#if 0
133	/* Enable DOZE */
134	mfspr	r2,SPRN_HID0
135	oris	r2,r2,HID0_DOZE@h
136	mtspr	SPRN_HID0, r2
137#endif
138
139#if !defined(CONFIG_BDI_SWITCH)
140	/*
141	 * The Abatron BDI JTAG debugger does not tolerate others
142	 * mucking with the debug registers.
143	 */
144	lis	r2,DBCR0_IDM@h
145	mtspr	SPRN_DBCR0,r2
146	isync
147	/* clear any residual debug events */
148	li	r2,-1
149	mtspr	SPRN_DBSR,r2
150#endif
151
152#ifdef CONFIG_SMP
153	/* Check to see if we're the second processor, and jump
154	 * to the secondary_start code if so
155	 */
156	lis	r24, boot_cpuid@h
157	ori	r24, r24, boot_cpuid@l
158	lwz	r24, 0(r24)
159	cmpwi	r24, -1
160	mfspr   r24,SPRN_PIR
161	bne	__secondary_start
162#endif
163
164	/*
165	 * This is where the main kernel code starts.
166	 */
167
168	/* ptr to current */
169	lis	r2,init_task@h
170	ori	r2,r2,init_task@l
171
172	/* ptr to current thread */
173	addi	r4,r2,THREAD	/* init task's THREAD */
174	mtspr	SPRN_SPRG_THREAD,r4
175
176	/* stack */
177	lis	r1,init_thread_union@h
178	ori	r1,r1,init_thread_union@l
179	li	r0,0
180	stwu	r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
181
182	rlwinm  r22,r1,0,0,31-THREAD_SHIFT      /* current thread_info */
183	stw	r24, TI_CPU(r22)
184
185	bl	early_init
186
187#ifdef CONFIG_RELOCATABLE
188	lis	r3,kernstart_addr@ha
189	la	r3,kernstart_addr@l(r3)
190#ifdef CONFIG_PHYS_64BIT
191	stw	r23,0(r3)
192	stw	r25,4(r3)
193#else
194	stw	r25,0(r3)
195#endif
196#endif
197
198/*
199 * Decide what sort of machine this is and initialize the MMU.
200 */
201	mr	r3,r31
202	mr	r4,r30
203	mr	r5,r29
204	mr	r6,r28
205	mr	r7,r27
206	bl	machine_init
207	bl	MMU_init
208
209	/* Setup PTE pointers for the Abatron bdiGDB */
210	lis	r6, swapper_pg_dir@h
211	ori	r6, r6, swapper_pg_dir@l
212	lis	r5, abatron_pteptrs@h
213	ori	r5, r5, abatron_pteptrs@l
214	lis	r4, KERNELBASE@h
215	ori	r4, r4, KERNELBASE@l
216	stw	r5, 0(r4)	/* Save abatron_pteptrs at a fixed location */
217	stw	r6, 0(r5)
218
219	/* Let's move on */
220	lis	r4,start_kernel@h
221	ori	r4,r4,start_kernel@l
222	lis	r3,MSR_KERNEL@h
223	ori	r3,r3,MSR_KERNEL@l
224	mtspr	SPRN_SRR0,r4
225	mtspr	SPRN_SRR1,r3
226	rfi			/* change context and jump to start_kernel */
227
228/* Macros to hide the PTE size differences
229 *
230 * FIND_PTE -- walks the page tables given EA & pgdir pointer
231 *   r10 -- EA of fault
232 *   r11 -- PGDIR pointer
233 *   r12 -- free
234 *   label 2: is the bailout case
235 *
236 * if we find the pte (fall through):
237 *   r11 is low pte word
238 *   r12 is pointer to the pte
239 */
240#ifdef CONFIG_PTE_64BIT
241#define FIND_PTE	\
242	rlwinm	r12, r10, 13, 19, 29;	/* Compute pgdir/pmd offset */	\
243	lwzx	r11, r12, r11;		/* Get pgd/pmd entry */		\
244	rlwinm.	r12, r11, 0, 0, 20;	/* Extract pt base address */	\
245	beq	2f;			/* Bail if no table */		\
246	rlwimi	r12, r10, 23, 20, 28;	/* Compute pte address */	\
247	lwz	r11, 4(r12);		/* Get pte entry */
248#else
249#define FIND_PTE	\
250	rlwimi	r11, r10, 12, 20, 29;	/* Create L1 (pgdir/pmd) address */	\
251	lwz	r11, 0(r11);		/* Get L1 entry */			\
252	rlwinm.	r12, r11, 0, 0, 19;	/* Extract L2 (pte) base address */	\
253	beq	2f;			/* Bail if no table */			\
254	rlwimi	r12, r10, 22, 20, 29;	/* Compute PTE address */		\
255	lwz	r11, 0(r12);		/* Get Linux PTE */
256#endif
257
258/*
259 * Interrupt vector entry code
260 *
261 * The Book E MMUs are always on so we don't need to handle
262 * interrupts in real mode as with previous PPC processors. In
263 * this case we handle interrupts in the kernel virtual address
264 * space.
265 *
266 * Interrupt vectors are dynamically placed relative to the
267 * interrupt prefix as determined by the address of interrupt_base.
268 * The interrupt vectors offsets are programmed using the labels
269 * for each interrupt vector entry.
270 *
271 * Interrupt vectors must be aligned on a 16 byte boundary.
272 * We align on a 32 byte cache line boundary for good measure.
273 */
274
275interrupt_base:
276	/* Critical Input Interrupt */
277	CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
278
279	/* Machine Check Interrupt */
280#ifdef CONFIG_E200
281	/* no RFMCI, MCSRRs on E200 */
282	CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
283#else
284	MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
285#endif
286
287	/* Data Storage Interrupt */
288	START_EXCEPTION(DataStorage)
289	NORMAL_EXCEPTION_PROLOG
290	mfspr	r5,SPRN_ESR		/* Grab the ESR, save it, pass arg3 */
291	stw	r5,_ESR(r11)
292	mfspr	r4,SPRN_DEAR		/* Grab the DEAR, save it, pass arg2 */
293	andis.	r10,r5,(ESR_ILK|ESR_DLK)@h
294	bne	1f
295	EXC_XFER_EE_LITE(0x0300, handle_page_fault)
2961:
297	addi	r3,r1,STACK_FRAME_OVERHEAD
298	EXC_XFER_EE_LITE(0x0300, CacheLockingException)
299
300	/* Instruction Storage Interrupt */
301	INSTRUCTION_STORAGE_EXCEPTION
302
303	/* External Input Interrupt */
304	EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
305
306	/* Alignment Interrupt */
307	ALIGNMENT_EXCEPTION
308
309	/* Program Interrupt */
310	PROGRAM_EXCEPTION
311
312	/* Floating Point Unavailable Interrupt */
313#ifdef CONFIG_PPC_FPU
314	FP_UNAVAILABLE_EXCEPTION
315#else
316#ifdef CONFIG_E200
317	/* E200 treats 'normal' floating point instructions as FP Unavail exception */
318	EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE)
319#else
320	EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
321#endif
322#endif
323
324	/* System Call Interrupt */
325	START_EXCEPTION(SystemCall)
326	NORMAL_EXCEPTION_PROLOG
327	EXC_XFER_EE_LITE(0x0c00, DoSyscall)
328
329	/* Auxiliary Processor Unavailable Interrupt */
330	EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
331
332	/* Decrementer Interrupt */
333	DECREMENTER_EXCEPTION
334
335	/* Fixed Internal Timer Interrupt */
336	/* TODO: Add FIT support */
337	EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
338
339	/* Watchdog Timer Interrupt */
340#ifdef CONFIG_BOOKE_WDT
341	CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException)
342#else
343	CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception)
344#endif
345
346	/* Data TLB Error Interrupt */
347	START_EXCEPTION(DataTLBError)
348	mtspr	SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
349	mtspr	SPRN_SPRG_WSCRATCH1, r11
350	mtspr	SPRN_SPRG_WSCRATCH2, r12
351	mtspr	SPRN_SPRG_WSCRATCH3, r13
352	mfcr	r11
353	mtspr	SPRN_SPRG_WSCRATCH4, r11
354	mfspr	r10, SPRN_DEAR		/* Get faulting address */
355
356	/* If we are faulting a kernel address, we have to use the
357	 * kernel page tables.
358	 */
359	lis	r11, PAGE_OFFSET@h
360	cmplw	5, r10, r11
361	blt	5, 3f
362	lis	r11, swapper_pg_dir@h
363	ori	r11, r11, swapper_pg_dir@l
364
365	mfspr	r12,SPRN_MAS1		/* Set TID to 0 */
366	rlwinm	r12,r12,0,16,1
367	mtspr	SPRN_MAS1,r12
368
369	b	4f
370
371	/* Get the PGD for the current thread */
3723:
373	mfspr	r11,SPRN_SPRG_THREAD
374	lwz	r11,PGDIR(r11)
375
3764:
377	/* Mask of required permission bits. Note that while we
378	 * do copy ESR:ST to _PAGE_RW position as trying to write
379	 * to an RO page is pretty common, we don't do it with
380	 * _PAGE_DIRTY. We could do it, but it's a fairly rare
381	 * event so I'd rather take the overhead when it happens
382	 * rather than adding an instruction here. We should measure
383	 * whether the whole thing is worth it in the first place
384	 * as we could avoid loading SPRN_ESR completely in the first
385	 * place...
386	 *
387	 * TODO: Is it worth doing that mfspr & rlwimi in the first
388	 *       place or can we save a couple of instructions here ?
389	 */
390	mfspr	r12,SPRN_ESR
391#ifdef CONFIG_PTE_64BIT
392	li	r13,_PAGE_PRESENT
393	oris	r13,r13,_PAGE_ACCESSED@h
394#else
395	li	r13,_PAGE_PRESENT|_PAGE_ACCESSED
396#endif
397	rlwimi	r13,r12,11,29,29
398
399	FIND_PTE
400	andc.	r13,r13,r11		/* Check permission */
401
402#ifdef CONFIG_PTE_64BIT
403#ifdef CONFIG_SMP
404	subf	r10,r11,r12		/* create false data dep */
405	lwzx	r13,r11,r10		/* Get upper pte bits */
406#else
407	lwz	r13,0(r12)		/* Get upper pte bits */
408#endif
409#endif
410
411	bne	2f			/* Bail if permission/valid mismach */
412
413	/* Jump to common tlb load */
414	b	finish_tlb_load
4152:
416	/* The bailout.  Restore registers to pre-exception conditions
417	 * and call the heavyweights to help us out.
418	 */
419	mfspr	r11, SPRN_SPRG_RSCRATCH4
420	mtcr	r11
421	mfspr	r13, SPRN_SPRG_RSCRATCH3
422	mfspr	r12, SPRN_SPRG_RSCRATCH2
423	mfspr	r11, SPRN_SPRG_RSCRATCH1
424	mfspr	r10, SPRN_SPRG_RSCRATCH0
425	b	DataStorage
426
427	/* Instruction TLB Error Interrupt */
428	/*
429	 * Nearly the same as above, except we get our
430	 * information from different registers and bailout
431	 * to a different point.
432	 */
433	START_EXCEPTION(InstructionTLBError)
434	mtspr	SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
435	mtspr	SPRN_SPRG_WSCRATCH1, r11
436	mtspr	SPRN_SPRG_WSCRATCH2, r12
437	mtspr	SPRN_SPRG_WSCRATCH3, r13
438	mfcr	r11
439	mtspr	SPRN_SPRG_WSCRATCH4, r11
440	mfspr	r10, SPRN_SRR0		/* Get faulting address */
441
442	/* If we are faulting a kernel address, we have to use the
443	 * kernel page tables.
444	 */
445	lis	r11, PAGE_OFFSET@h
446	cmplw	5, r10, r11
447	blt	5, 3f
448	lis	r11, swapper_pg_dir@h
449	ori	r11, r11, swapper_pg_dir@l
450
451	mfspr	r12,SPRN_MAS1		/* Set TID to 0 */
452	rlwinm	r12,r12,0,16,1
453	mtspr	SPRN_MAS1,r12
454
455	/* Make up the required permissions for kernel code */
456#ifdef CONFIG_PTE_64BIT
457	li	r13,_PAGE_PRESENT | _PAGE_BAP_SX
458	oris	r13,r13,_PAGE_ACCESSED@h
459#else
460	li	r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
461#endif
462	b	4f
463
464	/* Get the PGD for the current thread */
4653:
466	mfspr	r11,SPRN_SPRG_THREAD
467	lwz	r11,PGDIR(r11)
468
469	/* Make up the required permissions for user code */
470#ifdef CONFIG_PTE_64BIT
471	li	r13,_PAGE_PRESENT | _PAGE_BAP_UX
472	oris	r13,r13,_PAGE_ACCESSED@h
473#else
474	li	r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
475#endif
476
4774:
478	FIND_PTE
479	andc.	r13,r13,r11		/* Check permission */
480
481#ifdef CONFIG_PTE_64BIT
482#ifdef CONFIG_SMP
483	subf	r10,r11,r12		/* create false data dep */
484	lwzx	r13,r11,r10		/* Get upper pte bits */
485#else
486	lwz	r13,0(r12)		/* Get upper pte bits */
487#endif
488#endif
489
490	bne	2f			/* Bail if permission mismach */
491
492	/* Jump to common TLB load point */
493	b	finish_tlb_load
494
4952:
496	/* The bailout.  Restore registers to pre-exception conditions
497	 * and call the heavyweights to help us out.
498	 */
499	mfspr	r11, SPRN_SPRG_RSCRATCH4
500	mtcr	r11
501	mfspr	r13, SPRN_SPRG_RSCRATCH3
502	mfspr	r12, SPRN_SPRG_RSCRATCH2
503	mfspr	r11, SPRN_SPRG_RSCRATCH1
504	mfspr	r10, SPRN_SPRG_RSCRATCH0
505	b	InstructionStorage
506
507#ifdef CONFIG_SPE
508	/* SPE Unavailable */
509	START_EXCEPTION(SPEUnavailable)
510	NORMAL_EXCEPTION_PROLOG
511	bne	load_up_spe
512	addi	r3,r1,STACK_FRAME_OVERHEAD
513	EXC_XFER_EE_LITE(0x2010, KernelSPE)
514#else
515	EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE)
516#endif /* CONFIG_SPE */
517
518	/* SPE Floating Point Data */
519#ifdef CONFIG_SPE
520	EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
521
522	/* SPE Floating Point Round */
523	EXCEPTION(0x2050, SPEFloatingPointRound, SPEFloatingPointRoundException, EXC_XFER_EE)
524#else
525	EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE)
526	EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE)
527#endif /* CONFIG_SPE */
528
529	/* Performance Monitor */
530	EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
531
532	EXCEPTION(0x2070, Doorbell, doorbell_exception, EXC_XFER_STD)
533
534	CRITICAL_EXCEPTION(0x2080, CriticalDoorbell, unknown_exception)
535
536	/* Debug Interrupt */
537	DEBUG_DEBUG_EXCEPTION
538	DEBUG_CRIT_EXCEPTION
539
540/*
541 * Local functions
542 */
543
544/*
545 * Both the instruction and data TLB miss get to this
546 * point to load the TLB.
547 *	r10 - available to use
548 *	r11 - TLB (info from Linux PTE)
549 *	r12 - available to use
550 *	r13 - upper bits of PTE (if PTE_64BIT) or available to use
551 *	CR5 - results of addr >= PAGE_OFFSET
552 *	MAS0, MAS1 - loaded with proper value when we get here
553 *	MAS2, MAS3 - will need additional info from Linux PTE
554 *	Upon exit, we reload everything and RFI.
555 */
556finish_tlb_load:
557	/*
558	 * We set execute, because we don't have the granularity to
559	 * properly set this at the page level (Linux problem).
560	 * Many of these bits are software only.  Bits we don't set
561	 * here we (properly should) assume have the appropriate value.
562	 */
563
564	mfspr	r12, SPRN_MAS2
565#ifdef CONFIG_PTE_64BIT
566	rlwimi	r12, r11, 32-19, 27, 31	/* extract WIMGE from pte */
567#else
568	rlwimi	r12, r11, 26, 27, 31	/* extract WIMGE from pte */
569#endif
570	mtspr	SPRN_MAS2, r12
571
572#ifdef CONFIG_PTE_64BIT
573	rlwinm	r12, r11, 32-2, 26, 31	/* Move in perm bits */
574	andi.	r10, r11, _PAGE_DIRTY
575	bne	1f
576	li	r10, MAS3_SW | MAS3_UW
577	andc	r12, r12, r10
5781:	rlwimi	r12, r13, 20, 0, 11	/* grab RPN[32:43] */
579	rlwimi	r12, r11, 20, 12, 19	/* grab RPN[44:51] */
580	mtspr	SPRN_MAS3, r12
581BEGIN_MMU_FTR_SECTION
582	srwi	r10, r13, 12		/* grab RPN[12:31] */
583	mtspr	SPRN_MAS7, r10
584END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
585#else
586	li	r10, (_PAGE_EXEC | _PAGE_PRESENT)
587	rlwimi	r10, r11, 31, 29, 29	/* extract _PAGE_DIRTY into SW */
588	and	r12, r11, r10
589	andi.	r10, r11, _PAGE_USER	/* Test for _PAGE_USER */
590	slwi	r10, r12, 1
591	or	r10, r10, r12
592	iseleq	r12, r12, r10
593	rlwimi	r11, r12, 0, 20, 31	/* Extract RPN from PTE and merge with perms */
594	mtspr	SPRN_MAS3, r11
595#endif
596#ifdef CONFIG_E200
597	/* Round robin TLB1 entries assignment */
598	mfspr	r12, SPRN_MAS0
599
600	/* Extract TLB1CFG(NENTRY) */
601	mfspr	r11, SPRN_TLB1CFG
602	andi.	r11, r11, 0xfff
603
604	/* Extract MAS0(NV) */
605	andi.	r13, r12, 0xfff
606	addi	r13, r13, 1
607	cmpw	0, r13, r11
608	addi	r12, r12, 1
609
610	/* check if we need to wrap */
611	blt	7f
612
613	/* wrap back to first free tlbcam entry */
614	lis	r13, tlbcam_index@ha
615	lwz	r13, tlbcam_index@l(r13)
616	rlwimi	r12, r13, 0, 20, 31
6177:
618	mtspr	SPRN_MAS0,r12
619#endif /* CONFIG_E200 */
620
621	tlbwe
622
623	/* Done...restore registers and get out of here.  */
624	mfspr	r11, SPRN_SPRG_RSCRATCH4
625	mtcr	r11
626	mfspr	r13, SPRN_SPRG_RSCRATCH3
627	mfspr	r12, SPRN_SPRG_RSCRATCH2
628	mfspr	r11, SPRN_SPRG_RSCRATCH1
629	mfspr	r10, SPRN_SPRG_RSCRATCH0
630	rfi					/* Force context change */
631
632#ifdef CONFIG_SPE
633/* Note that the SPE support is closely modeled after the AltiVec
634 * support.  Changes to one are likely to be applicable to the
635 * other!  */
636load_up_spe:
637/*
638 * Disable SPE for the task which had SPE previously,
639 * and save its SPE registers in its thread_struct.
640 * Enables SPE for use in the kernel on return.
641 * On SMP we know the SPE units are free, since we give it up every
642 * switch.  -- Kumar
643 */
644	mfmsr	r5
645	oris	r5,r5,MSR_SPE@h
646	mtmsr	r5			/* enable use of SPE now */
647	isync
648/*
649 * For SMP, we don't do lazy SPE switching because it just gets too
650 * horrendously complex, especially when a task switches from one CPU
651 * to another.  Instead we call giveup_spe in switch_to.
652 */
653#ifndef CONFIG_SMP
654	lis	r3,last_task_used_spe@ha
655	lwz	r4,last_task_used_spe@l(r3)
656	cmpi	0,r4,0
657	beq	1f
658	addi	r4,r4,THREAD	/* want THREAD of last_task_used_spe */
659	SAVE_32EVRS(0,r10,r4)
660	evxor	evr10, evr10, evr10	/* clear out evr10 */
661	evmwumiaa evr10, evr10, evr10	/* evr10 <- ACC = 0 * 0 + ACC */
662	li	r5,THREAD_ACC
663	evstddx	evr10, r4, r5		/* save off accumulator */
664	lwz	r5,PT_REGS(r4)
665	lwz	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
666	lis	r10,MSR_SPE@h
667	andc	r4,r4,r10	/* disable SPE for previous task */
668	stw	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
6691:
670#endif /* !CONFIG_SMP */
671	/* enable use of SPE after return */
672	oris	r9,r9,MSR_SPE@h
673	mfspr	r5,SPRN_SPRG_THREAD	/* current task's THREAD (phys) */
674	li	r4,1
675	li	r10,THREAD_ACC
676	stw	r4,THREAD_USED_SPE(r5)
677	evlddx	evr4,r10,r5
678	evmra	evr4,evr4
679	REST_32EVRS(0,r10,r5)
680#ifndef CONFIG_SMP
681	subi	r4,r5,THREAD
682	stw	r4,last_task_used_spe@l(r3)
683#endif /* !CONFIG_SMP */
684	/* restore registers and return */
6852:	REST_4GPRS(3, r11)
686	lwz	r10,_CCR(r11)
687	REST_GPR(1, r11)
688	mtcr	r10
689	lwz	r10,_LINK(r11)
690	mtlr	r10
691	REST_GPR(10, r11)
692	mtspr	SPRN_SRR1,r9
693	mtspr	SPRN_SRR0,r12
694	REST_GPR(9, r11)
695	REST_GPR(12, r11)
696	lwz	r11,GPR11(r11)
697	rfi
698
699/*
700 * SPE unavailable trap from kernel - print a message, but let
701 * the task use SPE in the kernel until it returns to user mode.
702 */
703KernelSPE:
704	lwz	r3,_MSR(r1)
705	oris	r3,r3,MSR_SPE@h
706	stw	r3,_MSR(r1)	/* enable use of SPE after return */
707#ifdef CONFIG_PRINTK
708	lis	r3,87f@h
709	ori	r3,r3,87f@l
710	mr	r4,r2		/* current */
711	lwz	r5,_NIP(r1)
712	bl	printk
713#endif
714	b	ret_from_except
715#ifdef CONFIG_PRINTK
71687:	.string	"SPE used in kernel  (task=%p, pc=%x)  \n"
717#endif
718	.align	4,0
719
720#endif /* CONFIG_SPE */
721
722/*
723 * Global functions
724 */
725
726/* Adjust or setup IVORs for e200 */
727_GLOBAL(__setup_e200_ivors)
728	li	r3,DebugDebug@l
729	mtspr	SPRN_IVOR15,r3
730	li	r3,SPEUnavailable@l
731	mtspr	SPRN_IVOR32,r3
732	li	r3,SPEFloatingPointData@l
733	mtspr	SPRN_IVOR33,r3
734	li	r3,SPEFloatingPointRound@l
735	mtspr	SPRN_IVOR34,r3
736	sync
737	blr
738
739/* Adjust or setup IVORs for e500v1/v2 */
740_GLOBAL(__setup_e500_ivors)
741	li	r3,DebugCrit@l
742	mtspr	SPRN_IVOR15,r3
743	li	r3,SPEUnavailable@l
744	mtspr	SPRN_IVOR32,r3
745	li	r3,SPEFloatingPointData@l
746	mtspr	SPRN_IVOR33,r3
747	li	r3,SPEFloatingPointRound@l
748	mtspr	SPRN_IVOR34,r3
749	li	r3,PerformanceMonitor@l
750	mtspr	SPRN_IVOR35,r3
751	sync
752	blr
753
754/* Adjust or setup IVORs for e500mc */
755_GLOBAL(__setup_e500mc_ivors)
756	li	r3,DebugDebug@l
757	mtspr	SPRN_IVOR15,r3
758	li	r3,PerformanceMonitor@l
759	mtspr	SPRN_IVOR35,r3
760	li	r3,Doorbell@l
761	mtspr	SPRN_IVOR36,r3
762	li	r3,CriticalDoorbell@l
763	mtspr	SPRN_IVOR37,r3
764	sync
765	blr
766
767/*
768 * extern void giveup_altivec(struct task_struct *prev)
769 *
770 * The e500 core does not have an AltiVec unit.
771 */
772_GLOBAL(giveup_altivec)
773	blr
774
775#ifdef CONFIG_SPE
776/*
777 * extern void giveup_spe(struct task_struct *prev)
778 *
779 */
780_GLOBAL(giveup_spe)
781	mfmsr	r5
782	oris	r5,r5,MSR_SPE@h
783	mtmsr	r5			/* enable use of SPE now */
784	isync
785	cmpi	0,r3,0
786	beqlr-				/* if no previous owner, done */
787	addi	r3,r3,THREAD		/* want THREAD of task */
788	lwz	r5,PT_REGS(r3)
789	cmpi	0,r5,0
790	SAVE_32EVRS(0, r4, r3)
791	evxor	evr6, evr6, evr6	/* clear out evr6 */
792	evmwumiaa evr6, evr6, evr6	/* evr6 <- ACC = 0 * 0 + ACC */
793	li	r4,THREAD_ACC
794	evstddx	evr6, r4, r3		/* save off accumulator */
795	mfspr	r6,SPRN_SPEFSCR
796	stw	r6,THREAD_SPEFSCR(r3)	/* save spefscr register value */
797	beq	1f
798	lwz	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
799	lis	r3,MSR_SPE@h
800	andc	r4,r4,r3		/* disable SPE for previous task */
801	stw	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
8021:
803#ifndef CONFIG_SMP
804	li	r5,0
805	lis	r4,last_task_used_spe@ha
806	stw	r5,last_task_used_spe@l(r4)
807#endif /* !CONFIG_SMP */
808	blr
809#endif /* CONFIG_SPE */
810
811/*
812 * extern void giveup_fpu(struct task_struct *prev)
813 *
814 * Not all FSL Book-E cores have an FPU
815 */
816#ifndef CONFIG_PPC_FPU
817_GLOBAL(giveup_fpu)
818	blr
819#endif
820
821/*
822 * extern void abort(void)
823 *
824 * At present, this routine just applies a system reset.
825 */
826_GLOBAL(abort)
827	li	r13,0
828	mtspr	SPRN_DBCR0,r13		/* disable all debug events */
829	isync
830	mfmsr	r13
831	ori	r13,r13,MSR_DE@l	/* Enable Debug Events */
832	mtmsr	r13
833	isync
834	mfspr	r13,SPRN_DBCR0
835	lis	r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
836	mtspr	SPRN_DBCR0,r13
837	isync
838
839_GLOBAL(set_context)
840
841#ifdef CONFIG_BDI_SWITCH
842	/* Context switch the PTE pointer for the Abatron BDI2000.
843	 * The PGDIR is the second parameter.
844	 */
845	lis	r5, abatron_pteptrs@h
846	ori	r5, r5, abatron_pteptrs@l
847	stw	r4, 0x4(r5)
848#endif
849	mtspr	SPRN_PID,r3
850	isync			/* Force context change */
851	blr
852
853_GLOBAL(flush_dcache_L1)
854	mfspr	r3,SPRN_L1CFG0
855
856	rlwinm	r5,r3,9,3	/* Extract cache block size */
857	twlgti	r5,1		/* Only 32 and 64 byte cache blocks
858				 * are currently defined.
859				 */
860	li	r4,32
861	subfic	r6,r5,2		/* r6 = log2(1KiB / cache block size) -
862				 *      log2(number of ways)
863				 */
864	slw	r5,r4,r5	/* r5 = cache block size */
865
866	rlwinm	r7,r3,0,0xff	/* Extract number of KiB in the cache */
867	mulli	r7,r7,13	/* An 8-way cache will require 13
868				 * loads per set.
869				 */
870	slw	r7,r7,r6
871
872	/* save off HID0 and set DCFA */
873	mfspr	r8,SPRN_HID0
874	ori	r9,r8,HID0_DCFA@l
875	mtspr	SPRN_HID0,r9
876	isync
877
878	lis	r4,KERNELBASE@h
879	mtctr	r7
880
8811:	lwz	r3,0(r4)	/* Load... */
882	add	r4,r4,r5
883	bdnz	1b
884
885	msync
886	lis	r4,KERNELBASE@h
887	mtctr	r7
888
8891:	dcbf	0,r4		/* ...and flush. */
890	add	r4,r4,r5
891	bdnz	1b
892
893	/* restore HID0 */
894	mtspr	SPRN_HID0,r8
895	isync
896
897	blr
898
899#ifdef CONFIG_SMP
900/* When we get here, r24 needs to hold the CPU # */
901	.globl __secondary_start
902__secondary_start:
903	lis	r3,__secondary_hold_acknowledge@h
904	ori	r3,r3,__secondary_hold_acknowledge@l
905	stw	r24,0(r3)
906
907	li	r3,0
908	mr	r4,r24		/* Why? */
909	bl	call_setup_cpu
910
911	lis	r3,tlbcam_index@ha
912	lwz	r3,tlbcam_index@l(r3)
913	mtctr	r3
914	li	r26,0		/* r26 safe? */
915
916	/* Load each CAM entry */
9171:	mr	r3,r26
918	bl	loadcam_entry
919	addi	r26,r26,1
920	bdnz	1b
921
922	/* get current_thread_info and current */
923	lis	r1,secondary_ti@ha
924	lwz	r1,secondary_ti@l(r1)
925	lwz	r2,TI_TASK(r1)
926
927	/* stack */
928	addi	r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
929	li	r0,0
930	stw	r0,0(r1)
931
932	/* ptr to current thread */
933	addi	r4,r2,THREAD	/* address of our thread_struct */
934	mtspr	SPRN_SPRG_THREAD,r4
935
936	/* Setup the defaults for TLB entries */
937	li	r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
938	mtspr	SPRN_MAS4,r4
939
940	/* Jump to start_secondary */
941	lis	r4,MSR_KERNEL@h
942	ori	r4,r4,MSR_KERNEL@l
943	lis	r3,start_secondary@h
944	ori	r3,r3,start_secondary@l
945	mtspr	SPRN_SRR0,r3
946	mtspr	SPRN_SRR1,r4
947	sync
948	rfi
949	sync
950
951	.globl __secondary_hold_acknowledge
952__secondary_hold_acknowledge:
953	.long	-1
954#endif
955
956/*
957 * We put a few things here that have to be page-aligned. This stuff
958 * goes at the beginning of the data segment, which is page-aligned.
959 */
960	.data
961	.align	12
962	.globl	sdata
963sdata:
964	.globl	empty_zero_page
965empty_zero_page:
966	.space	4096
967	.globl	swapper_pg_dir
968swapper_pg_dir:
969	.space	PGD_TABLE_SIZE
970
971/*
972 * Room for two PTE pointers, usually the kernel and current user pointers
973 * to their respective root page table.
974 */
975abatron_pteptrs:
976	.space	8
977