1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "reg_helper.h"
27 
28 #include "core_types.h"
29 #include "link_encoder.h"
30 #include "dcn20_link_encoder.h"
31 #include "stream_encoder.h"
32 #include "i2caux_interface.h"
33 #include "dc_bios_types.h"
34 
35 #include "gpio_service_interface.h"
36 
37 #define CTX \
38 	enc10->base.ctx
39 #define DC_LOGGER \
40 	enc10->base.ctx->logger
41 
42 #define REG(reg)\
43 	(enc10->link_regs->reg)
44 
45 #undef FN
46 #define FN(reg_name, field_name) \
47 	enc10->link_shift->field_name, enc10->link_mask->field_name
48 
49 #define IND_REG(index) \
50 	(enc10->link_regs->index)
51 
52 #ifndef MAX
53 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
54 #endif
55 #ifndef MIN
56 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
57 #endif
58 
59 static struct mpll_cfg dcn2_mpll_cfg[] = {
60 	// RBR
61 	{
62 		.hdmimode_enable = 1,
63 		.ref_range = 3,
64 		.ref_clk_mpllb_div = 2,
65 		.mpllb_ssc_en = 1,
66 		.mpllb_div5_clk_en = 1,
67 		.mpllb_multiplier = 226,
68 		.mpllb_fracn_en = 1,
69 		.mpllb_fracn_quot = 39321,
70 		.mpllb_fracn_rem = 3,
71 		.mpllb_fracn_den = 5,
72 		.mpllb_ssc_up_spread = 0,
73 		.mpllb_ssc_peak = 38221,
74 		.mpllb_ssc_stepsize = 49314,
75 		.mpllb_div_clk_en = 0,
76 		.mpllb_div_multiplier = 0,
77 		.mpllb_hdmi_div = 0,
78 		.mpllb_tx_clk_div = 2,
79 		.tx_vboost_lvl = 4,
80 		.mpllb_pmix_en = 1,
81 		.mpllb_word_div2_en = 0,
82 		.mpllb_ana_v2i = 2,
83 		.mpllb_ana_freq_vco = 2,
84 		.mpllb_ana_cp_int = 7,
85 		.mpllb_ana_cp_prop = 18,
86 		.hdmi_pixel_clk_div = 0,
87 	},
88 	// HBR
89 	{
90 		.hdmimode_enable = 1,
91 		.ref_range = 3,
92 		.ref_clk_mpllb_div = 2,
93 		.mpllb_ssc_en = 1,
94 		.mpllb_div5_clk_en = 1,
95 		.mpllb_multiplier = 184,
96 		.mpllb_fracn_en = 0,
97 		.mpllb_fracn_quot = 0,
98 		.mpllb_fracn_rem = 0,
99 		.mpllb_fracn_den = 1,
100 		.mpllb_ssc_up_spread = 0,
101 		.mpllb_ssc_peak = 31850,
102 		.mpllb_ssc_stepsize = 41095,
103 		.mpllb_div_clk_en = 0,
104 		.mpllb_div_multiplier = 0,
105 		.mpllb_hdmi_div = 0,
106 		.mpllb_tx_clk_div = 1,
107 		.tx_vboost_lvl = 4,
108 		.mpllb_pmix_en = 1,
109 		.mpllb_word_div2_en = 0,
110 		.mpllb_ana_v2i = 2,
111 		.mpllb_ana_freq_vco = 3,
112 		.mpllb_ana_cp_int = 7,
113 		.mpllb_ana_cp_prop = 18,
114 		.hdmi_pixel_clk_div = 0,
115 	},
116 	//HBR2
117 	{
118 		.hdmimode_enable = 1,
119 		.ref_range = 3,
120 		.ref_clk_mpllb_div = 2,
121 		.mpllb_ssc_en = 1,
122 		.mpllb_div5_clk_en = 1,
123 		.mpllb_multiplier = 184,
124 		.mpllb_fracn_en = 0,
125 		.mpllb_fracn_quot = 0,
126 		.mpllb_fracn_rem = 0,
127 		.mpllb_fracn_den = 1,
128 		.mpllb_ssc_up_spread = 0,
129 		.mpllb_ssc_peak = 31850,
130 		.mpllb_ssc_stepsize = 41095,
131 		.mpllb_div_clk_en = 0,
132 		.mpllb_div_multiplier = 0,
133 		.mpllb_hdmi_div = 0,
134 		.mpllb_tx_clk_div = 0,
135 		.tx_vboost_lvl = 4,
136 		.mpllb_pmix_en = 1,
137 		.mpllb_word_div2_en = 0,
138 		.mpllb_ana_v2i = 2,
139 		.mpllb_ana_freq_vco = 3,
140 		.mpllb_ana_cp_int = 7,
141 		.mpllb_ana_cp_prop = 18,
142 		.hdmi_pixel_clk_div = 0,
143 	},
144 	//HBR3
145 	{
146 		.hdmimode_enable = 1,
147 		.ref_range = 3,
148 		.ref_clk_mpllb_div = 2,
149 		.mpllb_ssc_en = 1,
150 		.mpllb_div5_clk_en = 1,
151 		.mpllb_multiplier = 292,
152 		.mpllb_fracn_en = 0,
153 		.mpllb_fracn_quot = 0,
154 		.mpllb_fracn_rem = 0,
155 		.mpllb_fracn_den = 1,
156 		.mpllb_ssc_up_spread = 0,
157 		.mpllb_ssc_peak = 47776,
158 		.mpllb_ssc_stepsize = 61642,
159 		.mpllb_div_clk_en = 0,
160 		.mpllb_div_multiplier = 0,
161 		.mpllb_hdmi_div = 0,
162 		.mpllb_tx_clk_div = 0,
163 		.tx_vboost_lvl = 4,
164 		.mpllb_pmix_en = 1,
165 		.mpllb_word_div2_en = 0,
166 		.mpllb_ana_v2i = 2,
167 		.mpllb_ana_freq_vco = 0,
168 		.mpllb_ana_cp_int = 7,
169 		.mpllb_ana_cp_prop = 18,
170 		.hdmi_pixel_clk_div = 0,
171 	},
172 };
173 
enc2_fec_set_enable(struct link_encoder * enc,bool enable)174 void enc2_fec_set_enable(struct link_encoder *enc, bool enable)
175 {
176 	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
177 	DC_LOG_DSC("%s FEC at link encoder inst %d",
178 			enable ? "Enabling" : "Disabling", enc->id.enum_id);
179 	REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_EN, enable);
180 }
181 
enc2_fec_set_ready(struct link_encoder * enc,bool ready)182 void enc2_fec_set_ready(struct link_encoder *enc, bool ready)
183 {
184 	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
185 
186 	REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, ready);
187 }
188 
enc2_fec_is_active(struct link_encoder * enc)189 bool enc2_fec_is_active(struct link_encoder *enc)
190 {
191 	uint32_t active = 0;
192 	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
193 
194 	REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &active);
195 
196 	return (active != 0);
197 }
198 
199 /* this function reads dsc related register fields to be logged later in dcn10_log_hw_state
200  * into a dcn_dsc_state struct.
201  */
link_enc2_read_state(struct link_encoder * enc,struct link_enc_state * s)202 void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s)
203 {
204 	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
205 
206 	REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en);
207 	REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow);
208 	REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status);
209 	REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete);
210 }
211 
update_cfg_data(struct dcn10_link_encoder * enc10,const struct dc_link_settings * link_settings,struct dpcssys_phy_seq_cfg * cfg)212 static bool update_cfg_data(
213 		struct dcn10_link_encoder *enc10,
214 		const struct dc_link_settings *link_settings,
215 		struct dpcssys_phy_seq_cfg *cfg)
216 {
217 	int i;
218 
219 	cfg->load_sram_fw = false;
220 
221 	for (i = 0; i < link_settings->lane_count; i++)
222 		cfg->lane_en[i] = true;
223 
224 	switch (link_settings->link_rate) {
225 	case LINK_RATE_LOW:
226 		cfg->mpll_cfg = dcn2_mpll_cfg[0];
227 		break;
228 	case LINK_RATE_HIGH:
229 		cfg->mpll_cfg = dcn2_mpll_cfg[1];
230 		break;
231 	case LINK_RATE_HIGH2:
232 		cfg->mpll_cfg = dcn2_mpll_cfg[2];
233 		break;
234 	case LINK_RATE_HIGH3:
235 		cfg->mpll_cfg = dcn2_mpll_cfg[3];
236 		break;
237 	default:
238 		DC_LOG_ERROR("%s: No supported link rate found %X!\n",
239 				__func__, link_settings->link_rate);
240 		return false;
241 	}
242 
243 	return true;
244 }
245 
dcn20_link_encoder_enable_dp_output(struct link_encoder * enc,const struct dc_link_settings * link_settings,enum clock_source_id clock_source)246 void dcn20_link_encoder_enable_dp_output(
247 	struct link_encoder *enc,
248 	const struct dc_link_settings *link_settings,
249 	enum clock_source_id clock_source)
250 {
251 	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
252 	struct dcn20_link_encoder *enc20 = (struct dcn20_link_encoder *) enc10;
253 	struct dpcssys_phy_seq_cfg *cfg = &enc20->phy_seq_cfg;
254 
255 	if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
256 		dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source);
257 		return;
258 	}
259 
260 	if (!update_cfg_data(enc10, link_settings, cfg))
261 		return;
262 
263 	enc1_configure_encoder(enc10, link_settings);
264 
265 	dcn10_link_encoder_setup(enc, SIGNAL_TYPE_DISPLAY_PORT);
266 
267 }
268 
dcn20_link_encoder_get_max_link_cap(struct link_encoder * enc,struct dc_link_settings * link_settings)269 void dcn20_link_encoder_get_max_link_cap(struct link_encoder *enc,
270 	struct dc_link_settings *link_settings)
271 {
272 	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
273 	uint32_t is_in_usb_c_dp4_mode = 0;
274 
275 	dcn10_link_encoder_get_max_link_cap(enc, link_settings);
276 
277 	/* in usb c dp2 mode, max lane count is 2 */
278 	if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) {
279 		REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
280 		if (!is_in_usb_c_dp4_mode)
281 			link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
282 	}
283 
284 }
285 
dcn20_link_encoder_is_in_alt_mode(struct link_encoder * enc)286 bool dcn20_link_encoder_is_in_alt_mode(struct link_encoder *enc)
287 {
288 	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
289 	uint32_t dp_alt_mode_disable = 0;
290 	bool is_usb_c_alt_mode = false;
291 
292 	if (enc->features.flags.bits.DP_IS_USB_C) {
293 		/* if value == 1 alt mode is disabled, otherwise it is enabled */
294 		REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
295 		is_usb_c_alt_mode = (dp_alt_mode_disable == 0);
296 	}
297 
298 	return is_usb_c_alt_mode;
299 }
300 
301 #define AUX_REG(reg)\
302 	(enc10->aux_regs->reg)
303 
304 #define AUX_REG_READ(reg_name) \
305 		dm_read_reg(CTX, AUX_REG(reg_name))
306 
307 #define AUX_REG_WRITE(reg_name, val) \
308 			dm_write_reg(CTX, AUX_REG(reg_name), val)
enc2_hw_init(struct link_encoder * enc)309 void enc2_hw_init(struct link_encoder *enc)
310 {
311 	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
312 /*
313 	00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
314 	01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
315 	02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
316 	03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
317 	04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
318 	05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
319 	06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
320 	07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
321 */
322 
323 /*
324 	AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
325 	AUX_RX_START_WINDOW = 1 [6:4]
326 	AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
327 	AUX_RX_HALF_SYM_DETECT_LEN  = 1 [13:12] default is 1
328 	AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
329 	AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0  default is 0
330 	AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1  default is 1
331 	AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1  default is 1
332 	AUX_RX_PHASE_DETECT_LEN,  [21,20] = 0x3 default is 3
333 	AUX_RX_DETECTION_THRESHOLD [30:28] = 1
334 */
335 	if (enc->ctx->dc_bios->golden_table.dc_golden_table_ver > 0) {
336 		AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, enc->ctx->dc_bios->golden_table.aux_dphy_rx_control0_val);
337 
338 		AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, enc->ctx->dc_bios->golden_table.aux_dphy_tx_control_val);
339 
340 		AUX_REG_WRITE(AUX_DPHY_RX_CONTROL1, enc->ctx->dc_bios->golden_table.aux_dphy_rx_control1_val);
341 	} else {
342 		AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
343 
344 		AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
345 	}
346 
347 	//AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
348 	// Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
349 	// 27MHz -> 0xd
350 	// 100MHz -> 0x32
351 	// 48MHz -> 0x18
352 
353 	// Set TMDS_CTL0 to 1.  This is a legacy setting.
354 	REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
355 
356 	dcn10_aux_initialize(enc10);
357 }
358 
359 static const struct link_encoder_funcs dcn20_link_enc_funcs = {
360 	.read_state = link_enc2_read_state,
361 	.validate_output_with_stream =
362 		dcn10_link_encoder_validate_output_with_stream,
363 	.hw_init = enc2_hw_init,
364 	.setup = dcn10_link_encoder_setup,
365 	.enable_tmds_output = dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa,
366 	.enable_dp_output = dcn20_link_encoder_enable_dp_output,
367 	.enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
368 	.disable_output = dcn10_link_encoder_disable_output,
369 	.dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
370 	.dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
371 	.update_mst_stream_allocation_table =
372 		dcn10_link_encoder_update_mst_stream_allocation_table,
373 	.psr_program_dp_dphy_fast_training =
374 			dcn10_psr_program_dp_dphy_fast_training,
375 	.psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
376 	.connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
377 	.enable_hpd = dcn10_link_encoder_enable_hpd,
378 	.disable_hpd = dcn10_link_encoder_disable_hpd,
379 	.is_dig_enabled = dcn10_is_dig_enabled,
380 	.destroy = dcn10_link_encoder_destroy,
381 	.fec_set_enable = enc2_fec_set_enable,
382 	.fec_set_ready = enc2_fec_set_ready,
383 	.fec_is_active = enc2_fec_is_active,
384 	.get_dig_mode = dcn10_get_dig_mode,
385 	.get_dig_frontend = dcn10_get_dig_frontend,
386 	.is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
387 	.get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
388 };
389 
dcn20_link_encoder_construct(struct dcn20_link_encoder * enc20,const struct encoder_init_data * init_data,const struct encoder_feature_support * enc_features,const struct dcn10_link_enc_registers * link_regs,const struct dcn10_link_enc_aux_registers * aux_regs,const struct dcn10_link_enc_hpd_registers * hpd_regs,const struct dcn10_link_enc_shift * link_shift,const struct dcn10_link_enc_mask * link_mask)390 void dcn20_link_encoder_construct(
391 	struct dcn20_link_encoder *enc20,
392 	const struct encoder_init_data *init_data,
393 	const struct encoder_feature_support *enc_features,
394 	const struct dcn10_link_enc_registers *link_regs,
395 	const struct dcn10_link_enc_aux_registers *aux_regs,
396 	const struct dcn10_link_enc_hpd_registers *hpd_regs,
397 	const struct dcn10_link_enc_shift *link_shift,
398 	const struct dcn10_link_enc_mask *link_mask)
399 {
400 	struct bp_encoder_cap_info bp_cap_info = {0};
401 	const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
402 	enum bp_result result = BP_RESULT_OK;
403 	struct dcn10_link_encoder *enc10 = &enc20->enc10;
404 
405 	enc10->base.funcs = &dcn20_link_enc_funcs;
406 	enc10->base.ctx = init_data->ctx;
407 	enc10->base.id = init_data->encoder;
408 
409 	enc10->base.hpd_source = init_data->hpd_source;
410 	enc10->base.connector = init_data->connector;
411 
412 	enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
413 
414 	enc10->base.features = *enc_features;
415 
416 	enc10->base.transmitter = init_data->transmitter;
417 
418 	/* set the flag to indicate whether driver poll the I2C data pin
419 	 * while doing the DP sink detect
420 	 */
421 
422 /*	if (dal_adapter_service_is_feature_supported(as,
423 		FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
424 		enc10->base.features.flags.bits.
425 			DP_SINK_DETECT_POLL_DATA_PIN = true;*/
426 
427 	enc10->base.output_signals =
428 		SIGNAL_TYPE_DVI_SINGLE_LINK |
429 		SIGNAL_TYPE_DVI_DUAL_LINK |
430 		SIGNAL_TYPE_LVDS |
431 		SIGNAL_TYPE_DISPLAY_PORT |
432 		SIGNAL_TYPE_DISPLAY_PORT_MST |
433 		SIGNAL_TYPE_EDP |
434 		SIGNAL_TYPE_HDMI_TYPE_A;
435 
436 	/* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
437 	 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
438 	 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
439 	 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
440 	 * Prefer DIG assignment is decided by board design.
441 	 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
442 	 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
443 	 * By this, adding DIGG should not hurt DCE 8.0.
444 	 * This will let DCE 8.1 share DCE 8.0 as much as possible
445 	 */
446 
447 	enc10->link_regs = link_regs;
448 	enc10->aux_regs = aux_regs;
449 	enc10->hpd_regs = hpd_regs;
450 	enc10->link_shift = link_shift;
451 	enc10->link_mask = link_mask;
452 
453 	switch (enc10->base.transmitter) {
454 	case TRANSMITTER_UNIPHY_A:
455 		enc10->base.preferred_engine = ENGINE_ID_DIGA;
456 	break;
457 	case TRANSMITTER_UNIPHY_B:
458 		enc10->base.preferred_engine = ENGINE_ID_DIGB;
459 	break;
460 	case TRANSMITTER_UNIPHY_C:
461 		enc10->base.preferred_engine = ENGINE_ID_DIGC;
462 	break;
463 	case TRANSMITTER_UNIPHY_D:
464 		enc10->base.preferred_engine = ENGINE_ID_DIGD;
465 	break;
466 	case TRANSMITTER_UNIPHY_E:
467 		enc10->base.preferred_engine = ENGINE_ID_DIGE;
468 	break;
469 	case TRANSMITTER_UNIPHY_F:
470 		enc10->base.preferred_engine = ENGINE_ID_DIGF;
471 	break;
472 	case TRANSMITTER_UNIPHY_G:
473 		enc10->base.preferred_engine = ENGINE_ID_DIGG;
474 	break;
475 	default:
476 		ASSERT_CRITICAL(false);
477 		enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
478 	}
479 
480 	/* default to one to mirror Windows behavior */
481 	enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
482 
483 	result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
484 						enc10->base.id, &bp_cap_info);
485 
486 	/* Override features with DCE-specific values */
487 	if (result == BP_RESULT_OK) {
488 		enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
489 				bp_cap_info.DP_HBR2_EN;
490 		enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
491 				bp_cap_info.DP_HBR3_EN;
492 		enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
493 		enc10->base.features.flags.bits.DP_IS_USB_C =
494 				bp_cap_info.DP_IS_USB_C;
495 	} else {
496 		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
497 				__func__,
498 				result);
499 	}
500 	if (enc10->base.ctx->dc->debug.hdmi20_disable) {
501 		enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
502 	}
503 }
504