1 /*
2 * Copyright (C) 2001,2002 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19 /*
20 * BCM1250-specific PCI support
21 *
22 * This module provides the glue between Linux's PCI subsystem
23 * and the hardware. We basically provide glue for accessing
24 * configuration space, and set up the translation for I/O
25 * space accesses.
26 *
27 * To access configuration space, we use ioremap. In the 32-bit
28 * kernel, this consumes either 4 or 8 page table pages, and 16MB of
29 * kernel mapped memory. Hopefully neither of these should be a huge
30 * problem.
31 */
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/kernel.h>
35 #include <linux/init.h>
36 #include <linux/mm.h>
37 #include <linux/console.h>
38
39 #include <asm/sibyte/sb1250_defs.h>
40 #include <asm/sibyte/sb1250_regs.h>
41 #include <asm/sibyte/sb1250_scd.h>
42 #include <asm/io.h>
43
44 /*
45 * Macros for calculating offsets into config space given a device
46 * structure or dev/fun/reg
47 */
48 #define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where))
49 #define CFGADDR(dev,where) CFGOFFSET((dev)->bus->number,(dev)->devfn,where)
50
51 static void *cfg_space;
52
53 #define PCI_BUS_ENABLED 1
54 #define LDT_BUS_ENABLED 2
55 #define PCI_DEVICE_MODE 4
56
57 static int sb1250_bus_status = 0;
58
59 #define PCI_BRIDGE_DEVICE 0
60 #define LDT_BRIDGE_DEVICE 1
61
62 #ifdef CONFIG_SIBYTE_HAS_LDT
63 /*
64 * HT's level-sensitive interrupts require EOI, which is generated
65 * through a 4MB memory-mapped region
66 */
67 unsigned long ldt_eoi_space;
68 #endif
69
70 /*
71 * Read/write 32-bit values in config space.
72 */
READCFG32(u32 addr)73 static inline u32 READCFG32(u32 addr)
74 {
75 return *(u32 *)(cfg_space + (addr&~3));
76 }
77
WRITECFG32(u32 addr,u32 data)78 static inline void WRITECFG32(u32 addr, u32 data)
79 {
80 *(u32 *)(cfg_space + (addr & ~3)) = data;
81 }
82
83 /*
84 * Some checks before doing config cycles:
85 * In PCI Device Mode, hide everything on bus 0 except the LDT host
86 * bridge. Otherwise, access is controlled by bridge MasterEn bits.
87 */
88 static int
sb1250_pci_can_access(struct pci_dev * dev)89 sb1250_pci_can_access(struct pci_dev *dev)
90 {
91 u32 devno;
92
93 if (!(sb1250_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
94 return 0;
95
96 if (dev->bus->number == 0) {
97 devno = PCI_SLOT(dev->devfn);
98 if (devno == LDT_BRIDGE_DEVICE)
99 return (sb1250_bus_status & LDT_BUS_ENABLED) != 0;
100 else if (sb1250_bus_status & PCI_DEVICE_MODE)
101 return 0;
102 else
103 return 1;
104 } else
105 return 1;
106 }
107
108 /*
109 * Read/write access functions for various sizes of values
110 * in config space. Return all 1's for disallowed accesses
111 * for a kludgy but adequate simulation of master aborts.
112 */
113
114 static int
sb1250_pci_read_config_byte(struct pci_dev * dev,int where,u8 * val)115 sb1250_pci_read_config_byte(struct pci_dev *dev, int where, u8 * val)
116 {
117 u32 data = 0;
118 u32 cfgaddr = CFGADDR(dev, where);
119
120 if (sb1250_pci_can_access(dev))
121 data = READCFG32(cfgaddr);
122 else
123 data = 0xFFFFFFFF;
124
125 *val = (data >> ((where & 3) << 3)) & 0xff;
126
127 return PCIBIOS_SUCCESSFUL;
128 }
129
130 static int
sb1250_pci_read_config_word(struct pci_dev * dev,int where,u16 * val)131 sb1250_pci_read_config_word(struct pci_dev *dev, int where, u16 * val)
132 {
133 u32 data = 0;
134 u32 cfgaddr = CFGADDR(dev, where);
135
136 if (where & 1)
137 return PCIBIOS_BAD_REGISTER_NUMBER;
138
139 if (sb1250_pci_can_access(dev))
140 data = READCFG32(cfgaddr);
141 else
142 data = 0xFFFFFFFF;
143
144 *val = (data >> ((where & 3) << 3)) & 0xffff;
145
146 return PCIBIOS_SUCCESSFUL;
147 }
148
149 static int
sb1250_pci_read_config_dword(struct pci_dev * dev,int where,u32 * val)150 sb1250_pci_read_config_dword(struct pci_dev *dev, int where, u32 * val)
151 {
152 u32 data = 0;
153 u32 cfgaddr = CFGADDR(dev, where);
154
155 if (where & 3)
156 return PCIBIOS_BAD_REGISTER_NUMBER;
157
158 if (sb1250_pci_can_access(dev))
159 data = READCFG32(cfgaddr);
160 else
161 data = 0xFFFFFFFF;
162
163 *val = data;
164
165 return PCIBIOS_SUCCESSFUL;
166 }
167
168
169 static int
sb1250_pci_write_config_byte(struct pci_dev * dev,int where,u8 val)170 sb1250_pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
171 {
172 u32 data = 0;
173 u32 cfgaddr = CFGADDR(dev, where);
174
175 if (sb1250_pci_can_access(dev)) {
176 data = READCFG32(cfgaddr);
177
178 data = (data & ~(0xff << ((where & 3) << 3))) |
179 (val << ((where & 3) << 3));
180
181 WRITECFG32(cfgaddr, data);
182 }
183
184 return PCIBIOS_SUCCESSFUL;
185 }
186
187 static int
sb1250_pci_write_config_word(struct pci_dev * dev,int where,u16 val)188 sb1250_pci_write_config_word(struct pci_dev *dev, int where, u16 val)
189 {
190 u32 data = 0;
191 u32 cfgaddr = CFGADDR(dev, where);
192
193 if (where & 1)
194 return PCIBIOS_BAD_REGISTER_NUMBER;
195
196 if (sb1250_pci_can_access(dev)) {
197 data = READCFG32(cfgaddr);
198
199 data = (data & ~(0xffff << ((where & 3) << 3))) |
200 (val << ((where & 3) << 3));
201
202 WRITECFG32(cfgaddr, data);
203 }
204
205 return PCIBIOS_SUCCESSFUL;
206 }
207
208 static int
sb1250_pci_write_config_dword(struct pci_dev * dev,int where,u32 val)209 sb1250_pci_write_config_dword(struct pci_dev *dev, int where, u32 val)
210 {
211 u32 cfgaddr = CFGADDR(dev, where);
212
213 if (where & 3)
214 return PCIBIOS_BAD_REGISTER_NUMBER;
215
216 if (sb1250_pci_can_access(dev))
217 WRITECFG32(cfgaddr, val);
218
219 return PCIBIOS_SUCCESSFUL;
220 }
221
222 struct pci_ops sb1250_pci_ops = {
223 sb1250_pci_read_config_byte,
224 sb1250_pci_read_config_word,
225 sb1250_pci_read_config_dword,
226 sb1250_pci_write_config_byte,
227 sb1250_pci_write_config_word,
228 sb1250_pci_write_config_dword
229 };
230
231
pcibios_init(void)232 void __init pcibios_init(void)
233 {
234 uint32_t cmdreg;
235 uint64_t reg;
236
237 cfg_space = ioremap(A_PHYS_LDTPCI_CFG_MATCH_BITS, 16*1024*1024);
238
239 /*
240 * See if the PCI bus has been configured by the firmware.
241 */
242 reg = *((volatile uint64_t *) KSEG1ADDR(A_SCD_SYSTEM_CFG));
243 if (!(reg & M_SYS_PCI_HOST)) {
244 sb1250_bus_status |= PCI_DEVICE_MODE;
245 } else {
246 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
247 PCI_COMMAND));
248 if (!(cmdreg & PCI_COMMAND_MASTER)) {
249 printk
250 ("PCI: Skipping PCI probe. Bus is not initialized.\n");
251 iounmap(cfg_space);
252 return;
253 }
254 sb1250_bus_status |= PCI_BUS_ENABLED;
255 }
256
257 /*
258 * Establish mappings in KSEG2 (kernel virtual) to PCI I/O
259 * space. Use "match bytes" policy to make everything look
260 * little-endian. So, you need to also set
261 * CONFIG_SWAP_IO_SPACE, but this is the combination that
262 * works correctly with most of Linux's drivers.
263 * XXX ehs: Should this happen in PCI Device mode?
264 */
265
266 set_io_port_base((unsigned long)
267 ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 65536));
268 isa_slot_offset = (unsigned long)
269 ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES_32, 1024*1024);
270
271 #ifdef CONFIG_SIBYTE_HAS_LDT
272 /*
273 * Also check the LDT bridge's enable, just in case we didn't
274 * initialize that one.
275 */
276
277 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(LDT_BRIDGE_DEVICE, 0),
278 PCI_COMMAND));
279 if (cmdreg & PCI_COMMAND_MASTER) {
280 sb1250_bus_status |= LDT_BUS_ENABLED;
281
282 /*
283 * Need bits 23:16 to convey vector number. Note that
284 * this consumes 4MB of kernel-mapped memory
285 * (Kseg2/Kseg3) for 32-bit kernel.
286 */
287 ldt_eoi_space = (unsigned long)
288 ioremap(A_PHYS_LDT_SPECIAL_MATCH_BYTES, 4*1024*1024);
289 }
290 #endif
291
292 /* Probe for PCI hardware */
293
294 printk("PCI: Probing PCI hardware on host bus 0.\n");
295 pci_scan_bus(0, &sb1250_pci_ops, NULL);
296
297 #ifdef CONFIG_VGA_CONSOLE
298 take_over_console(&vga_con,0,MAX_NR_CONSOLES-1,1);
299 #endif
300 }
301
302 struct pci_fixup pcibios_fixups[] = {
303 {0}
304 };
305
306 /*
307 * Called after each bus is probed, but before its children
308 * are examined.
309 */
pcibios_fixup_bus(struct pci_bus * b)310 void __devinit pcibios_fixup_bus(struct pci_bus *b)
311 {
312 pci_read_bridge_bases(b);
313 }
314
pcibios_assign_all_busses(void)315 unsigned int pcibios_assign_all_busses(void)
316 {
317 return 1;
318 }
319