1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2022 Marek Vasut <marex@denx.de>
4 *
5 * This code is based on drivers/gpu/drm/mxsfb/mxsfb*
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/media-bus-format.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/spinlock.h>
15
16 #include <drm/drm_atomic.h>
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_bridge.h>
19 #include <drm/drm_crtc.h>
20 #include <drm/drm_encoder.h>
21 #include <drm/drm_fb_dma_helper.h>
22 #include <drm/drm_fourcc.h>
23 #include <drm/drm_framebuffer.h>
24 #include <drm/drm_gem_atomic_helper.h>
25 #include <drm/drm_gem_dma_helper.h>
26 #include <drm/drm_plane.h>
27 #include <drm/drm_vblank.h>
28
29 #include "lcdif_drv.h"
30 #include "lcdif_regs.h"
31
32 /* -----------------------------------------------------------------------------
33 * CRTC
34 */
lcdif_set_formats(struct lcdif_drm_private * lcdif,const u32 bus_format)35 static void lcdif_set_formats(struct lcdif_drm_private *lcdif,
36 const u32 bus_format)
37 {
38 struct drm_device *drm = lcdif->drm;
39 const u32 format = lcdif->crtc.primary->state->fb->format->format;
40
41 writel(CSC0_CTRL_BYPASS, lcdif->base + LCDC_V8_CSC0_CTRL);
42
43 switch (bus_format) {
44 case MEDIA_BUS_FMT_RGB565_1X16:
45 writel(DISP_PARA_LINE_PATTERN_RGB565,
46 lcdif->base + LCDC_V8_DISP_PARA);
47 break;
48 case MEDIA_BUS_FMT_RGB888_1X24:
49 writel(DISP_PARA_LINE_PATTERN_RGB888,
50 lcdif->base + LCDC_V8_DISP_PARA);
51 break;
52 case MEDIA_BUS_FMT_UYVY8_1X16:
53 writel(DISP_PARA_LINE_PATTERN_UYVY_H,
54 lcdif->base + LCDC_V8_DISP_PARA);
55
56 /*
57 * CSC: BT.601 Limited Range RGB to YCbCr coefficients.
58 *
59 * |Y | | 0.2568 0.5041 0.0979| |R| |16 |
60 * |Cb| = |-0.1482 -0.2910 0.4392| * |G| + |128|
61 * |Cr| | 0.4392 0.4392 -0.3678| |B| |128|
62 */
63 writel(CSC0_COEF0_A2(0x081) | CSC0_COEF0_A1(0x041),
64 lcdif->base + LCDC_V8_CSC0_COEF0);
65 writel(CSC0_COEF1_B1(0x7db) | CSC0_COEF1_A3(0x019),
66 lcdif->base + LCDC_V8_CSC0_COEF1);
67 writel(CSC0_COEF2_B3(0x070) | CSC0_COEF2_B2(0x7b6),
68 lcdif->base + LCDC_V8_CSC0_COEF2);
69 writel(CSC0_COEF3_C2(0x7a2) | CSC0_COEF3_C1(0x070),
70 lcdif->base + LCDC_V8_CSC0_COEF3);
71 writel(CSC0_COEF4_D1(0x010) | CSC0_COEF4_C3(0x7ee),
72 lcdif->base + LCDC_V8_CSC0_COEF4);
73 writel(CSC0_COEF5_D3(0x080) | CSC0_COEF5_D2(0x080),
74 lcdif->base + LCDC_V8_CSC0_COEF5);
75
76 writel(CSC0_CTRL_CSC_MODE_RGB2YCbCr,
77 lcdif->base + LCDC_V8_CSC0_CTRL);
78
79 break;
80 default:
81 dev_err(drm->dev, "Unknown media bus format 0x%x\n", bus_format);
82 break;
83 }
84
85 switch (format) {
86 case DRM_FORMAT_RGB565:
87 writel(CTRLDESCL0_5_BPP_16_RGB565,
88 lcdif->base + LCDC_V8_CTRLDESCL0_5);
89 break;
90 case DRM_FORMAT_RGB888:
91 writel(CTRLDESCL0_5_BPP_24_RGB888,
92 lcdif->base + LCDC_V8_CTRLDESCL0_5);
93 break;
94 case DRM_FORMAT_XRGB1555:
95 writel(CTRLDESCL0_5_BPP_16_ARGB1555,
96 lcdif->base + LCDC_V8_CTRLDESCL0_5);
97 break;
98 case DRM_FORMAT_XRGB4444:
99 writel(CTRLDESCL0_5_BPP_16_ARGB4444,
100 lcdif->base + LCDC_V8_CTRLDESCL0_5);
101 break;
102 case DRM_FORMAT_XBGR8888:
103 writel(CTRLDESCL0_5_BPP_32_ABGR8888,
104 lcdif->base + LCDC_V8_CTRLDESCL0_5);
105 break;
106 case DRM_FORMAT_XRGB8888:
107 writel(CTRLDESCL0_5_BPP_32_ARGB8888,
108 lcdif->base + LCDC_V8_CTRLDESCL0_5);
109 break;
110 default:
111 dev_err(drm->dev, "Unknown pixel format 0x%x\n", format);
112 break;
113 }
114 }
115
lcdif_set_mode(struct lcdif_drm_private * lcdif,u32 bus_flags)116 static void lcdif_set_mode(struct lcdif_drm_private *lcdif, u32 bus_flags)
117 {
118 struct drm_display_mode *m = &lcdif->crtc.state->adjusted_mode;
119 u32 ctrl = 0;
120
121 if (m->flags & DRM_MODE_FLAG_NHSYNC)
122 ctrl |= CTRL_INV_HS;
123 if (m->flags & DRM_MODE_FLAG_NVSYNC)
124 ctrl |= CTRL_INV_VS;
125 if (bus_flags & DRM_BUS_FLAG_DE_LOW)
126 ctrl |= CTRL_INV_DE;
127 if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
128 ctrl |= CTRL_INV_PXCK;
129
130 writel(ctrl, lcdif->base + LCDC_V8_CTRL);
131
132 writel(DISP_SIZE_DELTA_Y(m->vdisplay) |
133 DISP_SIZE_DELTA_X(m->hdisplay),
134 lcdif->base + LCDC_V8_DISP_SIZE);
135
136 writel(HSYN_PARA_BP_H(m->htotal - m->hsync_end) |
137 HSYN_PARA_FP_H(m->hsync_start - m->hdisplay),
138 lcdif->base + LCDC_V8_HSYN_PARA);
139
140 writel(VSYN_PARA_BP_V(m->vtotal - m->vsync_end) |
141 VSYN_PARA_FP_V(m->vsync_start - m->vdisplay),
142 lcdif->base + LCDC_V8_VSYN_PARA);
143
144 writel(VSYN_HSYN_WIDTH_PW_V(m->vsync_end - m->vsync_start) |
145 VSYN_HSYN_WIDTH_PW_H(m->hsync_end - m->hsync_start),
146 lcdif->base + LCDC_V8_VSYN_HSYN_WIDTH);
147
148 writel(CTRLDESCL0_1_HEIGHT(m->vdisplay) |
149 CTRLDESCL0_1_WIDTH(m->hdisplay),
150 lcdif->base + LCDC_V8_CTRLDESCL0_1);
151
152 /*
153 * Undocumented P_SIZE and T_SIZE register but those written in the
154 * downstream kernel those registers control the AXI burst size. As of
155 * now there are two known values:
156 * 1 - 128Byte
157 * 2 - 256Byte
158 * Downstream set it to 256B burst size to improve the memory
159 * efficiency so set it here too.
160 */
161 ctrl = CTRLDESCL0_3_P_SIZE(2) | CTRLDESCL0_3_T_SIZE(2) |
162 CTRLDESCL0_3_PITCH(lcdif->crtc.primary->state->fb->pitches[0]);
163 writel(ctrl, lcdif->base + LCDC_V8_CTRLDESCL0_3);
164 }
165
lcdif_enable_controller(struct lcdif_drm_private * lcdif)166 static void lcdif_enable_controller(struct lcdif_drm_private *lcdif)
167 {
168 u32 reg;
169
170 /* Set FIFO Panic watermarks, low 1/3, high 2/3 . */
171 writel(FIELD_PREP(PANIC0_THRES_LOW_MASK, 1 * PANIC0_THRES_MAX / 3) |
172 FIELD_PREP(PANIC0_THRES_HIGH_MASK, 2 * PANIC0_THRES_MAX / 3),
173 lcdif->base + LCDC_V8_PANIC0_THRES);
174
175 /*
176 * Enable FIFO Panic, this does not generate interrupt, but
177 * boosts NoC priority based on FIFO Panic watermarks.
178 */
179 writel(INT_ENABLE_D1_PLANE_PANIC_EN,
180 lcdif->base + LCDC_V8_INT_ENABLE_D1);
181
182 reg = readl(lcdif->base + LCDC_V8_DISP_PARA);
183 reg |= DISP_PARA_DISP_ON;
184 writel(reg, lcdif->base + LCDC_V8_DISP_PARA);
185
186 reg = readl(lcdif->base + LCDC_V8_CTRLDESCL0_5);
187 reg |= CTRLDESCL0_5_EN;
188 writel(reg, lcdif->base + LCDC_V8_CTRLDESCL0_5);
189 }
190
lcdif_disable_controller(struct lcdif_drm_private * lcdif)191 static void lcdif_disable_controller(struct lcdif_drm_private *lcdif)
192 {
193 u32 reg;
194 int ret;
195
196 reg = readl(lcdif->base + LCDC_V8_CTRLDESCL0_5);
197 reg &= ~CTRLDESCL0_5_EN;
198 writel(reg, lcdif->base + LCDC_V8_CTRLDESCL0_5);
199
200 ret = readl_poll_timeout(lcdif->base + LCDC_V8_CTRLDESCL0_5,
201 reg, !(reg & CTRLDESCL0_5_EN),
202 0, 36000); /* Wait ~2 frame times max */
203 if (ret)
204 drm_err(lcdif->drm, "Failed to disable controller!\n");
205
206 reg = readl(lcdif->base + LCDC_V8_DISP_PARA);
207 reg &= ~DISP_PARA_DISP_ON;
208 writel(reg, lcdif->base + LCDC_V8_DISP_PARA);
209
210 /* Disable FIFO Panic NoC priority booster. */
211 writel(0, lcdif->base + LCDC_V8_INT_ENABLE_D1);
212 }
213
lcdif_reset_block(struct lcdif_drm_private * lcdif)214 static void lcdif_reset_block(struct lcdif_drm_private *lcdif)
215 {
216 writel(CTRL_SW_RESET, lcdif->base + LCDC_V8_CTRL + REG_SET);
217 readl(lcdif->base + LCDC_V8_CTRL);
218 writel(CTRL_SW_RESET, lcdif->base + LCDC_V8_CTRL + REG_CLR);
219 readl(lcdif->base + LCDC_V8_CTRL);
220 }
221
lcdif_crtc_mode_set_nofb(struct lcdif_drm_private * lcdif,struct drm_bridge_state * bridge_state,const u32 bus_format)222 static void lcdif_crtc_mode_set_nofb(struct lcdif_drm_private *lcdif,
223 struct drm_bridge_state *bridge_state,
224 const u32 bus_format)
225 {
226 struct drm_device *drm = lcdif->crtc.dev;
227 struct drm_display_mode *m = &lcdif->crtc.state->adjusted_mode;
228 u32 bus_flags = 0;
229
230 if (lcdif->bridge && lcdif->bridge->timings)
231 bus_flags = lcdif->bridge->timings->input_bus_flags;
232 else if (bridge_state)
233 bus_flags = bridge_state->input_bus_cfg.flags;
234
235 DRM_DEV_DEBUG_DRIVER(drm->dev, "Pixel clock: %dkHz (actual: %dkHz)\n",
236 m->crtc_clock,
237 (int)(clk_get_rate(lcdif->clk) / 1000));
238 DRM_DEV_DEBUG_DRIVER(drm->dev, "Bridge bus_flags: 0x%08X\n",
239 bus_flags);
240 DRM_DEV_DEBUG_DRIVER(drm->dev, "Mode flags: 0x%08X\n", m->flags);
241
242 /* Mandatory eLCDIF reset as per the Reference Manual */
243 lcdif_reset_block(lcdif);
244
245 lcdif_set_formats(lcdif, bus_format);
246
247 lcdif_set_mode(lcdif, bus_flags);
248 }
249
lcdif_crtc_atomic_check(struct drm_crtc * crtc,struct drm_atomic_state * state)250 static int lcdif_crtc_atomic_check(struct drm_crtc *crtc,
251 struct drm_atomic_state *state)
252 {
253 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
254 crtc);
255 bool has_primary = crtc_state->plane_mask &
256 drm_plane_mask(crtc->primary);
257
258 /* The primary plane has to be enabled when the CRTC is active. */
259 if (crtc_state->active && !has_primary)
260 return -EINVAL;
261
262 return drm_atomic_add_affected_planes(state, crtc);
263 }
264
lcdif_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_atomic_state * state)265 static void lcdif_crtc_atomic_flush(struct drm_crtc *crtc,
266 struct drm_atomic_state *state)
267 {
268 struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev);
269 struct drm_pending_vblank_event *event;
270 u32 reg;
271
272 reg = readl(lcdif->base + LCDC_V8_CTRLDESCL0_5);
273 reg |= CTRLDESCL0_5_SHADOW_LOAD_EN;
274 writel(reg, lcdif->base + LCDC_V8_CTRLDESCL0_5);
275
276 event = crtc->state->event;
277 crtc->state->event = NULL;
278
279 if (!event)
280 return;
281
282 spin_lock_irq(&crtc->dev->event_lock);
283 if (drm_crtc_vblank_get(crtc) == 0)
284 drm_crtc_arm_vblank_event(crtc, event);
285 else
286 drm_crtc_send_vblank_event(crtc, event);
287 spin_unlock_irq(&crtc->dev->event_lock);
288 }
289
lcdif_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_atomic_state * state)290 static void lcdif_crtc_atomic_enable(struct drm_crtc *crtc,
291 struct drm_atomic_state *state)
292 {
293 struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev);
294 struct drm_plane_state *new_pstate = drm_atomic_get_new_plane_state(state,
295 crtc->primary);
296 struct drm_display_mode *m = &lcdif->crtc.state->adjusted_mode;
297 struct drm_bridge_state *bridge_state = NULL;
298 struct drm_device *drm = lcdif->drm;
299 u32 bus_format = 0;
300 dma_addr_t paddr;
301
302 /* If there is a bridge attached to the LCDIF, use its bus format */
303 if (lcdif->bridge) {
304 bridge_state =
305 drm_atomic_get_new_bridge_state(state,
306 lcdif->bridge);
307 if (!bridge_state)
308 bus_format = MEDIA_BUS_FMT_FIXED;
309 else
310 bus_format = bridge_state->input_bus_cfg.format;
311
312 if (bus_format == MEDIA_BUS_FMT_FIXED) {
313 dev_warn_once(drm->dev,
314 "Bridge does not provide bus format, assuming MEDIA_BUS_FMT_RGB888_1X24.\n"
315 "Please fix bridge driver by handling atomic_get_input_bus_fmts.\n");
316 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
317 }
318 }
319
320 /* If all else fails, default to RGB888_1X24 */
321 if (!bus_format)
322 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
323
324 clk_set_rate(lcdif->clk, m->crtc_clock * 1000);
325
326 pm_runtime_get_sync(drm->dev);
327
328 lcdif_crtc_mode_set_nofb(lcdif, bridge_state, bus_format);
329
330 /* Write cur_buf as well to avoid an initial corrupt frame */
331 paddr = drm_fb_dma_get_gem_addr(new_pstate->fb, new_pstate, 0);
332 if (paddr) {
333 writel(lower_32_bits(paddr),
334 lcdif->base + LCDC_V8_CTRLDESCL_LOW0_4);
335 writel(CTRLDESCL_HIGH0_4_ADDR_HIGH(upper_32_bits(paddr)),
336 lcdif->base + LCDC_V8_CTRLDESCL_HIGH0_4);
337 }
338 lcdif_enable_controller(lcdif);
339
340 drm_crtc_vblank_on(crtc);
341 }
342
lcdif_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_atomic_state * state)343 static void lcdif_crtc_atomic_disable(struct drm_crtc *crtc,
344 struct drm_atomic_state *state)
345 {
346 struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev);
347 struct drm_device *drm = lcdif->drm;
348 struct drm_pending_vblank_event *event;
349
350 drm_crtc_vblank_off(crtc);
351
352 lcdif_disable_controller(lcdif);
353
354 spin_lock_irq(&drm->event_lock);
355 event = crtc->state->event;
356 if (event) {
357 crtc->state->event = NULL;
358 drm_crtc_send_vblank_event(crtc, event);
359 }
360 spin_unlock_irq(&drm->event_lock);
361
362 pm_runtime_put_sync(drm->dev);
363 }
364
lcdif_crtc_enable_vblank(struct drm_crtc * crtc)365 static int lcdif_crtc_enable_vblank(struct drm_crtc *crtc)
366 {
367 struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev);
368
369 /* Clear and enable VBLANK IRQ */
370 writel(INT_STATUS_D0_VS_BLANK, lcdif->base + LCDC_V8_INT_STATUS_D0);
371 writel(INT_ENABLE_D0_VS_BLANK_EN, lcdif->base + LCDC_V8_INT_ENABLE_D0);
372
373 return 0;
374 }
375
lcdif_crtc_disable_vblank(struct drm_crtc * crtc)376 static void lcdif_crtc_disable_vblank(struct drm_crtc *crtc)
377 {
378 struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev);
379
380 /* Disable and clear VBLANK IRQ */
381 writel(0, lcdif->base + LCDC_V8_INT_ENABLE_D0);
382 writel(INT_STATUS_D0_VS_BLANK, lcdif->base + LCDC_V8_INT_STATUS_D0);
383 }
384
385 static const struct drm_crtc_helper_funcs lcdif_crtc_helper_funcs = {
386 .atomic_check = lcdif_crtc_atomic_check,
387 .atomic_flush = lcdif_crtc_atomic_flush,
388 .atomic_enable = lcdif_crtc_atomic_enable,
389 .atomic_disable = lcdif_crtc_atomic_disable,
390 };
391
392 static const struct drm_crtc_funcs lcdif_crtc_funcs = {
393 .reset = drm_atomic_helper_crtc_reset,
394 .destroy = drm_crtc_cleanup,
395 .set_config = drm_atomic_helper_set_config,
396 .page_flip = drm_atomic_helper_page_flip,
397 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
398 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
399 .enable_vblank = lcdif_crtc_enable_vblank,
400 .disable_vblank = lcdif_crtc_disable_vblank,
401 };
402
403 /* -----------------------------------------------------------------------------
404 * Encoder
405 */
406
407 static const struct drm_encoder_funcs lcdif_encoder_funcs = {
408 .destroy = drm_encoder_cleanup,
409 };
410
411 /* -----------------------------------------------------------------------------
412 * Planes
413 */
414
lcdif_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)415 static int lcdif_plane_atomic_check(struct drm_plane *plane,
416 struct drm_atomic_state *state)
417 {
418 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state,
419 plane);
420 struct lcdif_drm_private *lcdif = to_lcdif_drm_private(plane->dev);
421 struct drm_crtc_state *crtc_state;
422
423 crtc_state = drm_atomic_get_new_crtc_state(state,
424 &lcdif->crtc);
425
426 return drm_atomic_helper_check_plane_state(plane_state, crtc_state,
427 DRM_PLANE_NO_SCALING,
428 DRM_PLANE_NO_SCALING,
429 false, true);
430 }
431
lcdif_plane_primary_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)432 static void lcdif_plane_primary_atomic_update(struct drm_plane *plane,
433 struct drm_atomic_state *state)
434 {
435 struct lcdif_drm_private *lcdif = to_lcdif_drm_private(plane->dev);
436 struct drm_plane_state *new_pstate = drm_atomic_get_new_plane_state(state,
437 plane);
438 dma_addr_t paddr;
439
440 paddr = drm_fb_dma_get_gem_addr(new_pstate->fb, new_pstate, 0);
441 if (paddr) {
442 writel(lower_32_bits(paddr),
443 lcdif->base + LCDC_V8_CTRLDESCL_LOW0_4);
444 writel(CTRLDESCL_HIGH0_4_ADDR_HIGH(upper_32_bits(paddr)),
445 lcdif->base + LCDC_V8_CTRLDESCL_HIGH0_4);
446 }
447 }
448
lcdif_format_mod_supported(struct drm_plane * plane,uint32_t format,uint64_t modifier)449 static bool lcdif_format_mod_supported(struct drm_plane *plane,
450 uint32_t format,
451 uint64_t modifier)
452 {
453 return modifier == DRM_FORMAT_MOD_LINEAR;
454 }
455
456 static const struct drm_plane_helper_funcs lcdif_plane_primary_helper_funcs = {
457 .atomic_check = lcdif_plane_atomic_check,
458 .atomic_update = lcdif_plane_primary_atomic_update,
459 };
460
461 static const struct drm_plane_funcs lcdif_plane_funcs = {
462 .format_mod_supported = lcdif_format_mod_supported,
463 .update_plane = drm_atomic_helper_update_plane,
464 .disable_plane = drm_atomic_helper_disable_plane,
465 .destroy = drm_plane_cleanup,
466 .reset = drm_atomic_helper_plane_reset,
467 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
468 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
469 };
470
471 static const u32 lcdif_primary_plane_formats[] = {
472 DRM_FORMAT_RGB565,
473 DRM_FORMAT_RGB888,
474 DRM_FORMAT_XBGR8888,
475 DRM_FORMAT_XRGB1555,
476 DRM_FORMAT_XRGB4444,
477 DRM_FORMAT_XRGB8888,
478 };
479
480 static const u64 lcdif_modifiers[] = {
481 DRM_FORMAT_MOD_LINEAR,
482 DRM_FORMAT_MOD_INVALID
483 };
484
485 /* -----------------------------------------------------------------------------
486 * Initialization
487 */
488
lcdif_kms_init(struct lcdif_drm_private * lcdif)489 int lcdif_kms_init(struct lcdif_drm_private *lcdif)
490 {
491 struct drm_encoder *encoder = &lcdif->encoder;
492 struct drm_crtc *crtc = &lcdif->crtc;
493 int ret;
494
495 drm_plane_helper_add(&lcdif->planes.primary,
496 &lcdif_plane_primary_helper_funcs);
497 ret = drm_universal_plane_init(lcdif->drm, &lcdif->planes.primary, 1,
498 &lcdif_plane_funcs,
499 lcdif_primary_plane_formats,
500 ARRAY_SIZE(lcdif_primary_plane_formats),
501 lcdif_modifiers, DRM_PLANE_TYPE_PRIMARY,
502 NULL);
503 if (ret)
504 return ret;
505
506 drm_crtc_helper_add(crtc, &lcdif_crtc_helper_funcs);
507 ret = drm_crtc_init_with_planes(lcdif->drm, crtc,
508 &lcdif->planes.primary, NULL,
509 &lcdif_crtc_funcs, NULL);
510 if (ret)
511 return ret;
512
513 encoder->possible_crtcs = drm_crtc_mask(crtc);
514 return drm_encoder_init(lcdif->drm, encoder, &lcdif_encoder_funcs,
515 DRM_MODE_ENCODER_NONE, NULL);
516 }
517