1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * This header defines architecture specific interfaces, x86 version
6 */
7
8 #ifndef _ASM_X86_KVM_HOST_H
9 #define _ASM_X86_KVM_HOST_H
10
11 #include <linux/types.h>
12 #include <linux/mm.h>
13 #include <linux/mmu_notifier.h>
14 #include <linux/tracepoint.h>
15 #include <linux/cpumask.h>
16 #include <linux/irq_work.h>
17 #include <linux/irq.h>
18 #include <linux/workqueue.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22 #include <linux/kvm_types.h>
23 #include <linux/perf_event.h>
24 #include <linux/pvclock_gtod.h>
25 #include <linux/clocksource.h>
26 #include <linux/irqbypass.h>
27 #include <linux/hyperv.h>
28
29 #include <asm/apic.h>
30 #include <asm/pvclock-abi.h>
31 #include <asm/desc.h>
32 #include <asm/mtrr.h>
33 #include <asm/msr-index.h>
34 #include <asm/asm.h>
35 #include <asm/kvm_page_track.h>
36 #include <asm/kvm_vcpu_regs.h>
37 #include <asm/hyperv-tlfs.h>
38
39 #define __KVM_HAVE_ARCH_VCPU_DEBUGFS
40
41 #define KVM_MAX_VCPUS 1024
42
43 /*
44 * In x86, the VCPU ID corresponds to the APIC ID, and APIC IDs
45 * might be larger than the actual number of VCPUs because the
46 * APIC ID encodes CPU topology information.
47 *
48 * In the worst case, we'll need less than one extra bit for the
49 * Core ID, and less than one extra bit for the Package (Die) ID,
50 * so ratio of 4 should be enough.
51 */
52 #define KVM_VCPU_ID_RATIO 4
53 #define KVM_MAX_VCPU_IDS (KVM_MAX_VCPUS * KVM_VCPU_ID_RATIO)
54
55 /* memory slots that are not exposed to userspace */
56 #define KVM_PRIVATE_MEM_SLOTS 3
57
58 #define KVM_HALT_POLL_NS_DEFAULT 200000
59
60 #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS
61
62 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
63 KVM_DIRTY_LOG_INITIALLY_SET)
64
65 #define KVM_BUS_LOCK_DETECTION_VALID_MODE (KVM_BUS_LOCK_DETECTION_OFF | \
66 KVM_BUS_LOCK_DETECTION_EXIT)
67
68 /* x86-specific vcpu->requests bit members */
69 #define KVM_REQ_MIGRATE_TIMER KVM_ARCH_REQ(0)
70 #define KVM_REQ_REPORT_TPR_ACCESS KVM_ARCH_REQ(1)
71 #define KVM_REQ_TRIPLE_FAULT KVM_ARCH_REQ(2)
72 #define KVM_REQ_MMU_SYNC KVM_ARCH_REQ(3)
73 #define KVM_REQ_CLOCK_UPDATE KVM_ARCH_REQ(4)
74 #define KVM_REQ_LOAD_MMU_PGD KVM_ARCH_REQ(5)
75 #define KVM_REQ_EVENT KVM_ARCH_REQ(6)
76 #define KVM_REQ_APF_HALT KVM_ARCH_REQ(7)
77 #define KVM_REQ_STEAL_UPDATE KVM_ARCH_REQ(8)
78 #define KVM_REQ_NMI KVM_ARCH_REQ(9)
79 #define KVM_REQ_PMU KVM_ARCH_REQ(10)
80 #define KVM_REQ_PMI KVM_ARCH_REQ(11)
81 #define KVM_REQ_SMI KVM_ARCH_REQ(12)
82 #define KVM_REQ_MASTERCLOCK_UPDATE KVM_ARCH_REQ(13)
83 #define KVM_REQ_MCLOCK_INPROGRESS \
84 KVM_ARCH_REQ_FLAGS(14, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
85 #define KVM_REQ_SCAN_IOAPIC \
86 KVM_ARCH_REQ_FLAGS(15, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
87 #define KVM_REQ_GLOBAL_CLOCK_UPDATE KVM_ARCH_REQ(16)
88 #define KVM_REQ_APIC_PAGE_RELOAD \
89 KVM_ARCH_REQ_FLAGS(17, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
90 #define KVM_REQ_HV_CRASH KVM_ARCH_REQ(18)
91 #define KVM_REQ_IOAPIC_EOI_EXIT KVM_ARCH_REQ(19)
92 #define KVM_REQ_HV_RESET KVM_ARCH_REQ(20)
93 #define KVM_REQ_HV_EXIT KVM_ARCH_REQ(21)
94 #define KVM_REQ_HV_STIMER KVM_ARCH_REQ(22)
95 #define KVM_REQ_LOAD_EOI_EXITMAP KVM_ARCH_REQ(23)
96 #define KVM_REQ_GET_NESTED_STATE_PAGES KVM_ARCH_REQ(24)
97 #define KVM_REQ_APICV_UPDATE \
98 KVM_ARCH_REQ_FLAGS(25, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
99 #define KVM_REQ_TLB_FLUSH_CURRENT KVM_ARCH_REQ(26)
100 #define KVM_REQ_TLB_FLUSH_GUEST \
101 KVM_ARCH_REQ_FLAGS(27, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
102 #define KVM_REQ_APF_READY KVM_ARCH_REQ(28)
103 #define KVM_REQ_MSR_FILTER_CHANGED KVM_ARCH_REQ(29)
104 #define KVM_REQ_UPDATE_CPU_DIRTY_LOGGING \
105 KVM_ARCH_REQ_FLAGS(30, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
106 #define KVM_REQ_MMU_FREE_OBSOLETE_ROOTS \
107 KVM_ARCH_REQ_FLAGS(31, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
108
109 #define CR0_RESERVED_BITS \
110 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
111 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
112 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
113
114 #define CR4_RESERVED_BITS \
115 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
116 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
117 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \
118 | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \
119 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \
120 | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP))
121
122 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
123
124
125
126 #define INVALID_PAGE (~(hpa_t)0)
127 #define VALID_PAGE(x) ((x) != INVALID_PAGE)
128
129 #define UNMAPPED_GVA (~(gpa_t)0)
130 #define INVALID_GPA (~(gpa_t)0)
131
132 /* KVM Hugepage definitions for x86 */
133 #define KVM_MAX_HUGEPAGE_LEVEL PG_LEVEL_1G
134 #define KVM_NR_PAGE_SIZES (KVM_MAX_HUGEPAGE_LEVEL - PG_LEVEL_4K + 1)
135 #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9)
136 #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x))
137 #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x))
138 #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1))
139 #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE)
140
141 #define KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO 50
142 #define KVM_MIN_ALLOC_MMU_PAGES 64UL
143 #define KVM_MMU_HASH_SHIFT 12
144 #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT)
145 #define KVM_MIN_FREE_MMU_PAGES 5
146 #define KVM_REFILL_PAGES 25
147 #define KVM_MAX_CPUID_ENTRIES 256
148 #define KVM_NR_FIXED_MTRR_REGION 88
149 #define KVM_NR_VAR_MTRR 8
150
151 #define ASYNC_PF_PER_VCPU 64
152
153 enum kvm_reg {
154 VCPU_REGS_RAX = __VCPU_REGS_RAX,
155 VCPU_REGS_RCX = __VCPU_REGS_RCX,
156 VCPU_REGS_RDX = __VCPU_REGS_RDX,
157 VCPU_REGS_RBX = __VCPU_REGS_RBX,
158 VCPU_REGS_RSP = __VCPU_REGS_RSP,
159 VCPU_REGS_RBP = __VCPU_REGS_RBP,
160 VCPU_REGS_RSI = __VCPU_REGS_RSI,
161 VCPU_REGS_RDI = __VCPU_REGS_RDI,
162 #ifdef CONFIG_X86_64
163 VCPU_REGS_R8 = __VCPU_REGS_R8,
164 VCPU_REGS_R9 = __VCPU_REGS_R9,
165 VCPU_REGS_R10 = __VCPU_REGS_R10,
166 VCPU_REGS_R11 = __VCPU_REGS_R11,
167 VCPU_REGS_R12 = __VCPU_REGS_R12,
168 VCPU_REGS_R13 = __VCPU_REGS_R13,
169 VCPU_REGS_R14 = __VCPU_REGS_R14,
170 VCPU_REGS_R15 = __VCPU_REGS_R15,
171 #endif
172 VCPU_REGS_RIP,
173 NR_VCPU_REGS,
174
175 VCPU_EXREG_PDPTR = NR_VCPU_REGS,
176 VCPU_EXREG_CR0,
177 VCPU_EXREG_CR3,
178 VCPU_EXREG_CR4,
179 VCPU_EXREG_RFLAGS,
180 VCPU_EXREG_SEGMENTS,
181 VCPU_EXREG_EXIT_INFO_1,
182 VCPU_EXREG_EXIT_INFO_2,
183 };
184
185 enum {
186 VCPU_SREG_ES,
187 VCPU_SREG_CS,
188 VCPU_SREG_SS,
189 VCPU_SREG_DS,
190 VCPU_SREG_FS,
191 VCPU_SREG_GS,
192 VCPU_SREG_TR,
193 VCPU_SREG_LDTR,
194 };
195
196 enum exit_fastpath_completion {
197 EXIT_FASTPATH_NONE,
198 EXIT_FASTPATH_REENTER_GUEST,
199 EXIT_FASTPATH_EXIT_HANDLED,
200 };
201 typedef enum exit_fastpath_completion fastpath_t;
202
203 struct x86_emulate_ctxt;
204 struct x86_exception;
205 enum x86_intercept;
206 enum x86_intercept_stage;
207
208 #define KVM_NR_DB_REGS 4
209
210 #define DR6_BUS_LOCK (1 << 11)
211 #define DR6_BD (1 << 13)
212 #define DR6_BS (1 << 14)
213 #define DR6_BT (1 << 15)
214 #define DR6_RTM (1 << 16)
215 /*
216 * DR6_ACTIVE_LOW combines fixed-1 and active-low bits.
217 * We can regard all the bits in DR6_FIXED_1 as active_low bits;
218 * they will never be 0 for now, but when they are defined
219 * in the future it will require no code change.
220 *
221 * DR6_ACTIVE_LOW is also used as the init/reset value for DR6.
222 */
223 #define DR6_ACTIVE_LOW 0xffff0ff0
224 #define DR6_VOLATILE 0x0001e80f
225 #define DR6_FIXED_1 (DR6_ACTIVE_LOW & ~DR6_VOLATILE)
226
227 #define DR7_BP_EN_MASK 0x000000ff
228 #define DR7_GE (1 << 9)
229 #define DR7_GD (1 << 13)
230 #define DR7_FIXED_1 0x00000400
231 #define DR7_VOLATILE 0xffff2bff
232
233 #define KVM_GUESTDBG_VALID_MASK \
234 (KVM_GUESTDBG_ENABLE | \
235 KVM_GUESTDBG_SINGLESTEP | \
236 KVM_GUESTDBG_USE_HW_BP | \
237 KVM_GUESTDBG_USE_SW_BP | \
238 KVM_GUESTDBG_INJECT_BP | \
239 KVM_GUESTDBG_INJECT_DB | \
240 KVM_GUESTDBG_BLOCKIRQ)
241
242
243 #define PFERR_PRESENT_BIT 0
244 #define PFERR_WRITE_BIT 1
245 #define PFERR_USER_BIT 2
246 #define PFERR_RSVD_BIT 3
247 #define PFERR_FETCH_BIT 4
248 #define PFERR_PK_BIT 5
249 #define PFERR_SGX_BIT 15
250 #define PFERR_GUEST_FINAL_BIT 32
251 #define PFERR_GUEST_PAGE_BIT 33
252 #define PFERR_IMPLICIT_ACCESS_BIT 48
253
254 #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT)
255 #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT)
256 #define PFERR_USER_MASK (1U << PFERR_USER_BIT)
257 #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT)
258 #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT)
259 #define PFERR_PK_MASK (1U << PFERR_PK_BIT)
260 #define PFERR_SGX_MASK (1U << PFERR_SGX_BIT)
261 #define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT)
262 #define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT)
263 #define PFERR_IMPLICIT_ACCESS (1ULL << PFERR_IMPLICIT_ACCESS_BIT)
264
265 #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \
266 PFERR_WRITE_MASK | \
267 PFERR_PRESENT_MASK)
268
269 /* apic attention bits */
270 #define KVM_APIC_CHECK_VAPIC 0
271 /*
272 * The following bit is set with PV-EOI, unset on EOI.
273 * We detect PV-EOI changes by guest by comparing
274 * this bit with PV-EOI in guest memory.
275 * See the implementation in apic_update_pv_eoi.
276 */
277 #define KVM_APIC_PV_EOI_PENDING 1
278
279 struct kvm_kernel_irq_routing_entry;
280
281 /*
282 * kvm_mmu_page_role tracks the properties of a shadow page (where shadow page
283 * also includes TDP pages) to determine whether or not a page can be used in
284 * the given MMU context. This is a subset of the overall kvm_cpu_role to
285 * minimize the size of kvm_memory_slot.arch.gfn_track, i.e. allows allocating
286 * 2 bytes per gfn instead of 4 bytes per gfn.
287 *
288 * Upper-level shadow pages having gptes are tracked for write-protection via
289 * gfn_track. As above, gfn_track is a 16 bit counter, so KVM must not create
290 * more than 2^16-1 upper-level shadow pages at a single gfn, otherwise
291 * gfn_track will overflow and explosions will ensure.
292 *
293 * A unique shadow page (SP) for a gfn is created if and only if an existing SP
294 * cannot be reused. The ability to reuse a SP is tracked by its role, which
295 * incorporates various mode bits and properties of the SP. Roughly speaking,
296 * the number of unique SPs that can theoretically be created is 2^n, where n
297 * is the number of bits that are used to compute the role.
298 *
299 * But, even though there are 19 bits in the mask below, not all combinations
300 * of modes and flags are possible:
301 *
302 * - invalid shadow pages are not accounted, so the bits are effectively 18
303 *
304 * - quadrant will only be used if has_4_byte_gpte=1 (non-PAE paging);
305 * execonly and ad_disabled are only used for nested EPT which has
306 * has_4_byte_gpte=0. Therefore, 2 bits are always unused.
307 *
308 * - the 4 bits of level are effectively limited to the values 2/3/4/5,
309 * as 4k SPs are not tracked (allowed to go unsync). In addition non-PAE
310 * paging has exactly one upper level, making level completely redundant
311 * when has_4_byte_gpte=1.
312 *
313 * - on top of this, smep_andnot_wp and smap_andnot_wp are only set if
314 * cr0_wp=0, therefore these three bits only give rise to 5 possibilities.
315 *
316 * Therefore, the maximum number of possible upper-level shadow pages for a
317 * single gfn is a bit less than 2^13.
318 */
319 union kvm_mmu_page_role {
320 u32 word;
321 struct {
322 unsigned level:4;
323 unsigned has_4_byte_gpte:1;
324 unsigned quadrant:2;
325 unsigned direct:1;
326 unsigned access:3;
327 unsigned invalid:1;
328 unsigned efer_nx:1;
329 unsigned cr0_wp:1;
330 unsigned smep_andnot_wp:1;
331 unsigned smap_andnot_wp:1;
332 unsigned ad_disabled:1;
333 unsigned guest_mode:1;
334 unsigned passthrough:1;
335 unsigned :5;
336
337 /*
338 * This is left at the top of the word so that
339 * kvm_memslots_for_spte_role can extract it with a
340 * simple shift. While there is room, give it a whole
341 * byte so it is also faster to load it from memory.
342 */
343 unsigned smm:8;
344 };
345 };
346
347 /*
348 * kvm_mmu_extended_role complements kvm_mmu_page_role, tracking properties
349 * relevant to the current MMU configuration. When loading CR0, CR4, or EFER,
350 * including on nested transitions, if nothing in the full role changes then
351 * MMU re-configuration can be skipped. @valid bit is set on first usage so we
352 * don't treat all-zero structure as valid data.
353 *
354 * The properties that are tracked in the extended role but not the page role
355 * are for things that either (a) do not affect the validity of the shadow page
356 * or (b) are indirectly reflected in the shadow page's role. For example,
357 * CR4.PKE only affects permission checks for software walks of the guest page
358 * tables (because KVM doesn't support Protection Keys with shadow paging), and
359 * CR0.PG, CR4.PAE, and CR4.PSE are indirectly reflected in role.level.
360 *
361 * Note, SMEP and SMAP are not redundant with sm*p_andnot_wp in the page role.
362 * If CR0.WP=1, KVM can reuse shadow pages for the guest regardless of SMEP and
363 * SMAP, but the MMU's permission checks for software walks need to be SMEP and
364 * SMAP aware regardless of CR0.WP.
365 */
366 union kvm_mmu_extended_role {
367 u32 word;
368 struct {
369 unsigned int valid:1;
370 unsigned int execonly:1;
371 unsigned int cr4_pse:1;
372 unsigned int cr4_pke:1;
373 unsigned int cr4_smap:1;
374 unsigned int cr4_smep:1;
375 unsigned int cr4_la57:1;
376 unsigned int efer_lma:1;
377 };
378 };
379
380 union kvm_cpu_role {
381 u64 as_u64;
382 struct {
383 union kvm_mmu_page_role base;
384 union kvm_mmu_extended_role ext;
385 };
386 };
387
388 struct kvm_rmap_head {
389 unsigned long val;
390 };
391
392 struct kvm_pio_request {
393 unsigned long linear_rip;
394 unsigned long count;
395 int in;
396 int port;
397 int size;
398 };
399
400 #define PT64_ROOT_MAX_LEVEL 5
401
402 struct rsvd_bits_validate {
403 u64 rsvd_bits_mask[2][PT64_ROOT_MAX_LEVEL];
404 u64 bad_mt_xwr;
405 };
406
407 struct kvm_mmu_root_info {
408 gpa_t pgd;
409 hpa_t hpa;
410 };
411
412 #define KVM_MMU_ROOT_INFO_INVALID \
413 ((struct kvm_mmu_root_info) { .pgd = INVALID_PAGE, .hpa = INVALID_PAGE })
414
415 #define KVM_MMU_NUM_PREV_ROOTS 3
416
417 #define KVM_HAVE_MMU_RWLOCK
418
419 struct kvm_mmu_page;
420 struct kvm_page_fault;
421
422 /*
423 * x86 supports 4 paging modes (5-level 64-bit, 4-level 64-bit, 3-level 32-bit,
424 * and 2-level 32-bit). The kvm_mmu structure abstracts the details of the
425 * current mmu mode.
426 */
427 struct kvm_mmu {
428 unsigned long (*get_guest_pgd)(struct kvm_vcpu *vcpu);
429 u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index);
430 int (*page_fault)(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault);
431 void (*inject_page_fault)(struct kvm_vcpu *vcpu,
432 struct x86_exception *fault);
433 gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
434 gpa_t gva_or_gpa, u64 access,
435 struct x86_exception *exception);
436 int (*sync_page)(struct kvm_vcpu *vcpu,
437 struct kvm_mmu_page *sp);
438 void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa);
439 struct kvm_mmu_root_info root;
440 union kvm_cpu_role cpu_role;
441 union kvm_mmu_page_role root_role;
442
443 /*
444 * The pkru_mask indicates if protection key checks are needed. It
445 * consists of 16 domains indexed by page fault error code bits [4:1],
446 * with PFEC.RSVD replaced by ACC_USER_MASK from the page tables.
447 * Each domain has 2 bits which are ANDed with AD and WD from PKRU.
448 */
449 u32 pkru_mask;
450
451 struct kvm_mmu_root_info prev_roots[KVM_MMU_NUM_PREV_ROOTS];
452
453 /*
454 * Bitmap; bit set = permission fault
455 * Byte index: page fault error code [4:1]
456 * Bit index: pte permissions in ACC_* format
457 */
458 u8 permissions[16];
459
460 u64 *pae_root;
461 u64 *pml4_root;
462 u64 *pml5_root;
463
464 /*
465 * check zero bits on shadow page table entries, these
466 * bits include not only hardware reserved bits but also
467 * the bits spte never used.
468 */
469 struct rsvd_bits_validate shadow_zero_check;
470
471 struct rsvd_bits_validate guest_rsvd_check;
472
473 u64 pdptrs[4]; /* pae */
474 };
475
476 struct kvm_tlb_range {
477 u64 start_gfn;
478 u64 pages;
479 };
480
481 enum pmc_type {
482 KVM_PMC_GP = 0,
483 KVM_PMC_FIXED,
484 };
485
486 struct kvm_pmc {
487 enum pmc_type type;
488 u8 idx;
489 u64 counter;
490 u64 eventsel;
491 struct perf_event *perf_event;
492 struct kvm_vcpu *vcpu;
493 /*
494 * eventsel value for general purpose counters,
495 * ctrl value for fixed counters.
496 */
497 u64 current_config;
498 bool is_paused;
499 bool intr;
500 };
501
502 #define KVM_PMC_MAX_FIXED 3
503 struct kvm_pmu {
504 unsigned nr_arch_gp_counters;
505 unsigned nr_arch_fixed_counters;
506 unsigned available_event_types;
507 u64 fixed_ctr_ctrl;
508 u64 fixed_ctr_ctrl_mask;
509 u64 global_ctrl;
510 u64 global_status;
511 u64 counter_bitmask[2];
512 u64 global_ctrl_mask;
513 u64 global_ovf_ctrl_mask;
514 u64 reserved_bits;
515 u64 raw_event_mask;
516 u8 version;
517 struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC];
518 struct kvm_pmc fixed_counters[KVM_PMC_MAX_FIXED];
519 struct irq_work irq_work;
520 DECLARE_BITMAP(reprogram_pmi, X86_PMC_IDX_MAX);
521 DECLARE_BITMAP(all_valid_pmc_idx, X86_PMC_IDX_MAX);
522 DECLARE_BITMAP(pmc_in_use, X86_PMC_IDX_MAX);
523
524 /*
525 * The gate to release perf_events not marked in
526 * pmc_in_use only once in a vcpu time slice.
527 */
528 bool need_cleanup;
529
530 /*
531 * The total number of programmed perf_events and it helps to avoid
532 * redundant check before cleanup if guest don't use vPMU at all.
533 */
534 u8 event_count;
535 };
536
537 struct kvm_pmu_ops;
538
539 enum {
540 KVM_DEBUGREG_BP_ENABLED = 1,
541 KVM_DEBUGREG_WONT_EXIT = 2,
542 };
543
544 struct kvm_mtrr_range {
545 u64 base;
546 u64 mask;
547 struct list_head node;
548 };
549
550 struct kvm_mtrr {
551 struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR];
552 mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION];
553 u64 deftype;
554
555 struct list_head head;
556 };
557
558 /* Hyper-V SynIC timer */
559 struct kvm_vcpu_hv_stimer {
560 struct hrtimer timer;
561 int index;
562 union hv_stimer_config config;
563 u64 count;
564 u64 exp_time;
565 struct hv_message msg;
566 bool msg_pending;
567 };
568
569 /* Hyper-V synthetic interrupt controller (SynIC)*/
570 struct kvm_vcpu_hv_synic {
571 u64 version;
572 u64 control;
573 u64 msg_page;
574 u64 evt_page;
575 atomic64_t sint[HV_SYNIC_SINT_COUNT];
576 atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT];
577 DECLARE_BITMAP(auto_eoi_bitmap, 256);
578 DECLARE_BITMAP(vec_bitmap, 256);
579 bool active;
580 bool dont_zero_synic_pages;
581 };
582
583 /* Hyper-V per vcpu emulation context */
584 struct kvm_vcpu_hv {
585 struct kvm_vcpu *vcpu;
586 u32 vp_index;
587 u64 hv_vapic;
588 s64 runtime_offset;
589 struct kvm_vcpu_hv_synic synic;
590 struct kvm_hyperv_exit exit;
591 struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT];
592 DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT);
593 bool enforce_cpuid;
594 struct {
595 u32 features_eax; /* HYPERV_CPUID_FEATURES.EAX */
596 u32 features_ebx; /* HYPERV_CPUID_FEATURES.EBX */
597 u32 features_edx; /* HYPERV_CPUID_FEATURES.EDX */
598 u32 enlightenments_eax; /* HYPERV_CPUID_ENLIGHTMENT_INFO.EAX */
599 u32 enlightenments_ebx; /* HYPERV_CPUID_ENLIGHTMENT_INFO.EBX */
600 u32 syndbg_cap_eax; /* HYPERV_CPUID_SYNDBG_PLATFORM_CAPABILITIES.EAX */
601 } cpuid_cache;
602 };
603
604 /* Xen HVM per vcpu emulation context */
605 struct kvm_vcpu_xen {
606 u64 hypercall_rip;
607 u32 current_runstate;
608 u8 upcall_vector;
609 struct gfn_to_pfn_cache vcpu_info_cache;
610 struct gfn_to_pfn_cache vcpu_time_info_cache;
611 struct gfn_to_pfn_cache runstate_cache;
612 u64 last_steal;
613 u64 runstate_entry_time;
614 u64 runstate_times[4];
615 unsigned long evtchn_pending_sel;
616 u32 vcpu_id; /* The Xen / ACPI vCPU ID */
617 u32 timer_virq;
618 u64 timer_expires; /* In guest epoch */
619 atomic_t timer_pending;
620 struct hrtimer timer;
621 int poll_evtchn;
622 struct timer_list poll_timer;
623 };
624
625 struct kvm_vcpu_arch {
626 /*
627 * rip and regs accesses must go through
628 * kvm_{register,rip}_{read,write} functions.
629 */
630 unsigned long regs[NR_VCPU_REGS];
631 u32 regs_avail;
632 u32 regs_dirty;
633
634 unsigned long cr0;
635 unsigned long cr0_guest_owned_bits;
636 unsigned long cr2;
637 unsigned long cr3;
638 unsigned long cr4;
639 unsigned long cr4_guest_owned_bits;
640 unsigned long cr4_guest_rsvd_bits;
641 unsigned long cr8;
642 u32 host_pkru;
643 u32 pkru;
644 u32 hflags;
645 u64 efer;
646 u64 apic_base;
647 struct kvm_lapic *apic; /* kernel irqchip context */
648 bool apicv_active;
649 bool load_eoi_exitmap_pending;
650 DECLARE_BITMAP(ioapic_handled_vectors, 256);
651 unsigned long apic_attention;
652 int32_t apic_arb_prio;
653 int mp_state;
654 u64 ia32_misc_enable_msr;
655 u64 smbase;
656 u64 smi_count;
657 bool at_instruction_boundary;
658 bool tpr_access_reporting;
659 bool xsaves_enabled;
660 bool xfd_no_write_intercept;
661 u64 ia32_xss;
662 u64 microcode_version;
663 u64 arch_capabilities;
664 u64 perf_capabilities;
665
666 /*
667 * Paging state of the vcpu
668 *
669 * If the vcpu runs in guest mode with two level paging this still saves
670 * the paging mode of the l1 guest. This context is always used to
671 * handle faults.
672 */
673 struct kvm_mmu *mmu;
674
675 /* Non-nested MMU for L1 */
676 struct kvm_mmu root_mmu;
677
678 /* L1 MMU when running nested */
679 struct kvm_mmu guest_mmu;
680
681 /*
682 * Paging state of an L2 guest (used for nested npt)
683 *
684 * This context will save all necessary information to walk page tables
685 * of an L2 guest. This context is only initialized for page table
686 * walking and not for faulting since we never handle l2 page faults on
687 * the host.
688 */
689 struct kvm_mmu nested_mmu;
690
691 /*
692 * Pointer to the mmu context currently used for
693 * gva_to_gpa translations.
694 */
695 struct kvm_mmu *walk_mmu;
696
697 struct kvm_mmu_memory_cache mmu_pte_list_desc_cache;
698 struct kvm_mmu_memory_cache mmu_shadow_page_cache;
699 struct kvm_mmu_memory_cache mmu_gfn_array_cache;
700 struct kvm_mmu_memory_cache mmu_page_header_cache;
701
702 /*
703 * QEMU userspace and the guest each have their own FPU state.
704 * In vcpu_run, we switch between the user and guest FPU contexts.
705 * While running a VCPU, the VCPU thread will have the guest FPU
706 * context.
707 *
708 * Note that while the PKRU state lives inside the fpu registers,
709 * it is switched out separately at VMENTER and VMEXIT time. The
710 * "guest_fpstate" state here contains the guest FPU context, with the
711 * host PRKU bits.
712 */
713 struct fpu_guest guest_fpu;
714
715 u64 xcr0;
716
717 struct kvm_pio_request pio;
718 void *pio_data;
719 void *sev_pio_data;
720 unsigned sev_pio_count;
721
722 u8 event_exit_inst_len;
723
724 struct kvm_queued_exception {
725 bool pending;
726 bool injected;
727 bool has_error_code;
728 u8 nr;
729 u32 error_code;
730 unsigned long payload;
731 bool has_payload;
732 u8 nested_apf;
733 } exception;
734
735 struct kvm_queued_interrupt {
736 bool injected;
737 bool soft;
738 u8 nr;
739 } interrupt;
740
741 int halt_request; /* real mode on Intel only */
742
743 int cpuid_nent;
744 struct kvm_cpuid_entry2 *cpuid_entries;
745 u32 kvm_cpuid_base;
746
747 u64 reserved_gpa_bits;
748 int maxphyaddr;
749
750 /* emulate context */
751
752 struct x86_emulate_ctxt *emulate_ctxt;
753 bool emulate_regs_need_sync_to_vcpu;
754 bool emulate_regs_need_sync_from_vcpu;
755 int (*complete_userspace_io)(struct kvm_vcpu *vcpu);
756
757 gpa_t time;
758 struct pvclock_vcpu_time_info hv_clock;
759 unsigned int hw_tsc_khz;
760 struct gfn_to_pfn_cache pv_time;
761 /* set guest stopped flag in pvclock flags field */
762 bool pvclock_set_guest_stopped_request;
763
764 struct {
765 u8 preempted;
766 u64 msr_val;
767 u64 last_steal;
768 struct gfn_to_hva_cache cache;
769 } st;
770
771 u64 l1_tsc_offset;
772 u64 tsc_offset; /* current tsc offset */
773 u64 last_guest_tsc;
774 u64 last_host_tsc;
775 u64 tsc_offset_adjustment;
776 u64 this_tsc_nsec;
777 u64 this_tsc_write;
778 u64 this_tsc_generation;
779 bool tsc_catchup;
780 bool tsc_always_catchup;
781 s8 virtual_tsc_shift;
782 u32 virtual_tsc_mult;
783 u32 virtual_tsc_khz;
784 s64 ia32_tsc_adjust_msr;
785 u64 msr_ia32_power_ctl;
786 u64 l1_tsc_scaling_ratio;
787 u64 tsc_scaling_ratio; /* current scaling ratio */
788
789 atomic_t nmi_queued; /* unprocessed asynchronous NMIs */
790 unsigned nmi_pending; /* NMI queued after currently running handler */
791 bool nmi_injected; /* Trying to inject an NMI this entry */
792 bool smi_pending; /* SMI queued after currently running handler */
793 u8 handling_intr_from_guest;
794
795 struct kvm_mtrr mtrr_state;
796 u64 pat;
797
798 unsigned switch_db_regs;
799 unsigned long db[KVM_NR_DB_REGS];
800 unsigned long dr6;
801 unsigned long dr7;
802 unsigned long eff_db[KVM_NR_DB_REGS];
803 unsigned long guest_debug_dr7;
804 u64 msr_platform_info;
805 u64 msr_misc_features_enables;
806
807 u64 mcg_cap;
808 u64 mcg_status;
809 u64 mcg_ctl;
810 u64 mcg_ext_ctl;
811 u64 *mce_banks;
812
813 /* Cache MMIO info */
814 u64 mmio_gva;
815 unsigned mmio_access;
816 gfn_t mmio_gfn;
817 u64 mmio_gen;
818
819 struct kvm_pmu pmu;
820
821 /* used for guest single stepping over the given code position */
822 unsigned long singlestep_rip;
823
824 bool hyperv_enabled;
825 struct kvm_vcpu_hv *hyperv;
826 struct kvm_vcpu_xen xen;
827
828 cpumask_var_t wbinvd_dirty_mask;
829
830 unsigned long last_retry_eip;
831 unsigned long last_retry_addr;
832
833 struct {
834 bool halted;
835 gfn_t gfns[ASYNC_PF_PER_VCPU];
836 struct gfn_to_hva_cache data;
837 u64 msr_en_val; /* MSR_KVM_ASYNC_PF_EN */
838 u64 msr_int_val; /* MSR_KVM_ASYNC_PF_INT */
839 u16 vec;
840 u32 id;
841 bool send_user_only;
842 u32 host_apf_flags;
843 unsigned long nested_apf_token;
844 bool delivery_as_pf_vmexit;
845 bool pageready_pending;
846 } apf;
847
848 /* OSVW MSRs (AMD only) */
849 struct {
850 u64 length;
851 u64 status;
852 } osvw;
853
854 struct {
855 u64 msr_val;
856 struct gfn_to_hva_cache data;
857 } pv_eoi;
858
859 u64 msr_kvm_poll_control;
860
861 /*
862 * Indicates the guest is trying to write a gfn that contains one or
863 * more of the PTEs used to translate the write itself, i.e. the access
864 * is changing its own translation in the guest page tables. KVM exits
865 * to userspace if emulation of the faulting instruction fails and this
866 * flag is set, as KVM cannot make forward progress.
867 *
868 * If emulation fails for a write to guest page tables, KVM unprotects
869 * (zaps) the shadow page for the target gfn and resumes the guest to
870 * retry the non-emulatable instruction (on hardware). Unprotecting the
871 * gfn doesn't allow forward progress for a self-changing access because
872 * doing so also zaps the translation for the gfn, i.e. retrying the
873 * instruction will hit a !PRESENT fault, which results in a new shadow
874 * page and sends KVM back to square one.
875 */
876 bool write_fault_to_shadow_pgtable;
877
878 /* set at EPT violation at this point */
879 unsigned long exit_qualification;
880
881 /* pv related host specific info */
882 struct {
883 bool pv_unhalted;
884 } pv;
885
886 int pending_ioapic_eoi;
887 int pending_external_vector;
888
889 /* be preempted when it's in kernel-mode(cpl=0) */
890 bool preempted_in_kernel;
891
892 /* Flush the L1 Data cache for L1TF mitigation on VMENTER */
893 bool l1tf_flush_l1d;
894
895 /* Host CPU on which VM-entry was most recently attempted */
896 int last_vmentry_cpu;
897
898 /* AMD MSRC001_0015 Hardware Configuration */
899 u64 msr_hwcr;
900
901 /* pv related cpuid info */
902 struct {
903 /*
904 * value of the eax register in the KVM_CPUID_FEATURES CPUID
905 * leaf.
906 */
907 u32 features;
908
909 /*
910 * indicates whether pv emulation should be disabled if features
911 * are not present in the guest's cpuid
912 */
913 bool enforce;
914 } pv_cpuid;
915
916 /* Protected Guests */
917 bool guest_state_protected;
918
919 /*
920 * Set when PDPTS were loaded directly by the userspace without
921 * reading the guest memory
922 */
923 bool pdptrs_from_userspace;
924
925 #if IS_ENABLED(CONFIG_HYPERV)
926 hpa_t hv_root_tdp;
927 #endif
928 };
929
930 struct kvm_lpage_info {
931 int disallow_lpage;
932 };
933
934 struct kvm_arch_memory_slot {
935 struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES];
936 struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1];
937 unsigned short *gfn_track[KVM_PAGE_TRACK_MAX];
938 };
939
940 /*
941 * We use as the mode the number of bits allocated in the LDR for the
942 * logical processor ID. It happens that these are all powers of two.
943 * This makes it is very easy to detect cases where the APICs are
944 * configured for multiple modes; in that case, we cannot use the map and
945 * hence cannot use kvm_irq_delivery_to_apic_fast either.
946 */
947 #define KVM_APIC_MODE_XAPIC_CLUSTER 4
948 #define KVM_APIC_MODE_XAPIC_FLAT 8
949 #define KVM_APIC_MODE_X2APIC 16
950
951 struct kvm_apic_map {
952 struct rcu_head rcu;
953 u8 mode;
954 u32 max_apic_id;
955 union {
956 struct kvm_lapic *xapic_flat_map[8];
957 struct kvm_lapic *xapic_cluster_map[16][4];
958 };
959 struct kvm_lapic *phys_map[];
960 };
961
962 /* Hyper-V synthetic debugger (SynDbg)*/
963 struct kvm_hv_syndbg {
964 struct {
965 u64 control;
966 u64 status;
967 u64 send_page;
968 u64 recv_page;
969 u64 pending_page;
970 } control;
971 u64 options;
972 };
973
974 /* Current state of Hyper-V TSC page clocksource */
975 enum hv_tsc_page_status {
976 /* TSC page was not set up or disabled */
977 HV_TSC_PAGE_UNSET = 0,
978 /* TSC page MSR was written by the guest, update pending */
979 HV_TSC_PAGE_GUEST_CHANGED,
980 /* TSC page update was triggered from the host side */
981 HV_TSC_PAGE_HOST_CHANGED,
982 /* TSC page was properly set up and is currently active */
983 HV_TSC_PAGE_SET,
984 /* TSC page was set up with an inaccessible GPA */
985 HV_TSC_PAGE_BROKEN,
986 };
987
988 /* Hyper-V emulation context */
989 struct kvm_hv {
990 struct mutex hv_lock;
991 u64 hv_guest_os_id;
992 u64 hv_hypercall;
993 u64 hv_tsc_page;
994 enum hv_tsc_page_status hv_tsc_page_status;
995
996 /* Hyper-v based guest crash (NT kernel bugcheck) parameters */
997 u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS];
998 u64 hv_crash_ctl;
999
1000 struct ms_hyperv_tsc_page tsc_ref;
1001
1002 struct idr conn_to_evt;
1003
1004 u64 hv_reenlightenment_control;
1005 u64 hv_tsc_emulation_control;
1006 u64 hv_tsc_emulation_status;
1007
1008 /* How many vCPUs have VP index != vCPU index */
1009 atomic_t num_mismatched_vp_indexes;
1010
1011 /*
1012 * How many SynICs use 'AutoEOI' feature
1013 * (protected by arch.apicv_update_lock)
1014 */
1015 unsigned int synic_auto_eoi_used;
1016
1017 struct hv_partition_assist_pg *hv_pa_pg;
1018 struct kvm_hv_syndbg hv_syndbg;
1019 };
1020
1021 struct msr_bitmap_range {
1022 u32 flags;
1023 u32 nmsrs;
1024 u32 base;
1025 unsigned long *bitmap;
1026 };
1027
1028 /* Xen emulation context */
1029 struct kvm_xen {
1030 u32 xen_version;
1031 bool long_mode;
1032 u8 upcall_vector;
1033 struct gfn_to_pfn_cache shinfo_cache;
1034 struct idr evtchn_ports;
1035 unsigned long poll_mask[BITS_TO_LONGS(KVM_MAX_VCPUS)];
1036 };
1037
1038 enum kvm_irqchip_mode {
1039 KVM_IRQCHIP_NONE,
1040 KVM_IRQCHIP_KERNEL, /* created with KVM_CREATE_IRQCHIP */
1041 KVM_IRQCHIP_SPLIT, /* created with KVM_CAP_SPLIT_IRQCHIP */
1042 };
1043
1044 struct kvm_x86_msr_filter {
1045 u8 count;
1046 bool default_allow:1;
1047 struct msr_bitmap_range ranges[16];
1048 };
1049
1050 enum kvm_apicv_inhibit {
1051
1052 /********************************************************************/
1053 /* INHIBITs that are relevant to both Intel's APICv and AMD's AVIC. */
1054 /********************************************************************/
1055
1056 /*
1057 * APIC acceleration is disabled by a module parameter
1058 * and/or not supported in hardware.
1059 */
1060 APICV_INHIBIT_REASON_DISABLE,
1061
1062 /*
1063 * APIC acceleration is inhibited because AutoEOI feature is
1064 * being used by a HyperV guest.
1065 */
1066 APICV_INHIBIT_REASON_HYPERV,
1067
1068 /*
1069 * APIC acceleration is inhibited because the userspace didn't yet
1070 * enable the kernel/split irqchip.
1071 */
1072 APICV_INHIBIT_REASON_ABSENT,
1073
1074 /* APIC acceleration is inhibited because KVM_GUESTDBG_BLOCKIRQ
1075 * (out of band, debug measure of blocking all interrupts on this vCPU)
1076 * was enabled, to avoid AVIC/APICv bypassing it.
1077 */
1078 APICV_INHIBIT_REASON_BLOCKIRQ,
1079
1080 /*
1081 * For simplicity, the APIC acceleration is inhibited
1082 * first time either APIC ID or APIC base are changed by the guest
1083 * from their reset values.
1084 */
1085 APICV_INHIBIT_REASON_APIC_ID_MODIFIED,
1086 APICV_INHIBIT_REASON_APIC_BASE_MODIFIED,
1087
1088 /******************************************************/
1089 /* INHIBITs that are relevant only to the AMD's AVIC. */
1090 /******************************************************/
1091
1092 /*
1093 * AVIC is inhibited on a vCPU because it runs a nested guest.
1094 *
1095 * This is needed because unlike APICv, the peers of this vCPU
1096 * cannot use the doorbell mechanism to signal interrupts via AVIC when
1097 * a vCPU runs nested.
1098 */
1099 APICV_INHIBIT_REASON_NESTED,
1100
1101 /*
1102 * On SVM, the wait for the IRQ window is implemented with pending vIRQ,
1103 * which cannot be injected when the AVIC is enabled, thus AVIC
1104 * is inhibited while KVM waits for IRQ window.
1105 */
1106 APICV_INHIBIT_REASON_IRQWIN,
1107
1108 /*
1109 * PIT (i8254) 're-inject' mode, relies on EOI intercept,
1110 * which AVIC doesn't support for edge triggered interrupts.
1111 */
1112 APICV_INHIBIT_REASON_PIT_REINJ,
1113
1114 /*
1115 * AVIC is inhibited because the guest has x2apic in its CPUID.
1116 */
1117 APICV_INHIBIT_REASON_X2APIC,
1118
1119 /*
1120 * AVIC is disabled because SEV doesn't support it.
1121 */
1122 APICV_INHIBIT_REASON_SEV,
1123 };
1124
1125 struct kvm_arch {
1126 unsigned long n_used_mmu_pages;
1127 unsigned long n_requested_mmu_pages;
1128 unsigned long n_max_mmu_pages;
1129 unsigned int indirect_shadow_pages;
1130 u8 mmu_valid_gen;
1131 struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES];
1132 struct list_head active_mmu_pages;
1133 struct list_head zapped_obsolete_pages;
1134 struct list_head lpage_disallowed_mmu_pages;
1135 struct kvm_page_track_notifier_node mmu_sp_tracker;
1136 struct kvm_page_track_notifier_head track_notifier_head;
1137 /*
1138 * Protects marking pages unsync during page faults, as TDP MMU page
1139 * faults only take mmu_lock for read. For simplicity, the unsync
1140 * pages lock is always taken when marking pages unsync regardless of
1141 * whether mmu_lock is held for read or write.
1142 */
1143 spinlock_t mmu_unsync_pages_lock;
1144
1145 struct list_head assigned_dev_head;
1146 struct iommu_domain *iommu_domain;
1147 bool iommu_noncoherent;
1148 #define __KVM_HAVE_ARCH_NONCOHERENT_DMA
1149 atomic_t noncoherent_dma_count;
1150 #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE
1151 atomic_t assigned_device_count;
1152 struct kvm_pic *vpic;
1153 struct kvm_ioapic *vioapic;
1154 struct kvm_pit *vpit;
1155 atomic_t vapics_in_nmi_mode;
1156 struct mutex apic_map_lock;
1157 struct kvm_apic_map __rcu *apic_map;
1158 atomic_t apic_map_dirty;
1159
1160 /* Protects apic_access_memslot_enabled and apicv_inhibit_reasons */
1161 struct rw_semaphore apicv_update_lock;
1162
1163 bool apic_access_memslot_enabled;
1164 unsigned long apicv_inhibit_reasons;
1165
1166 gpa_t wall_clock;
1167
1168 bool mwait_in_guest;
1169 bool hlt_in_guest;
1170 bool pause_in_guest;
1171 bool cstate_in_guest;
1172
1173 unsigned long irq_sources_bitmap;
1174 s64 kvmclock_offset;
1175
1176 /*
1177 * This also protects nr_vcpus_matched_tsc which is read from a
1178 * preemption-disabled region, so it must be a raw spinlock.
1179 */
1180 raw_spinlock_t tsc_write_lock;
1181 u64 last_tsc_nsec;
1182 u64 last_tsc_write;
1183 u32 last_tsc_khz;
1184 u64 last_tsc_offset;
1185 u64 cur_tsc_nsec;
1186 u64 cur_tsc_write;
1187 u64 cur_tsc_offset;
1188 u64 cur_tsc_generation;
1189 int nr_vcpus_matched_tsc;
1190
1191 u32 default_tsc_khz;
1192
1193 seqcount_raw_spinlock_t pvclock_sc;
1194 bool use_master_clock;
1195 u64 master_kernel_ns;
1196 u64 master_cycle_now;
1197 struct delayed_work kvmclock_update_work;
1198 struct delayed_work kvmclock_sync_work;
1199
1200 struct kvm_xen_hvm_config xen_hvm_config;
1201
1202 /* reads protected by irq_srcu, writes by irq_lock */
1203 struct hlist_head mask_notifier_list;
1204
1205 struct kvm_hv hyperv;
1206 struct kvm_xen xen;
1207
1208 bool backwards_tsc_observed;
1209 bool boot_vcpu_runs_old_kvmclock;
1210 u32 bsp_vcpu_id;
1211
1212 u64 disabled_quirks;
1213 int cpu_dirty_logging_count;
1214
1215 enum kvm_irqchip_mode irqchip_mode;
1216 u8 nr_reserved_ioapic_pins;
1217
1218 bool disabled_lapic_found;
1219
1220 bool x2apic_format;
1221 bool x2apic_broadcast_quirk_disabled;
1222
1223 bool guest_can_read_msr_platform_info;
1224 bool exception_payload_enabled;
1225
1226 bool bus_lock_detection_enabled;
1227 bool enable_pmu;
1228 /*
1229 * If exit_on_emulation_error is set, and the in-kernel instruction
1230 * emulator fails to emulate an instruction, allow userspace
1231 * the opportunity to look at it.
1232 */
1233 bool exit_on_emulation_error;
1234
1235 /* Deflect RDMSR and WRMSR to user space when they trigger a #GP */
1236 u32 user_space_msr_mask;
1237 struct kvm_x86_msr_filter __rcu *msr_filter;
1238
1239 u32 hypercall_exit_enabled;
1240
1241 /* Guest can access the SGX PROVISIONKEY. */
1242 bool sgx_provisioning_allowed;
1243
1244 struct kvm_pmu_event_filter __rcu *pmu_event_filter;
1245 struct task_struct *nx_lpage_recovery_thread;
1246
1247 #ifdef CONFIG_X86_64
1248 /*
1249 * Whether the TDP MMU is enabled for this VM. This contains a
1250 * snapshot of the TDP MMU module parameter from when the VM was
1251 * created and remains unchanged for the life of the VM. If this is
1252 * true, TDP MMU handler functions will run for various MMU
1253 * operations.
1254 */
1255 bool tdp_mmu_enabled;
1256
1257 /*
1258 * List of struct kvm_mmu_pages being used as roots.
1259 * All struct kvm_mmu_pages in the list should have
1260 * tdp_mmu_page set.
1261 *
1262 * For reads, this list is protected by:
1263 * the MMU lock in read mode + RCU or
1264 * the MMU lock in write mode
1265 *
1266 * For writes, this list is protected by:
1267 * the MMU lock in read mode + the tdp_mmu_pages_lock or
1268 * the MMU lock in write mode
1269 *
1270 * Roots will remain in the list until their tdp_mmu_root_count
1271 * drops to zero, at which point the thread that decremented the
1272 * count to zero should removed the root from the list and clean
1273 * it up, freeing the root after an RCU grace period.
1274 */
1275 struct list_head tdp_mmu_roots;
1276
1277 /*
1278 * List of struct kvmp_mmu_pages not being used as roots.
1279 * All struct kvm_mmu_pages in the list should have
1280 * tdp_mmu_page set and a tdp_mmu_root_count of 0.
1281 */
1282 struct list_head tdp_mmu_pages;
1283
1284 /*
1285 * Protects accesses to the following fields when the MMU lock
1286 * is held in read mode:
1287 * - tdp_mmu_roots (above)
1288 * - tdp_mmu_pages (above)
1289 * - the link field of struct kvm_mmu_pages used by the TDP MMU
1290 * - lpage_disallowed_mmu_pages
1291 * - the lpage_disallowed_link field of struct kvm_mmu_pages used
1292 * by the TDP MMU
1293 * It is acceptable, but not necessary, to acquire this lock when
1294 * the thread holds the MMU lock in write mode.
1295 */
1296 spinlock_t tdp_mmu_pages_lock;
1297 struct workqueue_struct *tdp_mmu_zap_wq;
1298 #endif /* CONFIG_X86_64 */
1299
1300 /*
1301 * If set, at least one shadow root has been allocated. This flag
1302 * is used as one input when determining whether certain memslot
1303 * related allocations are necessary.
1304 */
1305 bool shadow_root_allocated;
1306
1307 #if IS_ENABLED(CONFIG_HYPERV)
1308 hpa_t hv_root_tdp;
1309 spinlock_t hv_root_tdp_lock;
1310 #endif
1311 };
1312
1313 struct kvm_vm_stat {
1314 struct kvm_vm_stat_generic generic;
1315 u64 mmu_shadow_zapped;
1316 u64 mmu_pte_write;
1317 u64 mmu_pde_zapped;
1318 u64 mmu_flooded;
1319 u64 mmu_recycled;
1320 u64 mmu_cache_miss;
1321 u64 mmu_unsync;
1322 union {
1323 struct {
1324 atomic64_t pages_4k;
1325 atomic64_t pages_2m;
1326 atomic64_t pages_1g;
1327 };
1328 atomic64_t pages[KVM_NR_PAGE_SIZES];
1329 };
1330 u64 nx_lpage_splits;
1331 u64 max_mmu_page_hash_collisions;
1332 u64 max_mmu_rmap_size;
1333 };
1334
1335 struct kvm_vcpu_stat {
1336 struct kvm_vcpu_stat_generic generic;
1337 u64 pf_taken;
1338 u64 pf_fixed;
1339 u64 pf_emulate;
1340 u64 pf_spurious;
1341 u64 pf_fast;
1342 u64 pf_mmio_spte_created;
1343 u64 pf_guest;
1344 u64 tlb_flush;
1345 u64 invlpg;
1346
1347 u64 exits;
1348 u64 io_exits;
1349 u64 mmio_exits;
1350 u64 signal_exits;
1351 u64 irq_window_exits;
1352 u64 nmi_window_exits;
1353 u64 l1d_flush;
1354 u64 halt_exits;
1355 u64 request_irq_exits;
1356 u64 irq_exits;
1357 u64 host_state_reload;
1358 u64 fpu_reload;
1359 u64 insn_emulation;
1360 u64 insn_emulation_fail;
1361 u64 hypercalls;
1362 u64 irq_injections;
1363 u64 nmi_injections;
1364 u64 req_event;
1365 u64 nested_run;
1366 u64 directed_yield_attempted;
1367 u64 directed_yield_successful;
1368 u64 preemption_reported;
1369 u64 preemption_other;
1370 u64 guest_mode;
1371 };
1372
1373 struct x86_instruction_info;
1374
1375 struct msr_data {
1376 bool host_initiated;
1377 u32 index;
1378 u64 data;
1379 };
1380
1381 struct kvm_lapic_irq {
1382 u32 vector;
1383 u16 delivery_mode;
1384 u16 dest_mode;
1385 bool level;
1386 u16 trig_mode;
1387 u32 shorthand;
1388 u32 dest_id;
1389 bool msi_redir_hint;
1390 };
1391
kvm_lapic_irq_dest_mode(bool dest_mode_logical)1392 static inline u16 kvm_lapic_irq_dest_mode(bool dest_mode_logical)
1393 {
1394 return dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL;
1395 }
1396
1397 struct kvm_x86_ops {
1398 const char *name;
1399
1400 int (*hardware_enable)(void);
1401 void (*hardware_disable)(void);
1402 void (*hardware_unsetup)(void);
1403 bool (*has_emulated_msr)(struct kvm *kvm, u32 index);
1404 void (*vcpu_after_set_cpuid)(struct kvm_vcpu *vcpu);
1405
1406 unsigned int vm_size;
1407 int (*vm_init)(struct kvm *kvm);
1408 void (*vm_destroy)(struct kvm *kvm);
1409
1410 /* Create, but do not attach this VCPU */
1411 int (*vcpu_create)(struct kvm_vcpu *vcpu);
1412 void (*vcpu_free)(struct kvm_vcpu *vcpu);
1413 void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event);
1414
1415 void (*prepare_switch_to_guest)(struct kvm_vcpu *vcpu);
1416 void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu);
1417 void (*vcpu_put)(struct kvm_vcpu *vcpu);
1418
1419 void (*update_exception_bitmap)(struct kvm_vcpu *vcpu);
1420 int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr);
1421 int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr);
1422 u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg);
1423 void (*get_segment)(struct kvm_vcpu *vcpu,
1424 struct kvm_segment *var, int seg);
1425 int (*get_cpl)(struct kvm_vcpu *vcpu);
1426 void (*set_segment)(struct kvm_vcpu *vcpu,
1427 struct kvm_segment *var, int seg);
1428 void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l);
1429 void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0);
1430 void (*post_set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3);
1431 bool (*is_valid_cr4)(struct kvm_vcpu *vcpu, unsigned long cr0);
1432 void (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4);
1433 int (*set_efer)(struct kvm_vcpu *vcpu, u64 efer);
1434 void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
1435 void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
1436 void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
1437 void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
1438 void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu);
1439 void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value);
1440 void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg);
1441 unsigned long (*get_rflags)(struct kvm_vcpu *vcpu);
1442 void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags);
1443 bool (*get_if_flag)(struct kvm_vcpu *vcpu);
1444
1445 void (*flush_tlb_all)(struct kvm_vcpu *vcpu);
1446 void (*flush_tlb_current)(struct kvm_vcpu *vcpu);
1447 int (*tlb_remote_flush)(struct kvm *kvm);
1448 int (*tlb_remote_flush_with_range)(struct kvm *kvm,
1449 struct kvm_tlb_range *range);
1450
1451 /*
1452 * Flush any TLB entries associated with the given GVA.
1453 * Does not need to flush GPA->HPA mappings.
1454 * Can potentially get non-canonical addresses through INVLPGs, which
1455 * the implementation may choose to ignore if appropriate.
1456 */
1457 void (*flush_tlb_gva)(struct kvm_vcpu *vcpu, gva_t addr);
1458
1459 /*
1460 * Flush any TLB entries created by the guest. Like tlb_flush_gva(),
1461 * does not need to flush GPA->HPA mappings.
1462 */
1463 void (*flush_tlb_guest)(struct kvm_vcpu *vcpu);
1464
1465 int (*vcpu_pre_run)(struct kvm_vcpu *vcpu);
1466 enum exit_fastpath_completion (*vcpu_run)(struct kvm_vcpu *vcpu);
1467 int (*handle_exit)(struct kvm_vcpu *vcpu,
1468 enum exit_fastpath_completion exit_fastpath);
1469 int (*skip_emulated_instruction)(struct kvm_vcpu *vcpu);
1470 void (*update_emulated_instruction)(struct kvm_vcpu *vcpu);
1471 void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask);
1472 u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu);
1473 void (*patch_hypercall)(struct kvm_vcpu *vcpu,
1474 unsigned char *hypercall_addr);
1475 void (*inject_irq)(struct kvm_vcpu *vcpu);
1476 void (*inject_nmi)(struct kvm_vcpu *vcpu);
1477 void (*queue_exception)(struct kvm_vcpu *vcpu);
1478 void (*cancel_injection)(struct kvm_vcpu *vcpu);
1479 int (*interrupt_allowed)(struct kvm_vcpu *vcpu, bool for_injection);
1480 int (*nmi_allowed)(struct kvm_vcpu *vcpu, bool for_injection);
1481 bool (*get_nmi_mask)(struct kvm_vcpu *vcpu);
1482 void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked);
1483 void (*enable_nmi_window)(struct kvm_vcpu *vcpu);
1484 void (*enable_irq_window)(struct kvm_vcpu *vcpu);
1485 void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr);
1486 bool (*check_apicv_inhibit_reasons)(enum kvm_apicv_inhibit reason);
1487 void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu);
1488 void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr);
1489 void (*hwapic_isr_update)(struct kvm_vcpu *vcpu, int isr);
1490 bool (*guest_apic_has_interrupt)(struct kvm_vcpu *vcpu);
1491 void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap);
1492 void (*set_virtual_apic_mode)(struct kvm_vcpu *vcpu);
1493 void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu);
1494 void (*deliver_interrupt)(struct kvm_lapic *apic, int delivery_mode,
1495 int trig_mode, int vector);
1496 int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu);
1497 int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
1498 int (*set_identity_map_addr)(struct kvm *kvm, u64 ident_addr);
1499 u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio);
1500
1501 void (*load_mmu_pgd)(struct kvm_vcpu *vcpu, hpa_t root_hpa,
1502 int root_level);
1503
1504 bool (*has_wbinvd_exit)(void);
1505
1506 u64 (*get_l2_tsc_offset)(struct kvm_vcpu *vcpu);
1507 u64 (*get_l2_tsc_multiplier)(struct kvm_vcpu *vcpu);
1508 void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset);
1509 void (*write_tsc_multiplier)(struct kvm_vcpu *vcpu, u64 multiplier);
1510
1511 /*
1512 * Retrieve somewhat arbitrary exit information. Intended to
1513 * be used only from within tracepoints or error paths.
1514 */
1515 void (*get_exit_info)(struct kvm_vcpu *vcpu, u32 *reason,
1516 u64 *info1, u64 *info2,
1517 u32 *exit_int_info, u32 *exit_int_info_err_code);
1518
1519 int (*check_intercept)(struct kvm_vcpu *vcpu,
1520 struct x86_instruction_info *info,
1521 enum x86_intercept_stage stage,
1522 struct x86_exception *exception);
1523 void (*handle_exit_irqoff)(struct kvm_vcpu *vcpu);
1524
1525 void (*request_immediate_exit)(struct kvm_vcpu *vcpu);
1526
1527 void (*sched_in)(struct kvm_vcpu *kvm, int cpu);
1528
1529 /*
1530 * Size of the CPU's dirty log buffer, i.e. VMX's PML buffer. A zero
1531 * value indicates CPU dirty logging is unsupported or disabled.
1532 */
1533 int cpu_dirty_log_size;
1534 void (*update_cpu_dirty_logging)(struct kvm_vcpu *vcpu);
1535
1536 const struct kvm_x86_nested_ops *nested_ops;
1537
1538 void (*vcpu_blocking)(struct kvm_vcpu *vcpu);
1539 void (*vcpu_unblocking)(struct kvm_vcpu *vcpu);
1540
1541 int (*pi_update_irte)(struct kvm *kvm, unsigned int host_irq,
1542 uint32_t guest_irq, bool set);
1543 void (*pi_start_assignment)(struct kvm *kvm);
1544 void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu);
1545 bool (*dy_apicv_has_pending_interrupt)(struct kvm_vcpu *vcpu);
1546
1547 int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
1548 bool *expired);
1549 void (*cancel_hv_timer)(struct kvm_vcpu *vcpu);
1550
1551 void (*setup_mce)(struct kvm_vcpu *vcpu);
1552
1553 int (*smi_allowed)(struct kvm_vcpu *vcpu, bool for_injection);
1554 int (*enter_smm)(struct kvm_vcpu *vcpu, char *smstate);
1555 int (*leave_smm)(struct kvm_vcpu *vcpu, const char *smstate);
1556 void (*enable_smi_window)(struct kvm_vcpu *vcpu);
1557
1558 int (*mem_enc_ioctl)(struct kvm *kvm, void __user *argp);
1559 int (*mem_enc_register_region)(struct kvm *kvm, struct kvm_enc_region *argp);
1560 int (*mem_enc_unregister_region)(struct kvm *kvm, struct kvm_enc_region *argp);
1561 int (*vm_copy_enc_context_from)(struct kvm *kvm, unsigned int source_fd);
1562 int (*vm_move_enc_context_from)(struct kvm *kvm, unsigned int source_fd);
1563 void (*guest_memory_reclaimed)(struct kvm *kvm);
1564
1565 int (*get_msr_feature)(struct kvm_msr_entry *entry);
1566
1567 bool (*can_emulate_instruction)(struct kvm_vcpu *vcpu, int emul_type,
1568 void *insn, int insn_len);
1569
1570 bool (*apic_init_signal_blocked)(struct kvm_vcpu *vcpu);
1571 int (*enable_direct_tlbflush)(struct kvm_vcpu *vcpu);
1572
1573 void (*migrate_timers)(struct kvm_vcpu *vcpu);
1574 void (*msr_filter_changed)(struct kvm_vcpu *vcpu);
1575 int (*complete_emulated_msr)(struct kvm_vcpu *vcpu, int err);
1576
1577 void (*vcpu_deliver_sipi_vector)(struct kvm_vcpu *vcpu, u8 vector);
1578
1579 /*
1580 * Returns vCPU specific APICv inhibit reasons
1581 */
1582 unsigned long (*vcpu_get_apicv_inhibit_reasons)(struct kvm_vcpu *vcpu);
1583 };
1584
1585 struct kvm_x86_nested_ops {
1586 void (*leave_nested)(struct kvm_vcpu *vcpu);
1587 int (*check_events)(struct kvm_vcpu *vcpu);
1588 bool (*handle_page_fault_workaround)(struct kvm_vcpu *vcpu,
1589 struct x86_exception *fault);
1590 bool (*hv_timer_pending)(struct kvm_vcpu *vcpu);
1591 void (*triple_fault)(struct kvm_vcpu *vcpu);
1592 int (*get_state)(struct kvm_vcpu *vcpu,
1593 struct kvm_nested_state __user *user_kvm_nested_state,
1594 unsigned user_data_size);
1595 int (*set_state)(struct kvm_vcpu *vcpu,
1596 struct kvm_nested_state __user *user_kvm_nested_state,
1597 struct kvm_nested_state *kvm_state);
1598 bool (*get_nested_state_pages)(struct kvm_vcpu *vcpu);
1599 int (*write_log_dirty)(struct kvm_vcpu *vcpu, gpa_t l2_gpa);
1600
1601 int (*enable_evmcs)(struct kvm_vcpu *vcpu,
1602 uint16_t *vmcs_version);
1603 uint16_t (*get_evmcs_version)(struct kvm_vcpu *vcpu);
1604 };
1605
1606 struct kvm_x86_init_ops {
1607 int (*cpu_has_kvm_support)(void);
1608 int (*disabled_by_bios)(void);
1609 int (*check_processor_compatibility)(void);
1610 int (*hardware_setup)(void);
1611 unsigned int (*handle_intel_pt_intr)(void);
1612
1613 struct kvm_x86_ops *runtime_ops;
1614 struct kvm_pmu_ops *pmu_ops;
1615 };
1616
1617 struct kvm_arch_async_pf {
1618 u32 token;
1619 gfn_t gfn;
1620 unsigned long cr3;
1621 bool direct_map;
1622 };
1623
1624 extern u32 __read_mostly kvm_nr_uret_msrs;
1625 extern u64 __read_mostly host_efer;
1626 extern bool __read_mostly allow_smaller_maxphyaddr;
1627 extern bool __read_mostly enable_apicv;
1628 extern struct kvm_x86_ops kvm_x86_ops;
1629
1630 #define KVM_X86_OP(func) \
1631 DECLARE_STATIC_CALL(kvm_x86_##func, *(((struct kvm_x86_ops *)0)->func));
1632 #define KVM_X86_OP_OPTIONAL KVM_X86_OP
1633 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP
1634 #include <asm/kvm-x86-ops.h>
1635
1636 #define __KVM_HAVE_ARCH_VM_ALLOC
kvm_arch_alloc_vm(void)1637 static inline struct kvm *kvm_arch_alloc_vm(void)
1638 {
1639 return __vmalloc(kvm_x86_ops.vm_size, GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1640 }
1641
1642 #define __KVM_HAVE_ARCH_VM_FREE
1643 void kvm_arch_free_vm(struct kvm *kvm);
1644
1645 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLB
kvm_arch_flush_remote_tlb(struct kvm * kvm)1646 static inline int kvm_arch_flush_remote_tlb(struct kvm *kvm)
1647 {
1648 if (kvm_x86_ops.tlb_remote_flush &&
1649 !static_call(kvm_x86_tlb_remote_flush)(kvm))
1650 return 0;
1651 else
1652 return -ENOTSUPP;
1653 }
1654
1655 #define kvm_arch_pmi_in_guest(vcpu) \
1656 ((vcpu) && (vcpu)->arch.handling_intr_from_guest)
1657
1658 void __init kvm_mmu_x86_module_init(void);
1659 int kvm_mmu_vendor_module_init(void);
1660 void kvm_mmu_vendor_module_exit(void);
1661
1662 void kvm_mmu_destroy(struct kvm_vcpu *vcpu);
1663 int kvm_mmu_create(struct kvm_vcpu *vcpu);
1664 int kvm_mmu_init_vm(struct kvm *kvm);
1665 void kvm_mmu_uninit_vm(struct kvm *kvm);
1666
1667 void kvm_mmu_after_set_cpuid(struct kvm_vcpu *vcpu);
1668 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu);
1669 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
1670 const struct kvm_memory_slot *memslot,
1671 int start_level);
1672 void kvm_mmu_slot_try_split_huge_pages(struct kvm *kvm,
1673 const struct kvm_memory_slot *memslot,
1674 int target_level);
1675 void kvm_mmu_try_split_huge_pages(struct kvm *kvm,
1676 const struct kvm_memory_slot *memslot,
1677 u64 start, u64 end,
1678 int target_level);
1679 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
1680 const struct kvm_memory_slot *memslot);
1681 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
1682 const struct kvm_memory_slot *memslot);
1683 void kvm_mmu_zap_all(struct kvm *kvm);
1684 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen);
1685 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long kvm_nr_mmu_pages);
1686
1687 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3);
1688
1689 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
1690 const void *val, int bytes);
1691
1692 struct kvm_irq_mask_notifier {
1693 void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked);
1694 int irq;
1695 struct hlist_node link;
1696 };
1697
1698 void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq,
1699 struct kvm_irq_mask_notifier *kimn);
1700 void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq,
1701 struct kvm_irq_mask_notifier *kimn);
1702 void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin,
1703 bool mask);
1704
1705 extern bool tdp_enabled;
1706
1707 u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu);
1708
1709 /* control of guest tsc rate supported? */
1710 extern bool kvm_has_tsc_control;
1711 /* maximum supported tsc_khz for guests */
1712 extern u32 kvm_max_guest_tsc_khz;
1713 /* number of bits of the fractional part of the TSC scaling ratio */
1714 extern u8 kvm_tsc_scaling_ratio_frac_bits;
1715 /* maximum allowed value of TSC scaling ratio */
1716 extern u64 kvm_max_tsc_scaling_ratio;
1717 /* 1ull << kvm_tsc_scaling_ratio_frac_bits */
1718 extern u64 kvm_default_tsc_scaling_ratio;
1719 /* bus lock detection supported? */
1720 extern bool kvm_has_bus_lock_exit;
1721
1722 extern u64 kvm_mce_cap_supported;
1723
1724 /*
1725 * EMULTYPE_NO_DECODE - Set when re-emulating an instruction (after completing
1726 * userspace I/O) to indicate that the emulation context
1727 * should be reused as is, i.e. skip initialization of
1728 * emulation context, instruction fetch and decode.
1729 *
1730 * EMULTYPE_TRAP_UD - Set when emulating an intercepted #UD from hardware.
1731 * Indicates that only select instructions (tagged with
1732 * EmulateOnUD) should be emulated (to minimize the emulator
1733 * attack surface). See also EMULTYPE_TRAP_UD_FORCED.
1734 *
1735 * EMULTYPE_SKIP - Set when emulating solely to skip an instruction, i.e. to
1736 * decode the instruction length. For use *only* by
1737 * kvm_x86_ops.skip_emulated_instruction() implementations if
1738 * EMULTYPE_COMPLETE_USER_EXIT is not set.
1739 *
1740 * EMULTYPE_ALLOW_RETRY_PF - Set when the emulator should resume the guest to
1741 * retry native execution under certain conditions,
1742 * Can only be set in conjunction with EMULTYPE_PF.
1743 *
1744 * EMULTYPE_TRAP_UD_FORCED - Set when emulating an intercepted #UD that was
1745 * triggered by KVM's magic "force emulation" prefix,
1746 * which is opt in via module param (off by default).
1747 * Bypasses EmulateOnUD restriction despite emulating
1748 * due to an intercepted #UD (see EMULTYPE_TRAP_UD).
1749 * Used to test the full emulator from userspace.
1750 *
1751 * EMULTYPE_VMWARE_GP - Set when emulating an intercepted #GP for VMware
1752 * backdoor emulation, which is opt in via module param.
1753 * VMware backdoor emulation handles select instructions
1754 * and reinjects the #GP for all other cases.
1755 *
1756 * EMULTYPE_PF - Set when emulating MMIO by way of an intercepted #PF, in which
1757 * case the CR2/GPA value pass on the stack is valid.
1758 *
1759 * EMULTYPE_COMPLETE_USER_EXIT - Set when the emulator should update interruptibility
1760 * state and inject single-step #DBs after skipping
1761 * an instruction (after completing userspace I/O).
1762 */
1763 #define EMULTYPE_NO_DECODE (1 << 0)
1764 #define EMULTYPE_TRAP_UD (1 << 1)
1765 #define EMULTYPE_SKIP (1 << 2)
1766 #define EMULTYPE_ALLOW_RETRY_PF (1 << 3)
1767 #define EMULTYPE_TRAP_UD_FORCED (1 << 4)
1768 #define EMULTYPE_VMWARE_GP (1 << 5)
1769 #define EMULTYPE_PF (1 << 6)
1770 #define EMULTYPE_COMPLETE_USER_EXIT (1 << 7)
1771
1772 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type);
1773 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
1774 void *insn, int insn_len);
1775 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu,
1776 u64 *data, u8 ndata);
1777 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu);
1778
1779 void kvm_enable_efer_bits(u64);
1780 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer);
1781 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, bool host_initiated);
1782 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data);
1783 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data);
1784 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu);
1785 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu);
1786 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu);
1787 int kvm_emulate_invd(struct kvm_vcpu *vcpu);
1788 int kvm_emulate_mwait(struct kvm_vcpu *vcpu);
1789 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu);
1790 int kvm_emulate_monitor(struct kvm_vcpu *vcpu);
1791
1792 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in);
1793 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu);
1794 int kvm_emulate_halt(struct kvm_vcpu *vcpu);
1795 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu);
1796 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu);
1797 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu);
1798
1799 void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
1800 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg);
1801 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector);
1802
1803 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
1804 int reason, bool has_error_code, u32 error_code);
1805
1806 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0);
1807 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4);
1808 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
1809 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
1810 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1811 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8);
1812 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val);
1813 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val);
1814 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu);
1815 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw);
1816 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu);
1817
1818 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr);
1819 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr);
1820
1821 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu);
1822 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
1823 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu);
1824
1825 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr);
1826 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
1827 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, unsigned long payload);
1828 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr);
1829 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
1830 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault);
1831 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
1832 struct x86_exception *fault);
1833 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl);
1834 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr);
1835
__kvm_irq_line_state(unsigned long * irq_state,int irq_source_id,int level)1836 static inline int __kvm_irq_line_state(unsigned long *irq_state,
1837 int irq_source_id, int level)
1838 {
1839 /* Logical OR for level trig interrupt */
1840 if (level)
1841 __set_bit(irq_source_id, irq_state);
1842 else
1843 __clear_bit(irq_source_id, irq_state);
1844
1845 return !!(*irq_state);
1846 }
1847
1848 #define KVM_MMU_ROOT_CURRENT BIT(0)
1849 #define KVM_MMU_ROOT_PREVIOUS(i) BIT(1+i)
1850 #define KVM_MMU_ROOTS_ALL (~0UL)
1851
1852 int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level);
1853 void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id);
1854
1855 void kvm_inject_nmi(struct kvm_vcpu *vcpu);
1856
1857 void kvm_update_dr7(struct kvm_vcpu *vcpu);
1858
1859 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn);
1860 void kvm_mmu_free_roots(struct kvm *kvm, struct kvm_mmu *mmu,
1861 ulong roots_to_free);
1862 void kvm_mmu_free_guest_mode_roots(struct kvm *kvm, struct kvm_mmu *mmu);
1863 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
1864 struct x86_exception *exception);
1865 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
1866 struct x86_exception *exception);
1867 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
1868 struct x86_exception *exception);
1869 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
1870 struct x86_exception *exception);
1871
1872 bool kvm_apicv_activated(struct kvm *kvm);
1873 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu);
1874 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu);
1875 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
1876 enum kvm_apicv_inhibit reason, bool set);
1877 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
1878 enum kvm_apicv_inhibit reason, bool set);
1879
kvm_set_apicv_inhibit(struct kvm * kvm,enum kvm_apicv_inhibit reason)1880 static inline void kvm_set_apicv_inhibit(struct kvm *kvm,
1881 enum kvm_apicv_inhibit reason)
1882 {
1883 kvm_set_or_clear_apicv_inhibit(kvm, reason, true);
1884 }
1885
kvm_clear_apicv_inhibit(struct kvm * kvm,enum kvm_apicv_inhibit reason)1886 static inline void kvm_clear_apicv_inhibit(struct kvm *kvm,
1887 enum kvm_apicv_inhibit reason)
1888 {
1889 kvm_set_or_clear_apicv_inhibit(kvm, reason, false);
1890 }
1891
1892 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu);
1893
1894 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
1895 void *insn, int insn_len);
1896 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva);
1897 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
1898 gva_t gva, hpa_t root_hpa);
1899 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid);
1900 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd);
1901
1902 void kvm_configure_mmu(bool enable_tdp, int tdp_forced_root_level,
1903 int tdp_max_root_level, int tdp_huge_page_level);
1904
kvm_read_ldt(void)1905 static inline u16 kvm_read_ldt(void)
1906 {
1907 u16 ldt;
1908 asm("sldt %0" : "=g"(ldt));
1909 return ldt;
1910 }
1911
kvm_load_ldt(u16 sel)1912 static inline void kvm_load_ldt(u16 sel)
1913 {
1914 asm("lldt %0" : : "rm"(sel));
1915 }
1916
1917 #ifdef CONFIG_X86_64
read_msr(unsigned long msr)1918 static inline unsigned long read_msr(unsigned long msr)
1919 {
1920 u64 value;
1921
1922 rdmsrl(msr, value);
1923 return value;
1924 }
1925 #endif
1926
kvm_inject_gp(struct kvm_vcpu * vcpu,u32 error_code)1927 static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code)
1928 {
1929 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1930 }
1931
1932 #define TSS_IOPB_BASE_OFFSET 0x66
1933 #define TSS_BASE_SIZE 0x68
1934 #define TSS_IOPB_SIZE (65536 / 8)
1935 #define TSS_REDIRECTION_SIZE (256 / 8)
1936 #define RMODE_TSS_SIZE \
1937 (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1)
1938
1939 enum {
1940 TASK_SWITCH_CALL = 0,
1941 TASK_SWITCH_IRET = 1,
1942 TASK_SWITCH_JMP = 2,
1943 TASK_SWITCH_GATE = 3,
1944 };
1945
1946 #define HF_GIF_MASK (1 << 0)
1947 #define HF_NMI_MASK (1 << 3)
1948 #define HF_IRET_MASK (1 << 4)
1949 #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */
1950 #define HF_SMM_MASK (1 << 6)
1951 #define HF_SMM_INSIDE_NMI_MASK (1 << 7)
1952
1953 #define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE
1954 #define KVM_ADDRESS_SPACE_NUM 2
1955
1956 #define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0)
1957 #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm)
1958
1959 #define KVM_ARCH_WANT_MMU_NOTIFIER
1960
1961 int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v);
1962 int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu);
1963 int kvm_cpu_has_extint(struct kvm_vcpu *v);
1964 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu);
1965 int kvm_cpu_get_interrupt(struct kvm_vcpu *v);
1966 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event);
1967
1968 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low,
1969 unsigned long ipi_bitmap_high, u32 min,
1970 unsigned long icr, int op_64_bit);
1971
1972 int kvm_add_user_return_msr(u32 msr);
1973 int kvm_find_user_return_msr(u32 msr);
1974 int kvm_set_user_return_msr(unsigned index, u64 val, u64 mask);
1975
kvm_is_supported_user_return_msr(u32 msr)1976 static inline bool kvm_is_supported_user_return_msr(u32 msr)
1977 {
1978 return kvm_find_user_return_msr(msr) >= 0;
1979 }
1980
1981 u64 kvm_scale_tsc(u64 tsc, u64 ratio);
1982 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc);
1983 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier);
1984 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier);
1985
1986 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu);
1987 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip);
1988
1989 void kvm_make_scan_ioapic_request(struct kvm *kvm);
1990 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
1991 unsigned long *vcpu_bitmap);
1992
1993 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
1994 struct kvm_async_pf *work);
1995 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
1996 struct kvm_async_pf *work);
1997 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu,
1998 struct kvm_async_pf *work);
1999 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu);
2000 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu);
2001 extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn);
2002
2003 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu);
2004 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err);
2005 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu);
2006
2007 void __user *__x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
2008 u32 size);
2009 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu);
2010 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu);
2011
2012 bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq,
2013 struct kvm_vcpu **dest_vcpu);
2014
2015 void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
2016 struct kvm_lapic_irq *irq);
2017
kvm_irq_is_postable(struct kvm_lapic_irq * irq)2018 static inline bool kvm_irq_is_postable(struct kvm_lapic_irq *irq)
2019 {
2020 /* We can only post Fixed and LowPrio IRQs */
2021 return (irq->delivery_mode == APIC_DM_FIXED ||
2022 irq->delivery_mode == APIC_DM_LOWEST);
2023 }
2024
kvm_arch_vcpu_blocking(struct kvm_vcpu * vcpu)2025 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu)
2026 {
2027 static_call_cond(kvm_x86_vcpu_blocking)(vcpu);
2028 }
2029
kvm_arch_vcpu_unblocking(struct kvm_vcpu * vcpu)2030 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu)
2031 {
2032 static_call_cond(kvm_x86_vcpu_unblocking)(vcpu);
2033 }
2034
kvm_cpu_get_apicid(int mps_cpu)2035 static inline int kvm_cpu_get_apicid(int mps_cpu)
2036 {
2037 #ifdef CONFIG_X86_LOCAL_APIC
2038 return default_cpu_present_to_apicid(mps_cpu);
2039 #else
2040 WARN_ON_ONCE(1);
2041 return BAD_APICID;
2042 #endif
2043 }
2044
2045 #define put_smstate(type, buf, offset, val) \
2046 *(type *)((buf) + (offset) - 0x7e00) = val
2047
2048 #define GET_SMSTATE(type, buf, offset) \
2049 (*(type *)((buf) + (offset) - 0x7e00))
2050
2051 int kvm_cpu_dirty_log_size(void);
2052
2053 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages);
2054
2055 #define KVM_CLOCK_VALID_FLAGS \
2056 (KVM_CLOCK_TSC_STABLE | KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC)
2057
2058 #define KVM_X86_VALID_QUIRKS \
2059 (KVM_X86_QUIRK_LINT0_REENABLED | \
2060 KVM_X86_QUIRK_CD_NW_CLEARED | \
2061 KVM_X86_QUIRK_LAPIC_MMIO_HOLE | \
2062 KVM_X86_QUIRK_OUT_7E_INC_RIP | \
2063 KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT | \
2064 KVM_X86_QUIRK_FIX_HYPERCALL_INSN)
2065
2066 #endif /* _ASM_X86_KVM_HOST_H */
2067