1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include "i915_reg.h"
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <drm/intel-gtt.h>
40 #include <linux/backlight.h>
41
42 /* General customization:
43 */
44
45 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
46
47 #define DRIVER_NAME "i915"
48 #define DRIVER_DESC "Intel Graphics"
49 #define DRIVER_DATE "20080730"
50
51 enum pipe {
52 PIPE_A = 0,
53 PIPE_B,
54 PIPE_C,
55 I915_MAX_PIPES
56 };
57 #define pipe_name(p) ((p) + 'A')
58
59 enum plane {
60 PLANE_A = 0,
61 PLANE_B,
62 PLANE_C,
63 };
64 #define plane_name(p) ((p) + 'A')
65
66 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
67
68 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
69
70 /* Interface history:
71 *
72 * 1.1: Original.
73 * 1.2: Add Power Management
74 * 1.3: Add vblank support
75 * 1.4: Fix cmdbuffer path, add heap destroy
76 * 1.5: Add vblank pipe configuration
77 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
78 * - Support vertical blank on secondary display pipe
79 */
80 #define DRIVER_MAJOR 1
81 #define DRIVER_MINOR 6
82 #define DRIVER_PATCHLEVEL 0
83
84 #define WATCH_COHERENCY 0
85 #define WATCH_LISTS 0
86
87 #define I915_GEM_PHYS_CURSOR_0 1
88 #define I915_GEM_PHYS_CURSOR_1 2
89 #define I915_GEM_PHYS_OVERLAY_REGS 3
90 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
91
92 struct drm_i915_gem_phys_object {
93 int id;
94 struct page **page_list;
95 drm_dma_handle_t *handle;
96 struct drm_i915_gem_object *cur_obj;
97 };
98
99 struct mem_block {
100 struct mem_block *next;
101 struct mem_block *prev;
102 int start;
103 int size;
104 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
105 };
106
107 struct opregion_header;
108 struct opregion_acpi;
109 struct opregion_swsci;
110 struct opregion_asle;
111 struct drm_i915_private;
112
113 struct intel_opregion {
114 struct opregion_header *header;
115 struct opregion_acpi *acpi;
116 struct opregion_swsci *swsci;
117 struct opregion_asle *asle;
118 void *vbt;
119 u32 __iomem *lid_state;
120 };
121 #define OPREGION_SIZE (8*1024)
122
123 struct intel_overlay;
124 struct intel_overlay_error_state;
125
126 struct drm_i915_master_private {
127 drm_local_map_t *sarea;
128 struct _drm_i915_sarea *sarea_priv;
129 };
130 #define I915_FENCE_REG_NONE -1
131 #define I915_MAX_NUM_FENCES 16
132 /* 16 fences + sign bit for FENCE_REG_NONE */
133 #define I915_MAX_NUM_FENCE_BITS 5
134
135 struct drm_i915_fence_reg {
136 struct list_head lru_list;
137 struct drm_i915_gem_object *obj;
138 uint32_t setup_seqno;
139 int pin_count;
140 };
141
142 struct sdvo_device_mapping {
143 u8 initialized;
144 u8 dvo_port;
145 u8 slave_addr;
146 u8 dvo_wiring;
147 u8 i2c_pin;
148 u8 ddc_pin;
149 };
150
151 struct intel_display_error_state;
152
153 struct drm_i915_error_state {
154 u32 eir;
155 u32 pgtbl_er;
156 u32 pipestat[I915_MAX_PIPES];
157 u32 tail[I915_NUM_RINGS];
158 u32 head[I915_NUM_RINGS];
159 u32 ipeir[I915_NUM_RINGS];
160 u32 ipehr[I915_NUM_RINGS];
161 u32 instdone[I915_NUM_RINGS];
162 u32 acthd[I915_NUM_RINGS];
163 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
164 /* our own tracking of ring head and tail */
165 u32 cpu_ring_head[I915_NUM_RINGS];
166 u32 cpu_ring_tail[I915_NUM_RINGS];
167 u32 error; /* gen6+ */
168 u32 instpm[I915_NUM_RINGS];
169 u32 instps[I915_NUM_RINGS];
170 u32 instdone1;
171 u32 seqno[I915_NUM_RINGS];
172 u64 bbaddr;
173 u32 fault_reg[I915_NUM_RINGS];
174 u32 done_reg;
175 u32 faddr[I915_NUM_RINGS];
176 u64 fence[I915_MAX_NUM_FENCES];
177 struct timeval time;
178 struct drm_i915_error_ring {
179 struct drm_i915_error_object {
180 int page_count;
181 u32 gtt_offset;
182 u32 *pages[0];
183 } *ringbuffer, *batchbuffer;
184 struct drm_i915_error_request {
185 long jiffies;
186 u32 seqno;
187 u32 tail;
188 } *requests;
189 int num_requests;
190 } ring[I915_NUM_RINGS];
191 struct drm_i915_error_buffer {
192 u32 size;
193 u32 name;
194 u32 seqno;
195 u32 gtt_offset;
196 u32 read_domains;
197 u32 write_domain;
198 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
199 s32 pinned:2;
200 u32 tiling:2;
201 u32 dirty:1;
202 u32 purgeable:1;
203 s32 ring:4;
204 u32 cache_level:2;
205 } *active_bo, *pinned_bo;
206 u32 active_bo_count, pinned_bo_count;
207 struct intel_overlay_error_state *overlay;
208 struct intel_display_error_state *display;
209 };
210
211 struct drm_i915_display_funcs {
212 void (*dpms)(struct drm_crtc *crtc, int mode);
213 bool (*fbc_enabled)(struct drm_device *dev);
214 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
215 void (*disable_fbc)(struct drm_device *dev);
216 int (*get_display_clock_speed)(struct drm_device *dev);
217 int (*get_fifo_size)(struct drm_device *dev, int plane);
218 void (*update_wm)(struct drm_device *dev);
219 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
220 uint32_t sprite_width, int pixel_size);
221 int (*crtc_mode_set)(struct drm_crtc *crtc,
222 struct drm_display_mode *mode,
223 struct drm_display_mode *adjusted_mode,
224 int x, int y,
225 struct drm_framebuffer *old_fb);
226 void (*write_eld)(struct drm_connector *connector,
227 struct drm_crtc *crtc);
228 void (*fdi_link_train)(struct drm_crtc *crtc);
229 void (*init_clock_gating)(struct drm_device *dev);
230 void (*init_pch_clock_gating)(struct drm_device *dev);
231 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
232 struct drm_framebuffer *fb,
233 struct drm_i915_gem_object *obj);
234 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
235 int x, int y);
236 void (*force_wake_get)(struct drm_i915_private *dev_priv);
237 void (*force_wake_put)(struct drm_i915_private *dev_priv);
238 /* clock updates for mode set */
239 /* cursor updates */
240 /* render clock increase/decrease */
241 /* display clock increase/decrease */
242 /* pll clock increase/decrease */
243 };
244
245 struct intel_device_info {
246 u8 gen;
247 u8 is_mobile:1;
248 u8 is_i85x:1;
249 u8 is_i915g:1;
250 u8 is_i945gm:1;
251 u8 is_g33:1;
252 u8 need_gfx_hws:1;
253 u8 is_g4x:1;
254 u8 is_pineview:1;
255 u8 is_broadwater:1;
256 u8 is_crestline:1;
257 u8 is_ivybridge:1;
258 u8 has_force_wake:1;
259 u8 has_fbc:1;
260 u8 has_pipe_cxsr:1;
261 u8 has_hotplug:1;
262 u8 cursor_needs_physical:1;
263 u8 has_overlay:1;
264 u8 overlay_needs_physical:1;
265 u8 supports_tv:1;
266 u8 has_bsd_ring:1;
267 u8 has_blt_ring:1;
268 u8 has_llc:1;
269 };
270
271 #define I915_PPGTT_PD_ENTRIES 512
272 #define I915_PPGTT_PT_ENTRIES 1024
273 struct i915_hw_ppgtt {
274 unsigned num_pd_entries;
275 struct page **pt_pages;
276 uint32_t pd_offset;
277 dma_addr_t *pt_dma_addr;
278 dma_addr_t scratch_page_dma_addr;
279 };
280
281 enum no_fbc_reason {
282 FBC_NO_OUTPUT, /* no outputs enabled to compress */
283 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
284 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
285 FBC_MODE_TOO_LARGE, /* mode too large for compression */
286 FBC_BAD_PLANE, /* fbc not supported on plane */
287 FBC_NOT_TILED, /* buffer not tiled */
288 FBC_MULTIPLE_PIPES, /* more than one pipe active */
289 FBC_MODULE_PARAM,
290 };
291
292 enum intel_pch {
293 PCH_IBX, /* Ibexpeak PCH */
294 PCH_CPT, /* Cougarpoint PCH */
295 };
296
297 #define QUIRK_PIPEA_FORCE (1<<0)
298 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
299 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
300 #define QUIRK_NO_PCH_PWM_ENABLE (1<<3)
301
302 struct intel_fbdev;
303 struct intel_fbc_work;
304
305 struct intel_gmbus {
306 struct i2c_adapter adapter;
307 bool force_bit;
308 bool has_gpio;
309 u32 reg0;
310 u32 gpio_reg;
311 struct i2c_algo_bit_data bit_algo;
312 struct drm_i915_private *dev_priv;
313 };
314
315 typedef struct drm_i915_private {
316 struct drm_device *dev;
317
318 const struct intel_device_info *info;
319
320 int has_gem;
321 int relative_constants_mode;
322
323 void __iomem *regs;
324 /** gt_fifo_count and the subsequent register write are synchronized
325 * with dev->struct_mutex. */
326 unsigned gt_fifo_count;
327 /** forcewake_count is protected by gt_lock */
328 unsigned forcewake_count;
329 /** gt_lock is also taken in irq contexts. */
330 struct spinlock gt_lock;
331
332 struct intel_gmbus *gmbus;
333
334 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
335 * controller on different i2c buses. */
336 struct mutex gmbus_mutex;
337
338 struct pci_dev *bridge_dev;
339 struct intel_ring_buffer ring[I915_NUM_RINGS];
340 uint32_t next_seqno;
341
342 drm_dma_handle_t *status_page_dmah;
343 uint32_t counter;
344 drm_local_map_t hws_map;
345 struct drm_i915_gem_object *pwrctx;
346 struct drm_i915_gem_object *renderctx;
347
348 struct resource mch_res;
349
350 unsigned int cpp;
351 int back_offset;
352 int front_offset;
353 int current_page;
354 int page_flipping;
355
356 atomic_t irq_received;
357
358 /* protects the irq masks */
359 spinlock_t irq_lock;
360 /** Cached value of IMR to avoid reads in updating the bitfield */
361 u32 pipestat[2];
362 u32 irq_mask;
363 u32 gt_irq_mask;
364 u32 pch_irq_mask;
365
366 u32 hotplug_supported_mask;
367 struct work_struct hotplug_work;
368
369 int tex_lru_log_granularity;
370 int allow_batchbuffer;
371 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
372 int vblank_pipe;
373 int num_pipe;
374
375 /* For hangcheck timer */
376 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
377 struct timer_list hangcheck_timer;
378 int hangcheck_count;
379 uint32_t last_acthd;
380 uint32_t last_acthd_bsd;
381 uint32_t last_acthd_blt;
382 uint32_t last_instdone;
383 uint32_t last_instdone1;
384
385 unsigned long cfb_size;
386 unsigned int cfb_fb;
387 enum plane cfb_plane;
388 int cfb_y;
389 struct intel_fbc_work *fbc_work;
390
391 struct intel_opregion opregion;
392
393 /* overlay */
394 struct intel_overlay *overlay;
395 bool sprite_scaling_enabled;
396
397 /* LVDS info */
398 int backlight_level; /* restore backlight to this value */
399 bool backlight_enabled;
400 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
401 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
402
403 /* Feature bits from the VBIOS */
404 unsigned int int_tv_support:1;
405 unsigned int lvds_dither:1;
406 unsigned int lvds_vbt:1;
407 unsigned int int_crt_support:1;
408 unsigned int lvds_use_ssc:1;
409 unsigned int display_clock_mode:1;
410 int lvds_ssc_freq;
411 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
412 unsigned int lvds_val; /* used for checking LVDS channel mode */
413 struct {
414 int rate;
415 int lanes;
416 int preemphasis;
417 int vswing;
418
419 bool initialized;
420 bool support;
421 int bpp;
422 struct edp_power_seq pps;
423 } edp;
424 bool no_aux_handshake;
425
426 struct notifier_block lid_notifier;
427
428 int crt_ddc_pin;
429 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
430 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
431 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
432
433 unsigned int fsb_freq, mem_freq, is_ddr3;
434
435 spinlock_t error_lock;
436 struct drm_i915_error_state *first_error;
437 struct work_struct error_work;
438 struct completion error_completion;
439 struct workqueue_struct *wq;
440
441 /* Display functions */
442 struct drm_i915_display_funcs display;
443
444 /* PCH chipset type */
445 enum intel_pch pch_type;
446
447 unsigned long quirks;
448
449 /* Register state */
450 bool modeset_on_lid;
451 u8 saveLBB;
452 u32 saveDSPACNTR;
453 u32 saveDSPBCNTR;
454 u32 saveDSPARB;
455 u32 saveHWS;
456 u32 savePIPEACONF;
457 u32 savePIPEBCONF;
458 u32 savePIPEASRC;
459 u32 savePIPEBSRC;
460 u32 saveFPA0;
461 u32 saveFPA1;
462 u32 saveDPLL_A;
463 u32 saveDPLL_A_MD;
464 u32 saveHTOTAL_A;
465 u32 saveHBLANK_A;
466 u32 saveHSYNC_A;
467 u32 saveVTOTAL_A;
468 u32 saveVBLANK_A;
469 u32 saveVSYNC_A;
470 u32 saveBCLRPAT_A;
471 u32 saveTRANSACONF;
472 u32 saveTRANS_HTOTAL_A;
473 u32 saveTRANS_HBLANK_A;
474 u32 saveTRANS_HSYNC_A;
475 u32 saveTRANS_VTOTAL_A;
476 u32 saveTRANS_VBLANK_A;
477 u32 saveTRANS_VSYNC_A;
478 u32 savePIPEASTAT;
479 u32 saveDSPASTRIDE;
480 u32 saveDSPASIZE;
481 u32 saveDSPAPOS;
482 u32 saveDSPAADDR;
483 u32 saveDSPASURF;
484 u32 saveDSPATILEOFF;
485 u32 savePFIT_PGM_RATIOS;
486 u32 saveBLC_HIST_CTL;
487 u32 saveBLC_PWM_CTL;
488 u32 saveBLC_PWM_CTL2;
489 u32 saveBLC_CPU_PWM_CTL;
490 u32 saveBLC_CPU_PWM_CTL2;
491 u32 saveFPB0;
492 u32 saveFPB1;
493 u32 saveDPLL_B;
494 u32 saveDPLL_B_MD;
495 u32 saveHTOTAL_B;
496 u32 saveHBLANK_B;
497 u32 saveHSYNC_B;
498 u32 saveVTOTAL_B;
499 u32 saveVBLANK_B;
500 u32 saveVSYNC_B;
501 u32 saveBCLRPAT_B;
502 u32 saveTRANSBCONF;
503 u32 saveTRANS_HTOTAL_B;
504 u32 saveTRANS_HBLANK_B;
505 u32 saveTRANS_HSYNC_B;
506 u32 saveTRANS_VTOTAL_B;
507 u32 saveTRANS_VBLANK_B;
508 u32 saveTRANS_VSYNC_B;
509 u32 savePIPEBSTAT;
510 u32 saveDSPBSTRIDE;
511 u32 saveDSPBSIZE;
512 u32 saveDSPBPOS;
513 u32 saveDSPBADDR;
514 u32 saveDSPBSURF;
515 u32 saveDSPBTILEOFF;
516 u32 saveVGA0;
517 u32 saveVGA1;
518 u32 saveVGA_PD;
519 u32 saveVGACNTRL;
520 u32 saveADPA;
521 u32 saveLVDS;
522 u32 savePP_ON_DELAYS;
523 u32 savePP_OFF_DELAYS;
524 u32 saveDVOA;
525 u32 saveDVOB;
526 u32 saveDVOC;
527 u32 savePP_ON;
528 u32 savePP_OFF;
529 u32 savePP_CONTROL;
530 u32 savePP_DIVISOR;
531 u32 savePFIT_CONTROL;
532 u32 save_palette_a[256];
533 u32 save_palette_b[256];
534 u32 saveDPFC_CB_BASE;
535 u32 saveFBC_CFB_BASE;
536 u32 saveFBC_LL_BASE;
537 u32 saveFBC_CONTROL;
538 u32 saveFBC_CONTROL2;
539 u32 saveIER;
540 u32 saveIIR;
541 u32 saveIMR;
542 u32 saveDEIER;
543 u32 saveDEIMR;
544 u32 saveGTIER;
545 u32 saveGTIMR;
546 u32 saveFDI_RXA_IMR;
547 u32 saveFDI_RXB_IMR;
548 u32 saveCACHE_MODE_0;
549 u32 saveMI_ARB_STATE;
550 u32 saveSWF0[16];
551 u32 saveSWF1[16];
552 u32 saveSWF2[3];
553 u8 saveMSR;
554 u8 saveSR[8];
555 u8 saveGR[25];
556 u8 saveAR_INDEX;
557 u8 saveAR[21];
558 u8 saveDACMASK;
559 u8 saveCR[37];
560 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
561 u32 saveCURACNTR;
562 u32 saveCURAPOS;
563 u32 saveCURABASE;
564 u32 saveCURBCNTR;
565 u32 saveCURBPOS;
566 u32 saveCURBBASE;
567 u32 saveCURSIZE;
568 u32 saveDP_B;
569 u32 saveDP_C;
570 u32 saveDP_D;
571 u32 savePIPEA_GMCH_DATA_M;
572 u32 savePIPEB_GMCH_DATA_M;
573 u32 savePIPEA_GMCH_DATA_N;
574 u32 savePIPEB_GMCH_DATA_N;
575 u32 savePIPEA_DP_LINK_M;
576 u32 savePIPEB_DP_LINK_M;
577 u32 savePIPEA_DP_LINK_N;
578 u32 savePIPEB_DP_LINK_N;
579 u32 saveFDI_RXA_CTL;
580 u32 saveFDI_TXA_CTL;
581 u32 saveFDI_RXB_CTL;
582 u32 saveFDI_TXB_CTL;
583 u32 savePFA_CTL_1;
584 u32 savePFB_CTL_1;
585 u32 savePFA_WIN_SZ;
586 u32 savePFB_WIN_SZ;
587 u32 savePFA_WIN_POS;
588 u32 savePFB_WIN_POS;
589 u32 savePCH_DREF_CONTROL;
590 u32 saveDISP_ARB_CTL;
591 u32 savePIPEA_DATA_M1;
592 u32 savePIPEA_DATA_N1;
593 u32 savePIPEA_LINK_M1;
594 u32 savePIPEA_LINK_N1;
595 u32 savePIPEB_DATA_M1;
596 u32 savePIPEB_DATA_N1;
597 u32 savePIPEB_LINK_M1;
598 u32 savePIPEB_LINK_N1;
599 u32 saveMCHBAR_RENDER_STANDBY;
600 u32 savePCH_PORT_HOTPLUG;
601
602 struct {
603 /** Bridge to intel-gtt-ko */
604 const struct intel_gtt *gtt;
605 /** Memory allocator for GTT stolen memory */
606 struct drm_mm stolen;
607 /** Memory allocator for GTT */
608 struct drm_mm gtt_space;
609 /** List of all objects in gtt_space. Used to restore gtt
610 * mappings on resume */
611 struct list_head gtt_list;
612
613 /** Usable portion of the GTT for GEM */
614 unsigned long gtt_start;
615 unsigned long gtt_mappable_end;
616 unsigned long gtt_end;
617
618 struct io_mapping *gtt_mapping;
619 int gtt_mtrr;
620
621 /** PPGTT used for aliasing the PPGTT with the GTT */
622 struct i915_hw_ppgtt *aliasing_ppgtt;
623
624 struct shrinker inactive_shrinker;
625
626 /**
627 * List of objects currently involved in rendering.
628 *
629 * Includes buffers having the contents of their GPU caches
630 * flushed, not necessarily primitives. last_rendering_seqno
631 * represents when the rendering involved will be completed.
632 *
633 * A reference is held on the buffer while on this list.
634 */
635 struct list_head active_list;
636
637 /**
638 * List of objects which are not in the ringbuffer but which
639 * still have a write_domain which needs to be flushed before
640 * unbinding.
641 *
642 * last_rendering_seqno is 0 while an object is in this list.
643 *
644 * A reference is held on the buffer while on this list.
645 */
646 struct list_head flushing_list;
647
648 /**
649 * LRU list of objects which are not in the ringbuffer and
650 * are ready to unbind, but are still in the GTT.
651 *
652 * last_rendering_seqno is 0 while an object is in this list.
653 *
654 * A reference is not held on the buffer while on this list,
655 * as merely being GTT-bound shouldn't prevent its being
656 * freed, and we'll pull it off the list in the free path.
657 */
658 struct list_head inactive_list;
659
660 /**
661 * LRU list of objects which are not in the ringbuffer but
662 * are still pinned in the GTT.
663 */
664 struct list_head pinned_list;
665
666 /** LRU list of objects with fence regs on them. */
667 struct list_head fence_list;
668
669 /**
670 * List of objects currently pending being freed.
671 *
672 * These objects are no longer in use, but due to a signal
673 * we were prevented from freeing them at the appointed time.
674 */
675 struct list_head deferred_free_list;
676
677 /**
678 * We leave the user IRQ off as much as possible,
679 * but this means that requests will finish and never
680 * be retired once the system goes idle. Set a timer to
681 * fire periodically while the ring is running. When it
682 * fires, go retire requests.
683 */
684 struct delayed_work retire_work;
685
686 /**
687 * Are we in a non-interruptible section of code like
688 * modesetting?
689 */
690 bool interruptible;
691
692 /**
693 * Flag if the X Server, and thus DRM, is not currently in
694 * control of the device.
695 *
696 * This is set between LeaveVT and EnterVT. It needs to be
697 * replaced with a semaphore. It also needs to be
698 * transitioned away from for kernel modesetting.
699 */
700 int suspended;
701
702 /**
703 * Flag if the hardware appears to be wedged.
704 *
705 * This is set when attempts to idle the device timeout.
706 * It prevents command submission from occurring and makes
707 * every pending request fail
708 */
709 atomic_t wedged;
710
711 /** Bit 6 swizzling required for X tiling */
712 uint32_t bit_6_swizzle_x;
713 /** Bit 6 swizzling required for Y tiling */
714 uint32_t bit_6_swizzle_y;
715
716 /* storage for physical objects */
717 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
718
719 /* accounting, useful for userland debugging */
720 size_t gtt_total;
721 size_t mappable_gtt_total;
722 size_t object_memory;
723 u32 object_count;
724 } mm;
725 struct sdvo_device_mapping sdvo_mappings[2];
726 /* indicate whether the LVDS_BORDER should be enabled or not */
727 unsigned int lvds_border_bits;
728 /* Panel fitter placement and size for Ironlake+ */
729 u32 pch_pf_pos, pch_pf_size;
730
731 struct drm_crtc *plane_to_crtc_mapping[3];
732 struct drm_crtc *pipe_to_crtc_mapping[3];
733 wait_queue_head_t pending_flip_queue;
734 bool flip_pending_is_done;
735
736 /* Reclocking support */
737 bool render_reclock_avail;
738 bool lvds_downclock_avail;
739 /* indicates the reduced downclock for LVDS*/
740 int lvds_downclock;
741 struct work_struct idle_work;
742 struct timer_list idle_timer;
743 bool busy;
744 u16 orig_clock;
745 int child_dev_num;
746 struct child_device_config *child_dev;
747 struct drm_connector *int_lvds_connector;
748 struct drm_connector *int_edp_connector;
749
750 bool mchbar_need_disable;
751
752 struct work_struct rps_work;
753 spinlock_t rps_lock;
754 u32 pm_iir;
755
756 u8 cur_delay;
757 u8 min_delay;
758 u8 max_delay;
759 u8 fmax;
760 u8 fstart;
761
762 u64 last_count1;
763 unsigned long last_time1;
764 unsigned long chipset_power;
765 u64 last_count2;
766 struct timespec last_time2;
767 unsigned long gfx_power;
768 int c_m;
769 int r_t;
770 u8 corr;
771 spinlock_t *mchdev_lock;
772
773 enum no_fbc_reason no_fbc_reason;
774
775 struct drm_mm_node *compressed_fb;
776 struct drm_mm_node *compressed_llb;
777
778 unsigned long last_gpu_reset;
779
780 /* list of fbdev register on this device */
781 struct intel_fbdev *fbdev;
782
783 struct backlight_device *backlight;
784
785 struct drm_property *broadcast_rgb_property;
786 struct drm_property *force_audio_property;
787 } drm_i915_private_t;
788
789 enum hdmi_force_audio {
790 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
791 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
792 HDMI_AUDIO_AUTO, /* trust EDID */
793 HDMI_AUDIO_ON, /* force turn on HDMI audio */
794 };
795
796 enum i915_cache_level {
797 I915_CACHE_NONE,
798 I915_CACHE_LLC,
799 I915_CACHE_LLC_MLC, /* gen6+ */
800 };
801
802 struct drm_i915_gem_object {
803 struct drm_gem_object base;
804
805 /** Current space allocated to this object in the GTT, if any. */
806 struct drm_mm_node *gtt_space;
807 struct list_head gtt_list;
808
809 /** This object's place on the active/flushing/inactive lists */
810 struct list_head ring_list;
811 struct list_head mm_list;
812 /** This object's place on GPU write list */
813 struct list_head gpu_write_list;
814 /** This object's place in the batchbuffer or on the eviction list */
815 struct list_head exec_list;
816
817 /**
818 * This is set if the object is on the active or flushing lists
819 * (has pending rendering), and is not set if it's on inactive (ready
820 * to be unbound).
821 */
822 unsigned int active:1;
823
824 /**
825 * This is set if the object has been written to since last bound
826 * to the GTT
827 */
828 unsigned int dirty:1;
829
830 /**
831 * This is set if the object has been written to since the last
832 * GPU flush.
833 */
834 unsigned int pending_gpu_write:1;
835
836 /**
837 * Fence register bits (if any) for this object. Will be set
838 * as needed when mapped into the GTT.
839 * Protected by dev->struct_mutex.
840 */
841 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
842
843 /**
844 * Advice: are the backing pages purgeable?
845 */
846 unsigned int madv:2;
847
848 /**
849 * Current tiling mode for the object.
850 */
851 unsigned int tiling_mode:2;
852 unsigned int tiling_changed:1;
853
854 /** How many users have pinned this object in GTT space. The following
855 * users can each hold at most one reference: pwrite/pread, pin_ioctl
856 * (via user_pin_count), execbuffer (objects are not allowed multiple
857 * times for the same batchbuffer), and the framebuffer code. When
858 * switching/pageflipping, the framebuffer code has at most two buffers
859 * pinned per crtc.
860 *
861 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
862 * bits with absolutely no headroom. So use 4 bits. */
863 unsigned int pin_count:4;
864 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
865
866 /**
867 * Is the object at the current location in the gtt mappable and
868 * fenceable? Used to avoid costly recalculations.
869 */
870 unsigned int map_and_fenceable:1;
871
872 /**
873 * Whether the current gtt mapping needs to be mappable (and isn't just
874 * mappable by accident). Track pin and fault separate for a more
875 * accurate mappable working set.
876 */
877 unsigned int fault_mappable:1;
878 unsigned int pin_mappable:1;
879
880 /*
881 * Is the GPU currently using a fence to access this buffer,
882 */
883 unsigned int pending_fenced_gpu_access:1;
884 unsigned int fenced_gpu_access:1;
885
886 unsigned int cache_level:2;
887
888 unsigned int has_aliasing_ppgtt_mapping:1;
889
890 struct page **pages;
891
892 /**
893 * DMAR support
894 */
895 struct scatterlist *sg_list;
896 int num_sg;
897
898 /**
899 * Used for performing relocations during execbuffer insertion.
900 */
901 struct hlist_node exec_node;
902 unsigned long exec_handle;
903 struct drm_i915_gem_exec_object2 *exec_entry;
904
905 /**
906 * Current offset of the object in GTT space.
907 *
908 * This is the same as gtt_space->start
909 */
910 uint32_t gtt_offset;
911
912 /** Breadcrumb of last rendering to the buffer. */
913 uint32_t last_rendering_seqno;
914 struct intel_ring_buffer *ring;
915
916 /** Breadcrumb of last fenced GPU access to the buffer. */
917 uint32_t last_fenced_seqno;
918 struct intel_ring_buffer *last_fenced_ring;
919
920 /** Current tiling stride for the object, if it's tiled. */
921 uint32_t stride;
922
923 /** Record of address bit 17 of each page at last unbind. */
924 unsigned long *bit_17;
925
926
927 /**
928 * If present, while GEM_DOMAIN_CPU is in the read domain this array
929 * flags which individual pages are valid.
930 */
931 uint8_t *page_cpu_valid;
932
933 /** User space pin count and filp owning the pin */
934 uint32_t user_pin_count;
935 struct drm_file *pin_filp;
936
937 /** for phy allocated objects */
938 struct drm_i915_gem_phys_object *phys_obj;
939
940 /**
941 * Number of crtcs where this object is currently the fb, but
942 * will be page flipped away on the next vblank. When it
943 * reaches 0, dev_priv->pending_flip_queue will be woken up.
944 */
945 atomic_t pending_flip;
946 };
947
948 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
949
950 /**
951 * Request queue structure.
952 *
953 * The request queue allows us to note sequence numbers that have been emitted
954 * and may be associated with active buffers to be retired.
955 *
956 * By keeping this list, we can avoid having to do questionable
957 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
958 * an emission time with seqnos for tracking how far ahead of the GPU we are.
959 */
960 struct drm_i915_gem_request {
961 /** On Which ring this request was generated */
962 struct intel_ring_buffer *ring;
963
964 /** GEM sequence number associated with this request. */
965 uint32_t seqno;
966
967 /** Postion in the ringbuffer of the end of the request */
968 u32 tail;
969
970 /** Time at which this request was emitted, in jiffies. */
971 unsigned long emitted_jiffies;
972
973 /** global list entry for this request */
974 struct list_head list;
975
976 struct drm_i915_file_private *file_priv;
977 /** file_priv list entry for this request */
978 struct list_head client_list;
979 };
980
981 struct drm_i915_file_private {
982 struct {
983 struct spinlock lock;
984 struct list_head request_list;
985 } mm;
986 };
987
988 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
989
990 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
991 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
992 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
993 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
994 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
995 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
996 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
997 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
998 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
999 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1000 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1001 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1002 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1003 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1004 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1005 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1006 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1007 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1008 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1009 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1010
1011 /*
1012 * The genX designation typically refers to the render engine, so render
1013 * capability related checks should use IS_GEN, while display and other checks
1014 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1015 * chips, etc.).
1016 */
1017 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1018 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1019 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1020 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1021 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1022 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1023
1024 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1025 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1026 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1027 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1028
1029 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6)
1030
1031 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1032 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1033
1034 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1035 * rows, which changed the alignment requirements and fence programming.
1036 */
1037 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1038 IS_I915GM(dev)))
1039 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1040 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1041 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1042 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1043 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1044 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1045 /* dsparb controlled by hw only */
1046 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1047
1048 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1049 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1050 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1051
1052 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
1053 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1054
1055 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1056 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1057 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1058
1059 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1060
1061 #include "i915_trace.h"
1062
1063 /**
1064 * RC6 is a special power stage which allows the GPU to enter an very
1065 * low-voltage mode when idle, using down to 0V while at this stage. This
1066 * stage is entered automatically when the GPU is idle when RC6 support is
1067 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1068 *
1069 * There are different RC6 modes available in Intel GPU, which differentiate
1070 * among each other with the latency required to enter and leave RC6 and
1071 * voltage consumed by the GPU in different states.
1072 *
1073 * The combination of the following flags define which states GPU is allowed
1074 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1075 * RC6pp is deepest RC6. Their support by hardware varies according to the
1076 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1077 * which brings the most power savings; deeper states save more power, but
1078 * require higher latency to switch to and wake up.
1079 */
1080 #define INTEL_RC6_ENABLE (1<<0)
1081 #define INTEL_RC6p_ENABLE (1<<1)
1082 #define INTEL_RC6pp_ENABLE (1<<2)
1083
1084 extern struct drm_ioctl_desc i915_ioctls[];
1085 extern int i915_max_ioctl;
1086 extern unsigned int i915_fbpercrtc __always_unused;
1087 extern int i915_panel_ignore_lid __read_mostly;
1088 extern unsigned int i915_powersave __read_mostly;
1089 extern int i915_semaphores __read_mostly;
1090 extern unsigned int i915_lvds_downclock __read_mostly;
1091 extern int i915_panel_use_ssc __read_mostly;
1092 extern int i915_vbt_sdvo_panel_type __read_mostly;
1093 extern int i915_enable_rc6 __read_mostly;
1094 extern int i915_enable_fbc __read_mostly;
1095 extern bool i915_enable_hangcheck __read_mostly;
1096 extern int i915_enable_ppgtt __read_mostly;
1097
1098 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1099 extern int i915_resume(struct drm_device *dev);
1100 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1101 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1102
1103 /* i915_dma.c */
1104 extern void i915_kernel_lost_context(struct drm_device * dev);
1105 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1106 extern int i915_driver_unload(struct drm_device *);
1107 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1108 extern void i915_driver_lastclose(struct drm_device * dev);
1109 extern void i915_driver_preclose(struct drm_device *dev,
1110 struct drm_file *file_priv);
1111 extern void i915_driver_postclose(struct drm_device *dev,
1112 struct drm_file *file_priv);
1113 extern int i915_driver_device_is_agp(struct drm_device * dev);
1114 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1115 unsigned long arg);
1116 extern int i915_emit_box(struct drm_device *dev,
1117 struct drm_clip_rect *box,
1118 int DR1, int DR4);
1119 extern int i915_reset(struct drm_device *dev, u8 flags);
1120 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1121 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1122 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1123 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1124
1125
1126 /* i915_irq.c */
1127 void i915_hangcheck_elapsed(unsigned long data);
1128 void i915_handle_error(struct drm_device *dev, bool wedged);
1129 extern int i915_irq_emit(struct drm_device *dev, void *data,
1130 struct drm_file *file_priv);
1131 extern int i915_irq_wait(struct drm_device *dev, void *data,
1132 struct drm_file *file_priv);
1133
1134 extern void intel_irq_init(struct drm_device *dev);
1135
1136 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1137 struct drm_file *file_priv);
1138 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1139 struct drm_file *file_priv);
1140 extern int i915_vblank_swap(struct drm_device *dev, void *data,
1141 struct drm_file *file_priv);
1142
1143 void
1144 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1145
1146 void
1147 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1148
1149 void intel_enable_asle(struct drm_device *dev);
1150
1151 #ifdef CONFIG_DEBUG_FS
1152 extern void i915_destroy_error_state(struct drm_device *dev);
1153 #else
1154 #define i915_destroy_error_state(x)
1155 #endif
1156
1157
1158 /* i915_gem.c */
1159 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1160 struct drm_file *file_priv);
1161 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1162 struct drm_file *file_priv);
1163 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1164 struct drm_file *file_priv);
1165 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1166 struct drm_file *file_priv);
1167 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1168 struct drm_file *file_priv);
1169 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1170 struct drm_file *file_priv);
1171 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1172 struct drm_file *file_priv);
1173 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1174 struct drm_file *file_priv);
1175 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1176 struct drm_file *file_priv);
1177 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1178 struct drm_file *file_priv);
1179 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1180 struct drm_file *file_priv);
1181 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1182 struct drm_file *file_priv);
1183 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1184 struct drm_file *file_priv);
1185 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1186 struct drm_file *file_priv);
1187 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1188 struct drm_file *file_priv);
1189 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1190 struct drm_file *file_priv);
1191 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1192 struct drm_file *file_priv);
1193 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1194 struct drm_file *file_priv);
1195 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1196 struct drm_file *file_priv);
1197 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1198 struct drm_file *file_priv);
1199 void i915_gem_load(struct drm_device *dev);
1200 int i915_gem_init_object(struct drm_gem_object *obj);
1201 int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
1202 uint32_t invalidate_domains,
1203 uint32_t flush_domains);
1204 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1205 size_t size);
1206 void i915_gem_free_object(struct drm_gem_object *obj);
1207 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1208 uint32_t alignment,
1209 bool map_and_fenceable);
1210 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1211 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1212 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1213 void i915_gem_lastclose(struct drm_device *dev);
1214
1215 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1216 int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
1217 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1218 struct intel_ring_buffer *ring,
1219 u32 seqno);
1220
1221 int i915_gem_dumb_create(struct drm_file *file_priv,
1222 struct drm_device *dev,
1223 struct drm_mode_create_dumb *args);
1224 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1225 uint32_t handle, uint64_t *offset);
1226 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1227 uint32_t handle);
1228 /**
1229 * Returns true if seq1 is later than seq2.
1230 */
1231 static inline bool
i915_seqno_passed(uint32_t seq1,uint32_t seq2)1232 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1233 {
1234 return (int32_t)(seq1 - seq2) >= 0;
1235 }
1236
1237 u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring);
1238
1239 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1240 struct intel_ring_buffer *pipelined);
1241 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1242
1243 static inline void
i915_gem_object_pin_fence(struct drm_i915_gem_object * obj)1244 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1245 {
1246 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1247 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1248 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1249 }
1250 }
1251
1252 static inline void
i915_gem_object_unpin_fence(struct drm_i915_gem_object * obj)1253 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1254 {
1255 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1256 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1257 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1258 }
1259 }
1260
1261 void i915_gem_retire_requests(struct drm_device *dev);
1262 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1263
1264 void i915_gem_reset(struct drm_device *dev);
1265 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1266 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1267 uint32_t read_domains,
1268 uint32_t write_domain);
1269 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1270 int __must_check i915_gem_init_hw(struct drm_device *dev);
1271 void i915_gem_init_swizzling(struct drm_device *dev);
1272 void i915_gem_init_ppgtt(struct drm_device *dev);
1273 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1274 void i915_gem_do_init(struct drm_device *dev,
1275 unsigned long start,
1276 unsigned long mappable_end,
1277 unsigned long end);
1278 int __must_check i915_gpu_idle(struct drm_device *dev, bool do_retire);
1279 int __must_check i915_gem_idle(struct drm_device *dev);
1280 int __must_check i915_add_request(struct intel_ring_buffer *ring,
1281 struct drm_file *file,
1282 struct drm_i915_gem_request *request);
1283 int __must_check i915_wait_request(struct intel_ring_buffer *ring,
1284 uint32_t seqno,
1285 bool do_retire);
1286 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1287 int __must_check
1288 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1289 bool write);
1290 int __must_check
1291 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1292 u32 alignment,
1293 struct intel_ring_buffer *pipelined);
1294 int i915_gem_attach_phys_object(struct drm_device *dev,
1295 struct drm_i915_gem_object *obj,
1296 int id,
1297 int align);
1298 void i915_gem_detach_phys_object(struct drm_device *dev,
1299 struct drm_i915_gem_object *obj);
1300 void i915_gem_free_all_phys_object(struct drm_device *dev);
1301 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1302
1303 uint32_t
1304 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1305 uint32_t size,
1306 int tiling_mode);
1307
1308 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1309 enum i915_cache_level cache_level);
1310
1311 /* i915_gem_gtt.c */
1312 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1313 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1314 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1315 struct drm_i915_gem_object *obj,
1316 enum i915_cache_level cache_level);
1317 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1318 struct drm_i915_gem_object *obj);
1319
1320 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1321 int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
1322 void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
1323 enum i915_cache_level cache_level);
1324 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1325
1326 /* i915_gem_evict.c */
1327 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1328 unsigned alignment, bool mappable);
1329 int __must_check i915_gem_evict_everything(struct drm_device *dev,
1330 bool purgeable_only);
1331 int __must_check i915_gem_evict_inactive(struct drm_device *dev,
1332 bool purgeable_only);
1333
1334 /* i915_gem_tiling.c */
1335 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1336 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1337 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1338
1339 /* i915_gem_debug.c */
1340 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1341 const char *where, uint32_t mark);
1342 #if WATCH_LISTS
1343 int i915_verify_lists(struct drm_device *dev);
1344 #else
1345 #define i915_verify_lists(dev) 0
1346 #endif
1347 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1348 int handle);
1349 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1350 const char *where, uint32_t mark);
1351
1352 /* i915_debugfs.c */
1353 int i915_debugfs_init(struct drm_minor *minor);
1354 void i915_debugfs_cleanup(struct drm_minor *minor);
1355
1356 /* i915_suspend.c */
1357 extern int i915_save_state(struct drm_device *dev);
1358 extern int i915_restore_state(struct drm_device *dev);
1359
1360 /* i915_suspend.c */
1361 extern int i915_save_state(struct drm_device *dev);
1362 extern int i915_restore_state(struct drm_device *dev);
1363
1364 /* intel_i2c.c */
1365 extern int intel_setup_gmbus(struct drm_device *dev);
1366 extern void intel_teardown_gmbus(struct drm_device *dev);
1367 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1368 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
intel_gmbus_is_forced_bit(struct i2c_adapter * adapter)1369 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1370 {
1371 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1372 }
1373 extern void intel_i2c_reset(struct drm_device *dev);
1374
1375 /* intel_opregion.c */
1376 extern int intel_opregion_setup(struct drm_device *dev);
1377 #ifdef CONFIG_ACPI
1378 extern void intel_opregion_init(struct drm_device *dev);
1379 extern void intel_opregion_fini(struct drm_device *dev);
1380 extern void intel_opregion_asle_intr(struct drm_device *dev);
1381 extern void intel_opregion_gse_intr(struct drm_device *dev);
1382 extern void intel_opregion_enable_asle(struct drm_device *dev);
1383 #else
intel_opregion_init(struct drm_device * dev)1384 static inline void intel_opregion_init(struct drm_device *dev) { return; }
intel_opregion_fini(struct drm_device * dev)1385 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
intel_opregion_asle_intr(struct drm_device * dev)1386 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
intel_opregion_gse_intr(struct drm_device * dev)1387 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
intel_opregion_enable_asle(struct drm_device * dev)1388 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1389 #endif
1390
1391 /* intel_acpi.c */
1392 #ifdef CONFIG_ACPI
1393 extern void intel_register_dsm_handler(void);
1394 extern void intel_unregister_dsm_handler(void);
1395 #else
intel_register_dsm_handler(void)1396 static inline void intel_register_dsm_handler(void) { return; }
intel_unregister_dsm_handler(void)1397 static inline void intel_unregister_dsm_handler(void) { return; }
1398 #endif /* CONFIG_ACPI */
1399
1400 /* modesetting */
1401 extern void i915_redisable_vga(struct drm_device *dev);
1402 extern void intel_modeset_init(struct drm_device *dev);
1403 extern void intel_modeset_gem_init(struct drm_device *dev);
1404 extern void intel_modeset_cleanup(struct drm_device *dev);
1405 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1406 extern bool intel_fbc_enabled(struct drm_device *dev);
1407 extern void intel_disable_fbc(struct drm_device *dev);
1408 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1409 extern void ironlake_init_pch_refclk(struct drm_device *dev);
1410 extern void ironlake_enable_rc6(struct drm_device *dev);
1411 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1412 extern void intel_detect_pch(struct drm_device *dev);
1413 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1414
1415 extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1416 extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv);
1417 extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1418 extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
1419
1420 /* overlay */
1421 #ifdef CONFIG_DEBUG_FS
1422 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1423 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1424
1425 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1426 extern void intel_display_print_error_state(struct seq_file *m,
1427 struct drm_device *dev,
1428 struct intel_display_error_state *error);
1429 #endif
1430
1431 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1432
1433 #define BEGIN_LP_RING(n) \
1434 intel_ring_begin(LP_RING(dev_priv), (n))
1435
1436 #define OUT_RING(x) \
1437 intel_ring_emit(LP_RING(dev_priv), x)
1438
1439 #define ADVANCE_LP_RING() \
1440 intel_ring_advance(LP_RING(dev_priv))
1441
1442 /**
1443 * Lock test for when it's just for synchronization of ring access.
1444 *
1445 * In that case, we don't need to do it when GEM is initialized as nobody else
1446 * has access to the ring.
1447 */
1448 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1449 if (LP_RING(dev->dev_private)->obj == NULL) \
1450 LOCK_TEST_WITH_RETURN(dev, file); \
1451 } while (0)
1452
1453 /* On SNB platform, before reading ring registers forcewake bit
1454 * must be set to prevent GT core from power down and stale values being
1455 * returned.
1456 */
1457 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1458 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1459 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1460
1461 #define __i915_read(x, y) \
1462 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1463
1464 __i915_read(8, b)
1465 __i915_read(16, w)
1466 __i915_read(32, l)
1467 __i915_read(64, q)
1468 #undef __i915_read
1469
1470 #define __i915_write(x, y) \
1471 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1472
1473 __i915_write(8, b)
1474 __i915_write(16, w)
1475 __i915_write(32, l)
1476 __i915_write(64, q)
1477 #undef __i915_write
1478
1479 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1480 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1481
1482 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1483 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1484 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1485 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1486
1487 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1488 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1489 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1490 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1491
1492 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1493 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1494
1495 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1496 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1497
1498
1499 #endif
1500