1 #ifndef _QIB_KERNEL_H
2 #define _QIB_KERNEL_H
3 /*
4 * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation.
5 * All rights reserved.
6 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 */
36
37 /*
38 * This header file is the base header file for qlogic_ib kernel code
39 * qib_user.h serves a similar purpose for user code.
40 */
41
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/mutex.h>
46 #include <linux/list.h>
47 #include <linux/scatterlist.h>
48 #include <linux/slab.h>
49 #include <linux/io.h>
50 #include <linux/fs.h>
51 #include <linux/completion.h>
52 #include <linux/kref.h>
53 #include <linux/sched.h>
54
55 #include "qib_common.h"
56 #include "qib_verbs.h"
57
58 /* only s/w major version of QLogic_IB we can handle */
59 #define QIB_CHIP_VERS_MAJ 2U
60
61 /* don't care about this except printing */
62 #define QIB_CHIP_VERS_MIN 0U
63
64 /* The Organization Unique Identifier (Mfg code), and its position in GUID */
65 #define QIB_OUI 0x001175
66 #define QIB_OUI_LSB 40
67
68 /*
69 * per driver stats, either not device nor port-specific, or
70 * summed over all of the devices and ports.
71 * They are described by name via ipathfs filesystem, so layout
72 * and number of elements can change without breaking compatibility.
73 * If members are added or deleted qib_statnames[] in qib_fs.c must
74 * change to match.
75 */
76 struct qlogic_ib_stats {
77 __u64 sps_ints; /* number of interrupts handled */
78 __u64 sps_errints; /* number of error interrupts */
79 __u64 sps_txerrs; /* tx-related packet errors */
80 __u64 sps_rcverrs; /* non-crc rcv packet errors */
81 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */
82 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */
83 __u64 sps_ctxts; /* number of contexts currently open */
84 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */
85 __u64 sps_buffull;
86 __u64 sps_hdrfull;
87 };
88
89 extern struct qlogic_ib_stats qib_stats;
90 extern struct pci_error_handlers qib_pci_err_handler;
91 extern struct pci_driver qib_driver;
92
93 #define QIB_CHIP_SWVERSION QIB_CHIP_VERS_MAJ
94 /*
95 * First-cut critierion for "device is active" is
96 * two thousand dwords combined Tx, Rx traffic per
97 * 5-second interval. SMA packets are 64 dwords,
98 * and occur "a few per second", presumably each way.
99 */
100 #define QIB_TRAFFIC_ACTIVE_THRESHOLD (2000)
101
102 /*
103 * Struct used to indicate which errors are logged in each of the
104 * error-counters that are logged to EEPROM. A counter is incremented
105 * _once_ (saturating at 255) for each event with any bits set in
106 * the error or hwerror register masks below.
107 */
108 #define QIB_EEP_LOG_CNT (4)
109 struct qib_eep_log_mask {
110 u64 errs_to_log;
111 u64 hwerrs_to_log;
112 };
113
114 /*
115 * Below contains all data related to a single context (formerly called port).
116 */
117 struct qib_ctxtdata {
118 void **rcvegrbuf;
119 dma_addr_t *rcvegrbuf_phys;
120 /* rcvhdrq base, needs mmap before useful */
121 void *rcvhdrq;
122 /* kernel virtual address where hdrqtail is updated */
123 void *rcvhdrtail_kvaddr;
124 /*
125 * temp buffer for expected send setup, allocated at open, instead
126 * of each setup call
127 */
128 void *tid_pg_list;
129 /*
130 * Shared page for kernel to signal user processes that send buffers
131 * need disarming. The process should call QIB_CMD_DISARM_BUFS
132 * or QIB_CMD_ACK_EVENT with IPATH_EVENT_DISARM_BUFS set.
133 */
134 unsigned long *user_event_mask;
135 /* when waiting for rcv or pioavail */
136 wait_queue_head_t wait;
137 /*
138 * rcvegr bufs base, physical, must fit
139 * in 44 bits so 32 bit programs mmap64 44 bit works)
140 */
141 dma_addr_t rcvegr_phys;
142 /* mmap of hdrq, must fit in 44 bits */
143 dma_addr_t rcvhdrq_phys;
144 dma_addr_t rcvhdrqtailaddr_phys;
145
146 /*
147 * number of opens (including slave sub-contexts) on this instance
148 * (ignoring forks, dup, etc. for now)
149 */
150 int cnt;
151 /*
152 * how much space to leave at start of eager TID entries for
153 * protocol use, on each TID
154 */
155 /* instead of calculating it */
156 unsigned ctxt;
157 /* non-zero if ctxt is being shared. */
158 u16 subctxt_cnt;
159 /* non-zero if ctxt is being shared. */
160 u16 subctxt_id;
161 /* number of eager TID entries. */
162 u16 rcvegrcnt;
163 /* index of first eager TID entry. */
164 u16 rcvegr_tid_base;
165 /* number of pio bufs for this ctxt (all procs, if shared) */
166 u32 piocnt;
167 /* first pio buffer for this ctxt */
168 u32 pio_base;
169 /* chip offset of PIO buffers for this ctxt */
170 u32 piobufs;
171 /* how many alloc_pages() chunks in rcvegrbuf_pages */
172 u32 rcvegrbuf_chunks;
173 /* how many egrbufs per chunk */
174 u32 rcvegrbufs_perchunk;
175 /* order for rcvegrbuf_pages */
176 size_t rcvegrbuf_size;
177 /* rcvhdrq size (for freeing) */
178 size_t rcvhdrq_size;
179 /* per-context flags for fileops/intr communication */
180 unsigned long flag;
181 /* next expected TID to check when looking for free */
182 u32 tidcursor;
183 /* WAIT_RCV that timed out, no interrupt */
184 u32 rcvwait_to;
185 /* WAIT_PIO that timed out, no interrupt */
186 u32 piowait_to;
187 /* WAIT_RCV already happened, no wait */
188 u32 rcvnowait;
189 /* WAIT_PIO already happened, no wait */
190 u32 pionowait;
191 /* total number of polled urgent packets */
192 u32 urgent;
193 /* saved total number of polled urgent packets for poll edge trigger */
194 u32 urgent_poll;
195 /* pid of process using this ctxt */
196 pid_t pid;
197 pid_t subpid[QLOGIC_IB_MAX_SUBCTXT];
198 /* same size as task_struct .comm[], command that opened context */
199 char comm[16];
200 /* pkeys set by this use of this ctxt */
201 u16 pkeys[4];
202 /* so file ops can get at unit */
203 struct qib_devdata *dd;
204 /* so funcs that need physical port can get it easily */
205 struct qib_pportdata *ppd;
206 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
207 void *subctxt_uregbase;
208 /* An array of pages for the eager receive buffers * N */
209 void *subctxt_rcvegrbuf;
210 /* An array of pages for the eager header queue entries * N */
211 void *subctxt_rcvhdr_base;
212 /* The version of the library which opened this ctxt */
213 u32 userversion;
214 /* Bitmask of active slaves */
215 u32 active_slaves;
216 /* Type of packets or conditions we want to poll for */
217 u16 poll_type;
218 /* receive packet sequence counter */
219 u8 seq_cnt;
220 u8 redirect_seq_cnt;
221 /* ctxt rcvhdrq head offset */
222 u32 head;
223 u32 pkt_count;
224 /* QPs waiting for context processing */
225 struct list_head qp_wait_list;
226 };
227
228 struct qib_sge_state;
229
230 struct qib_sdma_txreq {
231 int flags;
232 int sg_count;
233 dma_addr_t addr;
234 void (*callback)(struct qib_sdma_txreq *, int);
235 u16 start_idx; /* sdma private */
236 u16 next_descq_idx; /* sdma private */
237 struct list_head list; /* sdma private */
238 };
239
240 struct qib_sdma_desc {
241 __le64 qw[2];
242 };
243
244 struct qib_verbs_txreq {
245 struct qib_sdma_txreq txreq;
246 struct qib_qp *qp;
247 struct qib_swqe *wqe;
248 u32 dwords;
249 u16 hdr_dwords;
250 u16 hdr_inx;
251 struct qib_pio_header *align_buf;
252 struct qib_mregion *mr;
253 struct qib_sge_state *ss;
254 };
255
256 #define QIB_SDMA_TXREQ_F_USELARGEBUF 0x1
257 #define QIB_SDMA_TXREQ_F_HEADTOHOST 0x2
258 #define QIB_SDMA_TXREQ_F_INTREQ 0x4
259 #define QIB_SDMA_TXREQ_F_FREEBUF 0x8
260 #define QIB_SDMA_TXREQ_F_FREEDESC 0x10
261
262 #define QIB_SDMA_TXREQ_S_OK 0
263 #define QIB_SDMA_TXREQ_S_SENDERROR 1
264 #define QIB_SDMA_TXREQ_S_ABORTED 2
265 #define QIB_SDMA_TXREQ_S_SHUTDOWN 3
266
267 /*
268 * Get/Set IB link-level config parameters for f_get/set_ib_cfg()
269 * Mostly for MADs that set or query link parameters, also ipath
270 * config interfaces
271 */
272 #define QIB_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */
273 #define QIB_IB_CFG_LWID_ENB 2 /* allowed Link-width */
274 #define QIB_IB_CFG_LWID 3 /* currently active Link-width */
275 #define QIB_IB_CFG_SPD_ENB 4 /* allowed Link speeds */
276 #define QIB_IB_CFG_SPD 5 /* current Link spd */
277 #define QIB_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */
278 #define QIB_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */
279 #define QIB_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */
280 #define QIB_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */
281 #define QIB_IB_CFG_OP_VLS 10 /* operational VLs */
282 #define QIB_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */
283 #define QIB_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */
284 #define QIB_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */
285 #define QIB_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */
286 #define QIB_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */
287 #define QIB_IB_CFG_PKEYS 16 /* update partition keys */
288 #define QIB_IB_CFG_MTU 17 /* update MTU in IBC */
289 #define QIB_IB_CFG_LSTATE 18 /* update linkcmd and linkinitcmd in IBC */
290 #define QIB_IB_CFG_VL_HIGH_LIMIT 19
291 #define QIB_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */
292 #define QIB_IB_CFG_PORT 21 /* switch port we are connected to */
293
294 /*
295 * for CFG_LSTATE: LINKCMD in upper 16 bits, LINKINITCMD in lower 16
296 * IB_LINKINITCMD_POLL and SLEEP are also used as set/get values for
297 * QIB_IB_CFG_LINKDEFAULT cmd
298 */
299 #define IB_LINKCMD_DOWN (0 << 16)
300 #define IB_LINKCMD_ARMED (1 << 16)
301 #define IB_LINKCMD_ACTIVE (2 << 16)
302 #define IB_LINKINITCMD_NOP 0
303 #define IB_LINKINITCMD_POLL 1
304 #define IB_LINKINITCMD_SLEEP 2
305 #define IB_LINKINITCMD_DISABLE 3
306
307 /*
308 * valid states passed to qib_set_linkstate() user call
309 */
310 #define QIB_IB_LINKDOWN 0
311 #define QIB_IB_LINKARM 1
312 #define QIB_IB_LINKACTIVE 2
313 #define QIB_IB_LINKDOWN_ONLY 3
314 #define QIB_IB_LINKDOWN_SLEEP 4
315 #define QIB_IB_LINKDOWN_DISABLE 5
316
317 /*
318 * These 7 values (SDR, DDR, and QDR may be ORed for auto-speed
319 * negotiation) are used for the 3rd argument to path_f_set_ib_cfg
320 * with cmd QIB_IB_CFG_SPD_ENB, by direct calls or via sysfs. They
321 * are also the the possible values for qib_link_speed_enabled and active
322 * The values were chosen to match values used within the IB spec.
323 */
324 #define QIB_IB_SDR 1
325 #define QIB_IB_DDR 2
326 #define QIB_IB_QDR 4
327
328 #define QIB_DEFAULT_MTU 4096
329
330 /* max number of IB ports supported per HCA */
331 #define QIB_MAX_IB_PORTS 2
332
333 /*
334 * Possible IB config parameters for f_get/set_ib_table()
335 */
336 #define QIB_IB_TBL_VL_HIGH_ARB 1 /* Get/set VL high priority weights */
337 #define QIB_IB_TBL_VL_LOW_ARB 2 /* Get/set VL low priority weights */
338
339 /*
340 * Possible "operations" for f_rcvctrl(ppd, op, ctxt)
341 * these are bits so they can be combined, e.g.
342 * QIB_RCVCTRL_INTRAVAIL_ENB | QIB_RCVCTRL_CTXT_ENB
343 */
344 #define QIB_RCVCTRL_TAILUPD_ENB 0x01
345 #define QIB_RCVCTRL_TAILUPD_DIS 0x02
346 #define QIB_RCVCTRL_CTXT_ENB 0x04
347 #define QIB_RCVCTRL_CTXT_DIS 0x08
348 #define QIB_RCVCTRL_INTRAVAIL_ENB 0x10
349 #define QIB_RCVCTRL_INTRAVAIL_DIS 0x20
350 #define QIB_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */
351 #define QIB_RCVCTRL_PKEY_DIS 0x80
352 #define QIB_RCVCTRL_BP_ENB 0x0100
353 #define QIB_RCVCTRL_BP_DIS 0x0200
354 #define QIB_RCVCTRL_TIDFLOW_ENB 0x0400
355 #define QIB_RCVCTRL_TIDFLOW_DIS 0x0800
356
357 /*
358 * Possible "operations" for f_sendctrl(ppd, op, var)
359 * these are bits so they can be combined, e.g.
360 * QIB_SENDCTRL_BUFAVAIL_ENB | QIB_SENDCTRL_ENB
361 * Some operations (e.g. DISARM, ABORT) are known to
362 * be "one-shot", so do not modify shadow.
363 */
364 #define QIB_SENDCTRL_DISARM (0x1000)
365 #define QIB_SENDCTRL_DISARM_BUF(bufn) ((bufn) | QIB_SENDCTRL_DISARM)
366 /* available (0x2000) */
367 #define QIB_SENDCTRL_AVAIL_DIS (0x4000)
368 #define QIB_SENDCTRL_AVAIL_ENB (0x8000)
369 #define QIB_SENDCTRL_AVAIL_BLIP (0x10000)
370 #define QIB_SENDCTRL_SEND_DIS (0x20000)
371 #define QIB_SENDCTRL_SEND_ENB (0x40000)
372 #define QIB_SENDCTRL_FLUSH (0x80000)
373 #define QIB_SENDCTRL_CLEAR (0x100000)
374 #define QIB_SENDCTRL_DISARM_ALL (0x200000)
375
376 /*
377 * These are the generic indices for requesting per-port
378 * counter values via the f_portcntr function. They
379 * are always returned as 64 bit values, although most
380 * are 32 bit counters.
381 */
382 /* send-related counters */
383 #define QIBPORTCNTR_PKTSEND 0U
384 #define QIBPORTCNTR_WORDSEND 1U
385 #define QIBPORTCNTR_PSXMITDATA 2U
386 #define QIBPORTCNTR_PSXMITPKTS 3U
387 #define QIBPORTCNTR_PSXMITWAIT 4U
388 #define QIBPORTCNTR_SENDSTALL 5U
389 /* receive-related counters */
390 #define QIBPORTCNTR_PKTRCV 6U
391 #define QIBPORTCNTR_PSRCVDATA 7U
392 #define QIBPORTCNTR_PSRCVPKTS 8U
393 #define QIBPORTCNTR_RCVEBP 9U
394 #define QIBPORTCNTR_RCVOVFL 10U
395 #define QIBPORTCNTR_WORDRCV 11U
396 /* IB link related error counters */
397 #define QIBPORTCNTR_RXLOCALPHYERR 12U
398 #define QIBPORTCNTR_RXVLERR 13U
399 #define QIBPORTCNTR_ERRICRC 14U
400 #define QIBPORTCNTR_ERRVCRC 15U
401 #define QIBPORTCNTR_ERRLPCRC 16U
402 #define QIBPORTCNTR_BADFORMAT 17U
403 #define QIBPORTCNTR_ERR_RLEN 18U
404 #define QIBPORTCNTR_IBSYMBOLERR 19U
405 #define QIBPORTCNTR_INVALIDRLEN 20U
406 #define QIBPORTCNTR_UNSUPVL 21U
407 #define QIBPORTCNTR_EXCESSBUFOVFL 22U
408 #define QIBPORTCNTR_ERRLINK 23U
409 #define QIBPORTCNTR_IBLINKDOWN 24U
410 #define QIBPORTCNTR_IBLINKERRRECOV 25U
411 #define QIBPORTCNTR_LLI 26U
412 /* other error counters */
413 #define QIBPORTCNTR_RXDROPPKT 27U
414 #define QIBPORTCNTR_VL15PKTDROP 28U
415 #define QIBPORTCNTR_ERRPKEY 29U
416 #define QIBPORTCNTR_KHDROVFL 30U
417 /* sampling counters (these are actually control registers) */
418 #define QIBPORTCNTR_PSINTERVAL 31U
419 #define QIBPORTCNTR_PSSTART 32U
420 #define QIBPORTCNTR_PSSTAT 33U
421
422 /* how often we check for packet activity for "power on hours (in seconds) */
423 #define ACTIVITY_TIMER 5
424
425 /* Below is an opaque struct. Each chip (device) can maintain
426 * private data needed for its operation, but not germane to the
427 * rest of the driver. For convenience, we define another that
428 * is chip-specific, per-port
429 */
430 struct qib_chip_specific;
431 struct qib_chipport_specific;
432
433 enum qib_sdma_states {
434 qib_sdma_state_s00_hw_down,
435 qib_sdma_state_s10_hw_start_up_wait,
436 qib_sdma_state_s20_idle,
437 qib_sdma_state_s30_sw_clean_up_wait,
438 qib_sdma_state_s40_hw_clean_up_wait,
439 qib_sdma_state_s50_hw_halt_wait,
440 qib_sdma_state_s99_running,
441 };
442
443 enum qib_sdma_events {
444 qib_sdma_event_e00_go_hw_down,
445 qib_sdma_event_e10_go_hw_start,
446 qib_sdma_event_e20_hw_started,
447 qib_sdma_event_e30_go_running,
448 qib_sdma_event_e40_sw_cleaned,
449 qib_sdma_event_e50_hw_cleaned,
450 qib_sdma_event_e60_hw_halted,
451 qib_sdma_event_e70_go_idle,
452 qib_sdma_event_e7220_err_halted,
453 qib_sdma_event_e7322_err_halted,
454 qib_sdma_event_e90_timer_tick,
455 };
456
457 extern char *qib_sdma_state_names[];
458 extern char *qib_sdma_event_names[];
459
460 struct sdma_set_state_action {
461 unsigned op_enable:1;
462 unsigned op_intenable:1;
463 unsigned op_halt:1;
464 unsigned op_drain:1;
465 unsigned go_s99_running_tofalse:1;
466 unsigned go_s99_running_totrue:1;
467 };
468
469 struct qib_sdma_state {
470 struct kref kref;
471 struct completion comp;
472 enum qib_sdma_states current_state;
473 struct sdma_set_state_action *set_state_action;
474 unsigned current_op;
475 unsigned go_s99_running;
476 unsigned first_sendbuf;
477 unsigned last_sendbuf; /* really last +1 */
478 /* debugging/devel */
479 enum qib_sdma_states previous_state;
480 unsigned previous_op;
481 enum qib_sdma_events last_event;
482 };
483
484 struct xmit_wait {
485 struct timer_list timer;
486 u64 counter;
487 u8 flags;
488 struct cache {
489 u64 psxmitdata;
490 u64 psrcvdata;
491 u64 psxmitpkts;
492 u64 psrcvpkts;
493 u64 psxmitwait;
494 } counter_cache;
495 };
496
497 /*
498 * The structure below encapsulates data relevant to a physical IB Port.
499 * Current chips support only one such port, but the separation
500 * clarifies things a bit. Note that to conform to IB conventions,
501 * port-numbers are one-based. The first or only port is port1.
502 */
503 struct qib_pportdata {
504 struct qib_ibport ibport_data;
505
506 struct qib_devdata *dd;
507 struct qib_chippport_specific *cpspec; /* chip-specific per-port */
508 struct kobject pport_kobj;
509 struct kobject sl2vl_kobj;
510 struct kobject diagc_kobj;
511
512 /* GUID for this interface, in network order */
513 __be64 guid;
514
515 /* QIB_POLL, etc. link-state specific flags, per port */
516 u32 lflags;
517 /* qib_lflags driver is waiting for */
518 u32 state_wanted;
519 spinlock_t lflags_lock;
520 /* number of (port-specific) interrupts for this port -- saturates... */
521 u32 int_counter;
522
523 /* ref count for each pkey */
524 atomic_t pkeyrefs[4];
525
526 /*
527 * this address is mapped readonly into user processes so they can
528 * get status cheaply, whenever they want. One qword of status per port
529 */
530 u64 *statusp;
531
532 /* SendDMA related entries */
533 spinlock_t sdma_lock;
534 struct qib_sdma_state sdma_state;
535 unsigned long sdma_buf_jiffies;
536 struct qib_sdma_desc *sdma_descq;
537 u64 sdma_descq_added;
538 u64 sdma_descq_removed;
539 u16 sdma_descq_cnt;
540 u16 sdma_descq_tail;
541 u16 sdma_descq_head;
542 u16 sdma_next_intr;
543 u16 sdma_reset_wait;
544 u8 sdma_generation;
545 struct tasklet_struct sdma_sw_clean_up_task;
546 struct list_head sdma_activelist;
547
548 dma_addr_t sdma_descq_phys;
549 volatile __le64 *sdma_head_dma; /* DMA'ed by chip */
550 dma_addr_t sdma_head_phys;
551
552 wait_queue_head_t state_wait; /* for state_wanted */
553
554 /* HoL blocking for SMP replies */
555 unsigned hol_state;
556 struct timer_list hol_timer;
557
558 /*
559 * Shadow copies of registers; size indicates read access size.
560 * Most of them are readonly, but some are write-only register,
561 * where we manipulate the bits in the shadow copy, and then write
562 * the shadow copy to qlogic_ib.
563 *
564 * We deliberately make most of these 32 bits, since they have
565 * restricted range. For any that we read, we won't to generate 32
566 * bit accesses, since Opteron will generate 2 separate 32 bit HT
567 * transactions for a 64 bit read, and we want to avoid unnecessary
568 * bus transactions.
569 */
570
571 /* This is the 64 bit group */
572 /* last ibcstatus. opaque outside chip-specific code */
573 u64 lastibcstat;
574
575 /* these are the "32 bit" regs */
576
577 /*
578 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
579 * all expect bit fields to be "unsigned long"
580 */
581 unsigned long p_rcvctrl; /* shadow per-port rcvctrl */
582 unsigned long p_sendctrl; /* shadow per-port sendctrl */
583
584 u32 ibmtu; /* The MTU programmed for this unit */
585 /*
586 * Current max size IB packet (in bytes) including IB headers, that
587 * we can send. Changes when ibmtu changes.
588 */
589 u32 ibmaxlen;
590 /*
591 * ibmaxlen at init time, limited by chip and by receive buffer
592 * size. Not changed after init.
593 */
594 u32 init_ibmaxlen;
595 /* LID programmed for this instance */
596 u16 lid;
597 /* list of pkeys programmed; 0 if not set */
598 u16 pkeys[4];
599 /* LID mask control */
600 u8 lmc;
601 u8 link_width_supported;
602 u8 link_speed_supported;
603 u8 link_width_enabled;
604 u8 link_speed_enabled;
605 u8 link_width_active;
606 u8 link_speed_active;
607 u8 vls_supported;
608 u8 vls_operational;
609 /* Rx Polarity inversion (compensate for ~tx on partner) */
610 u8 rx_pol_inv;
611
612 u8 hw_pidx; /* physical port index */
613 u8 port; /* IB port number and index into dd->pports - 1 */
614
615 u8 delay_mult;
616
617 /* used to override LED behavior */
618 u8 led_override; /* Substituted for normal value, if non-zero */
619 u16 led_override_timeoff; /* delta to next timer event */
620 u8 led_override_vals[2]; /* Alternates per blink-frame */
621 u8 led_override_phase; /* Just counts, LSB picks from vals[] */
622 atomic_t led_override_timer_active;
623 /* Used to flash LEDs in override mode */
624 struct timer_list led_override_timer;
625 struct xmit_wait cong_stats;
626 struct timer_list symerr_clear_timer;
627 };
628
629 /* Observers. Not to be taken lightly, possibly not to ship. */
630 /*
631 * If a diag read or write is to (bottom <= offset <= top),
632 * the "hoook" is called, allowing, e.g. shadows to be
633 * updated in sync with the driver. struct diag_observer
634 * is the "visible" part.
635 */
636 struct diag_observer;
637
638 typedef int (*diag_hook) (struct qib_devdata *dd,
639 const struct diag_observer *op,
640 u32 offs, u64 *data, u64 mask, int only_32);
641
642 struct diag_observer {
643 diag_hook hook;
644 u32 bottom;
645 u32 top;
646 };
647
648 extern int qib_register_observer(struct qib_devdata *dd,
649 const struct diag_observer *op);
650
651 /* Only declared here, not defined. Private to diags */
652 struct diag_observer_list_elt;
653
654 /* device data struct now contains only "general per-device" info.
655 * fields related to a physical IB port are in a qib_pportdata struct,
656 * described above) while fields only used by a particular chip-type are in
657 * a qib_chipdata struct, whose contents are opaque to this file.
658 */
659 struct qib_devdata {
660 struct qib_ibdev verbs_dev; /* must be first */
661 struct list_head list;
662 /* pointers to related structs for this device */
663 /* pci access data structure */
664 struct pci_dev *pcidev;
665 struct cdev *user_cdev;
666 struct cdev *diag_cdev;
667 struct device *user_device;
668 struct device *diag_device;
669
670 /* mem-mapped pointer to base of chip regs */
671 u64 __iomem *kregbase;
672 /* end of mem-mapped chip space excluding sendbuf and user regs */
673 u64 __iomem *kregend;
674 /* physical address of chip for io_remap, etc. */
675 resource_size_t physaddr;
676 /* qib_cfgctxts pointers */
677 struct qib_ctxtdata **rcd; /* Receive Context Data */
678
679 /* qib_pportdata, points to array of (physical) port-specific
680 * data structs, indexed by pidx (0..n-1)
681 */
682 struct qib_pportdata *pport;
683 struct qib_chip_specific *cspec; /* chip-specific */
684
685 /* kvirt address of 1st 2k pio buffer */
686 void __iomem *pio2kbase;
687 /* kvirt address of 1st 4k pio buffer */
688 void __iomem *pio4kbase;
689 /* mem-mapped pointer to base of PIO buffers (if using WC PAT) */
690 void __iomem *piobase;
691 /* mem-mapped pointer to base of user chip regs (if using WC PAT) */
692 u64 __iomem *userbase;
693 void __iomem *piovl15base; /* base of VL15 buffers, if not WC */
694 /*
695 * points to area where PIOavail registers will be DMA'ed.
696 * Has to be on a page of it's own, because the page will be
697 * mapped into user program space. This copy is *ONLY* ever
698 * written by DMA, not by the driver! Need a copy per device
699 * when we get to multiple devices
700 */
701 volatile __le64 *pioavailregs_dma; /* DMA'ed by chip */
702 /* physical address where updates occur */
703 dma_addr_t pioavailregs_phys;
704
705 /* device-specific implementations of functions needed by
706 * common code. Contrary to previous consensus, we can't
707 * really just point to a device-specific table, because we
708 * may need to "bend", e.g. *_f_put_tid
709 */
710 /* fallback to alternate interrupt type if possible */
711 int (*f_intr_fallback)(struct qib_devdata *);
712 /* hard reset chip */
713 int (*f_reset)(struct qib_devdata *);
714 void (*f_quiet_serdes)(struct qib_pportdata *);
715 int (*f_bringup_serdes)(struct qib_pportdata *);
716 int (*f_early_init)(struct qib_devdata *);
717 void (*f_clear_tids)(struct qib_devdata *, struct qib_ctxtdata *);
718 void (*f_put_tid)(struct qib_devdata *, u64 __iomem*,
719 u32, unsigned long);
720 void (*f_cleanup)(struct qib_devdata *);
721 void (*f_setextled)(struct qib_pportdata *, u32);
722 /* fill out chip-specific fields */
723 int (*f_get_base_info)(struct qib_ctxtdata *, struct qib_base_info *);
724 /* free irq */
725 void (*f_free_irq)(struct qib_devdata *);
726 struct qib_message_header *(*f_get_msgheader)
727 (struct qib_devdata *, __le32 *);
728 void (*f_config_ctxts)(struct qib_devdata *);
729 int (*f_get_ib_cfg)(struct qib_pportdata *, int);
730 int (*f_set_ib_cfg)(struct qib_pportdata *, int, u32);
731 int (*f_set_ib_loopback)(struct qib_pportdata *, const char *);
732 int (*f_get_ib_table)(struct qib_pportdata *, int, void *);
733 int (*f_set_ib_table)(struct qib_pportdata *, int, void *);
734 u32 (*f_iblink_state)(u64);
735 u8 (*f_ibphys_portstate)(u64);
736 void (*f_xgxs_reset)(struct qib_pportdata *);
737 /* per chip actions needed for IB Link up/down changes */
738 int (*f_ib_updown)(struct qib_pportdata *, int, u64);
739 u32 __iomem *(*f_getsendbuf)(struct qib_pportdata *, u64, u32 *);
740 /* Read/modify/write of GPIO pins (potentially chip-specific */
741 int (*f_gpio_mod)(struct qib_devdata *dd, u32 out, u32 dir,
742 u32 mask);
743 /* Enable writes to config EEPROM (if supported) */
744 int (*f_eeprom_wen)(struct qib_devdata *dd, int wen);
745 /*
746 * modify rcvctrl shadow[s] and write to appropriate chip-regs.
747 * see above QIB_RCVCTRL_xxx_ENB/DIS for operations.
748 * (ctxt == -1) means "all contexts", only meaningful for
749 * clearing. Could remove if chip_spec shutdown properly done.
750 */
751 void (*f_rcvctrl)(struct qib_pportdata *, unsigned int op,
752 int ctxt);
753 /* Read/modify/write sendctrl appropriately for op and port. */
754 void (*f_sendctrl)(struct qib_pportdata *, u32 op);
755 void (*f_set_intr_state)(struct qib_devdata *, u32);
756 void (*f_set_armlaunch)(struct qib_devdata *, u32);
757 void (*f_wantpiobuf_intr)(struct qib_devdata *, u32);
758 int (*f_late_initreg)(struct qib_devdata *);
759 int (*f_init_sdma_regs)(struct qib_pportdata *);
760 u16 (*f_sdma_gethead)(struct qib_pportdata *);
761 int (*f_sdma_busy)(struct qib_pportdata *);
762 void (*f_sdma_update_tail)(struct qib_pportdata *, u16);
763 void (*f_sdma_set_desc_cnt)(struct qib_pportdata *, unsigned);
764 void (*f_sdma_sendctrl)(struct qib_pportdata *, unsigned);
765 void (*f_sdma_hw_clean_up)(struct qib_pportdata *);
766 void (*f_sdma_hw_start_up)(struct qib_pportdata *);
767 void (*f_sdma_init_early)(struct qib_pportdata *);
768 void (*f_set_cntr_sample)(struct qib_pportdata *, u32, u32);
769 void (*f_update_usrhead)(struct qib_ctxtdata *, u64, u32, u32, u32);
770 u32 (*f_hdrqempty)(struct qib_ctxtdata *);
771 u64 (*f_portcntr)(struct qib_pportdata *, u32);
772 u32 (*f_read_cntrs)(struct qib_devdata *, loff_t, char **,
773 u64 **);
774 u32 (*f_read_portcntrs)(struct qib_devdata *, loff_t, u32,
775 char **, u64 **);
776 u32 (*f_setpbc_control)(struct qib_pportdata *, u32, u8, u8);
777 void (*f_initvl15_bufs)(struct qib_devdata *);
778 void (*f_init_ctxt)(struct qib_ctxtdata *);
779 void (*f_txchk_change)(struct qib_devdata *, u32, u32, u32,
780 struct qib_ctxtdata *);
781 void (*f_writescratch)(struct qib_devdata *, u32);
782 int (*f_tempsense_rd)(struct qib_devdata *, int regnum);
783
784 char *boardname; /* human readable board info */
785
786 /* template for writing TIDs */
787 u64 tidtemplate;
788 /* value to write to free TIDs */
789 u64 tidinvalid;
790
791 /* number of registers used for pioavail */
792 u32 pioavregs;
793 /* device (not port) flags, basically device capabilities */
794 u32 flags;
795 /* last buffer for user use */
796 u32 lastctxt_piobuf;
797
798 /* saturating counter of (non-port-specific) device interrupts */
799 u32 int_counter;
800
801 /* pio bufs allocated per ctxt */
802 u32 pbufsctxt;
803 /* if remainder on bufs/ctxt, ctxts < extrabuf get 1 extra */
804 u32 ctxts_extrabuf;
805 /*
806 * number of ctxts configured as max; zero is set to number chip
807 * supports, less gives more pio bufs/ctxt, etc.
808 */
809 u32 cfgctxts;
810
811 /*
812 * hint that we should update pioavailshadow before
813 * looking for a PIO buffer
814 */
815 u32 upd_pio_shadow;
816
817 /* internal debugging stats */
818 u32 maxpkts_call;
819 u32 avgpkts_call;
820 u64 nopiobufs;
821
822 /* PCI Vendor ID (here for NodeInfo) */
823 u16 vendorid;
824 /* PCI Device ID (here for NodeInfo) */
825 u16 deviceid;
826 /* for write combining settings */
827 unsigned long wc_cookie;
828 unsigned long wc_base;
829 unsigned long wc_len;
830
831 /* shadow copy of struct page *'s for exp tid pages */
832 struct page **pageshadow;
833 /* shadow copy of dma handles for exp tid pages */
834 dma_addr_t *physshadow;
835 u64 __iomem *egrtidbase;
836 spinlock_t sendctrl_lock; /* protect changes to sendctrl shadow */
837 /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */
838 spinlock_t uctxt_lock; /* rcd and user context changes */
839 /*
840 * per unit status, see also portdata statusp
841 * mapped readonly into user processes so they can get unit and
842 * IB link status cheaply
843 */
844 u64 *devstatusp;
845 char *freezemsg; /* freeze msg if hw error put chip in freeze */
846 u32 freezelen; /* max length of freezemsg */
847 /* timer used to prevent stats overflow, error throttling, etc. */
848 struct timer_list stats_timer;
849
850 /* timer to verify interrupts work, and fallback if possible */
851 struct timer_list intrchk_timer;
852 unsigned long ureg_align; /* user register alignment */
853
854 /*
855 * Protects pioavailshadow, pioavailkernel, pio_need_disarm, and
856 * pio_writing.
857 */
858 spinlock_t pioavail_lock;
859
860 /*
861 * Shadow copies of registers; size indicates read access size.
862 * Most of them are readonly, but some are write-only register,
863 * where we manipulate the bits in the shadow copy, and then write
864 * the shadow copy to qlogic_ib.
865 *
866 * We deliberately make most of these 32 bits, since they have
867 * restricted range. For any that we read, we won't to generate 32
868 * bit accesses, since Opteron will generate 2 separate 32 bit HT
869 * transactions for a 64 bit read, and we want to avoid unnecessary
870 * bus transactions.
871 */
872
873 /* This is the 64 bit group */
874
875 unsigned long pioavailshadow[6];
876 /* bitmap of send buffers available for the kernel to use with PIO. */
877 unsigned long pioavailkernel[6];
878 /* bitmap of send buffers which need to be disarmed. */
879 unsigned long pio_need_disarm[3];
880 /* bitmap of send buffers which are being written to. */
881 unsigned long pio_writing[3];
882 /* kr_revision shadow */
883 u64 revision;
884 /* Base GUID for device (from eeprom, network order) */
885 __be64 base_guid;
886
887 /*
888 * kr_sendpiobufbase value (chip offset of pio buffers), and the
889 * base of the 2KB buffer s(user processes only use 2K)
890 */
891 u64 piobufbase;
892 u32 pio2k_bufbase;
893
894 /* these are the "32 bit" regs */
895
896 /* number of GUIDs in the flash for this interface */
897 u32 nguid;
898 /*
899 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
900 * all expect bit fields to be "unsigned long"
901 */
902 unsigned long rcvctrl; /* shadow per device rcvctrl */
903 unsigned long sendctrl; /* shadow per device sendctrl */
904
905 /* value we put in kr_rcvhdrcnt */
906 u32 rcvhdrcnt;
907 /* value we put in kr_rcvhdrsize */
908 u32 rcvhdrsize;
909 /* value we put in kr_rcvhdrentsize */
910 u32 rcvhdrentsize;
911 /* kr_ctxtcnt value */
912 u32 ctxtcnt;
913 /* kr_pagealign value */
914 u32 palign;
915 /* number of "2KB" PIO buffers */
916 u32 piobcnt2k;
917 /* size in bytes of "2KB" PIO buffers */
918 u32 piosize2k;
919 /* max usable size in dwords of a "2KB" PIO buffer before going "4KB" */
920 u32 piosize2kmax_dwords;
921 /* number of "4KB" PIO buffers */
922 u32 piobcnt4k;
923 /* size in bytes of "4KB" PIO buffers */
924 u32 piosize4k;
925 /* kr_rcvegrbase value */
926 u32 rcvegrbase;
927 /* kr_rcvtidbase value */
928 u32 rcvtidbase;
929 /* kr_rcvtidcnt value */
930 u32 rcvtidcnt;
931 /* kr_userregbase */
932 u32 uregbase;
933 /* shadow the control register contents */
934 u32 control;
935
936 /* chip address space used by 4k pio buffers */
937 u32 align4k;
938 /* size of each rcvegrbuffer */
939 u32 rcvegrbufsize;
940 /* localbus width (1, 2,4,8,16,32) from config space */
941 u32 lbus_width;
942 /* localbus speed in MHz */
943 u32 lbus_speed;
944 int unit; /* unit # of this chip */
945
946 /* start of CHIP_SPEC move to chipspec, but need code changes */
947 /* low and high portions of MSI capability/vector */
948 u32 msi_lo;
949 /* saved after PCIe init for restore after reset */
950 u32 msi_hi;
951 /* MSI data (vector) saved for restore */
952 u16 msi_data;
953 /* so we can rewrite it after a chip reset */
954 u32 pcibar0;
955 /* so we can rewrite it after a chip reset */
956 u32 pcibar1;
957 u64 rhdrhead_intr_off;
958
959 /*
960 * ASCII serial number, from flash, large enough for original
961 * all digit strings, and longer QLogic serial number format
962 */
963 u8 serial[16];
964 /* human readable board version */
965 u8 boardversion[96];
966 u8 lbus_info[32]; /* human readable localbus info */
967 /* chip major rev, from qib_revision */
968 u8 majrev;
969 /* chip minor rev, from qib_revision */
970 u8 minrev;
971
972 /* Misc small ints */
973 /* Number of physical ports available */
974 u8 num_pports;
975 /* Lowest context number which can be used by user processes */
976 u8 first_user_ctxt;
977 u8 n_krcv_queues;
978 u8 qpn_mask;
979 u8 skip_kctxt_mask;
980
981 u16 rhf_offset; /* offset of RHF within receive header entry */
982
983 /*
984 * GPIO pins for twsi-connected devices, and device code for eeprom
985 */
986 u8 gpio_sda_num;
987 u8 gpio_scl_num;
988 u8 twsi_eeprom_dev;
989 u8 board_atten;
990
991 /* Support (including locks) for EEPROM logging of errors and time */
992 /* control access to actual counters, timer */
993 spinlock_t eep_st_lock;
994 /* control high-level access to EEPROM */
995 struct mutex eep_lock;
996 uint64_t traffic_wds;
997 /* active time is kept in seconds, but logged in hours */
998 atomic_t active_time;
999 /* Below are nominal shadow of EEPROM, new since last EEPROM update */
1000 uint8_t eep_st_errs[QIB_EEP_LOG_CNT];
1001 uint8_t eep_st_new_errs[QIB_EEP_LOG_CNT];
1002 uint16_t eep_hrs;
1003 /*
1004 * masks for which bits of errs, hwerrs that cause
1005 * each of the counters to increment.
1006 */
1007 struct qib_eep_log_mask eep_st_masks[QIB_EEP_LOG_CNT];
1008 struct qib_diag_client *diag_client;
1009 spinlock_t qib_diag_trans_lock; /* protect diag observer ops */
1010 struct diag_observer_list_elt *diag_observer_list;
1011
1012 u8 psxmitwait_supported;
1013 /* cycle length of PS* counters in HW (in picoseconds) */
1014 u16 psxmitwait_check_rate;
1015 };
1016
1017 /* hol_state values */
1018 #define QIB_HOL_UP 0
1019 #define QIB_HOL_INIT 1
1020
1021 #define QIB_SDMA_SENDCTRL_OP_ENABLE (1U << 0)
1022 #define QIB_SDMA_SENDCTRL_OP_INTENABLE (1U << 1)
1023 #define QIB_SDMA_SENDCTRL_OP_HALT (1U << 2)
1024 #define QIB_SDMA_SENDCTRL_OP_CLEANUP (1U << 3)
1025 #define QIB_SDMA_SENDCTRL_OP_DRAIN (1U << 4)
1026
1027 /* operation types for f_txchk_change() */
1028 #define TXCHK_CHG_TYPE_DIS1 3
1029 #define TXCHK_CHG_TYPE_ENAB1 2
1030 #define TXCHK_CHG_TYPE_KERN 1
1031 #define TXCHK_CHG_TYPE_USER 0
1032
1033 #define QIB_CHASE_TIME msecs_to_jiffies(145)
1034 #define QIB_CHASE_DIS_TIME msecs_to_jiffies(160)
1035
1036 /* Private data for file operations */
1037 struct qib_filedata {
1038 struct qib_ctxtdata *rcd;
1039 unsigned subctxt;
1040 unsigned tidcursor;
1041 struct qib_user_sdma_queue *pq;
1042 int rec_cpu_num; /* for cpu affinity; -1 if none */
1043 };
1044
1045 extern struct list_head qib_dev_list;
1046 extern spinlock_t qib_devs_lock;
1047 extern struct qib_devdata *qib_lookup(int unit);
1048 extern u32 qib_cpulist_count;
1049 extern unsigned long *qib_cpulist;
1050
1051 extern unsigned qib_wc_pat;
1052 int qib_init(struct qib_devdata *, int);
1053 int init_chip_wc_pat(struct qib_devdata *dd, u32);
1054 int qib_enable_wc(struct qib_devdata *dd);
1055 void qib_disable_wc(struct qib_devdata *dd);
1056 int qib_count_units(int *npresentp, int *nupp);
1057 int qib_count_active_units(void);
1058
1059 int qib_cdev_init(int minor, const char *name,
1060 const struct file_operations *fops,
1061 struct cdev **cdevp, struct device **devp);
1062 void qib_cdev_cleanup(struct cdev **cdevp, struct device **devp);
1063 int qib_dev_init(void);
1064 void qib_dev_cleanup(void);
1065
1066 int qib_diag_add(struct qib_devdata *);
1067 void qib_diag_remove(struct qib_devdata *);
1068 void qib_handle_e_ibstatuschanged(struct qib_pportdata *, u64);
1069 void qib_sdma_update_tail(struct qib_pportdata *, u16); /* hold sdma_lock */
1070
1071 int qib_decode_err(struct qib_devdata *dd, char *buf, size_t blen, u64 err);
1072 void qib_bad_intrstatus(struct qib_devdata *);
1073 void qib_handle_urcv(struct qib_devdata *, u64);
1074
1075 /* clean up any per-chip chip-specific stuff */
1076 void qib_chip_cleanup(struct qib_devdata *);
1077 /* clean up any chip type-specific stuff */
1078 void qib_chip_done(void);
1079
1080 /* check to see if we have to force ordering for write combining */
1081 int qib_unordered_wc(void);
1082 void qib_pio_copy(void __iomem *to, const void *from, size_t count);
1083
1084 void qib_disarm_piobufs(struct qib_devdata *, unsigned, unsigned);
1085 int qib_disarm_piobufs_ifneeded(struct qib_ctxtdata *);
1086 void qib_disarm_piobufs_set(struct qib_devdata *, unsigned long *, unsigned);
1087 void qib_cancel_sends(struct qib_pportdata *);
1088
1089 int qib_create_rcvhdrq(struct qib_devdata *, struct qib_ctxtdata *);
1090 int qib_setup_eagerbufs(struct qib_ctxtdata *);
1091 void qib_set_ctxtcnt(struct qib_devdata *);
1092 int qib_create_ctxts(struct qib_devdata *dd);
1093 struct qib_ctxtdata *qib_create_ctxtdata(struct qib_pportdata *, u32);
1094 void qib_init_pportdata(struct qib_pportdata *, struct qib_devdata *, u8, u8);
1095 void qib_free_ctxtdata(struct qib_devdata *, struct qib_ctxtdata *);
1096
1097 u32 qib_kreceive(struct qib_ctxtdata *, u32 *, u32 *);
1098 int qib_reset_device(int);
1099 int qib_wait_linkstate(struct qib_pportdata *, u32, int);
1100 int qib_set_linkstate(struct qib_pportdata *, u8);
1101 int qib_set_mtu(struct qib_pportdata *, u16);
1102 int qib_set_lid(struct qib_pportdata *, u32, u8);
1103 void qib_hol_down(struct qib_pportdata *);
1104 void qib_hol_init(struct qib_pportdata *);
1105 void qib_hol_up(struct qib_pportdata *);
1106 void qib_hol_event(unsigned long);
1107 void qib_disable_after_error(struct qib_devdata *);
1108 int qib_set_uevent_bits(struct qib_pportdata *, const int);
1109
1110 /* for use in system calls, where we want to know device type, etc. */
1111 #define ctxt_fp(fp) \
1112 (((struct qib_filedata *)(fp)->private_data)->rcd)
1113 #define subctxt_fp(fp) \
1114 (((struct qib_filedata *)(fp)->private_data)->subctxt)
1115 #define tidcursor_fp(fp) \
1116 (((struct qib_filedata *)(fp)->private_data)->tidcursor)
1117 #define user_sdma_queue_fp(fp) \
1118 (((struct qib_filedata *)(fp)->private_data)->pq)
1119
dd_from_ppd(struct qib_pportdata * ppd)1120 static inline struct qib_devdata *dd_from_ppd(struct qib_pportdata *ppd)
1121 {
1122 return ppd->dd;
1123 }
1124
dd_from_dev(struct qib_ibdev * dev)1125 static inline struct qib_devdata *dd_from_dev(struct qib_ibdev *dev)
1126 {
1127 return container_of(dev, struct qib_devdata, verbs_dev);
1128 }
1129
dd_from_ibdev(struct ib_device * ibdev)1130 static inline struct qib_devdata *dd_from_ibdev(struct ib_device *ibdev)
1131 {
1132 return dd_from_dev(to_idev(ibdev));
1133 }
1134
ppd_from_ibp(struct qib_ibport * ibp)1135 static inline struct qib_pportdata *ppd_from_ibp(struct qib_ibport *ibp)
1136 {
1137 return container_of(ibp, struct qib_pportdata, ibport_data);
1138 }
1139
to_iport(struct ib_device * ibdev,u8 port)1140 static inline struct qib_ibport *to_iport(struct ib_device *ibdev, u8 port)
1141 {
1142 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1143 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */
1144
1145 WARN_ON(pidx >= dd->num_pports);
1146 return &dd->pport[pidx].ibport_data;
1147 }
1148
1149 /*
1150 * values for dd->flags (_device_ related flags) and
1151 */
1152 #define QIB_HAS_LINK_LATENCY 0x1 /* supports link latency (IB 1.2) */
1153 #define QIB_INITTED 0x2 /* chip and driver up and initted */
1154 #define QIB_DOING_RESET 0x4 /* in the middle of doing chip reset */
1155 #define QIB_PRESENT 0x8 /* chip accesses can be done */
1156 #define QIB_PIO_FLUSH_WC 0x10 /* Needs Write combining flush for PIO */
1157 #define QIB_HAS_THRESH_UPDATE 0x40
1158 #define QIB_HAS_SDMA_TIMEOUT 0x80
1159 #define QIB_USE_SPCL_TRIG 0x100 /* SpecialTrigger launch enabled */
1160 #define QIB_NODMA_RTAIL 0x200 /* rcvhdrtail register DMA enabled */
1161 #define QIB_HAS_INTX 0x800 /* Supports INTx interrupts */
1162 #define QIB_HAS_SEND_DMA 0x1000 /* Supports Send DMA */
1163 #define QIB_HAS_VLSUPP 0x2000 /* Supports multiple VLs; PBC different */
1164 #define QIB_HAS_HDRSUPP 0x4000 /* Supports header suppression */
1165 #define QIB_BADINTR 0x8000 /* severe interrupt problems */
1166 #define QIB_DCA_ENABLED 0x10000 /* Direct Cache Access enabled */
1167 #define QIB_HAS_QSFP 0x20000 /* device (card instance) has QSFP */
1168
1169 /*
1170 * values for ppd->lflags (_ib_port_ related flags)
1171 */
1172 #define QIBL_LINKV 0x1 /* IB link state valid */
1173 #define QIBL_LINKDOWN 0x8 /* IB link is down */
1174 #define QIBL_LINKINIT 0x10 /* IB link level is up */
1175 #define QIBL_LINKARMED 0x20 /* IB link is ARMED */
1176 #define QIBL_LINKACTIVE 0x40 /* IB link is ACTIVE */
1177 /* leave a gap for more IB-link state */
1178 #define QIBL_IB_AUTONEG_INPROG 0x1000 /* non-IBTA DDR/QDR neg active */
1179 #define QIBL_IB_AUTONEG_FAILED 0x2000 /* non-IBTA DDR/QDR neg failed */
1180 #define QIBL_IB_LINK_DISABLED 0x4000 /* Linkdown-disable forced,
1181 * Do not try to bring up */
1182 #define QIBL_IB_FORCE_NOTIFY 0x8000 /* force notify on next ib change */
1183
1184 /* IB dword length mask in PBC (lower 11 bits); same for all chips */
1185 #define QIB_PBC_LENGTH_MASK ((1 << 11) - 1)
1186
1187
1188 /* ctxt_flag bit offsets */
1189 /* waiting for a packet to arrive */
1190 #define QIB_CTXT_WAITING_RCV 2
1191 /* master has not finished initializing */
1192 #define QIB_CTXT_MASTER_UNINIT 4
1193 /* waiting for an urgent packet to arrive */
1194 #define QIB_CTXT_WAITING_URG 5
1195
1196 /* free up any allocated data at closes */
1197 void qib_free_data(struct qib_ctxtdata *dd);
1198 void qib_chg_pioavailkernel(struct qib_devdata *, unsigned, unsigned,
1199 u32, struct qib_ctxtdata *);
1200 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *,
1201 const struct pci_device_id *);
1202 struct qib_devdata *qib_init_iba7220_funcs(struct pci_dev *,
1203 const struct pci_device_id *);
1204 struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *,
1205 const struct pci_device_id *);
1206 void qib_free_devdata(struct qib_devdata *);
1207 struct qib_devdata *qib_alloc_devdata(struct pci_dev *pdev, size_t extra);
1208
1209 #define QIB_TWSI_NO_DEV 0xFF
1210 /* Below qib_twsi_ functions must be called with eep_lock held */
1211 int qib_twsi_reset(struct qib_devdata *dd);
1212 int qib_twsi_blk_rd(struct qib_devdata *dd, int dev, int addr, void *buffer,
1213 int len);
1214 int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr,
1215 const void *buffer, int len);
1216 void qib_get_eeprom_info(struct qib_devdata *);
1217 int qib_update_eeprom_log(struct qib_devdata *dd);
1218 void qib_inc_eeprom_err(struct qib_devdata *dd, u32 eidx, u32 incr);
1219 void qib_dump_lookup_output_queue(struct qib_devdata *);
1220 void qib_force_pio_avail_update(struct qib_devdata *);
1221 void qib_clear_symerror_on_linkup(unsigned long opaque);
1222
1223 /*
1224 * Set LED override, only the two LSBs have "public" meaning, but
1225 * any non-zero value substitutes them for the Link and LinkTrain
1226 * LED states.
1227 */
1228 #define QIB_LED_PHYS 1 /* Physical (linktraining) GREEN LED */
1229 #define QIB_LED_LOG 2 /* Logical (link) YELLOW LED */
1230 void qib_set_led_override(struct qib_pportdata *ppd, unsigned int val);
1231
1232 /* send dma routines */
1233 int qib_setup_sdma(struct qib_pportdata *);
1234 void qib_teardown_sdma(struct qib_pportdata *);
1235 void __qib_sdma_intr(struct qib_pportdata *);
1236 void qib_sdma_intr(struct qib_pportdata *);
1237 int qib_sdma_verbs_send(struct qib_pportdata *, struct qib_sge_state *,
1238 u32, struct qib_verbs_txreq *);
1239 /* ppd->sdma_lock should be locked before calling this. */
1240 int qib_sdma_make_progress(struct qib_pportdata *dd);
1241
1242 /* must be called under qib_sdma_lock */
qib_sdma_descq_freecnt(const struct qib_pportdata * ppd)1243 static inline u16 qib_sdma_descq_freecnt(const struct qib_pportdata *ppd)
1244 {
1245 return ppd->sdma_descq_cnt -
1246 (ppd->sdma_descq_added - ppd->sdma_descq_removed) - 1;
1247 }
1248
__qib_sdma_running(struct qib_pportdata * ppd)1249 static inline int __qib_sdma_running(struct qib_pportdata *ppd)
1250 {
1251 return ppd->sdma_state.current_state == qib_sdma_state_s99_running;
1252 }
1253 int qib_sdma_running(struct qib_pportdata *);
1254
1255 void __qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events);
1256 void qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events);
1257
1258 /*
1259 * number of words used for protocol header if not set by qib_userinit();
1260 */
1261 #define QIB_DFLT_RCVHDRSIZE 9
1262
1263 /*
1264 * We need to be able to handle an IB header of at least 24 dwords.
1265 * We need the rcvhdrq large enough to handle largest IB header, but
1266 * still have room for a 2KB MTU standard IB packet.
1267 * Additionally, some processor/memory controller combinations
1268 * benefit quite strongly from having the DMA'ed data be cacheline
1269 * aligned and a cacheline multiple, so we set the size to 32 dwords
1270 * (2 64-byte primary cachelines for pretty much all processors of
1271 * interest). The alignment hurts nothing, other than using somewhat
1272 * more memory.
1273 */
1274 #define QIB_RCVHDR_ENTSIZE 32
1275
1276 int qib_get_user_pages(unsigned long, size_t, struct page **);
1277 void qib_release_user_pages(struct page **, size_t);
1278 int qib_eeprom_read(struct qib_devdata *, u8, void *, int);
1279 int qib_eeprom_write(struct qib_devdata *, u8, const void *, int);
1280 u32 __iomem *qib_getsendbuf_range(struct qib_devdata *, u32 *, u32, u32);
1281 void qib_sendbuf_done(struct qib_devdata *, unsigned);
1282
qib_clear_rcvhdrtail(const struct qib_ctxtdata * rcd)1283 static inline void qib_clear_rcvhdrtail(const struct qib_ctxtdata *rcd)
1284 {
1285 *((u64 *) rcd->rcvhdrtail_kvaddr) = 0ULL;
1286 }
1287
qib_get_rcvhdrtail(const struct qib_ctxtdata * rcd)1288 static inline u32 qib_get_rcvhdrtail(const struct qib_ctxtdata *rcd)
1289 {
1290 /*
1291 * volatile because it's a DMA target from the chip, routine is
1292 * inlined, and don't want register caching or reordering.
1293 */
1294 return (u32) le64_to_cpu(
1295 *((volatile __le64 *)rcd->rcvhdrtail_kvaddr)); /* DMA'ed */
1296 }
1297
qib_get_hdrqtail(const struct qib_ctxtdata * rcd)1298 static inline u32 qib_get_hdrqtail(const struct qib_ctxtdata *rcd)
1299 {
1300 const struct qib_devdata *dd = rcd->dd;
1301 u32 hdrqtail;
1302
1303 if (dd->flags & QIB_NODMA_RTAIL) {
1304 __le32 *rhf_addr;
1305 u32 seq;
1306
1307 rhf_addr = (__le32 *) rcd->rcvhdrq +
1308 rcd->head + dd->rhf_offset;
1309 seq = qib_hdrget_seq(rhf_addr);
1310 hdrqtail = rcd->head;
1311 if (seq == rcd->seq_cnt)
1312 hdrqtail++;
1313 } else
1314 hdrqtail = qib_get_rcvhdrtail(rcd);
1315
1316 return hdrqtail;
1317 }
1318
1319 /*
1320 * sysfs interface.
1321 */
1322
1323 extern const char ib_qib_version[];
1324
1325 int qib_device_create(struct qib_devdata *);
1326 void qib_device_remove(struct qib_devdata *);
1327
1328 int qib_create_port_files(struct ib_device *ibdev, u8 port_num,
1329 struct kobject *kobj);
1330 int qib_verbs_register_sysfs(struct qib_devdata *);
1331 void qib_verbs_unregister_sysfs(struct qib_devdata *);
1332 /* Hook for sysfs read of QSFP */
1333 extern int qib_qsfp_dump(struct qib_pportdata *ppd, char *buf, int len);
1334
1335 int __init qib_init_qibfs(void);
1336 int __exit qib_exit_qibfs(void);
1337
1338 int qibfs_add(struct qib_devdata *);
1339 int qibfs_remove(struct qib_devdata *);
1340
1341 int qib_pcie_init(struct pci_dev *, const struct pci_device_id *);
1342 int qib_pcie_ddinit(struct qib_devdata *, struct pci_dev *,
1343 const struct pci_device_id *);
1344 void qib_pcie_ddcleanup(struct qib_devdata *);
1345 int qib_pcie_params(struct qib_devdata *, u32, u32 *, struct msix_entry *);
1346 int qib_reinit_intr(struct qib_devdata *);
1347 void qib_enable_intx(struct pci_dev *);
1348 void qib_nomsi(struct qib_devdata *);
1349 void qib_nomsix(struct qib_devdata *);
1350 void qib_pcie_getcmd(struct qib_devdata *, u16 *, u8 *, u8 *);
1351 void qib_pcie_reenable(struct qib_devdata *, u16, u8, u8);
1352
1353 /*
1354 * dma_addr wrappers - all 0's invalid for hw
1355 */
1356 dma_addr_t qib_map_page(struct pci_dev *, struct page *, unsigned long,
1357 size_t, int);
1358 const char *qib_get_unit_name(int unit);
1359
1360 /*
1361 * Flush write combining store buffers (if present) and perform a write
1362 * barrier.
1363 */
1364 #if defined(CONFIG_X86_64)
1365 #define qib_flush_wc() asm volatile("sfence" : : : "memory")
1366 #else
1367 #define qib_flush_wc() wmb() /* no reorder around wc flush */
1368 #endif
1369
1370 /* global module parameter variables */
1371 extern unsigned qib_ibmtu;
1372 extern ushort qib_cfgctxts;
1373 extern ushort qib_num_cfg_vls;
1374 extern ushort qib_mini_init; /* If set, do few (ideally 0) writes to chip */
1375 extern unsigned qib_n_krcv_queues;
1376 extern unsigned qib_sdma_fetch_arb;
1377 extern unsigned qib_compat_ddr_negotiate;
1378 extern int qib_special_trigger;
1379
1380 extern struct mutex qib_mutex;
1381
1382 /* Number of seconds before our card status check... */
1383 #define STATUS_TIMEOUT 60
1384
1385 #define QIB_DRV_NAME "ib_qib"
1386 #define QIB_USER_MINOR_BASE 0
1387 #define QIB_TRACE_MINOR 127
1388 #define QIB_DIAGPKT_MINOR 128
1389 #define QIB_DIAG_MINOR_BASE 129
1390 #define QIB_NMINORS 255
1391
1392 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1
1393 #define PCI_VENDOR_ID_QLOGIC 0x1077
1394 #define PCI_DEVICE_ID_QLOGIC_IB_6120 0x10
1395 #define PCI_DEVICE_ID_QLOGIC_IB_7220 0x7220
1396 #define PCI_DEVICE_ID_QLOGIC_IB_7322 0x7322
1397
1398 /*
1399 * qib_early_err is used (only!) to print early errors before devdata is
1400 * allocated, or when dd->pcidev may not be valid, and at the tail end of
1401 * cleanup when devdata may have been freed, etc. qib_dev_porterr is
1402 * the same as qib_dev_err, but is used when the message really needs
1403 * the IB port# to be definitive as to what's happening..
1404 * All of these go to the trace log, and the trace log entry is done
1405 * first to avoid possible serial port delays from printk.
1406 */
1407 #define qib_early_err(dev, fmt, ...) \
1408 do { \
1409 dev_err(dev, fmt, ##__VA_ARGS__); \
1410 } while (0)
1411
1412 #define qib_dev_err(dd, fmt, ...) \
1413 do { \
1414 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
1415 qib_get_unit_name((dd)->unit), ##__VA_ARGS__); \
1416 } while (0)
1417
1418 #define qib_dev_porterr(dd, port, fmt, ...) \
1419 do { \
1420 dev_err(&(dd)->pcidev->dev, "%s: IB%u:%u " fmt, \
1421 qib_get_unit_name((dd)->unit), (dd)->unit, (port), \
1422 ##__VA_ARGS__); \
1423 } while (0)
1424
1425 #define qib_devinfo(pcidev, fmt, ...) \
1426 do { \
1427 dev_info(&(pcidev)->dev, fmt, ##__VA_ARGS__); \
1428 } while (0)
1429
1430 /*
1431 * this is used for formatting hw error messages...
1432 */
1433 struct qib_hwerror_msgs {
1434 u64 mask;
1435 const char *msg;
1436 };
1437
1438 #define QLOGIC_IB_HWE_MSG(a, b) { .mask = a, .msg = b }
1439
1440 /* in qib_intr.c... */
1441 void qib_format_hwerrors(u64 hwerrs,
1442 const struct qib_hwerror_msgs *hwerrmsgs,
1443 size_t nhwerrmsgs, char *msg, size_t lmsg);
1444 #endif /* _QIB_KERNEL_H */
1445