1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Kernel-based Virtual Machine driver for Linux
4 * cpuid support routines
5 *
6 * derived from arch/x86/kvm/x86.c
7 *
8 * Copyright 2011 Red Hat, Inc. and/or its affiliates.
9 * Copyright IBM Corporation, 2008
10 */
11
12 #include <linux/kvm_host.h>
13 #include <linux/export.h>
14 #include <linux/vmalloc.h>
15 #include <linux/uaccess.h>
16 #include <linux/sched/stat.h>
17
18 #include <asm/processor.h>
19 #include <asm/user.h>
20 #include <asm/fpu/xstate.h>
21 #include <asm/sgx.h>
22 #include <asm/cpuid.h>
23 #include "cpuid.h"
24 #include "lapic.h"
25 #include "mmu.h"
26 #include "trace.h"
27 #include "pmu.h"
28
29 /*
30 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be
31 * aligned to sizeof(unsigned long) because it's not accessed via bitops.
32 */
33 u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly;
34 EXPORT_SYMBOL_GPL(kvm_cpu_caps);
35
xstate_required_size(u64 xstate_bv,bool compacted)36 u32 xstate_required_size(u64 xstate_bv, bool compacted)
37 {
38 int feature_bit = 0;
39 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
40
41 xstate_bv &= XFEATURE_MASK_EXTEND;
42 while (xstate_bv) {
43 if (xstate_bv & 0x1) {
44 u32 eax, ebx, ecx, edx, offset;
45 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx);
46 /* ECX[1]: 64B alignment in compacted form */
47 if (compacted)
48 offset = (ecx & 0x2) ? ALIGN(ret, 64) : ret;
49 else
50 offset = ebx;
51 ret = max(ret, offset + eax);
52 }
53
54 xstate_bv >>= 1;
55 feature_bit++;
56 }
57
58 return ret;
59 }
60
61 /*
62 * This one is tied to SSB in the user API, and not
63 * visible in /proc/cpuinfo.
64 */
65 #define KVM_X86_FEATURE_PSFD (13*32+28) /* Predictive Store Forwarding Disable */
66
67 #define F feature_bit
68 #define SF(name) (boot_cpu_has(X86_FEATURE_##name) ? F(name) : 0)
69
70 /*
71 * Magic value used by KVM when querying userspace-provided CPUID entries and
72 * doesn't care about the CPIUD index because the index of the function in
73 * question is not significant. Note, this magic value must have at least one
74 * bit set in bits[63:32] and must be consumed as a u64 by cpuid_entry2_find()
75 * to avoid false positives when processing guest CPUID input.
76 */
77 #define KVM_CPUID_INDEX_NOT_SIGNIFICANT -1ull
78
cpuid_entry2_find(struct kvm_cpuid_entry2 * entries,int nent,u32 function,u64 index)79 static inline struct kvm_cpuid_entry2 *cpuid_entry2_find(
80 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u64 index)
81 {
82 struct kvm_cpuid_entry2 *e;
83 int i;
84
85 for (i = 0; i < nent; i++) {
86 e = &entries[i];
87
88 if (e->function != function)
89 continue;
90
91 /*
92 * If the index isn't significant, use the first entry with a
93 * matching function. It's userspace's responsibilty to not
94 * provide "duplicate" entries in all cases.
95 */
96 if (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index)
97 return e;
98
99
100 /*
101 * Similarly, use the first matching entry if KVM is doing a
102 * lookup (as opposed to emulating CPUID) for a function that's
103 * architecturally defined as not having a significant index.
104 */
105 if (index == KVM_CPUID_INDEX_NOT_SIGNIFICANT) {
106 /*
107 * Direct lookups from KVM should not diverge from what
108 * KVM defines internally (the architectural behavior).
109 */
110 WARN_ON_ONCE(cpuid_function_is_indexed(function));
111 return e;
112 }
113 }
114
115 return NULL;
116 }
117
kvm_check_cpuid(struct kvm_vcpu * vcpu,struct kvm_cpuid_entry2 * entries,int nent)118 static int kvm_check_cpuid(struct kvm_vcpu *vcpu,
119 struct kvm_cpuid_entry2 *entries,
120 int nent)
121 {
122 struct kvm_cpuid_entry2 *best;
123 u64 xfeatures;
124
125 /*
126 * The existing code assumes virtual address is 48-bit or 57-bit in the
127 * canonical address checks; exit if it is ever changed.
128 */
129 best = cpuid_entry2_find(entries, nent, 0x80000008,
130 KVM_CPUID_INDEX_NOT_SIGNIFICANT);
131 if (best) {
132 int vaddr_bits = (best->eax & 0xff00) >> 8;
133
134 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0)
135 return -EINVAL;
136 }
137
138 /*
139 * Exposing dynamic xfeatures to the guest requires additional
140 * enabling in the FPU, e.g. to expand the guest XSAVE state size.
141 */
142 best = cpuid_entry2_find(entries, nent, 0xd, 0);
143 if (!best)
144 return 0;
145
146 xfeatures = best->eax | ((u64)best->edx << 32);
147 xfeatures &= XFEATURE_MASK_USER_DYNAMIC;
148 if (!xfeatures)
149 return 0;
150
151 return fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, xfeatures);
152 }
153
154 /* Check whether the supplied CPUID data is equal to what is already set for the vCPU. */
kvm_cpuid_check_equal(struct kvm_vcpu * vcpu,struct kvm_cpuid_entry2 * e2,int nent)155 static int kvm_cpuid_check_equal(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2,
156 int nent)
157 {
158 struct kvm_cpuid_entry2 *orig;
159 int i;
160
161 if (nent != vcpu->arch.cpuid_nent)
162 return -EINVAL;
163
164 for (i = 0; i < nent; i++) {
165 orig = &vcpu->arch.cpuid_entries[i];
166 if (e2[i].function != orig->function ||
167 e2[i].index != orig->index ||
168 e2[i].flags != orig->flags ||
169 e2[i].eax != orig->eax || e2[i].ebx != orig->ebx ||
170 e2[i].ecx != orig->ecx || e2[i].edx != orig->edx)
171 return -EINVAL;
172 }
173
174 return 0;
175 }
176
kvm_update_kvm_cpuid_base(struct kvm_vcpu * vcpu)177 static void kvm_update_kvm_cpuid_base(struct kvm_vcpu *vcpu)
178 {
179 u32 function;
180 struct kvm_cpuid_entry2 *entry;
181
182 vcpu->arch.kvm_cpuid_base = 0;
183
184 for_each_possible_hypervisor_cpuid_base(function) {
185 entry = kvm_find_cpuid_entry(vcpu, function);
186
187 if (entry) {
188 u32 signature[3];
189
190 signature[0] = entry->ebx;
191 signature[1] = entry->ecx;
192 signature[2] = entry->edx;
193
194 BUILD_BUG_ON(sizeof(signature) > sizeof(KVM_SIGNATURE));
195 if (!memcmp(signature, KVM_SIGNATURE, sizeof(signature))) {
196 vcpu->arch.kvm_cpuid_base = function;
197 break;
198 }
199 }
200 }
201 }
202
__kvm_find_kvm_cpuid_features(struct kvm_vcpu * vcpu,struct kvm_cpuid_entry2 * entries,int nent)203 static struct kvm_cpuid_entry2 *__kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu,
204 struct kvm_cpuid_entry2 *entries, int nent)
205 {
206 u32 base = vcpu->arch.kvm_cpuid_base;
207
208 if (!base)
209 return NULL;
210
211 return cpuid_entry2_find(entries, nent, base | KVM_CPUID_FEATURES,
212 KVM_CPUID_INDEX_NOT_SIGNIFICANT);
213 }
214
kvm_find_kvm_cpuid_features(struct kvm_vcpu * vcpu)215 static struct kvm_cpuid_entry2 *kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu)
216 {
217 return __kvm_find_kvm_cpuid_features(vcpu, vcpu->arch.cpuid_entries,
218 vcpu->arch.cpuid_nent);
219 }
220
kvm_update_pv_runtime(struct kvm_vcpu * vcpu)221 void kvm_update_pv_runtime(struct kvm_vcpu *vcpu)
222 {
223 struct kvm_cpuid_entry2 *best = kvm_find_kvm_cpuid_features(vcpu);
224
225 /*
226 * save the feature bitmap to avoid cpuid lookup for every PV
227 * operation
228 */
229 if (best)
230 vcpu->arch.pv_cpuid.features = best->eax;
231 }
232
233 /*
234 * Calculate guest's supported XCR0 taking into account guest CPUID data and
235 * KVM's supported XCR0 (comprised of host's XCR0 and KVM_SUPPORTED_XCR0).
236 */
cpuid_get_supported_xcr0(struct kvm_cpuid_entry2 * entries,int nent)237 static u64 cpuid_get_supported_xcr0(struct kvm_cpuid_entry2 *entries, int nent)
238 {
239 struct kvm_cpuid_entry2 *best;
240
241 best = cpuid_entry2_find(entries, nent, 0xd, 0);
242 if (!best)
243 return 0;
244
245 return (best->eax | ((u64)best->edx << 32)) & kvm_caps.supported_xcr0;
246 }
247
__kvm_update_cpuid_runtime(struct kvm_vcpu * vcpu,struct kvm_cpuid_entry2 * entries,int nent)248 static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *entries,
249 int nent)
250 {
251 struct kvm_cpuid_entry2 *best;
252 u64 guest_supported_xcr0 = cpuid_get_supported_xcr0(entries, nent);
253
254 best = cpuid_entry2_find(entries, nent, 1, KVM_CPUID_INDEX_NOT_SIGNIFICANT);
255 if (best) {
256 /* Update OSXSAVE bit */
257 if (boot_cpu_has(X86_FEATURE_XSAVE))
258 cpuid_entry_change(best, X86_FEATURE_OSXSAVE,
259 kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE));
260
261 cpuid_entry_change(best, X86_FEATURE_APIC,
262 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE);
263 }
264
265 best = cpuid_entry2_find(entries, nent, 7, 0);
266 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7)
267 cpuid_entry_change(best, X86_FEATURE_OSPKE,
268 kvm_read_cr4_bits(vcpu, X86_CR4_PKE));
269
270 best = cpuid_entry2_find(entries, nent, 0xD, 0);
271 if (best)
272 best->ebx = xstate_required_size(vcpu->arch.xcr0, false);
273
274 best = cpuid_entry2_find(entries, nent, 0xD, 1);
275 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) ||
276 cpuid_entry_has(best, X86_FEATURE_XSAVEC)))
277 best->ebx = xstate_required_size(vcpu->arch.xcr0, true);
278
279 best = __kvm_find_kvm_cpuid_features(vcpu, entries, nent);
280 if (kvm_hlt_in_guest(vcpu->kvm) && best &&
281 (best->eax & (1 << KVM_FEATURE_PV_UNHALT)))
282 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT);
283
284 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) {
285 best = cpuid_entry2_find(entries, nent, 0x1, KVM_CPUID_INDEX_NOT_SIGNIFICANT);
286 if (best)
287 cpuid_entry_change(best, X86_FEATURE_MWAIT,
288 vcpu->arch.ia32_misc_enable_msr &
289 MSR_IA32_MISC_ENABLE_MWAIT);
290 }
291
292 /*
293 * Bits 127:0 of the allowed SECS.ATTRIBUTES (CPUID.0x12.0x1) enumerate
294 * the supported XSAVE Feature Request Mask (XFRM), i.e. the enclave's
295 * requested XCR0 value. The enclave's XFRM must be a subset of XCRO
296 * at the time of EENTER, thus adjust the allowed XFRM by the guest's
297 * supported XCR0. Similar to XCR0 handling, FP and SSE are forced to
298 * '1' even on CPUs that don't support XSAVE.
299 */
300 best = cpuid_entry2_find(entries, nent, 0x12, 0x1);
301 if (best) {
302 best->ecx &= guest_supported_xcr0 & 0xffffffff;
303 best->edx &= guest_supported_xcr0 >> 32;
304 best->ecx |= XFEATURE_MASK_FPSSE;
305 }
306 }
307
kvm_update_cpuid_runtime(struct kvm_vcpu * vcpu)308 void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu)
309 {
310 __kvm_update_cpuid_runtime(vcpu, vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent);
311 }
312 EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime);
313
kvm_cpuid_has_hyperv(struct kvm_cpuid_entry2 * entries,int nent)314 static bool kvm_cpuid_has_hyperv(struct kvm_cpuid_entry2 *entries, int nent)
315 {
316 struct kvm_cpuid_entry2 *entry;
317
318 entry = cpuid_entry2_find(entries, nent, HYPERV_CPUID_INTERFACE,
319 KVM_CPUID_INDEX_NOT_SIGNIFICANT);
320 return entry && entry->eax == HYPERV_CPUID_SIGNATURE_EAX;
321 }
322
kvm_vcpu_after_set_cpuid(struct kvm_vcpu * vcpu)323 static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
324 {
325 struct kvm_lapic *apic = vcpu->arch.apic;
326 struct kvm_cpuid_entry2 *best;
327
328 best = kvm_find_cpuid_entry(vcpu, 1);
329 if (best && apic) {
330 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER))
331 apic->lapic_timer.timer_mode_mask = 3 << 17;
332 else
333 apic->lapic_timer.timer_mode_mask = 1 << 17;
334
335 kvm_apic_set_version(vcpu);
336 }
337
338 vcpu->arch.guest_supported_xcr0 =
339 cpuid_get_supported_xcr0(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent);
340
341 /*
342 * FP+SSE can always be saved/restored via KVM_{G,S}ET_XSAVE, even if
343 * XSAVE/XCRO are not exposed to the guest, and even if XSAVE isn't
344 * supported by the host.
345 */
346 vcpu->arch.guest_fpu.fpstate->user_xfeatures = vcpu->arch.guest_supported_xcr0 |
347 XFEATURE_MASK_FPSSE;
348
349 kvm_update_pv_runtime(vcpu);
350
351 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
352 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
353
354 kvm_pmu_refresh(vcpu);
355 vcpu->arch.cr4_guest_rsvd_bits =
356 __cr4_reserved_bits(guest_cpuid_has, vcpu);
357
358 kvm_hv_set_cpuid(vcpu, kvm_cpuid_has_hyperv(vcpu->arch.cpuid_entries,
359 vcpu->arch.cpuid_nent));
360
361 /* Invoke the vendor callback only after the above state is updated. */
362 static_call(kvm_x86_vcpu_after_set_cpuid)(vcpu);
363
364 /*
365 * Except for the MMU, which needs to do its thing any vendor specific
366 * adjustments to the reserved GPA bits.
367 */
368 kvm_mmu_after_set_cpuid(vcpu);
369 }
370
cpuid_query_maxphyaddr(struct kvm_vcpu * vcpu)371 int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu)
372 {
373 struct kvm_cpuid_entry2 *best;
374
375 best = kvm_find_cpuid_entry(vcpu, 0x80000000);
376 if (!best || best->eax < 0x80000008)
377 goto not_found;
378 best = kvm_find_cpuid_entry(vcpu, 0x80000008);
379 if (best)
380 return best->eax & 0xff;
381 not_found:
382 return 36;
383 }
384
385 /*
386 * This "raw" version returns the reserved GPA bits without any adjustments for
387 * encryption technologies that usurp bits. The raw mask should be used if and
388 * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs.
389 */
kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu * vcpu)390 u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu)
391 {
392 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63);
393 }
394
kvm_set_cpuid(struct kvm_vcpu * vcpu,struct kvm_cpuid_entry2 * e2,int nent)395 static int kvm_set_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2,
396 int nent)
397 {
398 int r;
399
400 __kvm_update_cpuid_runtime(vcpu, e2, nent);
401
402 /*
403 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as
404 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't
405 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page
406 * faults due to reusing SPs/SPTEs. In practice no sane VMM mucks with
407 * the core vCPU model on the fly. It would've been better to forbid any
408 * KVM_SET_CPUID{,2} calls after KVM_RUN altogether but unfortunately
409 * some VMMs (e.g. QEMU) reuse vCPU fds for CPU hotplug/unplug and do
410 * KVM_SET_CPUID{,2} again. To support this legacy behavior, check
411 * whether the supplied CPUID data is equal to what's already set.
412 */
413 if (vcpu->arch.last_vmentry_cpu != -1) {
414 r = kvm_cpuid_check_equal(vcpu, e2, nent);
415 if (r)
416 return r;
417
418 kvfree(e2);
419 return 0;
420 }
421
422 if (kvm_cpuid_has_hyperv(e2, nent)) {
423 r = kvm_hv_vcpu_init(vcpu);
424 if (r)
425 return r;
426 }
427
428 r = kvm_check_cpuid(vcpu, e2, nent);
429 if (r)
430 return r;
431
432 kvfree(vcpu->arch.cpuid_entries);
433 vcpu->arch.cpuid_entries = e2;
434 vcpu->arch.cpuid_nent = nent;
435
436 kvm_update_kvm_cpuid_base(vcpu);
437 kvm_vcpu_after_set_cpuid(vcpu);
438
439 return 0;
440 }
441
442 /* when an old userspace process fills a new kernel module */
kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu * vcpu,struct kvm_cpuid * cpuid,struct kvm_cpuid_entry __user * entries)443 int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
444 struct kvm_cpuid *cpuid,
445 struct kvm_cpuid_entry __user *entries)
446 {
447 int r, i;
448 struct kvm_cpuid_entry *e = NULL;
449 struct kvm_cpuid_entry2 *e2 = NULL;
450
451 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
452 return -E2BIG;
453
454 if (cpuid->nent) {
455 e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent));
456 if (IS_ERR(e))
457 return PTR_ERR(e);
458
459 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT);
460 if (!e2) {
461 r = -ENOMEM;
462 goto out_free_cpuid;
463 }
464 }
465 for (i = 0; i < cpuid->nent; i++) {
466 e2[i].function = e[i].function;
467 e2[i].eax = e[i].eax;
468 e2[i].ebx = e[i].ebx;
469 e2[i].ecx = e[i].ecx;
470 e2[i].edx = e[i].edx;
471 e2[i].index = 0;
472 e2[i].flags = 0;
473 e2[i].padding[0] = 0;
474 e2[i].padding[1] = 0;
475 e2[i].padding[2] = 0;
476 }
477
478 r = kvm_set_cpuid(vcpu, e2, cpuid->nent);
479 if (r)
480 kvfree(e2);
481
482 out_free_cpuid:
483 kvfree(e);
484
485 return r;
486 }
487
kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu * vcpu,struct kvm_cpuid2 * cpuid,struct kvm_cpuid_entry2 __user * entries)488 int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
489 struct kvm_cpuid2 *cpuid,
490 struct kvm_cpuid_entry2 __user *entries)
491 {
492 struct kvm_cpuid_entry2 *e2 = NULL;
493 int r;
494
495 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
496 return -E2BIG;
497
498 if (cpuid->nent) {
499 e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent));
500 if (IS_ERR(e2))
501 return PTR_ERR(e2);
502 }
503
504 r = kvm_set_cpuid(vcpu, e2, cpuid->nent);
505 if (r)
506 kvfree(e2);
507
508 return r;
509 }
510
kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu * vcpu,struct kvm_cpuid2 * cpuid,struct kvm_cpuid_entry2 __user * entries)511 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
512 struct kvm_cpuid2 *cpuid,
513 struct kvm_cpuid_entry2 __user *entries)
514 {
515 int r;
516
517 r = -E2BIG;
518 if (cpuid->nent < vcpu->arch.cpuid_nent)
519 goto out;
520 r = -EFAULT;
521 if (copy_to_user(entries, vcpu->arch.cpuid_entries,
522 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
523 goto out;
524 return 0;
525
526 out:
527 cpuid->nent = vcpu->arch.cpuid_nent;
528 return r;
529 }
530
531 /* Mask kvm_cpu_caps for @leaf with the raw CPUID capabilities of this CPU. */
__kvm_cpu_cap_mask(unsigned int leaf)532 static __always_inline void __kvm_cpu_cap_mask(unsigned int leaf)
533 {
534 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32);
535 struct kvm_cpuid_entry2 entry;
536
537 reverse_cpuid_check(leaf);
538
539 cpuid_count(cpuid.function, cpuid.index,
540 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx);
541
542 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg);
543 }
544
545 static __always_inline
kvm_cpu_cap_init_scattered(enum kvm_only_cpuid_leafs leaf,u32 mask)546 void kvm_cpu_cap_init_scattered(enum kvm_only_cpuid_leafs leaf, u32 mask)
547 {
548 /* Use kvm_cpu_cap_mask for non-scattered leafs. */
549 BUILD_BUG_ON(leaf < NCAPINTS);
550
551 kvm_cpu_caps[leaf] = mask;
552
553 __kvm_cpu_cap_mask(leaf);
554 }
555
kvm_cpu_cap_mask(enum cpuid_leafs leaf,u32 mask)556 static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask)
557 {
558 /* Use kvm_cpu_cap_init_scattered for scattered leafs. */
559 BUILD_BUG_ON(leaf >= NCAPINTS);
560
561 kvm_cpu_caps[leaf] &= mask;
562
563 __kvm_cpu_cap_mask(leaf);
564 }
565
kvm_set_cpu_caps(void)566 void kvm_set_cpu_caps(void)
567 {
568 #ifdef CONFIG_X86_64
569 unsigned int f_gbpages = F(GBPAGES);
570 unsigned int f_lm = F(LM);
571 unsigned int f_xfd = F(XFD);
572 #else
573 unsigned int f_gbpages = 0;
574 unsigned int f_lm = 0;
575 unsigned int f_xfd = 0;
576 #endif
577 memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps));
578
579 BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)) >
580 sizeof(boot_cpu_data.x86_capability));
581
582 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability,
583 sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)));
584
585 kvm_cpu_cap_mask(CPUID_1_ECX,
586 /*
587 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not*
588 * advertised to guests via CPUID!
589 */
590 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
591 0 /* DS-CPL, VMX, SMX, EST */ |
592 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
593 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) |
594 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) |
595 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
596 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
597 F(F16C) | F(RDRAND)
598 );
599 /* KVM emulates x2apic in software irrespective of host support. */
600 kvm_cpu_cap_set(X86_FEATURE_X2APIC);
601
602 kvm_cpu_cap_mask(CPUID_1_EDX,
603 F(FPU) | F(VME) | F(DE) | F(PSE) |
604 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
605 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
606 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
607 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) |
608 0 /* Reserved, DS, ACPI */ | F(MMX) |
609 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
610 0 /* HTT, TM, Reserved, PBE */
611 );
612
613 kvm_cpu_cap_mask(CPUID_7_0_EBX,
614 F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) |
615 F(FDP_EXCPTN_ONLY) | F(SMEP) | F(BMI2) | F(ERMS) | F(INVPCID) |
616 F(RTM) | F(ZERO_FCS_FDS) | 0 /*MPX*/ | F(AVX512F) |
617 F(AVX512DQ) | F(RDSEED) | F(ADX) | F(SMAP) | F(AVX512IFMA) |
618 F(CLFLUSHOPT) | F(CLWB) | 0 /*INTEL_PT*/ | F(AVX512PF) |
619 F(AVX512ER) | F(AVX512CD) | F(SHA_NI) | F(AVX512BW) |
620 F(AVX512VL));
621
622 kvm_cpu_cap_mask(CPUID_7_ECX,
623 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) |
624 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) |
625 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) |
626 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ |
627 F(SGX_LC) | F(BUS_LOCK_DETECT)
628 );
629 /* Set LA57 based on hardware capability. */
630 if (cpuid_ecx(7) & F(LA57))
631 kvm_cpu_cap_set(X86_FEATURE_LA57);
632
633 /*
634 * PKU not yet implemented for shadow paging and requires OSPKE
635 * to be set on the host. Clear it if that is not the case
636 */
637 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE))
638 kvm_cpu_cap_clear(X86_FEATURE_PKU);
639
640 kvm_cpu_cap_mask(CPUID_7_EDX,
641 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
642 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
643 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
644 F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) |
645 F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16)
646 );
647
648 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
649 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST);
650 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES);
651
652 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS))
653 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL);
654 if (boot_cpu_has(X86_FEATURE_STIBP))
655 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP);
656 if (boot_cpu_has(X86_FEATURE_AMD_SSBD))
657 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
658
659 kvm_cpu_cap_mask(CPUID_7_1_EAX,
660 F(AVX_VNNI) | F(AVX512_BF16)
661 );
662
663 kvm_cpu_cap_mask(CPUID_D_1_EAX,
664 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd
665 );
666
667 kvm_cpu_cap_init_scattered(CPUID_12_EAX,
668 SF(SGX1) | SF(SGX2)
669 );
670
671 kvm_cpu_cap_mask(CPUID_8000_0001_ECX,
672 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
673 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
674 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) |
675 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) |
676 F(TOPOEXT) | 0 /* PERFCTR_CORE */
677 );
678
679 kvm_cpu_cap_mask(CPUID_8000_0001_EDX,
680 F(FPU) | F(VME) | F(DE) | F(PSE) |
681 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
682 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
683 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
684 F(PAT) | F(PSE36) | 0 /* Reserved */ |
685 F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
686 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) |
687 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW)
688 );
689
690 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64))
691 kvm_cpu_cap_set(X86_FEATURE_GBPAGES);
692
693 kvm_cpu_cap_mask(CPUID_8000_0008_EBX,
694 F(CLZERO) | F(XSAVEERPTR) |
695 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) |
696 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) |
697 __feature_bit(KVM_X86_FEATURE_PSFD)
698 );
699
700 /*
701 * AMD has separate bits for each SPEC_CTRL bit.
702 * arch/x86/kernel/cpu/bugs.c is kind enough to
703 * record that in cpufeatures so use them.
704 */
705 if (boot_cpu_has(X86_FEATURE_IBPB))
706 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB);
707 if (boot_cpu_has(X86_FEATURE_IBRS))
708 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS);
709 if (boot_cpu_has(X86_FEATURE_STIBP))
710 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP);
711 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
712 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD);
713 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
714 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO);
715 /*
716 * The preference is to use SPEC CTRL MSR instead of the
717 * VIRT_SPEC MSR.
718 */
719 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
720 !boot_cpu_has(X86_FEATURE_AMD_SSBD))
721 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
722
723 /*
724 * Hide all SVM features by default, SVM will set the cap bits for
725 * features it emulates and/or exposes for L1.
726 */
727 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0);
728
729 kvm_cpu_cap_mask(CPUID_8000_001F_EAX,
730 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) |
731 F(SME_COHERENT));
732
733 kvm_cpu_cap_mask(CPUID_C000_0001_EDX,
734 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
735 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
736 F(PMM) | F(PMM_EN)
737 );
738
739 /*
740 * Hide RDTSCP and RDPID if either feature is reported as supported but
741 * probing MSR_TSC_AUX failed. This is purely a sanity check and
742 * should never happen, but the guest will likely crash if RDTSCP or
743 * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in
744 * the past. For example, the sanity check may fire if this instance of
745 * KVM is running as L1 on top of an older, broken KVM.
746 */
747 if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) ||
748 kvm_cpu_cap_has(X86_FEATURE_RDPID)) &&
749 !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) {
750 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
751 kvm_cpu_cap_clear(X86_FEATURE_RDPID);
752 }
753 }
754 EXPORT_SYMBOL_GPL(kvm_set_cpu_caps);
755
756 struct kvm_cpuid_array {
757 struct kvm_cpuid_entry2 *entries;
758 int maxnent;
759 int nent;
760 };
761
get_next_cpuid(struct kvm_cpuid_array * array)762 static struct kvm_cpuid_entry2 *get_next_cpuid(struct kvm_cpuid_array *array)
763 {
764 if (array->nent >= array->maxnent)
765 return NULL;
766
767 return &array->entries[array->nent++];
768 }
769
do_host_cpuid(struct kvm_cpuid_array * array,u32 function,u32 index)770 static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array,
771 u32 function, u32 index)
772 {
773 struct kvm_cpuid_entry2 *entry = get_next_cpuid(array);
774
775 if (!entry)
776 return NULL;
777
778 memset(entry, 0, sizeof(*entry));
779 entry->function = function;
780 entry->index = index;
781 switch (function & 0xC0000000) {
782 case 0x40000000:
783 /* Hypervisor leaves are always synthesized by __do_cpuid_func. */
784 return entry;
785
786 case 0x80000000:
787 /*
788 * 0x80000021 is sometimes synthesized by __do_cpuid_func, which
789 * would result in out-of-bounds calls to do_host_cpuid.
790 */
791 {
792 static int max_cpuid_80000000;
793 if (!READ_ONCE(max_cpuid_80000000))
794 WRITE_ONCE(max_cpuid_80000000, cpuid_eax(0x80000000));
795 if (function > READ_ONCE(max_cpuid_80000000))
796 return entry;
797 }
798 break;
799
800 default:
801 break;
802 }
803
804 cpuid_count(entry->function, entry->index,
805 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
806
807 if (cpuid_function_is_indexed(function))
808 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
809
810 return entry;
811 }
812
__do_cpuid_func_emulated(struct kvm_cpuid_array * array,u32 func)813 static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func)
814 {
815 struct kvm_cpuid_entry2 *entry;
816
817 if (array->nent >= array->maxnent)
818 return -E2BIG;
819
820 entry = &array->entries[array->nent];
821 entry->function = func;
822 entry->index = 0;
823 entry->flags = 0;
824
825 switch (func) {
826 case 0:
827 entry->eax = 7;
828 ++array->nent;
829 break;
830 case 1:
831 entry->ecx = F(MOVBE);
832 ++array->nent;
833 break;
834 case 7:
835 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
836 entry->eax = 0;
837 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
838 entry->ecx = F(RDPID);
839 ++array->nent;
840 break;
841 default:
842 break;
843 }
844
845 return 0;
846 }
847
__do_cpuid_func(struct kvm_cpuid_array * array,u32 function)848 static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
849 {
850 struct kvm_cpuid_entry2 *entry;
851 int r, i, max_idx;
852
853 /* all calls to cpuid_count() should be made on the same cpu */
854 get_cpu();
855
856 r = -E2BIG;
857
858 entry = do_host_cpuid(array, function, 0);
859 if (!entry)
860 goto out;
861
862 switch (function) {
863 case 0:
864 /* Limited to the highest leaf implemented in KVM. */
865 entry->eax = min(entry->eax, 0x1fU);
866 break;
867 case 1:
868 cpuid_entry_override(entry, CPUID_1_EDX);
869 cpuid_entry_override(entry, CPUID_1_ECX);
870 break;
871 case 2:
872 /*
873 * On ancient CPUs, function 2 entries are STATEFUL. That is,
874 * CPUID(function=2, index=0) may return different results each
875 * time, with the least-significant byte in EAX enumerating the
876 * number of times software should do CPUID(2, 0).
877 *
878 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less
879 * idiotic. Intel's SDM states that EAX & 0xff "will always
880 * return 01H. Software should ignore this value and not
881 * interpret it as an informational descriptor", while AMD's
882 * APM states that CPUID(2) is reserved.
883 *
884 * WARN if a frankenstein CPU that supports virtualization and
885 * a stateful CPUID.0x2 is encountered.
886 */
887 WARN_ON_ONCE((entry->eax & 0xff) > 1);
888 break;
889 /* functions 4 and 0x8000001d have additional index. */
890 case 4:
891 case 0x8000001d:
892 /*
893 * Read entries until the cache type in the previous entry is
894 * zero, i.e. indicates an invalid entry.
895 */
896 for (i = 1; entry->eax & 0x1f; ++i) {
897 entry = do_host_cpuid(array, function, i);
898 if (!entry)
899 goto out;
900 }
901 break;
902 case 6: /* Thermal management */
903 entry->eax = 0x4; /* allow ARAT */
904 entry->ebx = 0;
905 entry->ecx = 0;
906 entry->edx = 0;
907 break;
908 /* function 7 has additional index. */
909 case 7:
910 entry->eax = min(entry->eax, 1u);
911 cpuid_entry_override(entry, CPUID_7_0_EBX);
912 cpuid_entry_override(entry, CPUID_7_ECX);
913 cpuid_entry_override(entry, CPUID_7_EDX);
914
915 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */
916 if (entry->eax == 1) {
917 entry = do_host_cpuid(array, function, 1);
918 if (!entry)
919 goto out;
920
921 cpuid_entry_override(entry, CPUID_7_1_EAX);
922 entry->ebx = 0;
923 entry->ecx = 0;
924 entry->edx = 0;
925 }
926 break;
927 case 0xa: { /* Architectural Performance Monitoring */
928 union cpuid10_eax eax;
929 union cpuid10_edx edx;
930
931 if (!static_cpu_has(X86_FEATURE_ARCH_PERFMON)) {
932 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
933 break;
934 }
935
936 eax.split.version_id = kvm_pmu_cap.version;
937 eax.split.num_counters = kvm_pmu_cap.num_counters_gp;
938 eax.split.bit_width = kvm_pmu_cap.bit_width_gp;
939 eax.split.mask_length = kvm_pmu_cap.events_mask_len;
940 edx.split.num_counters_fixed = kvm_pmu_cap.num_counters_fixed;
941 edx.split.bit_width_fixed = kvm_pmu_cap.bit_width_fixed;
942
943 if (kvm_pmu_cap.version)
944 edx.split.anythread_deprecated = 1;
945 edx.split.reserved1 = 0;
946 edx.split.reserved2 = 0;
947
948 entry->eax = eax.full;
949 entry->ebx = kvm_pmu_cap.events_mask;
950 entry->ecx = 0;
951 entry->edx = edx.full;
952 break;
953 }
954 case 0x1f:
955 case 0xb:
956 /*
957 * No topology; a valid topology is indicated by the presence
958 * of subleaf 1.
959 */
960 entry->eax = entry->ebx = entry->ecx = 0;
961 break;
962 case 0xd: {
963 u64 permitted_xcr0 = kvm_caps.supported_xcr0 & xstate_get_guest_group_perm();
964 u64 permitted_xss = kvm_caps.supported_xss;
965
966 entry->eax &= permitted_xcr0;
967 entry->ebx = xstate_required_size(permitted_xcr0, false);
968 entry->ecx = entry->ebx;
969 entry->edx &= permitted_xcr0 >> 32;
970 if (!permitted_xcr0)
971 break;
972
973 entry = do_host_cpuid(array, function, 1);
974 if (!entry)
975 goto out;
976
977 cpuid_entry_override(entry, CPUID_D_1_EAX);
978 if (entry->eax & (F(XSAVES)|F(XSAVEC)))
979 entry->ebx = xstate_required_size(permitted_xcr0 | permitted_xss,
980 true);
981 else {
982 WARN_ON_ONCE(permitted_xss != 0);
983 entry->ebx = 0;
984 }
985 entry->ecx &= permitted_xss;
986 entry->edx &= permitted_xss >> 32;
987
988 for (i = 2; i < 64; ++i) {
989 bool s_state;
990 if (permitted_xcr0 & BIT_ULL(i))
991 s_state = false;
992 else if (permitted_xss & BIT_ULL(i))
993 s_state = true;
994 else
995 continue;
996
997 entry = do_host_cpuid(array, function, i);
998 if (!entry)
999 goto out;
1000
1001 /*
1002 * The supported check above should have filtered out
1003 * invalid sub-leafs. Only valid sub-leafs should
1004 * reach this point, and they should have a non-zero
1005 * save state size. Furthermore, check whether the
1006 * processor agrees with permitted_xcr0/permitted_xss
1007 * on whether this is an XCR0- or IA32_XSS-managed area.
1008 */
1009 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) {
1010 --array->nent;
1011 continue;
1012 }
1013
1014 if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
1015 entry->ecx &= ~BIT_ULL(2);
1016 entry->edx = 0;
1017 }
1018 break;
1019 }
1020 case 0x12:
1021 /* Intel SGX */
1022 if (!kvm_cpu_cap_has(X86_FEATURE_SGX)) {
1023 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1024 break;
1025 }
1026
1027 /*
1028 * Index 0: Sub-features, MISCSELECT (a.k.a extended features)
1029 * and max enclave sizes. The SGX sub-features and MISCSELECT
1030 * are restricted by kernel and KVM capabilities (like most
1031 * feature flags), while enclave size is unrestricted.
1032 */
1033 cpuid_entry_override(entry, CPUID_12_EAX);
1034 entry->ebx &= SGX_MISC_EXINFO;
1035
1036 entry = do_host_cpuid(array, function, 1);
1037 if (!entry)
1038 goto out;
1039
1040 /*
1041 * Index 1: SECS.ATTRIBUTES. ATTRIBUTES are restricted a la
1042 * feature flags. Advertise all supported flags, including
1043 * privileged attributes that require explicit opt-in from
1044 * userspace. ATTRIBUTES.XFRM is not adjusted as userspace is
1045 * expected to derive it from supported XCR0.
1046 */
1047 entry->eax &= SGX_ATTR_DEBUG | SGX_ATTR_MODE64BIT |
1048 SGX_ATTR_PROVISIONKEY | SGX_ATTR_EINITTOKENKEY |
1049 SGX_ATTR_KSS;
1050 entry->ebx &= 0;
1051 break;
1052 /* Intel PT */
1053 case 0x14:
1054 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) {
1055 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1056 break;
1057 }
1058
1059 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) {
1060 if (!do_host_cpuid(array, function, i))
1061 goto out;
1062 }
1063 break;
1064 /* Intel AMX TILE */
1065 case 0x1d:
1066 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) {
1067 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1068 break;
1069 }
1070
1071 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) {
1072 if (!do_host_cpuid(array, function, i))
1073 goto out;
1074 }
1075 break;
1076 case 0x1e: /* TMUL information */
1077 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) {
1078 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1079 break;
1080 }
1081 break;
1082 case KVM_CPUID_SIGNATURE: {
1083 const u32 *sigptr = (const u32 *)KVM_SIGNATURE;
1084 entry->eax = KVM_CPUID_FEATURES;
1085 entry->ebx = sigptr[0];
1086 entry->ecx = sigptr[1];
1087 entry->edx = sigptr[2];
1088 break;
1089 }
1090 case KVM_CPUID_FEATURES:
1091 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
1092 (1 << KVM_FEATURE_NOP_IO_DELAY) |
1093 (1 << KVM_FEATURE_CLOCKSOURCE2) |
1094 (1 << KVM_FEATURE_ASYNC_PF) |
1095 (1 << KVM_FEATURE_PV_EOI) |
1096 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) |
1097 (1 << KVM_FEATURE_PV_UNHALT) |
1098 (1 << KVM_FEATURE_PV_TLB_FLUSH) |
1099 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) |
1100 (1 << KVM_FEATURE_PV_SEND_IPI) |
1101 (1 << KVM_FEATURE_POLL_CONTROL) |
1102 (1 << KVM_FEATURE_PV_SCHED_YIELD) |
1103 (1 << KVM_FEATURE_ASYNC_PF_INT);
1104
1105 if (sched_info_on())
1106 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
1107
1108 entry->ebx = 0;
1109 entry->ecx = 0;
1110 entry->edx = 0;
1111 break;
1112 case 0x80000000:
1113 entry->eax = min(entry->eax, 0x80000021);
1114 /*
1115 * Serializing LFENCE is reported in a multitude of ways, and
1116 * NullSegClearsBase is not reported in CPUID on Zen2; help
1117 * userspace by providing the CPUID leaf ourselves.
1118 *
1119 * However, only do it if the host has CPUID leaf 0x8000001d.
1120 * QEMU thinks that it can query the host blindly for that
1121 * CPUID leaf if KVM reports that it supports 0x8000001d or
1122 * above. The processor merrily returns values from the
1123 * highest Intel leaf which QEMU tries to use as the guest's
1124 * 0x8000001d. Even worse, this can result in an infinite
1125 * loop if said highest leaf has no subleaves indexed by ECX.
1126 */
1127 if (entry->eax >= 0x8000001d &&
1128 (static_cpu_has(X86_FEATURE_LFENCE_RDTSC)
1129 || !static_cpu_has_bug(X86_BUG_NULL_SEG)))
1130 entry->eax = max(entry->eax, 0x80000021);
1131 break;
1132 case 0x80000001:
1133 entry->ebx &= ~GENMASK(27, 16);
1134 cpuid_entry_override(entry, CPUID_8000_0001_EDX);
1135 cpuid_entry_override(entry, CPUID_8000_0001_ECX);
1136 break;
1137 case 0x80000006:
1138 /* Drop reserved bits, pass host L2 cache and TLB info. */
1139 entry->edx &= ~GENMASK(17, 16);
1140 break;
1141 case 0x80000007: /* Advanced power management */
1142 /* invariant TSC is CPUID.80000007H:EDX[8] */
1143 entry->edx &= (1 << 8);
1144 /* mask against host */
1145 entry->edx &= boot_cpu_data.x86_power;
1146 entry->eax = entry->ebx = entry->ecx = 0;
1147 break;
1148 case 0x80000008: {
1149 unsigned g_phys_as = (entry->eax >> 16) & 0xff;
1150 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
1151 unsigned phys_as = entry->eax & 0xff;
1152
1153 /*
1154 * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as
1155 * the guest operates in the same PA space as the host, i.e.
1156 * reductions in MAXPHYADDR for memory encryption affect shadow
1157 * paging, too.
1158 *
1159 * If TDP is enabled but an explicit guest MAXPHYADDR is not
1160 * provided, use the raw bare metal MAXPHYADDR as reductions to
1161 * the HPAs do not affect GPAs.
1162 */
1163 if (!tdp_enabled)
1164 g_phys_as = boot_cpu_data.x86_phys_bits;
1165 else if (!g_phys_as)
1166 g_phys_as = phys_as;
1167
1168 entry->eax = g_phys_as | (virt_as << 8);
1169 entry->ecx &= ~(GENMASK(31, 16) | GENMASK(11, 8));
1170 entry->edx = 0;
1171 cpuid_entry_override(entry, CPUID_8000_0008_EBX);
1172 break;
1173 }
1174 case 0x8000000A:
1175 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) {
1176 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1177 break;
1178 }
1179 entry->eax = 1; /* SVM revision 1 */
1180 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
1181 ASID emulation to nested SVM */
1182 entry->ecx = 0; /* Reserved */
1183 cpuid_entry_override(entry, CPUID_8000_000A_EDX);
1184 break;
1185 case 0x80000019:
1186 entry->ecx = entry->edx = 0;
1187 break;
1188 case 0x8000001a:
1189 entry->eax &= GENMASK(2, 0);
1190 entry->ebx = entry->ecx = entry->edx = 0;
1191 break;
1192 case 0x8000001e:
1193 /* Do not return host topology information. */
1194 entry->eax = entry->ebx = entry->ecx = 0;
1195 entry->edx = 0; /* reserved */
1196 break;
1197 case 0x8000001F:
1198 if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) {
1199 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1200 } else {
1201 cpuid_entry_override(entry, CPUID_8000_001F_EAX);
1202 /* Clear NumVMPL since KVM does not support VMPL. */
1203 entry->ebx &= ~GENMASK(31, 12);
1204 /*
1205 * Enumerate '0' for "PA bits reduction", the adjusted
1206 * MAXPHYADDR is enumerated directly (see 0x80000008).
1207 */
1208 entry->ebx &= ~GENMASK(11, 6);
1209 }
1210 break;
1211 case 0x80000020:
1212 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1213 break;
1214 case 0x80000021:
1215 entry->ebx = entry->ecx = entry->edx = 0;
1216 /*
1217 * Pass down these bits:
1218 * EAX 0 NNDBP, Processor ignores nested data breakpoints
1219 * EAX 2 LAS, LFENCE always serializing
1220 * EAX 6 NSCB, Null selector clear base
1221 *
1222 * Other defined bits are for MSRs that KVM does not expose:
1223 * EAX 3 SPCL, SMM page configuration lock
1224 * EAX 13 PCMSR, Prefetch control MSR
1225 */
1226 entry->eax &= BIT(0) | BIT(2) | BIT(6);
1227 if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC))
1228 entry->eax |= BIT(2);
1229 if (!static_cpu_has_bug(X86_BUG_NULL_SEG))
1230 entry->eax |= BIT(6);
1231 break;
1232 /*Add support for Centaur's CPUID instruction*/
1233 case 0xC0000000:
1234 /*Just support up to 0xC0000004 now*/
1235 entry->eax = min(entry->eax, 0xC0000004);
1236 break;
1237 case 0xC0000001:
1238 cpuid_entry_override(entry, CPUID_C000_0001_EDX);
1239 break;
1240 case 3: /* Processor serial number */
1241 case 5: /* MONITOR/MWAIT */
1242 case 0xC0000002:
1243 case 0xC0000003:
1244 case 0xC0000004:
1245 default:
1246 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
1247 break;
1248 }
1249
1250 r = 0;
1251
1252 out:
1253 put_cpu();
1254
1255 return r;
1256 }
1257
do_cpuid_func(struct kvm_cpuid_array * array,u32 func,unsigned int type)1258 static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func,
1259 unsigned int type)
1260 {
1261 if (type == KVM_GET_EMULATED_CPUID)
1262 return __do_cpuid_func_emulated(array, func);
1263
1264 return __do_cpuid_func(array, func);
1265 }
1266
1267 #define CENTAUR_CPUID_SIGNATURE 0xC0000000
1268
get_cpuid_func(struct kvm_cpuid_array * array,u32 func,unsigned int type)1269 static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func,
1270 unsigned int type)
1271 {
1272 u32 limit;
1273 int r;
1274
1275 if (func == CENTAUR_CPUID_SIGNATURE &&
1276 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR)
1277 return 0;
1278
1279 r = do_cpuid_func(array, func, type);
1280 if (r)
1281 return r;
1282
1283 limit = array->entries[array->nent - 1].eax;
1284 for (func = func + 1; func <= limit; ++func) {
1285 r = do_cpuid_func(array, func, type);
1286 if (r)
1287 break;
1288 }
1289
1290 return r;
1291 }
1292
sanity_check_entries(struct kvm_cpuid_entry2 __user * entries,__u32 num_entries,unsigned int ioctl_type)1293 static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries,
1294 __u32 num_entries, unsigned int ioctl_type)
1295 {
1296 int i;
1297 __u32 pad[3];
1298
1299 if (ioctl_type != KVM_GET_EMULATED_CPUID)
1300 return false;
1301
1302 /*
1303 * We want to make sure that ->padding is being passed clean from
1304 * userspace in case we want to use it for something in the future.
1305 *
1306 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we
1307 * have to give ourselves satisfied only with the emulated side. /me
1308 * sheds a tear.
1309 */
1310 for (i = 0; i < num_entries; i++) {
1311 if (copy_from_user(pad, entries[i].padding, sizeof(pad)))
1312 return true;
1313
1314 if (pad[0] || pad[1] || pad[2])
1315 return true;
1316 }
1317 return false;
1318 }
1319
kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 * cpuid,struct kvm_cpuid_entry2 __user * entries,unsigned int type)1320 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid,
1321 struct kvm_cpuid_entry2 __user *entries,
1322 unsigned int type)
1323 {
1324 static const u32 funcs[] = {
1325 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE,
1326 };
1327
1328 struct kvm_cpuid_array array = {
1329 .nent = 0,
1330 };
1331 int r, i;
1332
1333 if (cpuid->nent < 1)
1334 return -E2BIG;
1335 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1336 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
1337
1338 if (sanity_check_entries(entries, cpuid->nent, type))
1339 return -EINVAL;
1340
1341 array.entries = kvcalloc(cpuid->nent, sizeof(struct kvm_cpuid_entry2), GFP_KERNEL);
1342 if (!array.entries)
1343 return -ENOMEM;
1344
1345 array.maxnent = cpuid->nent;
1346
1347 for (i = 0; i < ARRAY_SIZE(funcs); i++) {
1348 r = get_cpuid_func(&array, funcs[i], type);
1349 if (r)
1350 goto out_free;
1351 }
1352 cpuid->nent = array.nent;
1353
1354 if (copy_to_user(entries, array.entries,
1355 array.nent * sizeof(struct kvm_cpuid_entry2)))
1356 r = -EFAULT;
1357
1358 out_free:
1359 kvfree(array.entries);
1360 return r;
1361 }
1362
kvm_find_cpuid_entry_index(struct kvm_vcpu * vcpu,u32 function,u32 index)1363 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry_index(struct kvm_vcpu *vcpu,
1364 u32 function, u32 index)
1365 {
1366 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent,
1367 function, index);
1368 }
1369 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry_index);
1370
kvm_find_cpuid_entry(struct kvm_vcpu * vcpu,u32 function)1371 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
1372 u32 function)
1373 {
1374 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent,
1375 function, KVM_CPUID_INDEX_NOT_SIGNIFICANT);
1376 }
1377 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
1378
1379 /*
1380 * Intel CPUID semantics treats any query for an out-of-range leaf as if the
1381 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics
1382 * returns all zeroes for any undefined leaf, whether or not the leaf is in
1383 * range. Centaur/VIA follows Intel semantics.
1384 *
1385 * A leaf is considered out-of-range if its function is higher than the maximum
1386 * supported leaf of its associated class or if its associated class does not
1387 * exist.
1388 *
1389 * There are three primary classes to be considered, with their respective
1390 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary
1391 * class exists if a guest CPUID entry for its <base> leaf exists. For a given
1392 * class, CPUID.<base>.EAX contains the max supported leaf for the class.
1393 *
1394 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff
1395 * - Hypervisor: 0x40000000 - 0x4fffffff
1396 * - Extended: 0x80000000 - 0xbfffffff
1397 * - Centaur: 0xc0000000 - 0xcfffffff
1398 *
1399 * The Hypervisor class is further subdivided into sub-classes that each act as
1400 * their own independent class associated with a 0x100 byte range. E.g. if Qemu
1401 * is advertising support for both HyperV and KVM, the resulting Hypervisor
1402 * CPUID sub-classes are:
1403 *
1404 * - HyperV: 0x40000000 - 0x400000ff
1405 * - KVM: 0x40000100 - 0x400001ff
1406 */
1407 static struct kvm_cpuid_entry2 *
get_out_of_range_cpuid_entry(struct kvm_vcpu * vcpu,u32 * fn_ptr,u32 index)1408 get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index)
1409 {
1410 struct kvm_cpuid_entry2 *basic, *class;
1411 u32 function = *fn_ptr;
1412
1413 basic = kvm_find_cpuid_entry(vcpu, 0);
1414 if (!basic)
1415 return NULL;
1416
1417 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) ||
1418 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx))
1419 return NULL;
1420
1421 if (function >= 0x40000000 && function <= 0x4fffffff)
1422 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00);
1423 else if (function >= 0xc0000000)
1424 class = kvm_find_cpuid_entry(vcpu, 0xc0000000);
1425 else
1426 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000);
1427
1428 if (class && function <= class->eax)
1429 return NULL;
1430
1431 /*
1432 * Leaf specific adjustments are also applied when redirecting to the
1433 * max basic entry, e.g. if the max basic leaf is 0xb but there is no
1434 * entry for CPUID.0xb.index (see below), then the output value for EDX
1435 * needs to be pulled from CPUID.0xb.1.
1436 */
1437 *fn_ptr = basic->eax;
1438
1439 /*
1440 * The class does not exist or the requested function is out of range;
1441 * the effective CPUID entry is the max basic leaf. Note, the index of
1442 * the original requested leaf is observed!
1443 */
1444 return kvm_find_cpuid_entry_index(vcpu, basic->eax, index);
1445 }
1446
kvm_cpuid(struct kvm_vcpu * vcpu,u32 * eax,u32 * ebx,u32 * ecx,u32 * edx,bool exact_only)1447 bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx,
1448 u32 *ecx, u32 *edx, bool exact_only)
1449 {
1450 u32 orig_function = *eax, function = *eax, index = *ecx;
1451 struct kvm_cpuid_entry2 *entry;
1452 bool exact, used_max_basic = false;
1453
1454 entry = kvm_find_cpuid_entry_index(vcpu, function, index);
1455 exact = !!entry;
1456
1457 if (!entry && !exact_only) {
1458 entry = get_out_of_range_cpuid_entry(vcpu, &function, index);
1459 used_max_basic = !!entry;
1460 }
1461
1462 if (entry) {
1463 *eax = entry->eax;
1464 *ebx = entry->ebx;
1465 *ecx = entry->ecx;
1466 *edx = entry->edx;
1467 if (function == 7 && index == 0) {
1468 u64 data;
1469 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) &&
1470 (data & TSX_CTRL_CPUID_CLEAR))
1471 *ebx &= ~(F(RTM) | F(HLE));
1472 }
1473 } else {
1474 *eax = *ebx = *ecx = *edx = 0;
1475 /*
1476 * When leaf 0BH or 1FH is defined, CL is pass-through
1477 * and EDX is always the x2APIC ID, even for undefined
1478 * subleaves. Index 1 will exist iff the leaf is
1479 * implemented, so we pass through CL iff leaf 1
1480 * exists. EDX can be copied from any existing index.
1481 */
1482 if (function == 0xb || function == 0x1f) {
1483 entry = kvm_find_cpuid_entry_index(vcpu, function, 1);
1484 if (entry) {
1485 *ecx = index & 0xff;
1486 *edx = entry->edx;
1487 }
1488 }
1489 }
1490 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact,
1491 used_max_basic);
1492 return exact;
1493 }
1494 EXPORT_SYMBOL_GPL(kvm_cpuid);
1495
kvm_emulate_cpuid(struct kvm_vcpu * vcpu)1496 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
1497 {
1498 u32 eax, ebx, ecx, edx;
1499
1500 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0))
1501 return 1;
1502
1503 eax = kvm_rax_read(vcpu);
1504 ecx = kvm_rcx_read(vcpu);
1505 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false);
1506 kvm_rax_write(vcpu, eax);
1507 kvm_rbx_write(vcpu, ebx);
1508 kvm_rcx_write(vcpu, ecx);
1509 kvm_rdx_write(vcpu, edx);
1510 return kvm_skip_emulated_instruction(vcpu);
1511 }
1512 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
1513