1
2 /*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
23 #include <linux/mm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
27 #include <linux/io.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
32 #include <asm/msr.h>
33 #include <asm/page.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <linux/atomic.h>
37 #include "kvm_cache_regs.h"
38 #include "irq.h"
39 #include "trace.h"
40 #include "x86.h"
41 #include "cpuid.h"
42
43 #ifndef CONFIG_X86_64
44 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
45 #else
46 #define mod_64(x, y) ((x) % (y))
47 #endif
48
49 #define PRId64 "d"
50 #define PRIx64 "llx"
51 #define PRIu64 "u"
52 #define PRIo64 "o"
53
54 #define APIC_BUS_CYCLE_NS 1
55
56 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
57 #define apic_debug(fmt, arg...)
58
59 #define APIC_LVT_NUM 6
60 /* 14 is the version for Xeon and Pentium 8.4.8*/
61 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
62 #define LAPIC_MMIO_LENGTH (1 << 12)
63 /* followed define is not in apicdef.h */
64 #define APIC_SHORT_MASK 0xc0000
65 #define APIC_DEST_NOSHORT 0x0
66 #define APIC_DEST_MASK 0x800
67 #define MAX_APIC_VECTOR 256
68
69 #define VEC_POS(v) ((v) & (32 - 1))
70 #define REG_POS(v) (((v) >> 5) << 4)
71
72 static unsigned int min_timer_period_us = 500;
73 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
74
apic_get_reg(struct kvm_lapic * apic,int reg_off)75 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
76 {
77 return *((u32 *) (apic->regs + reg_off));
78 }
79
apic_set_reg(struct kvm_lapic * apic,int reg_off,u32 val)80 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
81 {
82 *((u32 *) (apic->regs + reg_off)) = val;
83 }
84
apic_test_and_set_vector(int vec,void * bitmap)85 static inline int apic_test_and_set_vector(int vec, void *bitmap)
86 {
87 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
88 }
89
apic_test_and_clear_vector(int vec,void * bitmap)90 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
91 {
92 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
93 }
94
apic_set_vector(int vec,void * bitmap)95 static inline void apic_set_vector(int vec, void *bitmap)
96 {
97 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
98 }
99
apic_clear_vector(int vec,void * bitmap)100 static inline void apic_clear_vector(int vec, void *bitmap)
101 {
102 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
103 }
104
apic_hw_enabled(struct kvm_lapic * apic)105 static inline int apic_hw_enabled(struct kvm_lapic *apic)
106 {
107 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
108 }
109
apic_sw_enabled(struct kvm_lapic * apic)110 static inline int apic_sw_enabled(struct kvm_lapic *apic)
111 {
112 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
113 }
114
apic_enabled(struct kvm_lapic * apic)115 static inline int apic_enabled(struct kvm_lapic *apic)
116 {
117 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
118 }
119
120 #define LVT_MASK \
121 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
122
123 #define LINT_MASK \
124 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
125 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
126
kvm_apic_id(struct kvm_lapic * apic)127 static inline int kvm_apic_id(struct kvm_lapic *apic)
128 {
129 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
130 }
131
apic_lvt_enabled(struct kvm_lapic * apic,int lvt_type)132 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
133 {
134 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
135 }
136
apic_lvt_vector(struct kvm_lapic * apic,int lvt_type)137 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
138 {
139 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
140 }
141
apic_lvtt_oneshot(struct kvm_lapic * apic)142 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
143 {
144 return ((apic_get_reg(apic, APIC_LVTT) &
145 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT);
146 }
147
apic_lvtt_period(struct kvm_lapic * apic)148 static inline int apic_lvtt_period(struct kvm_lapic *apic)
149 {
150 return ((apic_get_reg(apic, APIC_LVTT) &
151 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC);
152 }
153
apic_lvtt_tscdeadline(struct kvm_lapic * apic)154 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
155 {
156 return ((apic_get_reg(apic, APIC_LVTT) &
157 apic->lapic_timer.timer_mode_mask) ==
158 APIC_LVT_TIMER_TSCDEADLINE);
159 }
160
apic_lvt_nmi_mode(u32 lvt_val)161 static inline int apic_lvt_nmi_mode(u32 lvt_val)
162 {
163 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
164 }
165
kvm_apic_set_version(struct kvm_vcpu * vcpu)166 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
167 {
168 struct kvm_lapic *apic = vcpu->arch.apic;
169 struct kvm_cpuid_entry2 *feat;
170 u32 v = APIC_VERSION;
171
172 if (!irqchip_in_kernel(vcpu->kvm))
173 return;
174
175 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
176 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
177 v |= APIC_LVR_DIRECTED_EOI;
178 apic_set_reg(apic, APIC_LVR, v);
179 }
180
apic_x2apic_mode(struct kvm_lapic * apic)181 static inline int apic_x2apic_mode(struct kvm_lapic *apic)
182 {
183 return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
184 }
185
186 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
187 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
188 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
189 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
190 LINT_MASK, LINT_MASK, /* LVT0-1 */
191 LVT_MASK /* LVTERR */
192 };
193
find_highest_vector(void * bitmap)194 static int find_highest_vector(void *bitmap)
195 {
196 u32 *word = bitmap;
197 int word_offset = MAX_APIC_VECTOR >> 5;
198
199 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
200 continue;
201
202 if (likely(!word_offset && !word[0]))
203 return -1;
204 else
205 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
206 }
207
apic_test_and_set_irr(int vec,struct kvm_lapic * apic)208 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
209 {
210 apic->irr_pending = true;
211 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
212 }
213
apic_search_irr(struct kvm_lapic * apic)214 static inline int apic_search_irr(struct kvm_lapic *apic)
215 {
216 return find_highest_vector(apic->regs + APIC_IRR);
217 }
218
apic_find_highest_irr(struct kvm_lapic * apic)219 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
220 {
221 int result;
222
223 if (!apic->irr_pending)
224 return -1;
225
226 result = apic_search_irr(apic);
227 ASSERT(result == -1 || result >= 16);
228
229 return result;
230 }
231
apic_clear_irr(int vec,struct kvm_lapic * apic)232 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
233 {
234 apic->irr_pending = false;
235 apic_clear_vector(vec, apic->regs + APIC_IRR);
236 if (apic_search_irr(apic) != -1)
237 apic->irr_pending = true;
238 }
239
kvm_lapic_find_highest_irr(struct kvm_vcpu * vcpu)240 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
241 {
242 struct kvm_lapic *apic = vcpu->arch.apic;
243 int highest_irr;
244
245 /* This may race with setting of irr in __apic_accept_irq() and
246 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
247 * will cause vmexit immediately and the value will be recalculated
248 * on the next vmentry.
249 */
250 if (!apic)
251 return 0;
252 highest_irr = apic_find_highest_irr(apic);
253
254 return highest_irr;
255 }
256
257 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
258 int vector, int level, int trig_mode);
259
kvm_apic_set_irq(struct kvm_vcpu * vcpu,struct kvm_lapic_irq * irq)260 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
261 {
262 struct kvm_lapic *apic = vcpu->arch.apic;
263
264 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
265 irq->level, irq->trig_mode);
266 }
267
apic_find_highest_isr(struct kvm_lapic * apic)268 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
269 {
270 int result;
271
272 result = find_highest_vector(apic->regs + APIC_ISR);
273 ASSERT(result == -1 || result >= 16);
274
275 return result;
276 }
277
apic_update_ppr(struct kvm_lapic * apic)278 static void apic_update_ppr(struct kvm_lapic *apic)
279 {
280 u32 tpr, isrv, ppr, old_ppr;
281 int isr;
282
283 old_ppr = apic_get_reg(apic, APIC_PROCPRI);
284 tpr = apic_get_reg(apic, APIC_TASKPRI);
285 isr = apic_find_highest_isr(apic);
286 isrv = (isr != -1) ? isr : 0;
287
288 if ((tpr & 0xf0) >= (isrv & 0xf0))
289 ppr = tpr & 0xff;
290 else
291 ppr = isrv & 0xf0;
292
293 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
294 apic, ppr, isr, isrv);
295
296 if (old_ppr != ppr) {
297 apic_set_reg(apic, APIC_PROCPRI, ppr);
298 if (ppr < old_ppr)
299 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
300 }
301 }
302
apic_set_tpr(struct kvm_lapic * apic,u32 tpr)303 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
304 {
305 apic_set_reg(apic, APIC_TASKPRI, tpr);
306 apic_update_ppr(apic);
307 }
308
kvm_apic_match_physical_addr(struct kvm_lapic * apic,u16 dest)309 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
310 {
311 return dest == 0xff || kvm_apic_id(apic) == dest;
312 }
313
kvm_apic_match_logical_addr(struct kvm_lapic * apic,u8 mda)314 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
315 {
316 int result = 0;
317 u32 logical_id;
318
319 if (apic_x2apic_mode(apic)) {
320 logical_id = apic_get_reg(apic, APIC_LDR);
321 return logical_id & mda;
322 }
323
324 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
325
326 switch (apic_get_reg(apic, APIC_DFR)) {
327 case APIC_DFR_FLAT:
328 if (logical_id & mda)
329 result = 1;
330 break;
331 case APIC_DFR_CLUSTER:
332 if (((logical_id >> 4) == (mda >> 0x4))
333 && (logical_id & mda & 0xf))
334 result = 1;
335 break;
336 default:
337 apic_debug("Bad DFR vcpu %d: %08x\n",
338 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
339 break;
340 }
341
342 return result;
343 }
344
kvm_apic_match_dest(struct kvm_vcpu * vcpu,struct kvm_lapic * source,int short_hand,int dest,int dest_mode)345 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
346 int short_hand, int dest, int dest_mode)
347 {
348 int result = 0;
349 struct kvm_lapic *target = vcpu->arch.apic;
350
351 apic_debug("target %p, source %p, dest 0x%x, "
352 "dest_mode 0x%x, short_hand 0x%x\n",
353 target, source, dest, dest_mode, short_hand);
354
355 ASSERT(target);
356 switch (short_hand) {
357 case APIC_DEST_NOSHORT:
358 if (dest_mode == 0)
359 /* Physical mode. */
360 result = kvm_apic_match_physical_addr(target, dest);
361 else
362 /* Logical mode. */
363 result = kvm_apic_match_logical_addr(target, dest);
364 break;
365 case APIC_DEST_SELF:
366 result = (target == source);
367 break;
368 case APIC_DEST_ALLINC:
369 result = 1;
370 break;
371 case APIC_DEST_ALLBUT:
372 result = (target != source);
373 break;
374 default:
375 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
376 short_hand);
377 break;
378 }
379
380 return result;
381 }
382
383 /*
384 * Add a pending IRQ into lapic.
385 * Return 1 if successfully added and 0 if discarded.
386 */
__apic_accept_irq(struct kvm_lapic * apic,int delivery_mode,int vector,int level,int trig_mode)387 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
388 int vector, int level, int trig_mode)
389 {
390 int result = 0;
391 struct kvm_vcpu *vcpu = apic->vcpu;
392
393 switch (delivery_mode) {
394 case APIC_DM_LOWEST:
395 vcpu->arch.apic_arb_prio++;
396 case APIC_DM_FIXED:
397 /* FIXME add logic for vcpu on reset */
398 if (unlikely(!apic_enabled(apic)))
399 break;
400
401 if (trig_mode) {
402 apic_debug("level trig mode for vector %d", vector);
403 apic_set_vector(vector, apic->regs + APIC_TMR);
404 } else
405 apic_clear_vector(vector, apic->regs + APIC_TMR);
406
407 result = !apic_test_and_set_irr(vector, apic);
408 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
409 trig_mode, vector, !result);
410 if (!result) {
411 if (trig_mode)
412 apic_debug("level trig mode repeatedly for "
413 "vector %d", vector);
414 break;
415 }
416
417 kvm_make_request(KVM_REQ_EVENT, vcpu);
418 kvm_vcpu_kick(vcpu);
419 break;
420
421 case APIC_DM_REMRD:
422 apic_debug("Ignoring delivery mode 3\n");
423 break;
424
425 case APIC_DM_SMI:
426 apic_debug("Ignoring guest SMI\n");
427 break;
428
429 case APIC_DM_NMI:
430 result = 1;
431 kvm_inject_nmi(vcpu);
432 kvm_vcpu_kick(vcpu);
433 break;
434
435 case APIC_DM_INIT:
436 if (!trig_mode || level) {
437 result = 1;
438 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
439 kvm_make_request(KVM_REQ_EVENT, vcpu);
440 kvm_vcpu_kick(vcpu);
441 } else {
442 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
443 vcpu->vcpu_id);
444 }
445 break;
446
447 case APIC_DM_STARTUP:
448 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
449 vcpu->vcpu_id, vector);
450 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
451 result = 1;
452 vcpu->arch.sipi_vector = vector;
453 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
454 kvm_make_request(KVM_REQ_EVENT, vcpu);
455 kvm_vcpu_kick(vcpu);
456 }
457 break;
458
459 case APIC_DM_EXTINT:
460 /*
461 * Should only be called by kvm_apic_local_deliver() with LVT0,
462 * before NMI watchdog was enabled. Already handled by
463 * kvm_apic_accept_pic_intr().
464 */
465 break;
466
467 default:
468 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
469 delivery_mode);
470 break;
471 }
472 return result;
473 }
474
kvm_apic_compare_prio(struct kvm_vcpu * vcpu1,struct kvm_vcpu * vcpu2)475 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
476 {
477 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
478 }
479
apic_set_eoi(struct kvm_lapic * apic)480 static void apic_set_eoi(struct kvm_lapic *apic)
481 {
482 int vector = apic_find_highest_isr(apic);
483 int trigger_mode;
484 /*
485 * Not every write EOI will has corresponding ISR,
486 * one example is when Kernel check timer on setup_IO_APIC
487 */
488 if (vector == -1)
489 return;
490
491 apic_clear_vector(vector, apic->regs + APIC_ISR);
492 apic_update_ppr(apic);
493
494 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
495 trigger_mode = IOAPIC_LEVEL_TRIG;
496 else
497 trigger_mode = IOAPIC_EDGE_TRIG;
498 if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI))
499 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
500 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
501 }
502
apic_send_ipi(struct kvm_lapic * apic)503 static void apic_send_ipi(struct kvm_lapic *apic)
504 {
505 u32 icr_low = apic_get_reg(apic, APIC_ICR);
506 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
507 struct kvm_lapic_irq irq;
508
509 irq.vector = icr_low & APIC_VECTOR_MASK;
510 irq.delivery_mode = icr_low & APIC_MODE_MASK;
511 irq.dest_mode = icr_low & APIC_DEST_MASK;
512 irq.level = icr_low & APIC_INT_ASSERT;
513 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
514 irq.shorthand = icr_low & APIC_SHORT_MASK;
515 if (apic_x2apic_mode(apic))
516 irq.dest_id = icr_high;
517 else
518 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
519
520 trace_kvm_apic_ipi(icr_low, irq.dest_id);
521
522 apic_debug("icr_high 0x%x, icr_low 0x%x, "
523 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
524 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
525 icr_high, icr_low, irq.shorthand, irq.dest_id,
526 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
527 irq.vector);
528
529 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
530 }
531
apic_get_tmcct(struct kvm_lapic * apic)532 static u32 apic_get_tmcct(struct kvm_lapic *apic)
533 {
534 ktime_t remaining;
535 s64 ns;
536 u32 tmcct;
537
538 ASSERT(apic != NULL);
539
540 /* if initial count is 0, current count should also be 0 */
541 if (apic_get_reg(apic, APIC_TMICT) == 0 ||
542 apic->lapic_timer.period == 0)
543 return 0;
544
545 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
546 if (ktime_to_ns(remaining) < 0)
547 remaining = ktime_set(0, 0);
548
549 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
550 tmcct = div64_u64(ns,
551 (APIC_BUS_CYCLE_NS * apic->divide_count));
552
553 return tmcct;
554 }
555
__report_tpr_access(struct kvm_lapic * apic,bool write)556 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
557 {
558 struct kvm_vcpu *vcpu = apic->vcpu;
559 struct kvm_run *run = vcpu->run;
560
561 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
562 run->tpr_access.rip = kvm_rip_read(vcpu);
563 run->tpr_access.is_write = write;
564 }
565
report_tpr_access(struct kvm_lapic * apic,bool write)566 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
567 {
568 if (apic->vcpu->arch.tpr_access_reporting)
569 __report_tpr_access(apic, write);
570 }
571
__apic_read(struct kvm_lapic * apic,unsigned int offset)572 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
573 {
574 u32 val = 0;
575
576 if (offset >= LAPIC_MMIO_LENGTH)
577 return 0;
578
579 switch (offset) {
580 case APIC_ID:
581 if (apic_x2apic_mode(apic))
582 val = kvm_apic_id(apic);
583 else
584 val = kvm_apic_id(apic) << 24;
585 break;
586 case APIC_ARBPRI:
587 apic_debug("Access APIC ARBPRI register which is for P6\n");
588 break;
589
590 case APIC_TMCCT: /* Timer CCR */
591 if (apic_lvtt_tscdeadline(apic))
592 return 0;
593
594 val = apic_get_tmcct(apic);
595 break;
596
597 case APIC_TASKPRI:
598 report_tpr_access(apic, false);
599 /* fall thru */
600 default:
601 apic_update_ppr(apic);
602 val = apic_get_reg(apic, offset);
603 break;
604 }
605
606 return val;
607 }
608
to_lapic(struct kvm_io_device * dev)609 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
610 {
611 return container_of(dev, struct kvm_lapic, dev);
612 }
613
apic_reg_read(struct kvm_lapic * apic,u32 offset,int len,void * data)614 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
615 void *data)
616 {
617 unsigned char alignment = offset & 0xf;
618 u32 result;
619 /* this bitmask has a bit cleared for each reserver register */
620 static const u64 rmask = 0x43ff01ffffffe70cULL;
621
622 if ((alignment + len) > 4) {
623 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
624 offset, len);
625 return 1;
626 }
627
628 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
629 apic_debug("KVM_APIC_READ: read reserved register %x\n",
630 offset);
631 return 1;
632 }
633
634 result = __apic_read(apic, offset & ~0xf);
635
636 trace_kvm_apic_read(offset, result);
637
638 switch (len) {
639 case 1:
640 case 2:
641 case 4:
642 memcpy(data, (char *)&result + alignment, len);
643 break;
644 default:
645 printk(KERN_ERR "Local APIC read with len = %x, "
646 "should be 1,2, or 4 instead\n", len);
647 break;
648 }
649 return 0;
650 }
651
apic_mmio_in_range(struct kvm_lapic * apic,gpa_t addr)652 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
653 {
654 return apic_hw_enabled(apic) &&
655 addr >= apic->base_address &&
656 addr < apic->base_address + LAPIC_MMIO_LENGTH;
657 }
658
apic_mmio_read(struct kvm_io_device * this,gpa_t address,int len,void * data)659 static int apic_mmio_read(struct kvm_io_device *this,
660 gpa_t address, int len, void *data)
661 {
662 struct kvm_lapic *apic = to_lapic(this);
663 u32 offset = address - apic->base_address;
664
665 if (!apic_mmio_in_range(apic, address))
666 return -EOPNOTSUPP;
667
668 apic_reg_read(apic, offset, len, data);
669
670 return 0;
671 }
672
update_divide_count(struct kvm_lapic * apic)673 static void update_divide_count(struct kvm_lapic *apic)
674 {
675 u32 tmp1, tmp2, tdcr;
676
677 tdcr = apic_get_reg(apic, APIC_TDCR);
678 tmp1 = tdcr & 0xf;
679 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
680 apic->divide_count = 0x1 << (tmp2 & 0x7);
681
682 apic_debug("timer divide count is 0x%x\n",
683 apic->divide_count);
684 }
685
start_apic_timer(struct kvm_lapic * apic)686 static void start_apic_timer(struct kvm_lapic *apic)
687 {
688 ktime_t now;
689 atomic_set(&apic->lapic_timer.pending, 0);
690
691 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
692 /* lapic timer in oneshot or peroidic mode */
693 now = apic->lapic_timer.timer.base->get_time();
694 apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT)
695 * APIC_BUS_CYCLE_NS * apic->divide_count;
696
697 if (!apic->lapic_timer.period)
698 return;
699 /*
700 * Do not allow the guest to program periodic timers with small
701 * interval, since the hrtimers are not throttled by the host
702 * scheduler.
703 */
704 if (apic_lvtt_period(apic)) {
705 s64 min_period = min_timer_period_us * 1000LL;
706
707 if (apic->lapic_timer.period < min_period) {
708 pr_info_ratelimited(
709 "kvm: vcpu %i: requested %lld ns "
710 "lapic timer period limited to %lld ns\n",
711 apic->vcpu->vcpu_id,
712 apic->lapic_timer.period, min_period);
713 apic->lapic_timer.period = min_period;
714 }
715 }
716
717 hrtimer_start(&apic->lapic_timer.timer,
718 ktime_add_ns(now, apic->lapic_timer.period),
719 HRTIMER_MODE_ABS);
720
721 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
722 PRIx64 ", "
723 "timer initial count 0x%x, period %lldns, "
724 "expire @ 0x%016" PRIx64 ".\n", __func__,
725 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
726 apic_get_reg(apic, APIC_TMICT),
727 apic->lapic_timer.period,
728 ktime_to_ns(ktime_add_ns(now,
729 apic->lapic_timer.period)));
730 } else if (apic_lvtt_tscdeadline(apic)) {
731 /* lapic timer in tsc deadline mode */
732 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
733 u64 ns = 0;
734 struct kvm_vcpu *vcpu = apic->vcpu;
735 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
736 unsigned long flags;
737
738 if (unlikely(!tscdeadline || !this_tsc_khz))
739 return;
740
741 local_irq_save(flags);
742
743 now = apic->lapic_timer.timer.base->get_time();
744 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
745 if (likely(tscdeadline > guest_tsc)) {
746 ns = (tscdeadline - guest_tsc) * 1000000ULL;
747 do_div(ns, this_tsc_khz);
748 }
749 hrtimer_start(&apic->lapic_timer.timer,
750 ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
751
752 local_irq_restore(flags);
753 }
754 }
755
apic_manage_nmi_watchdog(struct kvm_lapic * apic,u32 lvt0_val)756 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
757 {
758 int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
759
760 if (apic_lvt_nmi_mode(lvt0_val)) {
761 if (!nmi_wd_enabled) {
762 apic_debug("Receive NMI setting on APIC_LVT0 "
763 "for cpu %d\n", apic->vcpu->vcpu_id);
764 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
765 }
766 } else if (nmi_wd_enabled)
767 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
768 }
769
apic_reg_write(struct kvm_lapic * apic,u32 reg,u32 val)770 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
771 {
772 int ret = 0;
773
774 trace_kvm_apic_write(reg, val);
775
776 switch (reg) {
777 case APIC_ID: /* Local APIC ID */
778 if (!apic_x2apic_mode(apic))
779 apic_set_reg(apic, APIC_ID, val);
780 else
781 ret = 1;
782 break;
783
784 case APIC_TASKPRI:
785 report_tpr_access(apic, true);
786 apic_set_tpr(apic, val & 0xff);
787 break;
788
789 case APIC_EOI:
790 apic_set_eoi(apic);
791 break;
792
793 case APIC_LDR:
794 if (!apic_x2apic_mode(apic))
795 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
796 else
797 ret = 1;
798 break;
799
800 case APIC_DFR:
801 if (!apic_x2apic_mode(apic))
802 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
803 else
804 ret = 1;
805 break;
806
807 case APIC_SPIV: {
808 u32 mask = 0x3ff;
809 if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
810 mask |= APIC_SPIV_DIRECTED_EOI;
811 apic_set_reg(apic, APIC_SPIV, val & mask);
812 if (!(val & APIC_SPIV_APIC_ENABLED)) {
813 int i;
814 u32 lvt_val;
815
816 for (i = 0; i < APIC_LVT_NUM; i++) {
817 lvt_val = apic_get_reg(apic,
818 APIC_LVTT + 0x10 * i);
819 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
820 lvt_val | APIC_LVT_MASKED);
821 }
822 atomic_set(&apic->lapic_timer.pending, 0);
823
824 }
825 break;
826 }
827 case APIC_ICR:
828 /* No delay here, so we always clear the pending bit */
829 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
830 apic_send_ipi(apic);
831 break;
832
833 case APIC_ICR2:
834 if (!apic_x2apic_mode(apic))
835 val &= 0xff000000;
836 apic_set_reg(apic, APIC_ICR2, val);
837 break;
838
839 case APIC_LVT0:
840 apic_manage_nmi_watchdog(apic, val);
841 case APIC_LVTTHMR:
842 case APIC_LVTPC:
843 case APIC_LVT1:
844 case APIC_LVTERR:
845 /* TODO: Check vector */
846 if (!apic_sw_enabled(apic))
847 val |= APIC_LVT_MASKED;
848
849 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
850 apic_set_reg(apic, reg, val);
851
852 break;
853
854 case APIC_LVTT:
855 if ((apic_get_reg(apic, APIC_LVTT) &
856 apic->lapic_timer.timer_mode_mask) !=
857 (val & apic->lapic_timer.timer_mode_mask))
858 hrtimer_cancel(&apic->lapic_timer.timer);
859
860 if (!apic_sw_enabled(apic))
861 val |= APIC_LVT_MASKED;
862 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
863 apic_set_reg(apic, APIC_LVTT, val);
864 break;
865
866 case APIC_TMICT:
867 if (apic_lvtt_tscdeadline(apic))
868 break;
869
870 hrtimer_cancel(&apic->lapic_timer.timer);
871 apic_set_reg(apic, APIC_TMICT, val);
872 start_apic_timer(apic);
873 break;
874
875 case APIC_TDCR:
876 if (val & 4)
877 apic_debug("KVM_WRITE:TDCR %x\n", val);
878 apic_set_reg(apic, APIC_TDCR, val);
879 update_divide_count(apic);
880 break;
881
882 case APIC_ESR:
883 if (apic_x2apic_mode(apic) && val != 0) {
884 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
885 ret = 1;
886 }
887 break;
888
889 case APIC_SELF_IPI:
890 if (apic_x2apic_mode(apic)) {
891 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
892 } else
893 ret = 1;
894 break;
895 default:
896 ret = 1;
897 break;
898 }
899 if (ret)
900 apic_debug("Local APIC Write to read-only register %x\n", reg);
901 return ret;
902 }
903
apic_mmio_write(struct kvm_io_device * this,gpa_t address,int len,const void * data)904 static int apic_mmio_write(struct kvm_io_device *this,
905 gpa_t address, int len, const void *data)
906 {
907 struct kvm_lapic *apic = to_lapic(this);
908 unsigned int offset = address - apic->base_address;
909 u32 val;
910
911 if (!apic_mmio_in_range(apic, address))
912 return -EOPNOTSUPP;
913
914 /*
915 * APIC register must be aligned on 128-bits boundary.
916 * 32/64/128 bits registers must be accessed thru 32 bits.
917 * Refer SDM 8.4.1
918 */
919 if (len != 4 || (offset & 0xf)) {
920 /* Don't shout loud, $infamous_os would cause only noise. */
921 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
922 return 0;
923 }
924
925 val = *(u32*)data;
926
927 /* too common printing */
928 if (offset != APIC_EOI)
929 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
930 "0x%x\n", __func__, offset, len, val);
931
932 apic_reg_write(apic, offset & 0xff0, val);
933
934 return 0;
935 }
936
kvm_lapic_set_eoi(struct kvm_vcpu * vcpu)937 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
938 {
939 struct kvm_lapic *apic = vcpu->arch.apic;
940
941 if (apic)
942 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
943 }
944 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
945
kvm_free_lapic(struct kvm_vcpu * vcpu)946 void kvm_free_lapic(struct kvm_vcpu *vcpu)
947 {
948 if (!vcpu->arch.apic)
949 return;
950
951 hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
952
953 if (vcpu->arch.apic->regs)
954 free_page((unsigned long)vcpu->arch.apic->regs);
955
956 kfree(vcpu->arch.apic);
957 }
958
959 /*
960 *----------------------------------------------------------------------
961 * LAPIC interface
962 *----------------------------------------------------------------------
963 */
964
kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu * vcpu)965 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
966 {
967 struct kvm_lapic *apic = vcpu->arch.apic;
968 if (!apic)
969 return 0;
970
971 if (apic_lvtt_oneshot(apic) || apic_lvtt_period(apic))
972 return 0;
973
974 return apic->lapic_timer.tscdeadline;
975 }
976
kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu * vcpu,u64 data)977 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
978 {
979 struct kvm_lapic *apic = vcpu->arch.apic;
980 if (!apic)
981 return;
982
983 if (apic_lvtt_oneshot(apic) || apic_lvtt_period(apic))
984 return;
985
986 hrtimer_cancel(&apic->lapic_timer.timer);
987 apic->lapic_timer.tscdeadline = data;
988 start_apic_timer(apic);
989 }
990
kvm_lapic_set_tpr(struct kvm_vcpu * vcpu,unsigned long cr8)991 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
992 {
993 struct kvm_lapic *apic = vcpu->arch.apic;
994
995 if (!apic)
996 return;
997 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
998 | (apic_get_reg(apic, APIC_TASKPRI) & 4));
999 }
1000
kvm_lapic_get_cr8(struct kvm_vcpu * vcpu)1001 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1002 {
1003 struct kvm_lapic *apic = vcpu->arch.apic;
1004 u64 tpr;
1005
1006 if (!apic)
1007 return 0;
1008 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
1009
1010 return (tpr & 0xf0) >> 4;
1011 }
1012
kvm_lapic_set_base(struct kvm_vcpu * vcpu,u64 value)1013 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1014 {
1015 struct kvm_lapic *apic = vcpu->arch.apic;
1016
1017 if (!apic) {
1018 value |= MSR_IA32_APICBASE_BSP;
1019 vcpu->arch.apic_base = value;
1020 return;
1021 }
1022
1023 if (!kvm_vcpu_is_bsp(apic->vcpu))
1024 value &= ~MSR_IA32_APICBASE_BSP;
1025
1026 vcpu->arch.apic_base = value;
1027 if (apic_x2apic_mode(apic)) {
1028 u32 id = kvm_apic_id(apic);
1029 u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf));
1030 apic_set_reg(apic, APIC_LDR, ldr);
1031 }
1032 apic->base_address = apic->vcpu->arch.apic_base &
1033 MSR_IA32_APICBASE_BASE;
1034
1035 /* with FSB delivery interrupt, we can restart APIC functionality */
1036 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1037 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1038
1039 }
1040
kvm_lapic_reset(struct kvm_vcpu * vcpu)1041 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1042 {
1043 struct kvm_lapic *apic;
1044 int i;
1045
1046 apic_debug("%s\n", __func__);
1047
1048 ASSERT(vcpu);
1049 apic = vcpu->arch.apic;
1050 ASSERT(apic != NULL);
1051
1052 /* Stop the timer in case it's a reset to an active apic */
1053 hrtimer_cancel(&apic->lapic_timer.timer);
1054
1055 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
1056 kvm_apic_set_version(apic->vcpu);
1057
1058 for (i = 0; i < APIC_LVT_NUM; i++)
1059 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1060 apic_set_reg(apic, APIC_LVT0,
1061 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1062
1063 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1064 apic_set_reg(apic, APIC_SPIV, 0xff);
1065 apic_set_reg(apic, APIC_TASKPRI, 0);
1066 apic_set_reg(apic, APIC_LDR, 0);
1067 apic_set_reg(apic, APIC_ESR, 0);
1068 apic_set_reg(apic, APIC_ICR, 0);
1069 apic_set_reg(apic, APIC_ICR2, 0);
1070 apic_set_reg(apic, APIC_TDCR, 0);
1071 apic_set_reg(apic, APIC_TMICT, 0);
1072 for (i = 0; i < 8; i++) {
1073 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1074 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1075 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1076 }
1077 apic->irr_pending = false;
1078 update_divide_count(apic);
1079 atomic_set(&apic->lapic_timer.pending, 0);
1080 if (kvm_vcpu_is_bsp(vcpu))
1081 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
1082 apic_update_ppr(apic);
1083
1084 vcpu->arch.apic_arb_prio = 0;
1085
1086 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
1087 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1088 vcpu, kvm_apic_id(apic),
1089 vcpu->arch.apic_base, apic->base_address);
1090 }
1091
kvm_apic_present(struct kvm_vcpu * vcpu)1092 bool kvm_apic_present(struct kvm_vcpu *vcpu)
1093 {
1094 return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
1095 }
1096
kvm_lapic_enabled(struct kvm_vcpu * vcpu)1097 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
1098 {
1099 return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
1100 }
1101
1102 /*
1103 *----------------------------------------------------------------------
1104 * timer interface
1105 *----------------------------------------------------------------------
1106 */
1107
lapic_is_periodic(struct kvm_timer * ktimer)1108 static bool lapic_is_periodic(struct kvm_timer *ktimer)
1109 {
1110 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
1111 lapic_timer);
1112 return apic_lvtt_period(apic);
1113 }
1114
apic_has_pending_timer(struct kvm_vcpu * vcpu)1115 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1116 {
1117 struct kvm_lapic *lapic = vcpu->arch.apic;
1118
1119 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
1120 return atomic_read(&lapic->lapic_timer.pending);
1121
1122 return 0;
1123 }
1124
kvm_apic_local_deliver(struct kvm_lapic * apic,int lvt_type)1125 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1126 {
1127 u32 reg = apic_get_reg(apic, lvt_type);
1128 int vector, mode, trig_mode;
1129
1130 if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1131 vector = reg & APIC_VECTOR_MASK;
1132 mode = reg & APIC_MODE_MASK;
1133 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1134 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
1135 }
1136 return 0;
1137 }
1138
kvm_apic_nmi_wd_deliver(struct kvm_vcpu * vcpu)1139 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1140 {
1141 struct kvm_lapic *apic = vcpu->arch.apic;
1142
1143 if (apic)
1144 kvm_apic_local_deliver(apic, APIC_LVT0);
1145 }
1146
1147 static struct kvm_timer_ops lapic_timer_ops = {
1148 .is_periodic = lapic_is_periodic,
1149 };
1150
1151 static const struct kvm_io_device_ops apic_mmio_ops = {
1152 .read = apic_mmio_read,
1153 .write = apic_mmio_write,
1154 };
1155
kvm_create_lapic(struct kvm_vcpu * vcpu)1156 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1157 {
1158 struct kvm_lapic *apic;
1159
1160 ASSERT(vcpu != NULL);
1161 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1162
1163 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1164 if (!apic)
1165 goto nomem;
1166
1167 vcpu->arch.apic = apic;
1168
1169 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1170 if (!apic->regs) {
1171 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1172 vcpu->vcpu_id);
1173 goto nomem_free_apic;
1174 }
1175 apic->vcpu = vcpu;
1176
1177 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1178 HRTIMER_MODE_ABS);
1179 apic->lapic_timer.timer.function = kvm_timer_fn;
1180 apic->lapic_timer.t_ops = &lapic_timer_ops;
1181 apic->lapic_timer.kvm = vcpu->kvm;
1182 apic->lapic_timer.vcpu = vcpu;
1183
1184 apic->base_address = APIC_DEFAULT_PHYS_BASE;
1185 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
1186
1187 kvm_lapic_reset(vcpu);
1188 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1189
1190 return 0;
1191 nomem_free_apic:
1192 kfree(apic);
1193 nomem:
1194 return -ENOMEM;
1195 }
1196
kvm_apic_has_interrupt(struct kvm_vcpu * vcpu)1197 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1198 {
1199 struct kvm_lapic *apic = vcpu->arch.apic;
1200 int highest_irr;
1201
1202 if (!apic || !apic_enabled(apic))
1203 return -1;
1204
1205 apic_update_ppr(apic);
1206 highest_irr = apic_find_highest_irr(apic);
1207 if ((highest_irr == -1) ||
1208 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1209 return -1;
1210 return highest_irr;
1211 }
1212
kvm_apic_accept_pic_intr(struct kvm_vcpu * vcpu)1213 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1214 {
1215 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1216 int r = 0;
1217
1218 if (!apic_hw_enabled(vcpu->arch.apic))
1219 r = 1;
1220 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1221 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1222 r = 1;
1223 return r;
1224 }
1225
kvm_inject_apic_timer_irqs(struct kvm_vcpu * vcpu)1226 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1227 {
1228 struct kvm_lapic *apic = vcpu->arch.apic;
1229
1230 if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1231 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1232 atomic_dec(&apic->lapic_timer.pending);
1233 }
1234 }
1235
kvm_get_apic_interrupt(struct kvm_vcpu * vcpu)1236 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1237 {
1238 int vector = kvm_apic_has_interrupt(vcpu);
1239 struct kvm_lapic *apic = vcpu->arch.apic;
1240
1241 if (vector == -1)
1242 return -1;
1243
1244 apic_set_vector(vector, apic->regs + APIC_ISR);
1245 apic_update_ppr(apic);
1246 apic_clear_irr(vector, apic);
1247 return vector;
1248 }
1249
kvm_apic_post_state_restore(struct kvm_vcpu * vcpu)1250 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1251 {
1252 struct kvm_lapic *apic = vcpu->arch.apic;
1253
1254 apic->base_address = vcpu->arch.apic_base &
1255 MSR_IA32_APICBASE_BASE;
1256 kvm_apic_set_version(vcpu);
1257
1258 apic_update_ppr(apic);
1259 hrtimer_cancel(&apic->lapic_timer.timer);
1260 update_divide_count(apic);
1261 start_apic_timer(apic);
1262 apic->irr_pending = true;
1263 kvm_make_request(KVM_REQ_EVENT, vcpu);
1264 }
1265
__kvm_migrate_apic_timer(struct kvm_vcpu * vcpu)1266 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1267 {
1268 struct kvm_lapic *apic = vcpu->arch.apic;
1269 struct hrtimer *timer;
1270
1271 if (!apic)
1272 return;
1273
1274 timer = &apic->lapic_timer.timer;
1275 if (hrtimer_cancel(timer))
1276 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1277 }
1278
kvm_lapic_sync_from_vapic(struct kvm_vcpu * vcpu)1279 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1280 {
1281 u32 data;
1282
1283 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1284 return;
1285
1286 kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1287 sizeof(u32));
1288
1289 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1290 }
1291
kvm_lapic_sync_to_vapic(struct kvm_vcpu * vcpu)1292 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1293 {
1294 u32 data, tpr;
1295 int max_irr, max_isr;
1296 struct kvm_lapic *apic;
1297
1298 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1299 return;
1300
1301 apic = vcpu->arch.apic;
1302 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1303 max_irr = apic_find_highest_irr(apic);
1304 if (max_irr < 0)
1305 max_irr = 0;
1306 max_isr = apic_find_highest_isr(apic);
1307 if (max_isr < 0)
1308 max_isr = 0;
1309 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1310
1311 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1312 sizeof(u32));
1313 }
1314
kvm_lapic_set_vapic_addr(struct kvm_vcpu * vcpu,gpa_t vapic_addr)1315 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1316 {
1317 if (!irqchip_in_kernel(vcpu->kvm))
1318 return -EINVAL;
1319
1320 if (vapic_addr) {
1321 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1322 &vcpu->arch.apic->vapic_cache,
1323 vapic_addr, sizeof(u32)))
1324 return -EINVAL;
1325 }
1326
1327 vcpu->arch.apic->vapic_addr = vapic_addr;
1328 return 0;
1329 }
1330
kvm_x2apic_msr_write(struct kvm_vcpu * vcpu,u32 msr,u64 data)1331 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1332 {
1333 struct kvm_lapic *apic = vcpu->arch.apic;
1334 u32 reg = (msr - APIC_BASE_MSR) << 4;
1335
1336 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1337 return 1;
1338
1339 /* if this is ICR write vector before command */
1340 if (msr == 0x830)
1341 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1342 return apic_reg_write(apic, reg, (u32)data);
1343 }
1344
kvm_x2apic_msr_read(struct kvm_vcpu * vcpu,u32 msr,u64 * data)1345 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1346 {
1347 struct kvm_lapic *apic = vcpu->arch.apic;
1348 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1349
1350 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1351 return 1;
1352
1353 if (apic_reg_read(apic, reg, 4, &low))
1354 return 1;
1355 if (msr == 0x830)
1356 apic_reg_read(apic, APIC_ICR2, 4, &high);
1357
1358 *data = (((u64)high) << 32) | low;
1359
1360 return 0;
1361 }
1362
kvm_hv_vapic_msr_write(struct kvm_vcpu * vcpu,u32 reg,u64 data)1363 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1364 {
1365 struct kvm_lapic *apic = vcpu->arch.apic;
1366
1367 if (!irqchip_in_kernel(vcpu->kvm))
1368 return 1;
1369
1370 /* if this is ICR write vector before command */
1371 if (reg == APIC_ICR)
1372 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1373 return apic_reg_write(apic, reg, (u32)data);
1374 }
1375
kvm_hv_vapic_msr_read(struct kvm_vcpu * vcpu,u32 reg,u64 * data)1376 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1377 {
1378 struct kvm_lapic *apic = vcpu->arch.apic;
1379 u32 low, high = 0;
1380
1381 if (!irqchip_in_kernel(vcpu->kvm))
1382 return 1;
1383
1384 if (apic_reg_read(apic, reg, 4, &low))
1385 return 1;
1386 if (reg == APIC_ICR)
1387 apic_reg_read(apic, APIC_ICR2, 4, &high);
1388
1389 *data = (((u64)high) << 32) | low;
1390
1391 return 0;
1392 }
1393