1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Microchip switch driver main logic
4 *
5 * Copyright (C) 2017-2019 Microchip Technology Inc.
6 */
7
8 #include <linux/delay.h>
9 #include <linux/export.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/platform_data/microchip-ksz.h>
14 #include <linux/phy.h>
15 #include <linux/etherdevice.h>
16 #include <linux/if_bridge.h>
17 #include <linux/irq.h>
18 #include <linux/irqdomain.h>
19 #include <linux/of_mdio.h>
20 #include <linux/of_device.h>
21 #include <linux/of_net.h>
22 #include <linux/micrel_phy.h>
23 #include <net/dsa.h>
24 #include <net/switchdev.h>
25
26 #include "ksz_common.h"
27 #include "ksz8.h"
28 #include "ksz9477.h"
29 #include "lan937x.h"
30
31 #define MIB_COUNTER_NUM 0x20
32
33 struct ksz_stats_raw {
34 u64 rx_hi;
35 u64 rx_undersize;
36 u64 rx_fragments;
37 u64 rx_oversize;
38 u64 rx_jabbers;
39 u64 rx_symbol_err;
40 u64 rx_crc_err;
41 u64 rx_align_err;
42 u64 rx_mac_ctrl;
43 u64 rx_pause;
44 u64 rx_bcast;
45 u64 rx_mcast;
46 u64 rx_ucast;
47 u64 rx_64_or_less;
48 u64 rx_65_127;
49 u64 rx_128_255;
50 u64 rx_256_511;
51 u64 rx_512_1023;
52 u64 rx_1024_1522;
53 u64 rx_1523_2000;
54 u64 rx_2001;
55 u64 tx_hi;
56 u64 tx_late_col;
57 u64 tx_pause;
58 u64 tx_bcast;
59 u64 tx_mcast;
60 u64 tx_ucast;
61 u64 tx_deferred;
62 u64 tx_total_col;
63 u64 tx_exc_col;
64 u64 tx_single_col;
65 u64 tx_mult_col;
66 u64 rx_total;
67 u64 tx_total;
68 u64 rx_discards;
69 u64 tx_discards;
70 };
71
72 static const struct ksz_mib_names ksz88xx_mib_names[] = {
73 { 0x00, "rx" },
74 { 0x01, "rx_hi" },
75 { 0x02, "rx_undersize" },
76 { 0x03, "rx_fragments" },
77 { 0x04, "rx_oversize" },
78 { 0x05, "rx_jabbers" },
79 { 0x06, "rx_symbol_err" },
80 { 0x07, "rx_crc_err" },
81 { 0x08, "rx_align_err" },
82 { 0x09, "rx_mac_ctrl" },
83 { 0x0a, "rx_pause" },
84 { 0x0b, "rx_bcast" },
85 { 0x0c, "rx_mcast" },
86 { 0x0d, "rx_ucast" },
87 { 0x0e, "rx_64_or_less" },
88 { 0x0f, "rx_65_127" },
89 { 0x10, "rx_128_255" },
90 { 0x11, "rx_256_511" },
91 { 0x12, "rx_512_1023" },
92 { 0x13, "rx_1024_1522" },
93 { 0x14, "tx" },
94 { 0x15, "tx_hi" },
95 { 0x16, "tx_late_col" },
96 { 0x17, "tx_pause" },
97 { 0x18, "tx_bcast" },
98 { 0x19, "tx_mcast" },
99 { 0x1a, "tx_ucast" },
100 { 0x1b, "tx_deferred" },
101 { 0x1c, "tx_total_col" },
102 { 0x1d, "tx_exc_col" },
103 { 0x1e, "tx_single_col" },
104 { 0x1f, "tx_mult_col" },
105 { 0x100, "rx_discards" },
106 { 0x101, "tx_discards" },
107 };
108
109 static const struct ksz_mib_names ksz9477_mib_names[] = {
110 { 0x00, "rx_hi" },
111 { 0x01, "rx_undersize" },
112 { 0x02, "rx_fragments" },
113 { 0x03, "rx_oversize" },
114 { 0x04, "rx_jabbers" },
115 { 0x05, "rx_symbol_err" },
116 { 0x06, "rx_crc_err" },
117 { 0x07, "rx_align_err" },
118 { 0x08, "rx_mac_ctrl" },
119 { 0x09, "rx_pause" },
120 { 0x0A, "rx_bcast" },
121 { 0x0B, "rx_mcast" },
122 { 0x0C, "rx_ucast" },
123 { 0x0D, "rx_64_or_less" },
124 { 0x0E, "rx_65_127" },
125 { 0x0F, "rx_128_255" },
126 { 0x10, "rx_256_511" },
127 { 0x11, "rx_512_1023" },
128 { 0x12, "rx_1024_1522" },
129 { 0x13, "rx_1523_2000" },
130 { 0x14, "rx_2001" },
131 { 0x15, "tx_hi" },
132 { 0x16, "tx_late_col" },
133 { 0x17, "tx_pause" },
134 { 0x18, "tx_bcast" },
135 { 0x19, "tx_mcast" },
136 { 0x1A, "tx_ucast" },
137 { 0x1B, "tx_deferred" },
138 { 0x1C, "tx_total_col" },
139 { 0x1D, "tx_exc_col" },
140 { 0x1E, "tx_single_col" },
141 { 0x1F, "tx_mult_col" },
142 { 0x80, "rx_total" },
143 { 0x81, "tx_total" },
144 { 0x82, "rx_discards" },
145 { 0x83, "tx_discards" },
146 };
147
148 static const struct ksz_dev_ops ksz8_dev_ops = {
149 .setup = ksz8_setup,
150 .get_port_addr = ksz8_get_port_addr,
151 .cfg_port_member = ksz8_cfg_port_member,
152 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
153 .port_setup = ksz8_port_setup,
154 .r_phy = ksz8_r_phy,
155 .w_phy = ksz8_w_phy,
156 .r_mib_cnt = ksz8_r_mib_cnt,
157 .r_mib_pkt = ksz8_r_mib_pkt,
158 .freeze_mib = ksz8_freeze_mib,
159 .port_init_cnt = ksz8_port_init_cnt,
160 .fdb_dump = ksz8_fdb_dump,
161 .mdb_add = ksz8_mdb_add,
162 .mdb_del = ksz8_mdb_del,
163 .vlan_filtering = ksz8_port_vlan_filtering,
164 .vlan_add = ksz8_port_vlan_add,
165 .vlan_del = ksz8_port_vlan_del,
166 .mirror_add = ksz8_port_mirror_add,
167 .mirror_del = ksz8_port_mirror_del,
168 .get_caps = ksz8_get_caps,
169 .config_cpu_port = ksz8_config_cpu_port,
170 .enable_stp_addr = ksz8_enable_stp_addr,
171 .reset = ksz8_reset_switch,
172 .init = ksz8_switch_init,
173 .exit = ksz8_switch_exit,
174 };
175
176 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port,
177 unsigned int mode,
178 phy_interface_t interface,
179 struct phy_device *phydev, int speed,
180 int duplex, bool tx_pause,
181 bool rx_pause);
182
183 static const struct ksz_dev_ops ksz9477_dev_ops = {
184 .setup = ksz9477_setup,
185 .get_port_addr = ksz9477_get_port_addr,
186 .cfg_port_member = ksz9477_cfg_port_member,
187 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
188 .port_setup = ksz9477_port_setup,
189 .set_ageing_time = ksz9477_set_ageing_time,
190 .r_phy = ksz9477_r_phy,
191 .w_phy = ksz9477_w_phy,
192 .r_mib_cnt = ksz9477_r_mib_cnt,
193 .r_mib_pkt = ksz9477_r_mib_pkt,
194 .r_mib_stat64 = ksz_r_mib_stats64,
195 .freeze_mib = ksz9477_freeze_mib,
196 .port_init_cnt = ksz9477_port_init_cnt,
197 .vlan_filtering = ksz9477_port_vlan_filtering,
198 .vlan_add = ksz9477_port_vlan_add,
199 .vlan_del = ksz9477_port_vlan_del,
200 .mirror_add = ksz9477_port_mirror_add,
201 .mirror_del = ksz9477_port_mirror_del,
202 .get_caps = ksz9477_get_caps,
203 .fdb_dump = ksz9477_fdb_dump,
204 .fdb_add = ksz9477_fdb_add,
205 .fdb_del = ksz9477_fdb_del,
206 .mdb_add = ksz9477_mdb_add,
207 .mdb_del = ksz9477_mdb_del,
208 .change_mtu = ksz9477_change_mtu,
209 .max_mtu = ksz9477_max_mtu,
210 .phylink_mac_link_up = ksz9477_phylink_mac_link_up,
211 .config_cpu_port = ksz9477_config_cpu_port,
212 .enable_stp_addr = ksz9477_enable_stp_addr,
213 .reset = ksz9477_reset_switch,
214 .init = ksz9477_switch_init,
215 .exit = ksz9477_switch_exit,
216 };
217
218 static const struct ksz_dev_ops lan937x_dev_ops = {
219 .setup = lan937x_setup,
220 .teardown = lan937x_teardown,
221 .get_port_addr = ksz9477_get_port_addr,
222 .cfg_port_member = ksz9477_cfg_port_member,
223 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
224 .port_setup = lan937x_port_setup,
225 .set_ageing_time = lan937x_set_ageing_time,
226 .r_phy = lan937x_r_phy,
227 .w_phy = lan937x_w_phy,
228 .r_mib_cnt = ksz9477_r_mib_cnt,
229 .r_mib_pkt = ksz9477_r_mib_pkt,
230 .r_mib_stat64 = ksz_r_mib_stats64,
231 .freeze_mib = ksz9477_freeze_mib,
232 .port_init_cnt = ksz9477_port_init_cnt,
233 .vlan_filtering = ksz9477_port_vlan_filtering,
234 .vlan_add = ksz9477_port_vlan_add,
235 .vlan_del = ksz9477_port_vlan_del,
236 .mirror_add = ksz9477_port_mirror_add,
237 .mirror_del = ksz9477_port_mirror_del,
238 .get_caps = lan937x_phylink_get_caps,
239 .setup_rgmii_delay = lan937x_setup_rgmii_delay,
240 .fdb_dump = ksz9477_fdb_dump,
241 .fdb_add = ksz9477_fdb_add,
242 .fdb_del = ksz9477_fdb_del,
243 .mdb_add = ksz9477_mdb_add,
244 .mdb_del = ksz9477_mdb_del,
245 .change_mtu = lan937x_change_mtu,
246 .max_mtu = ksz9477_max_mtu,
247 .phylink_mac_link_up = ksz9477_phylink_mac_link_up,
248 .config_cpu_port = lan937x_config_cpu_port,
249 .enable_stp_addr = ksz9477_enable_stp_addr,
250 .reset = lan937x_reset_switch,
251 .init = lan937x_switch_init,
252 .exit = lan937x_switch_exit,
253 };
254
255 static const u16 ksz8795_regs[] = {
256 [REG_IND_CTRL_0] = 0x6E,
257 [REG_IND_DATA_8] = 0x70,
258 [REG_IND_DATA_CHECK] = 0x72,
259 [REG_IND_DATA_HI] = 0x71,
260 [REG_IND_DATA_LO] = 0x75,
261 [REG_IND_MIB_CHECK] = 0x74,
262 [REG_IND_BYTE] = 0xA0,
263 [P_FORCE_CTRL] = 0x0C,
264 [P_LINK_STATUS] = 0x0E,
265 [P_LOCAL_CTRL] = 0x07,
266 [P_NEG_RESTART_CTRL] = 0x0D,
267 [P_REMOTE_STATUS] = 0x08,
268 [P_SPEED_STATUS] = 0x09,
269 [S_TAIL_TAG_CTRL] = 0x0C,
270 [P_STP_CTRL] = 0x02,
271 [S_START_CTRL] = 0x01,
272 [S_BROADCAST_CTRL] = 0x06,
273 [S_MULTICAST_CTRL] = 0x04,
274 [P_XMII_CTRL_0] = 0x06,
275 [P_XMII_CTRL_1] = 0x56,
276 };
277
278 static const u32 ksz8795_masks[] = {
279 [PORT_802_1P_REMAPPING] = BIT(7),
280 [SW_TAIL_TAG_ENABLE] = BIT(1),
281 [MIB_COUNTER_OVERFLOW] = BIT(6),
282 [MIB_COUNTER_VALID] = BIT(5),
283 [VLAN_TABLE_FID] = GENMASK(6, 0),
284 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
285 [VLAN_TABLE_VALID] = BIT(12),
286 [STATIC_MAC_TABLE_VALID] = BIT(21),
287 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
288 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
289 [STATIC_MAC_TABLE_OVERRIDE] = BIT(26),
290 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(24, 20),
291 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
292 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(8),
293 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
294 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
295 [DYNAMIC_MAC_TABLE_FID] = GENMASK(26, 20),
296 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
297 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
298 [P_MII_TX_FLOW_CTRL] = BIT(5),
299 [P_MII_RX_FLOW_CTRL] = BIT(5),
300 };
301
302 static const u8 ksz8795_xmii_ctrl0[] = {
303 [P_MII_100MBIT] = 0,
304 [P_MII_10MBIT] = 1,
305 [P_MII_FULL_DUPLEX] = 0,
306 [P_MII_HALF_DUPLEX] = 1,
307 };
308
309 static const u8 ksz8795_xmii_ctrl1[] = {
310 [P_RGMII_SEL] = 3,
311 [P_GMII_SEL] = 2,
312 [P_RMII_SEL] = 1,
313 [P_MII_SEL] = 0,
314 [P_GMII_1GBIT] = 1,
315 [P_GMII_NOT_1GBIT] = 0,
316 };
317
318 static const u8 ksz8795_shifts[] = {
319 [VLAN_TABLE_MEMBERSHIP_S] = 7,
320 [VLAN_TABLE] = 16,
321 [STATIC_MAC_FWD_PORTS] = 16,
322 [STATIC_MAC_FID] = 24,
323 [DYNAMIC_MAC_ENTRIES_H] = 3,
324 [DYNAMIC_MAC_ENTRIES] = 29,
325 [DYNAMIC_MAC_FID] = 16,
326 [DYNAMIC_MAC_TIMESTAMP] = 27,
327 [DYNAMIC_MAC_SRC_PORT] = 24,
328 };
329
330 static const u16 ksz8863_regs[] = {
331 [REG_IND_CTRL_0] = 0x79,
332 [REG_IND_DATA_8] = 0x7B,
333 [REG_IND_DATA_CHECK] = 0x7B,
334 [REG_IND_DATA_HI] = 0x7C,
335 [REG_IND_DATA_LO] = 0x80,
336 [REG_IND_MIB_CHECK] = 0x80,
337 [P_FORCE_CTRL] = 0x0C,
338 [P_LINK_STATUS] = 0x0E,
339 [P_LOCAL_CTRL] = 0x0C,
340 [P_NEG_RESTART_CTRL] = 0x0D,
341 [P_REMOTE_STATUS] = 0x0E,
342 [P_SPEED_STATUS] = 0x0F,
343 [S_TAIL_TAG_CTRL] = 0x03,
344 [P_STP_CTRL] = 0x02,
345 [S_START_CTRL] = 0x01,
346 [S_BROADCAST_CTRL] = 0x06,
347 [S_MULTICAST_CTRL] = 0x04,
348 };
349
350 static const u32 ksz8863_masks[] = {
351 [PORT_802_1P_REMAPPING] = BIT(3),
352 [SW_TAIL_TAG_ENABLE] = BIT(6),
353 [MIB_COUNTER_OVERFLOW] = BIT(7),
354 [MIB_COUNTER_VALID] = BIT(6),
355 [VLAN_TABLE_FID] = GENMASK(15, 12),
356 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
357 [VLAN_TABLE_VALID] = BIT(19),
358 [STATIC_MAC_TABLE_VALID] = BIT(19),
359 [STATIC_MAC_TABLE_USE_FID] = BIT(21),
360 [STATIC_MAC_TABLE_FID] = GENMASK(29, 26),
361 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
362 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
363 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(5, 0),
364 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
365 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
366 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 28),
367 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
368 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
369 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
370 };
371
372 static u8 ksz8863_shifts[] = {
373 [VLAN_TABLE_MEMBERSHIP_S] = 16,
374 [STATIC_MAC_FWD_PORTS] = 16,
375 [STATIC_MAC_FID] = 22,
376 [DYNAMIC_MAC_ENTRIES_H] = 3,
377 [DYNAMIC_MAC_ENTRIES] = 24,
378 [DYNAMIC_MAC_FID] = 16,
379 [DYNAMIC_MAC_TIMESTAMP] = 24,
380 [DYNAMIC_MAC_SRC_PORT] = 20,
381 };
382
383 static const u16 ksz9477_regs[] = {
384 [P_STP_CTRL] = 0x0B04,
385 [S_START_CTRL] = 0x0300,
386 [S_BROADCAST_CTRL] = 0x0332,
387 [S_MULTICAST_CTRL] = 0x0331,
388 [P_XMII_CTRL_0] = 0x0300,
389 [P_XMII_CTRL_1] = 0x0301,
390 };
391
392 static const u32 ksz9477_masks[] = {
393 [ALU_STAT_WRITE] = 0,
394 [ALU_STAT_READ] = 1,
395 [P_MII_TX_FLOW_CTRL] = BIT(5),
396 [P_MII_RX_FLOW_CTRL] = BIT(3),
397 };
398
399 static const u8 ksz9477_shifts[] = {
400 [ALU_STAT_INDEX] = 16,
401 };
402
403 static const u8 ksz9477_xmii_ctrl0[] = {
404 [P_MII_100MBIT] = 1,
405 [P_MII_10MBIT] = 0,
406 [P_MII_FULL_DUPLEX] = 1,
407 [P_MII_HALF_DUPLEX] = 0,
408 };
409
410 static const u8 ksz9477_xmii_ctrl1[] = {
411 [P_RGMII_SEL] = 0,
412 [P_RMII_SEL] = 1,
413 [P_GMII_SEL] = 2,
414 [P_MII_SEL] = 3,
415 [P_GMII_1GBIT] = 0,
416 [P_GMII_NOT_1GBIT] = 1,
417 };
418
419 static const u32 lan937x_masks[] = {
420 [ALU_STAT_WRITE] = 1,
421 [ALU_STAT_READ] = 2,
422 [P_MII_TX_FLOW_CTRL] = BIT(5),
423 [P_MII_RX_FLOW_CTRL] = BIT(3),
424 };
425
426 static const u8 lan937x_shifts[] = {
427 [ALU_STAT_INDEX] = 8,
428 };
429
430 static const struct regmap_range ksz8563_valid_regs[] = {
431 regmap_reg_range(0x0000, 0x0003),
432 regmap_reg_range(0x0006, 0x0006),
433 regmap_reg_range(0x000f, 0x001f),
434 regmap_reg_range(0x0100, 0x0100),
435 regmap_reg_range(0x0104, 0x0107),
436 regmap_reg_range(0x010d, 0x010d),
437 regmap_reg_range(0x0110, 0x0113),
438 regmap_reg_range(0x0120, 0x012b),
439 regmap_reg_range(0x0201, 0x0201),
440 regmap_reg_range(0x0210, 0x0213),
441 regmap_reg_range(0x0300, 0x0300),
442 regmap_reg_range(0x0302, 0x031b),
443 regmap_reg_range(0x0320, 0x032b),
444 regmap_reg_range(0x0330, 0x0336),
445 regmap_reg_range(0x0338, 0x033e),
446 regmap_reg_range(0x0340, 0x035f),
447 regmap_reg_range(0x0370, 0x0370),
448 regmap_reg_range(0x0378, 0x0378),
449 regmap_reg_range(0x037c, 0x037d),
450 regmap_reg_range(0x0390, 0x0393),
451 regmap_reg_range(0x0400, 0x040e),
452 regmap_reg_range(0x0410, 0x042f),
453 regmap_reg_range(0x0500, 0x0519),
454 regmap_reg_range(0x0520, 0x054b),
455 regmap_reg_range(0x0550, 0x05b3),
456
457 /* port 1 */
458 regmap_reg_range(0x1000, 0x1001),
459 regmap_reg_range(0x1004, 0x100b),
460 regmap_reg_range(0x1013, 0x1013),
461 regmap_reg_range(0x1017, 0x1017),
462 regmap_reg_range(0x101b, 0x101b),
463 regmap_reg_range(0x101f, 0x1021),
464 regmap_reg_range(0x1030, 0x1030),
465 regmap_reg_range(0x1100, 0x1111),
466 regmap_reg_range(0x111a, 0x111d),
467 regmap_reg_range(0x1122, 0x1127),
468 regmap_reg_range(0x112a, 0x112b),
469 regmap_reg_range(0x1136, 0x1139),
470 regmap_reg_range(0x113e, 0x113f),
471 regmap_reg_range(0x1400, 0x1401),
472 regmap_reg_range(0x1403, 0x1403),
473 regmap_reg_range(0x1410, 0x1417),
474 regmap_reg_range(0x1420, 0x1423),
475 regmap_reg_range(0x1500, 0x1507),
476 regmap_reg_range(0x1600, 0x1612),
477 regmap_reg_range(0x1800, 0x180f),
478 regmap_reg_range(0x1900, 0x1907),
479 regmap_reg_range(0x1914, 0x191b),
480 regmap_reg_range(0x1a00, 0x1a03),
481 regmap_reg_range(0x1a04, 0x1a08),
482 regmap_reg_range(0x1b00, 0x1b01),
483 regmap_reg_range(0x1b04, 0x1b04),
484 regmap_reg_range(0x1c00, 0x1c05),
485 regmap_reg_range(0x1c08, 0x1c1b),
486
487 /* port 2 */
488 regmap_reg_range(0x2000, 0x2001),
489 regmap_reg_range(0x2004, 0x200b),
490 regmap_reg_range(0x2013, 0x2013),
491 regmap_reg_range(0x2017, 0x2017),
492 regmap_reg_range(0x201b, 0x201b),
493 regmap_reg_range(0x201f, 0x2021),
494 regmap_reg_range(0x2030, 0x2030),
495 regmap_reg_range(0x2100, 0x2111),
496 regmap_reg_range(0x211a, 0x211d),
497 regmap_reg_range(0x2122, 0x2127),
498 regmap_reg_range(0x212a, 0x212b),
499 regmap_reg_range(0x2136, 0x2139),
500 regmap_reg_range(0x213e, 0x213f),
501 regmap_reg_range(0x2400, 0x2401),
502 regmap_reg_range(0x2403, 0x2403),
503 regmap_reg_range(0x2410, 0x2417),
504 regmap_reg_range(0x2420, 0x2423),
505 regmap_reg_range(0x2500, 0x2507),
506 regmap_reg_range(0x2600, 0x2612),
507 regmap_reg_range(0x2800, 0x280f),
508 regmap_reg_range(0x2900, 0x2907),
509 regmap_reg_range(0x2914, 0x291b),
510 regmap_reg_range(0x2a00, 0x2a03),
511 regmap_reg_range(0x2a04, 0x2a08),
512 regmap_reg_range(0x2b00, 0x2b01),
513 regmap_reg_range(0x2b04, 0x2b04),
514 regmap_reg_range(0x2c00, 0x2c05),
515 regmap_reg_range(0x2c08, 0x2c1b),
516
517 /* port 3 */
518 regmap_reg_range(0x3000, 0x3001),
519 regmap_reg_range(0x3004, 0x300b),
520 regmap_reg_range(0x3013, 0x3013),
521 regmap_reg_range(0x3017, 0x3017),
522 regmap_reg_range(0x301b, 0x301b),
523 regmap_reg_range(0x301f, 0x3021),
524 regmap_reg_range(0x3030, 0x3030),
525 regmap_reg_range(0x3300, 0x3301),
526 regmap_reg_range(0x3303, 0x3303),
527 regmap_reg_range(0x3400, 0x3401),
528 regmap_reg_range(0x3403, 0x3403),
529 regmap_reg_range(0x3410, 0x3417),
530 regmap_reg_range(0x3420, 0x3423),
531 regmap_reg_range(0x3500, 0x3507),
532 regmap_reg_range(0x3600, 0x3612),
533 regmap_reg_range(0x3800, 0x380f),
534 regmap_reg_range(0x3900, 0x3907),
535 regmap_reg_range(0x3914, 0x391b),
536 regmap_reg_range(0x3a00, 0x3a03),
537 regmap_reg_range(0x3a04, 0x3a08),
538 regmap_reg_range(0x3b00, 0x3b01),
539 regmap_reg_range(0x3b04, 0x3b04),
540 regmap_reg_range(0x3c00, 0x3c05),
541 regmap_reg_range(0x3c08, 0x3c1b),
542 };
543
544 static const struct regmap_access_table ksz8563_register_set = {
545 .yes_ranges = ksz8563_valid_regs,
546 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs),
547 };
548
549 static const struct regmap_range ksz9477_valid_regs[] = {
550 regmap_reg_range(0x0000, 0x0003),
551 regmap_reg_range(0x0006, 0x0006),
552 regmap_reg_range(0x0010, 0x001f),
553 regmap_reg_range(0x0100, 0x0100),
554 regmap_reg_range(0x0103, 0x0107),
555 regmap_reg_range(0x010d, 0x010d),
556 regmap_reg_range(0x0110, 0x0113),
557 regmap_reg_range(0x0120, 0x012b),
558 regmap_reg_range(0x0201, 0x0201),
559 regmap_reg_range(0x0210, 0x0213),
560 regmap_reg_range(0x0300, 0x0300),
561 regmap_reg_range(0x0302, 0x031b),
562 regmap_reg_range(0x0320, 0x032b),
563 regmap_reg_range(0x0330, 0x0336),
564 regmap_reg_range(0x0338, 0x033b),
565 regmap_reg_range(0x033e, 0x033e),
566 regmap_reg_range(0x0340, 0x035f),
567 regmap_reg_range(0x0370, 0x0370),
568 regmap_reg_range(0x0378, 0x0378),
569 regmap_reg_range(0x037c, 0x037d),
570 regmap_reg_range(0x0390, 0x0393),
571 regmap_reg_range(0x0400, 0x040e),
572 regmap_reg_range(0x0410, 0x042f),
573 regmap_reg_range(0x0444, 0x044b),
574 regmap_reg_range(0x0450, 0x046f),
575 regmap_reg_range(0x0500, 0x0519),
576 regmap_reg_range(0x0520, 0x054b),
577 regmap_reg_range(0x0550, 0x05b3),
578 regmap_reg_range(0x0604, 0x060b),
579 regmap_reg_range(0x0610, 0x0612),
580 regmap_reg_range(0x0614, 0x062c),
581 regmap_reg_range(0x0640, 0x0645),
582 regmap_reg_range(0x0648, 0x064d),
583
584 /* port 1 */
585 regmap_reg_range(0x1000, 0x1001),
586 regmap_reg_range(0x1013, 0x1013),
587 regmap_reg_range(0x1017, 0x1017),
588 regmap_reg_range(0x101b, 0x101b),
589 regmap_reg_range(0x101f, 0x1020),
590 regmap_reg_range(0x1030, 0x1030),
591 regmap_reg_range(0x1100, 0x1115),
592 regmap_reg_range(0x111a, 0x111f),
593 regmap_reg_range(0x1122, 0x1127),
594 regmap_reg_range(0x112a, 0x112b),
595 regmap_reg_range(0x1136, 0x1139),
596 regmap_reg_range(0x113e, 0x113f),
597 regmap_reg_range(0x1400, 0x1401),
598 regmap_reg_range(0x1403, 0x1403),
599 regmap_reg_range(0x1410, 0x1417),
600 regmap_reg_range(0x1420, 0x1423),
601 regmap_reg_range(0x1500, 0x1507),
602 regmap_reg_range(0x1600, 0x1613),
603 regmap_reg_range(0x1800, 0x180f),
604 regmap_reg_range(0x1820, 0x1827),
605 regmap_reg_range(0x1830, 0x1837),
606 regmap_reg_range(0x1840, 0x184b),
607 regmap_reg_range(0x1900, 0x1907),
608 regmap_reg_range(0x1914, 0x191b),
609 regmap_reg_range(0x1920, 0x1920),
610 regmap_reg_range(0x1923, 0x1927),
611 regmap_reg_range(0x1a00, 0x1a03),
612 regmap_reg_range(0x1a04, 0x1a07),
613 regmap_reg_range(0x1b00, 0x1b01),
614 regmap_reg_range(0x1b04, 0x1b04),
615 regmap_reg_range(0x1c00, 0x1c05),
616 regmap_reg_range(0x1c08, 0x1c1b),
617
618 /* port 2 */
619 regmap_reg_range(0x2000, 0x2001),
620 regmap_reg_range(0x2013, 0x2013),
621 regmap_reg_range(0x2017, 0x2017),
622 regmap_reg_range(0x201b, 0x201b),
623 regmap_reg_range(0x201f, 0x2020),
624 regmap_reg_range(0x2030, 0x2030),
625 regmap_reg_range(0x2100, 0x2115),
626 regmap_reg_range(0x211a, 0x211f),
627 regmap_reg_range(0x2122, 0x2127),
628 regmap_reg_range(0x212a, 0x212b),
629 regmap_reg_range(0x2136, 0x2139),
630 regmap_reg_range(0x213e, 0x213f),
631 regmap_reg_range(0x2400, 0x2401),
632 regmap_reg_range(0x2403, 0x2403),
633 regmap_reg_range(0x2410, 0x2417),
634 regmap_reg_range(0x2420, 0x2423),
635 regmap_reg_range(0x2500, 0x2507),
636 regmap_reg_range(0x2600, 0x2613),
637 regmap_reg_range(0x2800, 0x280f),
638 regmap_reg_range(0x2820, 0x2827),
639 regmap_reg_range(0x2830, 0x2837),
640 regmap_reg_range(0x2840, 0x284b),
641 regmap_reg_range(0x2900, 0x2907),
642 regmap_reg_range(0x2914, 0x291b),
643 regmap_reg_range(0x2920, 0x2920),
644 regmap_reg_range(0x2923, 0x2927),
645 regmap_reg_range(0x2a00, 0x2a03),
646 regmap_reg_range(0x2a04, 0x2a07),
647 regmap_reg_range(0x2b00, 0x2b01),
648 regmap_reg_range(0x2b04, 0x2b04),
649 regmap_reg_range(0x2c00, 0x2c05),
650 regmap_reg_range(0x2c08, 0x2c1b),
651
652 /* port 3 */
653 regmap_reg_range(0x3000, 0x3001),
654 regmap_reg_range(0x3013, 0x3013),
655 regmap_reg_range(0x3017, 0x3017),
656 regmap_reg_range(0x301b, 0x301b),
657 regmap_reg_range(0x301f, 0x3020),
658 regmap_reg_range(0x3030, 0x3030),
659 regmap_reg_range(0x3100, 0x3115),
660 regmap_reg_range(0x311a, 0x311f),
661 regmap_reg_range(0x3122, 0x3127),
662 regmap_reg_range(0x312a, 0x312b),
663 regmap_reg_range(0x3136, 0x3139),
664 regmap_reg_range(0x313e, 0x313f),
665 regmap_reg_range(0x3400, 0x3401),
666 regmap_reg_range(0x3403, 0x3403),
667 regmap_reg_range(0x3410, 0x3417),
668 regmap_reg_range(0x3420, 0x3423),
669 regmap_reg_range(0x3500, 0x3507),
670 regmap_reg_range(0x3600, 0x3613),
671 regmap_reg_range(0x3800, 0x380f),
672 regmap_reg_range(0x3820, 0x3827),
673 regmap_reg_range(0x3830, 0x3837),
674 regmap_reg_range(0x3840, 0x384b),
675 regmap_reg_range(0x3900, 0x3907),
676 regmap_reg_range(0x3914, 0x391b),
677 regmap_reg_range(0x3920, 0x3920),
678 regmap_reg_range(0x3923, 0x3927),
679 regmap_reg_range(0x3a00, 0x3a03),
680 regmap_reg_range(0x3a04, 0x3a07),
681 regmap_reg_range(0x3b00, 0x3b01),
682 regmap_reg_range(0x3b04, 0x3b04),
683 regmap_reg_range(0x3c00, 0x3c05),
684 regmap_reg_range(0x3c08, 0x3c1b),
685
686 /* port 4 */
687 regmap_reg_range(0x4000, 0x4001),
688 regmap_reg_range(0x4013, 0x4013),
689 regmap_reg_range(0x4017, 0x4017),
690 regmap_reg_range(0x401b, 0x401b),
691 regmap_reg_range(0x401f, 0x4020),
692 regmap_reg_range(0x4030, 0x4030),
693 regmap_reg_range(0x4100, 0x4115),
694 regmap_reg_range(0x411a, 0x411f),
695 regmap_reg_range(0x4122, 0x4127),
696 regmap_reg_range(0x412a, 0x412b),
697 regmap_reg_range(0x4136, 0x4139),
698 regmap_reg_range(0x413e, 0x413f),
699 regmap_reg_range(0x4400, 0x4401),
700 regmap_reg_range(0x4403, 0x4403),
701 regmap_reg_range(0x4410, 0x4417),
702 regmap_reg_range(0x4420, 0x4423),
703 regmap_reg_range(0x4500, 0x4507),
704 regmap_reg_range(0x4600, 0x4613),
705 regmap_reg_range(0x4800, 0x480f),
706 regmap_reg_range(0x4820, 0x4827),
707 regmap_reg_range(0x4830, 0x4837),
708 regmap_reg_range(0x4840, 0x484b),
709 regmap_reg_range(0x4900, 0x4907),
710 regmap_reg_range(0x4914, 0x491b),
711 regmap_reg_range(0x4920, 0x4920),
712 regmap_reg_range(0x4923, 0x4927),
713 regmap_reg_range(0x4a00, 0x4a03),
714 regmap_reg_range(0x4a04, 0x4a07),
715 regmap_reg_range(0x4b00, 0x4b01),
716 regmap_reg_range(0x4b04, 0x4b04),
717 regmap_reg_range(0x4c00, 0x4c05),
718 regmap_reg_range(0x4c08, 0x4c1b),
719
720 /* port 5 */
721 regmap_reg_range(0x5000, 0x5001),
722 regmap_reg_range(0x5013, 0x5013),
723 regmap_reg_range(0x5017, 0x5017),
724 regmap_reg_range(0x501b, 0x501b),
725 regmap_reg_range(0x501f, 0x5020),
726 regmap_reg_range(0x5030, 0x5030),
727 regmap_reg_range(0x5100, 0x5115),
728 regmap_reg_range(0x511a, 0x511f),
729 regmap_reg_range(0x5122, 0x5127),
730 regmap_reg_range(0x512a, 0x512b),
731 regmap_reg_range(0x5136, 0x5139),
732 regmap_reg_range(0x513e, 0x513f),
733 regmap_reg_range(0x5400, 0x5401),
734 regmap_reg_range(0x5403, 0x5403),
735 regmap_reg_range(0x5410, 0x5417),
736 regmap_reg_range(0x5420, 0x5423),
737 regmap_reg_range(0x5500, 0x5507),
738 regmap_reg_range(0x5600, 0x5613),
739 regmap_reg_range(0x5800, 0x580f),
740 regmap_reg_range(0x5820, 0x5827),
741 regmap_reg_range(0x5830, 0x5837),
742 regmap_reg_range(0x5840, 0x584b),
743 regmap_reg_range(0x5900, 0x5907),
744 regmap_reg_range(0x5914, 0x591b),
745 regmap_reg_range(0x5920, 0x5920),
746 regmap_reg_range(0x5923, 0x5927),
747 regmap_reg_range(0x5a00, 0x5a03),
748 regmap_reg_range(0x5a04, 0x5a07),
749 regmap_reg_range(0x5b00, 0x5b01),
750 regmap_reg_range(0x5b04, 0x5b04),
751 regmap_reg_range(0x5c00, 0x5c05),
752 regmap_reg_range(0x5c08, 0x5c1b),
753
754 /* port 6 */
755 regmap_reg_range(0x6000, 0x6001),
756 regmap_reg_range(0x6013, 0x6013),
757 regmap_reg_range(0x6017, 0x6017),
758 regmap_reg_range(0x601b, 0x601b),
759 regmap_reg_range(0x601f, 0x6020),
760 regmap_reg_range(0x6030, 0x6030),
761 regmap_reg_range(0x6300, 0x6301),
762 regmap_reg_range(0x6400, 0x6401),
763 regmap_reg_range(0x6403, 0x6403),
764 regmap_reg_range(0x6410, 0x6417),
765 regmap_reg_range(0x6420, 0x6423),
766 regmap_reg_range(0x6500, 0x6507),
767 regmap_reg_range(0x6600, 0x6613),
768 regmap_reg_range(0x6800, 0x680f),
769 regmap_reg_range(0x6820, 0x6827),
770 regmap_reg_range(0x6830, 0x6837),
771 regmap_reg_range(0x6840, 0x684b),
772 regmap_reg_range(0x6900, 0x6907),
773 regmap_reg_range(0x6914, 0x691b),
774 regmap_reg_range(0x6920, 0x6920),
775 regmap_reg_range(0x6923, 0x6927),
776 regmap_reg_range(0x6a00, 0x6a03),
777 regmap_reg_range(0x6a04, 0x6a07),
778 regmap_reg_range(0x6b00, 0x6b01),
779 regmap_reg_range(0x6b04, 0x6b04),
780 regmap_reg_range(0x6c00, 0x6c05),
781 regmap_reg_range(0x6c08, 0x6c1b),
782
783 /* port 7 */
784 regmap_reg_range(0x7000, 0x7001),
785 regmap_reg_range(0x7013, 0x7013),
786 regmap_reg_range(0x7017, 0x7017),
787 regmap_reg_range(0x701b, 0x701b),
788 regmap_reg_range(0x701f, 0x7020),
789 regmap_reg_range(0x7030, 0x7030),
790 regmap_reg_range(0x7200, 0x7203),
791 regmap_reg_range(0x7206, 0x7207),
792 regmap_reg_range(0x7300, 0x7301),
793 regmap_reg_range(0x7400, 0x7401),
794 regmap_reg_range(0x7403, 0x7403),
795 regmap_reg_range(0x7410, 0x7417),
796 regmap_reg_range(0x7420, 0x7423),
797 regmap_reg_range(0x7500, 0x7507),
798 regmap_reg_range(0x7600, 0x7613),
799 regmap_reg_range(0x7800, 0x780f),
800 regmap_reg_range(0x7820, 0x7827),
801 regmap_reg_range(0x7830, 0x7837),
802 regmap_reg_range(0x7840, 0x784b),
803 regmap_reg_range(0x7900, 0x7907),
804 regmap_reg_range(0x7914, 0x791b),
805 regmap_reg_range(0x7920, 0x7920),
806 regmap_reg_range(0x7923, 0x7927),
807 regmap_reg_range(0x7a00, 0x7a03),
808 regmap_reg_range(0x7a04, 0x7a07),
809 regmap_reg_range(0x7b00, 0x7b01),
810 regmap_reg_range(0x7b04, 0x7b04),
811 regmap_reg_range(0x7c00, 0x7c05),
812 regmap_reg_range(0x7c08, 0x7c1b),
813 };
814
815 static const struct regmap_access_table ksz9477_register_set = {
816 .yes_ranges = ksz9477_valid_regs,
817 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs),
818 };
819
820 static const struct regmap_range ksz9896_valid_regs[] = {
821 regmap_reg_range(0x0000, 0x0003),
822 regmap_reg_range(0x0006, 0x0006),
823 regmap_reg_range(0x0010, 0x001f),
824 regmap_reg_range(0x0100, 0x0100),
825 regmap_reg_range(0x0103, 0x0107),
826 regmap_reg_range(0x010d, 0x010d),
827 regmap_reg_range(0x0110, 0x0113),
828 regmap_reg_range(0x0120, 0x0127),
829 regmap_reg_range(0x0201, 0x0201),
830 regmap_reg_range(0x0210, 0x0213),
831 regmap_reg_range(0x0300, 0x0300),
832 regmap_reg_range(0x0302, 0x030b),
833 regmap_reg_range(0x0310, 0x031b),
834 regmap_reg_range(0x0320, 0x032b),
835 regmap_reg_range(0x0330, 0x0336),
836 regmap_reg_range(0x0338, 0x033b),
837 regmap_reg_range(0x033e, 0x033e),
838 regmap_reg_range(0x0340, 0x035f),
839 regmap_reg_range(0x0370, 0x0370),
840 regmap_reg_range(0x0378, 0x0378),
841 regmap_reg_range(0x037c, 0x037d),
842 regmap_reg_range(0x0390, 0x0393),
843 regmap_reg_range(0x0400, 0x040e),
844 regmap_reg_range(0x0410, 0x042f),
845
846 /* port 1 */
847 regmap_reg_range(0x1000, 0x1001),
848 regmap_reg_range(0x1013, 0x1013),
849 regmap_reg_range(0x1017, 0x1017),
850 regmap_reg_range(0x101b, 0x101b),
851 regmap_reg_range(0x101f, 0x1020),
852 regmap_reg_range(0x1030, 0x1030),
853 regmap_reg_range(0x1100, 0x1115),
854 regmap_reg_range(0x111a, 0x111f),
855 regmap_reg_range(0x1122, 0x1127),
856 regmap_reg_range(0x112a, 0x112b),
857 regmap_reg_range(0x1136, 0x1139),
858 regmap_reg_range(0x113e, 0x113f),
859 regmap_reg_range(0x1400, 0x1401),
860 regmap_reg_range(0x1403, 0x1403),
861 regmap_reg_range(0x1410, 0x1417),
862 regmap_reg_range(0x1420, 0x1423),
863 regmap_reg_range(0x1500, 0x1507),
864 regmap_reg_range(0x1600, 0x1612),
865 regmap_reg_range(0x1800, 0x180f),
866 regmap_reg_range(0x1820, 0x1827),
867 regmap_reg_range(0x1830, 0x1837),
868 regmap_reg_range(0x1840, 0x184b),
869 regmap_reg_range(0x1900, 0x1907),
870 regmap_reg_range(0x1914, 0x1915),
871 regmap_reg_range(0x1a00, 0x1a03),
872 regmap_reg_range(0x1a04, 0x1a07),
873 regmap_reg_range(0x1b00, 0x1b01),
874 regmap_reg_range(0x1b04, 0x1b04),
875
876 /* port 2 */
877 regmap_reg_range(0x2000, 0x2001),
878 regmap_reg_range(0x2013, 0x2013),
879 regmap_reg_range(0x2017, 0x2017),
880 regmap_reg_range(0x201b, 0x201b),
881 regmap_reg_range(0x201f, 0x2020),
882 regmap_reg_range(0x2030, 0x2030),
883 regmap_reg_range(0x2100, 0x2115),
884 regmap_reg_range(0x211a, 0x211f),
885 regmap_reg_range(0x2122, 0x2127),
886 regmap_reg_range(0x212a, 0x212b),
887 regmap_reg_range(0x2136, 0x2139),
888 regmap_reg_range(0x213e, 0x213f),
889 regmap_reg_range(0x2400, 0x2401),
890 regmap_reg_range(0x2403, 0x2403),
891 regmap_reg_range(0x2410, 0x2417),
892 regmap_reg_range(0x2420, 0x2423),
893 regmap_reg_range(0x2500, 0x2507),
894 regmap_reg_range(0x2600, 0x2612),
895 regmap_reg_range(0x2800, 0x280f),
896 regmap_reg_range(0x2820, 0x2827),
897 regmap_reg_range(0x2830, 0x2837),
898 regmap_reg_range(0x2840, 0x284b),
899 regmap_reg_range(0x2900, 0x2907),
900 regmap_reg_range(0x2914, 0x2915),
901 regmap_reg_range(0x2a00, 0x2a03),
902 regmap_reg_range(0x2a04, 0x2a07),
903 regmap_reg_range(0x2b00, 0x2b01),
904 regmap_reg_range(0x2b04, 0x2b04),
905
906 /* port 3 */
907 regmap_reg_range(0x3000, 0x3001),
908 regmap_reg_range(0x3013, 0x3013),
909 regmap_reg_range(0x3017, 0x3017),
910 regmap_reg_range(0x301b, 0x301b),
911 regmap_reg_range(0x301f, 0x3020),
912 regmap_reg_range(0x3030, 0x3030),
913 regmap_reg_range(0x3100, 0x3115),
914 regmap_reg_range(0x311a, 0x311f),
915 regmap_reg_range(0x3122, 0x3127),
916 regmap_reg_range(0x312a, 0x312b),
917 regmap_reg_range(0x3136, 0x3139),
918 regmap_reg_range(0x313e, 0x313f),
919 regmap_reg_range(0x3400, 0x3401),
920 regmap_reg_range(0x3403, 0x3403),
921 regmap_reg_range(0x3410, 0x3417),
922 regmap_reg_range(0x3420, 0x3423),
923 regmap_reg_range(0x3500, 0x3507),
924 regmap_reg_range(0x3600, 0x3612),
925 regmap_reg_range(0x3800, 0x380f),
926 regmap_reg_range(0x3820, 0x3827),
927 regmap_reg_range(0x3830, 0x3837),
928 regmap_reg_range(0x3840, 0x384b),
929 regmap_reg_range(0x3900, 0x3907),
930 regmap_reg_range(0x3914, 0x3915),
931 regmap_reg_range(0x3a00, 0x3a03),
932 regmap_reg_range(0x3a04, 0x3a07),
933 regmap_reg_range(0x3b00, 0x3b01),
934 regmap_reg_range(0x3b04, 0x3b04),
935
936 /* port 4 */
937 regmap_reg_range(0x4000, 0x4001),
938 regmap_reg_range(0x4013, 0x4013),
939 regmap_reg_range(0x4017, 0x4017),
940 regmap_reg_range(0x401b, 0x401b),
941 regmap_reg_range(0x401f, 0x4020),
942 regmap_reg_range(0x4030, 0x4030),
943 regmap_reg_range(0x4100, 0x4115),
944 regmap_reg_range(0x411a, 0x411f),
945 regmap_reg_range(0x4122, 0x4127),
946 regmap_reg_range(0x412a, 0x412b),
947 regmap_reg_range(0x4136, 0x4139),
948 regmap_reg_range(0x413e, 0x413f),
949 regmap_reg_range(0x4400, 0x4401),
950 regmap_reg_range(0x4403, 0x4403),
951 regmap_reg_range(0x4410, 0x4417),
952 regmap_reg_range(0x4420, 0x4423),
953 regmap_reg_range(0x4500, 0x4507),
954 regmap_reg_range(0x4600, 0x4612),
955 regmap_reg_range(0x4800, 0x480f),
956 regmap_reg_range(0x4820, 0x4827),
957 regmap_reg_range(0x4830, 0x4837),
958 regmap_reg_range(0x4840, 0x484b),
959 regmap_reg_range(0x4900, 0x4907),
960 regmap_reg_range(0x4914, 0x4915),
961 regmap_reg_range(0x4a00, 0x4a03),
962 regmap_reg_range(0x4a04, 0x4a07),
963 regmap_reg_range(0x4b00, 0x4b01),
964 regmap_reg_range(0x4b04, 0x4b04),
965
966 /* port 5 */
967 regmap_reg_range(0x5000, 0x5001),
968 regmap_reg_range(0x5013, 0x5013),
969 regmap_reg_range(0x5017, 0x5017),
970 regmap_reg_range(0x501b, 0x501b),
971 regmap_reg_range(0x501f, 0x5020),
972 regmap_reg_range(0x5030, 0x5030),
973 regmap_reg_range(0x5100, 0x5115),
974 regmap_reg_range(0x511a, 0x511f),
975 regmap_reg_range(0x5122, 0x5127),
976 regmap_reg_range(0x512a, 0x512b),
977 regmap_reg_range(0x5136, 0x5139),
978 regmap_reg_range(0x513e, 0x513f),
979 regmap_reg_range(0x5400, 0x5401),
980 regmap_reg_range(0x5403, 0x5403),
981 regmap_reg_range(0x5410, 0x5417),
982 regmap_reg_range(0x5420, 0x5423),
983 regmap_reg_range(0x5500, 0x5507),
984 regmap_reg_range(0x5600, 0x5612),
985 regmap_reg_range(0x5800, 0x580f),
986 regmap_reg_range(0x5820, 0x5827),
987 regmap_reg_range(0x5830, 0x5837),
988 regmap_reg_range(0x5840, 0x584b),
989 regmap_reg_range(0x5900, 0x5907),
990 regmap_reg_range(0x5914, 0x5915),
991 regmap_reg_range(0x5a00, 0x5a03),
992 regmap_reg_range(0x5a04, 0x5a07),
993 regmap_reg_range(0x5b00, 0x5b01),
994 regmap_reg_range(0x5b04, 0x5b04),
995
996 /* port 6 */
997 regmap_reg_range(0x6000, 0x6001),
998 regmap_reg_range(0x6013, 0x6013),
999 regmap_reg_range(0x6017, 0x6017),
1000 regmap_reg_range(0x601b, 0x601b),
1001 regmap_reg_range(0x601f, 0x6020),
1002 regmap_reg_range(0x6030, 0x6030),
1003 regmap_reg_range(0x6100, 0x6115),
1004 regmap_reg_range(0x611a, 0x611f),
1005 regmap_reg_range(0x6122, 0x6127),
1006 regmap_reg_range(0x612a, 0x612b),
1007 regmap_reg_range(0x6136, 0x6139),
1008 regmap_reg_range(0x613e, 0x613f),
1009 regmap_reg_range(0x6300, 0x6301),
1010 regmap_reg_range(0x6400, 0x6401),
1011 regmap_reg_range(0x6403, 0x6403),
1012 regmap_reg_range(0x6410, 0x6417),
1013 regmap_reg_range(0x6420, 0x6423),
1014 regmap_reg_range(0x6500, 0x6507),
1015 regmap_reg_range(0x6600, 0x6612),
1016 regmap_reg_range(0x6800, 0x680f),
1017 regmap_reg_range(0x6820, 0x6827),
1018 regmap_reg_range(0x6830, 0x6837),
1019 regmap_reg_range(0x6840, 0x684b),
1020 regmap_reg_range(0x6900, 0x6907),
1021 regmap_reg_range(0x6914, 0x6915),
1022 regmap_reg_range(0x6a00, 0x6a03),
1023 regmap_reg_range(0x6a04, 0x6a07),
1024 regmap_reg_range(0x6b00, 0x6b01),
1025 regmap_reg_range(0x6b04, 0x6b04),
1026 };
1027
1028 static const struct regmap_access_table ksz9896_register_set = {
1029 .yes_ranges = ksz9896_valid_regs,
1030 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs),
1031 };
1032
1033 const struct ksz_chip_data ksz_switch_chips[] = {
1034 [KSZ8563] = {
1035 .chip_id = KSZ8563_CHIP_ID,
1036 .dev_name = "KSZ8563",
1037 .num_vlans = 4096,
1038 .num_alus = 4096,
1039 .num_statics = 16,
1040 .cpu_ports = 0x07, /* can be configured as cpu port */
1041 .port_cnt = 3, /* total port count */
1042 .ops = &ksz9477_dev_ops,
1043 .mib_names = ksz9477_mib_names,
1044 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1045 .reg_mib_cnt = MIB_COUNTER_NUM,
1046 .regs = ksz9477_regs,
1047 .masks = ksz9477_masks,
1048 .shifts = ksz9477_shifts,
1049 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1050 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1051 .supports_mii = {false, false, true},
1052 .supports_rmii = {false, false, true},
1053 .supports_rgmii = {false, false, true},
1054 .internal_phy = {true, true, false},
1055 .gbit_capable = {false, false, true},
1056 .wr_table = &ksz8563_register_set,
1057 .rd_table = &ksz8563_register_set,
1058 },
1059
1060 [KSZ8795] = {
1061 .chip_id = KSZ8795_CHIP_ID,
1062 .dev_name = "KSZ8795",
1063 .num_vlans = 4096,
1064 .num_alus = 0,
1065 .num_statics = 8,
1066 .cpu_ports = 0x10, /* can be configured as cpu port */
1067 .port_cnt = 5, /* total cpu and user ports */
1068 .ops = &ksz8_dev_ops,
1069 .ksz87xx_eee_link_erratum = true,
1070 .mib_names = ksz9477_mib_names,
1071 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1072 .reg_mib_cnt = MIB_COUNTER_NUM,
1073 .regs = ksz8795_regs,
1074 .masks = ksz8795_masks,
1075 .shifts = ksz8795_shifts,
1076 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1077 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1078 .supports_mii = {false, false, false, false, true},
1079 .supports_rmii = {false, false, false, false, true},
1080 .supports_rgmii = {false, false, false, false, true},
1081 .internal_phy = {true, true, true, true, false},
1082 },
1083
1084 [KSZ8794] = {
1085 /* WARNING
1086 * =======
1087 * KSZ8794 is similar to KSZ8795, except the port map
1088 * contains a gap between external and CPU ports, the
1089 * port map is NOT continuous. The per-port register
1090 * map is shifted accordingly too, i.e. registers at
1091 * offset 0x40 are NOT used on KSZ8794 and they ARE
1092 * used on KSZ8795 for external port 3.
1093 * external cpu
1094 * KSZ8794 0,1,2 4
1095 * KSZ8795 0,1,2,3 4
1096 * KSZ8765 0,1,2,3 4
1097 * port_cnt is configured as 5, even though it is 4
1098 */
1099 .chip_id = KSZ8794_CHIP_ID,
1100 .dev_name = "KSZ8794",
1101 .num_vlans = 4096,
1102 .num_alus = 0,
1103 .num_statics = 8,
1104 .cpu_ports = 0x10, /* can be configured as cpu port */
1105 .port_cnt = 5, /* total cpu and user ports */
1106 .ops = &ksz8_dev_ops,
1107 .ksz87xx_eee_link_erratum = true,
1108 .mib_names = ksz9477_mib_names,
1109 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1110 .reg_mib_cnt = MIB_COUNTER_NUM,
1111 .regs = ksz8795_regs,
1112 .masks = ksz8795_masks,
1113 .shifts = ksz8795_shifts,
1114 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1115 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1116 .supports_mii = {false, false, false, false, true},
1117 .supports_rmii = {false, false, false, false, true},
1118 .supports_rgmii = {false, false, false, false, true},
1119 .internal_phy = {true, true, true, false, false},
1120 },
1121
1122 [KSZ8765] = {
1123 .chip_id = KSZ8765_CHIP_ID,
1124 .dev_name = "KSZ8765",
1125 .num_vlans = 4096,
1126 .num_alus = 0,
1127 .num_statics = 8,
1128 .cpu_ports = 0x10, /* can be configured as cpu port */
1129 .port_cnt = 5, /* total cpu and user ports */
1130 .ops = &ksz8_dev_ops,
1131 .ksz87xx_eee_link_erratum = true,
1132 .mib_names = ksz9477_mib_names,
1133 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1134 .reg_mib_cnt = MIB_COUNTER_NUM,
1135 .regs = ksz8795_regs,
1136 .masks = ksz8795_masks,
1137 .shifts = ksz8795_shifts,
1138 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1139 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1140 .supports_mii = {false, false, false, false, true},
1141 .supports_rmii = {false, false, false, false, true},
1142 .supports_rgmii = {false, false, false, false, true},
1143 .internal_phy = {true, true, true, true, false},
1144 },
1145
1146 [KSZ8830] = {
1147 .chip_id = KSZ8830_CHIP_ID,
1148 .dev_name = "KSZ8863/KSZ8873",
1149 .num_vlans = 16,
1150 .num_alus = 0,
1151 .num_statics = 8,
1152 .cpu_ports = 0x4, /* can be configured as cpu port */
1153 .port_cnt = 3,
1154 .ops = &ksz8_dev_ops,
1155 .mib_names = ksz88xx_mib_names,
1156 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1157 .reg_mib_cnt = MIB_COUNTER_NUM,
1158 .regs = ksz8863_regs,
1159 .masks = ksz8863_masks,
1160 .shifts = ksz8863_shifts,
1161 .supports_mii = {false, false, true},
1162 .supports_rmii = {false, false, true},
1163 .internal_phy = {true, true, false},
1164 },
1165
1166 [KSZ9477] = {
1167 .chip_id = KSZ9477_CHIP_ID,
1168 .dev_name = "KSZ9477",
1169 .num_vlans = 4096,
1170 .num_alus = 4096,
1171 .num_statics = 16,
1172 .cpu_ports = 0x7F, /* can be configured as cpu port */
1173 .port_cnt = 7, /* total physical port count */
1174 .port_nirqs = 4,
1175 .ops = &ksz9477_dev_ops,
1176 .phy_errata_9477 = true,
1177 .mib_names = ksz9477_mib_names,
1178 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1179 .reg_mib_cnt = MIB_COUNTER_NUM,
1180 .regs = ksz9477_regs,
1181 .masks = ksz9477_masks,
1182 .shifts = ksz9477_shifts,
1183 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1184 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1185 .supports_mii = {false, false, false, false,
1186 false, true, false},
1187 .supports_rmii = {false, false, false, false,
1188 false, true, false},
1189 .supports_rgmii = {false, false, false, false,
1190 false, true, false},
1191 .internal_phy = {true, true, true, true,
1192 true, false, false},
1193 .gbit_capable = {true, true, true, true, true, true, true},
1194 .wr_table = &ksz9477_register_set,
1195 .rd_table = &ksz9477_register_set,
1196 },
1197
1198 [KSZ9896] = {
1199 .chip_id = KSZ9896_CHIP_ID,
1200 .dev_name = "KSZ9896",
1201 .num_vlans = 4096,
1202 .num_alus = 4096,
1203 .num_statics = 16,
1204 .cpu_ports = 0x3F, /* can be configured as cpu port */
1205 .port_cnt = 6, /* total physical port count */
1206 .port_nirqs = 2,
1207 .ops = &ksz9477_dev_ops,
1208 .phy_errata_9477 = true,
1209 .mib_names = ksz9477_mib_names,
1210 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1211 .reg_mib_cnt = MIB_COUNTER_NUM,
1212 .regs = ksz9477_regs,
1213 .masks = ksz9477_masks,
1214 .shifts = ksz9477_shifts,
1215 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1216 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1217 .supports_mii = {false, false, false, false,
1218 false, true},
1219 .supports_rmii = {false, false, false, false,
1220 false, true},
1221 .supports_rgmii = {false, false, false, false,
1222 false, true},
1223 .internal_phy = {true, true, true, true,
1224 true, false},
1225 .gbit_capable = {true, true, true, true, true, true},
1226 .wr_table = &ksz9896_register_set,
1227 .rd_table = &ksz9896_register_set,
1228 },
1229
1230 [KSZ9897] = {
1231 .chip_id = KSZ9897_CHIP_ID,
1232 .dev_name = "KSZ9897",
1233 .num_vlans = 4096,
1234 .num_alus = 4096,
1235 .num_statics = 16,
1236 .cpu_ports = 0x7F, /* can be configured as cpu port */
1237 .port_cnt = 7, /* total physical port count */
1238 .port_nirqs = 2,
1239 .ops = &ksz9477_dev_ops,
1240 .phy_errata_9477 = true,
1241 .mib_names = ksz9477_mib_names,
1242 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1243 .reg_mib_cnt = MIB_COUNTER_NUM,
1244 .regs = ksz9477_regs,
1245 .masks = ksz9477_masks,
1246 .shifts = ksz9477_shifts,
1247 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1248 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1249 .supports_mii = {false, false, false, false,
1250 false, true, true},
1251 .supports_rmii = {false, false, false, false,
1252 false, true, true},
1253 .supports_rgmii = {false, false, false, false,
1254 false, true, true},
1255 .internal_phy = {true, true, true, true,
1256 true, false, false},
1257 .gbit_capable = {true, true, true, true, true, true, true},
1258 },
1259
1260 [KSZ9893] = {
1261 .chip_id = KSZ9893_CHIP_ID,
1262 .dev_name = "KSZ9893",
1263 .num_vlans = 4096,
1264 .num_alus = 4096,
1265 .num_statics = 16,
1266 .cpu_ports = 0x07, /* can be configured as cpu port */
1267 .port_cnt = 3, /* total port count */
1268 .port_nirqs = 2,
1269 .ops = &ksz9477_dev_ops,
1270 .mib_names = ksz9477_mib_names,
1271 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1272 .reg_mib_cnt = MIB_COUNTER_NUM,
1273 .regs = ksz9477_regs,
1274 .masks = ksz9477_masks,
1275 .shifts = ksz9477_shifts,
1276 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1277 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1278 .supports_mii = {false, false, true},
1279 .supports_rmii = {false, false, true},
1280 .supports_rgmii = {false, false, true},
1281 .internal_phy = {true, true, false},
1282 .gbit_capable = {true, true, true},
1283 },
1284
1285 [KSZ9567] = {
1286 .chip_id = KSZ9567_CHIP_ID,
1287 .dev_name = "KSZ9567",
1288 .num_vlans = 4096,
1289 .num_alus = 4096,
1290 .num_statics = 16,
1291 .cpu_ports = 0x7F, /* can be configured as cpu port */
1292 .port_cnt = 7, /* total physical port count */
1293 .port_nirqs = 3,
1294 .ops = &ksz9477_dev_ops,
1295 .phy_errata_9477 = true,
1296 .mib_names = ksz9477_mib_names,
1297 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1298 .reg_mib_cnt = MIB_COUNTER_NUM,
1299 .regs = ksz9477_regs,
1300 .masks = ksz9477_masks,
1301 .shifts = ksz9477_shifts,
1302 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1303 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1304 .supports_mii = {false, false, false, false,
1305 false, true, true},
1306 .supports_rmii = {false, false, false, false,
1307 false, true, true},
1308 .supports_rgmii = {false, false, false, false,
1309 false, true, true},
1310 .internal_phy = {true, true, true, true,
1311 true, false, false},
1312 .gbit_capable = {true, true, true, true, true, true, true},
1313 },
1314
1315 [LAN9370] = {
1316 .chip_id = LAN9370_CHIP_ID,
1317 .dev_name = "LAN9370",
1318 .num_vlans = 4096,
1319 .num_alus = 1024,
1320 .num_statics = 256,
1321 .cpu_ports = 0x10, /* can be configured as cpu port */
1322 .port_cnt = 5, /* total physical port count */
1323 .port_nirqs = 6,
1324 .ops = &lan937x_dev_ops,
1325 .mib_names = ksz9477_mib_names,
1326 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1327 .reg_mib_cnt = MIB_COUNTER_NUM,
1328 .regs = ksz9477_regs,
1329 .masks = lan937x_masks,
1330 .shifts = lan937x_shifts,
1331 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1332 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1333 .supports_mii = {false, false, false, false, true},
1334 .supports_rmii = {false, false, false, false, true},
1335 .supports_rgmii = {false, false, false, false, true},
1336 .internal_phy = {true, true, true, true, false},
1337 },
1338
1339 [LAN9371] = {
1340 .chip_id = LAN9371_CHIP_ID,
1341 .dev_name = "LAN9371",
1342 .num_vlans = 4096,
1343 .num_alus = 1024,
1344 .num_statics = 256,
1345 .cpu_ports = 0x30, /* can be configured as cpu port */
1346 .port_cnt = 6, /* total physical port count */
1347 .port_nirqs = 6,
1348 .ops = &lan937x_dev_ops,
1349 .mib_names = ksz9477_mib_names,
1350 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1351 .reg_mib_cnt = MIB_COUNTER_NUM,
1352 .regs = ksz9477_regs,
1353 .masks = lan937x_masks,
1354 .shifts = lan937x_shifts,
1355 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1356 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1357 .supports_mii = {false, false, false, false, true, true},
1358 .supports_rmii = {false, false, false, false, true, true},
1359 .supports_rgmii = {false, false, false, false, true, true},
1360 .internal_phy = {true, true, true, true, false, false},
1361 },
1362
1363 [LAN9372] = {
1364 .chip_id = LAN9372_CHIP_ID,
1365 .dev_name = "LAN9372",
1366 .num_vlans = 4096,
1367 .num_alus = 1024,
1368 .num_statics = 256,
1369 .cpu_ports = 0x30, /* can be configured as cpu port */
1370 .port_cnt = 8, /* total physical port count */
1371 .port_nirqs = 6,
1372 .ops = &lan937x_dev_ops,
1373 .mib_names = ksz9477_mib_names,
1374 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1375 .reg_mib_cnt = MIB_COUNTER_NUM,
1376 .regs = ksz9477_regs,
1377 .masks = lan937x_masks,
1378 .shifts = lan937x_shifts,
1379 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1380 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1381 .supports_mii = {false, false, false, false,
1382 true, true, false, false},
1383 .supports_rmii = {false, false, false, false,
1384 true, true, false, false},
1385 .supports_rgmii = {false, false, false, false,
1386 true, true, false, false},
1387 .internal_phy = {true, true, true, true,
1388 false, false, true, true},
1389 },
1390
1391 [LAN9373] = {
1392 .chip_id = LAN9373_CHIP_ID,
1393 .dev_name = "LAN9373",
1394 .num_vlans = 4096,
1395 .num_alus = 1024,
1396 .num_statics = 256,
1397 .cpu_ports = 0x38, /* can be configured as cpu port */
1398 .port_cnt = 5, /* total physical port count */
1399 .port_nirqs = 6,
1400 .ops = &lan937x_dev_ops,
1401 .mib_names = ksz9477_mib_names,
1402 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1403 .reg_mib_cnt = MIB_COUNTER_NUM,
1404 .regs = ksz9477_regs,
1405 .masks = lan937x_masks,
1406 .shifts = lan937x_shifts,
1407 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1408 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1409 .supports_mii = {false, false, false, false,
1410 true, true, false, false},
1411 .supports_rmii = {false, false, false, false,
1412 true, true, false, false},
1413 .supports_rgmii = {false, false, false, false,
1414 true, true, false, false},
1415 .internal_phy = {true, true, true, false,
1416 false, false, true, true},
1417 },
1418
1419 [LAN9374] = {
1420 .chip_id = LAN9374_CHIP_ID,
1421 .dev_name = "LAN9374",
1422 .num_vlans = 4096,
1423 .num_alus = 1024,
1424 .num_statics = 256,
1425 .cpu_ports = 0x30, /* can be configured as cpu port */
1426 .port_cnt = 8, /* total physical port count */
1427 .port_nirqs = 6,
1428 .ops = &lan937x_dev_ops,
1429 .mib_names = ksz9477_mib_names,
1430 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1431 .reg_mib_cnt = MIB_COUNTER_NUM,
1432 .regs = ksz9477_regs,
1433 .masks = lan937x_masks,
1434 .shifts = lan937x_shifts,
1435 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1436 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1437 .supports_mii = {false, false, false, false,
1438 true, true, false, false},
1439 .supports_rmii = {false, false, false, false,
1440 true, true, false, false},
1441 .supports_rgmii = {false, false, false, false,
1442 true, true, false, false},
1443 .internal_phy = {true, true, true, true,
1444 false, false, true, true},
1445 },
1446 };
1447 EXPORT_SYMBOL_GPL(ksz_switch_chips);
1448
ksz_lookup_info(unsigned int prod_num)1449 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num)
1450 {
1451 int i;
1452
1453 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
1454 const struct ksz_chip_data *chip = &ksz_switch_chips[i];
1455
1456 if (chip->chip_id == prod_num)
1457 return chip;
1458 }
1459
1460 return NULL;
1461 }
1462
ksz_check_device_id(struct ksz_device * dev)1463 static int ksz_check_device_id(struct ksz_device *dev)
1464 {
1465 const struct ksz_chip_data *dt_chip_data;
1466
1467 dt_chip_data = of_device_get_match_data(dev->dev);
1468
1469 /* Check for Device Tree and Chip ID */
1470 if (dt_chip_data->chip_id != dev->chip_id) {
1471 dev_err(dev->dev,
1472 "Device tree specifies chip %s but found %s, please fix it!\n",
1473 dt_chip_data->dev_name, dev->info->dev_name);
1474 return -ENODEV;
1475 }
1476
1477 return 0;
1478 }
1479
ksz_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)1480 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
1481 struct phylink_config *config)
1482 {
1483 struct ksz_device *dev = ds->priv;
1484
1485 config->legacy_pre_march2020 = false;
1486
1487 if (dev->info->supports_mii[port])
1488 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1489
1490 if (dev->info->supports_rmii[port])
1491 __set_bit(PHY_INTERFACE_MODE_RMII,
1492 config->supported_interfaces);
1493
1494 if (dev->info->supports_rgmii[port])
1495 phy_interface_set_rgmii(config->supported_interfaces);
1496
1497 if (dev->info->internal_phy[port]) {
1498 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1499 config->supported_interfaces);
1500 /* Compatibility for phylib's default interface type when the
1501 * phy-mode property is absent
1502 */
1503 __set_bit(PHY_INTERFACE_MODE_GMII,
1504 config->supported_interfaces);
1505 }
1506
1507 if (dev->dev_ops->get_caps)
1508 dev->dev_ops->get_caps(dev, port, config);
1509 }
1510
ksz_r_mib_stats64(struct ksz_device * dev,int port)1511 void ksz_r_mib_stats64(struct ksz_device *dev, int port)
1512 {
1513 struct ethtool_pause_stats *pstats;
1514 struct rtnl_link_stats64 *stats;
1515 struct ksz_stats_raw *raw;
1516 struct ksz_port_mib *mib;
1517
1518 mib = &dev->ports[port].mib;
1519 stats = &mib->stats64;
1520 pstats = &mib->pause_stats;
1521 raw = (struct ksz_stats_raw *)mib->counters;
1522
1523 spin_lock(&mib->stats64_lock);
1524
1525 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
1526 raw->rx_pause;
1527 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
1528 raw->tx_pause;
1529
1530 /* HW counters are counting bytes + FCS which is not acceptable
1531 * for rtnl_link_stats64 interface
1532 */
1533 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN;
1534 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN;
1535
1536 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
1537 raw->rx_oversize;
1538
1539 stats->rx_crc_errors = raw->rx_crc_err;
1540 stats->rx_frame_errors = raw->rx_align_err;
1541 stats->rx_dropped = raw->rx_discards;
1542 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
1543 stats->rx_frame_errors + stats->rx_dropped;
1544
1545 stats->tx_window_errors = raw->tx_late_col;
1546 stats->tx_fifo_errors = raw->tx_discards;
1547 stats->tx_aborted_errors = raw->tx_exc_col;
1548 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
1549 stats->tx_aborted_errors;
1550
1551 stats->multicast = raw->rx_mcast;
1552 stats->collisions = raw->tx_total_col;
1553
1554 pstats->tx_pause_frames = raw->tx_pause;
1555 pstats->rx_pause_frames = raw->rx_pause;
1556
1557 spin_unlock(&mib->stats64_lock);
1558 }
1559
ksz_get_stats64(struct dsa_switch * ds,int port,struct rtnl_link_stats64 * s)1560 static void ksz_get_stats64(struct dsa_switch *ds, int port,
1561 struct rtnl_link_stats64 *s)
1562 {
1563 struct ksz_device *dev = ds->priv;
1564 struct ksz_port_mib *mib;
1565
1566 mib = &dev->ports[port].mib;
1567
1568 spin_lock(&mib->stats64_lock);
1569 memcpy(s, &mib->stats64, sizeof(*s));
1570 spin_unlock(&mib->stats64_lock);
1571 }
1572
ksz_get_pause_stats(struct dsa_switch * ds,int port,struct ethtool_pause_stats * pause_stats)1573 static void ksz_get_pause_stats(struct dsa_switch *ds, int port,
1574 struct ethtool_pause_stats *pause_stats)
1575 {
1576 struct ksz_device *dev = ds->priv;
1577 struct ksz_port_mib *mib;
1578
1579 mib = &dev->ports[port].mib;
1580
1581 spin_lock(&mib->stats64_lock);
1582 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats));
1583 spin_unlock(&mib->stats64_lock);
1584 }
1585
ksz_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * buf)1586 static void ksz_get_strings(struct dsa_switch *ds, int port,
1587 u32 stringset, uint8_t *buf)
1588 {
1589 struct ksz_device *dev = ds->priv;
1590 int i;
1591
1592 if (stringset != ETH_SS_STATS)
1593 return;
1594
1595 for (i = 0; i < dev->info->mib_cnt; i++) {
1596 memcpy(buf + i * ETH_GSTRING_LEN,
1597 dev->info->mib_names[i].string, ETH_GSTRING_LEN);
1598 }
1599 }
1600
ksz_update_port_member(struct ksz_device * dev,int port)1601 static void ksz_update_port_member(struct ksz_device *dev, int port)
1602 {
1603 struct ksz_port *p = &dev->ports[port];
1604 struct dsa_switch *ds = dev->ds;
1605 u8 port_member = 0, cpu_port;
1606 const struct dsa_port *dp;
1607 int i, j;
1608
1609 if (!dsa_is_user_port(ds, port))
1610 return;
1611
1612 dp = dsa_to_port(ds, port);
1613 cpu_port = BIT(dsa_upstream_port(ds, port));
1614
1615 for (i = 0; i < ds->num_ports; i++) {
1616 const struct dsa_port *other_dp = dsa_to_port(ds, i);
1617 struct ksz_port *other_p = &dev->ports[i];
1618 u8 val = 0;
1619
1620 if (!dsa_is_user_port(ds, i))
1621 continue;
1622 if (port == i)
1623 continue;
1624 if (!dsa_port_bridge_same(dp, other_dp))
1625 continue;
1626 if (other_p->stp_state != BR_STATE_FORWARDING)
1627 continue;
1628
1629 if (p->stp_state == BR_STATE_FORWARDING) {
1630 val |= BIT(port);
1631 port_member |= BIT(i);
1632 }
1633
1634 /* Retain port [i]'s relationship to other ports than [port] */
1635 for (j = 0; j < ds->num_ports; j++) {
1636 const struct dsa_port *third_dp;
1637 struct ksz_port *third_p;
1638
1639 if (j == i)
1640 continue;
1641 if (j == port)
1642 continue;
1643 if (!dsa_is_user_port(ds, j))
1644 continue;
1645 third_p = &dev->ports[j];
1646 if (third_p->stp_state != BR_STATE_FORWARDING)
1647 continue;
1648 third_dp = dsa_to_port(ds, j);
1649 if (dsa_port_bridge_same(other_dp, third_dp))
1650 val |= BIT(j);
1651 }
1652
1653 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port);
1654 }
1655
1656 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port);
1657 }
1658
ksz_sw_mdio_read(struct mii_bus * bus,int addr,int regnum)1659 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
1660 {
1661 struct ksz_device *dev = bus->priv;
1662 u16 val;
1663 int ret;
1664
1665 if (regnum & MII_ADDR_C45)
1666 return -EOPNOTSUPP;
1667
1668 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val);
1669 if (ret < 0)
1670 return ret;
1671
1672 return val;
1673 }
1674
ksz_sw_mdio_write(struct mii_bus * bus,int addr,int regnum,u16 val)1675 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
1676 u16 val)
1677 {
1678 struct ksz_device *dev = bus->priv;
1679
1680 if (regnum & MII_ADDR_C45)
1681 return -EOPNOTSUPP;
1682
1683 return dev->dev_ops->w_phy(dev, addr, regnum, val);
1684 }
1685
ksz_irq_phy_setup(struct ksz_device * dev)1686 static int ksz_irq_phy_setup(struct ksz_device *dev)
1687 {
1688 struct dsa_switch *ds = dev->ds;
1689 int phy;
1690 int irq;
1691 int ret;
1692
1693 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) {
1694 if (BIT(phy) & ds->phys_mii_mask) {
1695 irq = irq_find_mapping(dev->ports[phy].pirq.domain,
1696 PORT_SRC_PHY_INT);
1697 if (irq < 0) {
1698 ret = irq;
1699 goto out;
1700 }
1701 ds->slave_mii_bus->irq[phy] = irq;
1702 }
1703 }
1704 return 0;
1705 out:
1706 while (phy--)
1707 if (BIT(phy) & ds->phys_mii_mask)
1708 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]);
1709
1710 return ret;
1711 }
1712
ksz_irq_phy_free(struct ksz_device * dev)1713 static void ksz_irq_phy_free(struct ksz_device *dev)
1714 {
1715 struct dsa_switch *ds = dev->ds;
1716 int phy;
1717
1718 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++)
1719 if (BIT(phy) & ds->phys_mii_mask)
1720 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]);
1721 }
1722
ksz_mdio_register(struct ksz_device * dev)1723 static int ksz_mdio_register(struct ksz_device *dev)
1724 {
1725 struct dsa_switch *ds = dev->ds;
1726 struct device_node *mdio_np;
1727 struct mii_bus *bus;
1728 int ret;
1729
1730 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio");
1731 if (!mdio_np)
1732 return 0;
1733
1734 bus = devm_mdiobus_alloc(ds->dev);
1735 if (!bus) {
1736 of_node_put(mdio_np);
1737 return -ENOMEM;
1738 }
1739
1740 bus->priv = dev;
1741 bus->read = ksz_sw_mdio_read;
1742 bus->write = ksz_sw_mdio_write;
1743 bus->name = "ksz slave smi";
1744 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index);
1745 bus->parent = ds->dev;
1746 bus->phy_mask = ~ds->phys_mii_mask;
1747
1748 ds->slave_mii_bus = bus;
1749
1750 if (dev->irq > 0) {
1751 ret = ksz_irq_phy_setup(dev);
1752 if (ret) {
1753 of_node_put(mdio_np);
1754 return ret;
1755 }
1756 }
1757
1758 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np);
1759 if (ret) {
1760 dev_err(ds->dev, "unable to register MDIO bus %s\n",
1761 bus->id);
1762 if (dev->irq > 0)
1763 ksz_irq_phy_free(dev);
1764 }
1765
1766 of_node_put(mdio_np);
1767
1768 return ret;
1769 }
1770
ksz_irq_mask(struct irq_data * d)1771 static void ksz_irq_mask(struct irq_data *d)
1772 {
1773 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1774
1775 kirq->masked |= BIT(d->hwirq);
1776 }
1777
ksz_irq_unmask(struct irq_data * d)1778 static void ksz_irq_unmask(struct irq_data *d)
1779 {
1780 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1781
1782 kirq->masked &= ~BIT(d->hwirq);
1783 }
1784
ksz_irq_bus_lock(struct irq_data * d)1785 static void ksz_irq_bus_lock(struct irq_data *d)
1786 {
1787 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1788
1789 mutex_lock(&kirq->dev->lock_irq);
1790 }
1791
ksz_irq_bus_sync_unlock(struct irq_data * d)1792 static void ksz_irq_bus_sync_unlock(struct irq_data *d)
1793 {
1794 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1795 struct ksz_device *dev = kirq->dev;
1796 int ret;
1797
1798 ret = ksz_write32(dev, kirq->reg_mask, kirq->masked);
1799 if (ret)
1800 dev_err(dev->dev, "failed to change IRQ mask\n");
1801
1802 mutex_unlock(&dev->lock_irq);
1803 }
1804
1805 static const struct irq_chip ksz_irq_chip = {
1806 .name = "ksz-irq",
1807 .irq_mask = ksz_irq_mask,
1808 .irq_unmask = ksz_irq_unmask,
1809 .irq_bus_lock = ksz_irq_bus_lock,
1810 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock,
1811 };
1812
ksz_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)1813 static int ksz_irq_domain_map(struct irq_domain *d,
1814 unsigned int irq, irq_hw_number_t hwirq)
1815 {
1816 irq_set_chip_data(irq, d->host_data);
1817 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq);
1818 irq_set_noprobe(irq);
1819
1820 return 0;
1821 }
1822
1823 static const struct irq_domain_ops ksz_irq_domain_ops = {
1824 .map = ksz_irq_domain_map,
1825 .xlate = irq_domain_xlate_twocell,
1826 };
1827
ksz_irq_free(struct ksz_irq * kirq)1828 static void ksz_irq_free(struct ksz_irq *kirq)
1829 {
1830 int irq, virq;
1831
1832 free_irq(kirq->irq_num, kirq);
1833
1834 for (irq = 0; irq < kirq->nirqs; irq++) {
1835 virq = irq_find_mapping(kirq->domain, irq);
1836 irq_dispose_mapping(virq);
1837 }
1838
1839 irq_domain_remove(kirq->domain);
1840 }
1841
ksz_irq_thread_fn(int irq,void * dev_id)1842 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id)
1843 {
1844 struct ksz_irq *kirq = dev_id;
1845 unsigned int nhandled = 0;
1846 struct ksz_device *dev;
1847 unsigned int sub_irq;
1848 u8 data;
1849 int ret;
1850 u8 n;
1851
1852 dev = kirq->dev;
1853
1854 /* Read interrupt status register */
1855 ret = ksz_read8(dev, kirq->reg_status, &data);
1856 if (ret)
1857 goto out;
1858
1859 for (n = 0; n < kirq->nirqs; ++n) {
1860 if (data & BIT(n)) {
1861 sub_irq = irq_find_mapping(kirq->domain, n);
1862 handle_nested_irq(sub_irq);
1863 ++nhandled;
1864 }
1865 }
1866 out:
1867 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
1868 }
1869
ksz_irq_common_setup(struct ksz_device * dev,struct ksz_irq * kirq)1870 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq)
1871 {
1872 int ret, n;
1873
1874 kirq->dev = dev;
1875 kirq->masked = ~0;
1876
1877 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0,
1878 &ksz_irq_domain_ops, kirq);
1879 if (!kirq->domain)
1880 return -ENOMEM;
1881
1882 for (n = 0; n < kirq->nirqs; n++)
1883 irq_create_mapping(kirq->domain, n);
1884
1885 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn,
1886 IRQF_ONESHOT, kirq->name, kirq);
1887 if (ret)
1888 goto out;
1889
1890 return 0;
1891
1892 out:
1893 ksz_irq_free(kirq);
1894
1895 return ret;
1896 }
1897
ksz_girq_setup(struct ksz_device * dev)1898 static int ksz_girq_setup(struct ksz_device *dev)
1899 {
1900 struct ksz_irq *girq = &dev->girq;
1901
1902 girq->nirqs = dev->info->port_cnt;
1903 girq->reg_mask = REG_SW_PORT_INT_MASK__1;
1904 girq->reg_status = REG_SW_PORT_INT_STATUS__1;
1905 snprintf(girq->name, sizeof(girq->name), "global_port_irq");
1906
1907 girq->irq_num = dev->irq;
1908
1909 return ksz_irq_common_setup(dev, girq);
1910 }
1911
ksz_pirq_setup(struct ksz_device * dev,u8 p)1912 static int ksz_pirq_setup(struct ksz_device *dev, u8 p)
1913 {
1914 struct ksz_irq *pirq = &dev->ports[p].pirq;
1915
1916 pirq->nirqs = dev->info->port_nirqs;
1917 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK);
1918 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS);
1919 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p);
1920
1921 pirq->irq_num = irq_find_mapping(dev->girq.domain, p);
1922 if (pirq->irq_num < 0)
1923 return pirq->irq_num;
1924
1925 return ksz_irq_common_setup(dev, pirq);
1926 }
1927
ksz_setup(struct dsa_switch * ds)1928 static int ksz_setup(struct dsa_switch *ds)
1929 {
1930 struct ksz_device *dev = ds->priv;
1931 struct dsa_port *dp;
1932 struct ksz_port *p;
1933 const u16 *regs;
1934 int ret;
1935
1936 regs = dev->info->regs;
1937
1938 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
1939 dev->info->num_vlans, GFP_KERNEL);
1940 if (!dev->vlan_cache)
1941 return -ENOMEM;
1942
1943 ret = dev->dev_ops->reset(dev);
1944 if (ret) {
1945 dev_err(ds->dev, "failed to reset switch\n");
1946 return ret;
1947 }
1948
1949 /* set broadcast storm protection 10% rate */
1950 regmap_update_bits(dev->regmap[1], regs[S_BROADCAST_CTRL],
1951 BROADCAST_STORM_RATE,
1952 (BROADCAST_STORM_VALUE *
1953 BROADCAST_STORM_PROT_RATE) / 100);
1954
1955 dev->dev_ops->config_cpu_port(ds);
1956
1957 dev->dev_ops->enable_stp_addr(dev);
1958
1959 regmap_update_bits(dev->regmap[0], regs[S_MULTICAST_CTRL],
1960 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
1961
1962 ksz_init_mib_timer(dev);
1963
1964 ds->configure_vlan_while_not_filtering = false;
1965
1966 if (dev->dev_ops->setup) {
1967 ret = dev->dev_ops->setup(ds);
1968 if (ret)
1969 return ret;
1970 }
1971
1972 /* Start with learning disabled on standalone user ports, and enabled
1973 * on the CPU port. In lack of other finer mechanisms, learning on the
1974 * CPU port will avoid flooding bridge local addresses on the network
1975 * in some cases.
1976 */
1977 p = &dev->ports[dev->cpu_port];
1978 p->learning = true;
1979
1980 if (dev->irq > 0) {
1981 ret = ksz_girq_setup(dev);
1982 if (ret)
1983 return ret;
1984
1985 dsa_switch_for_each_user_port(dp, dev->ds) {
1986 ret = ksz_pirq_setup(dev, dp->index);
1987 if (ret)
1988 goto out_girq;
1989 }
1990 }
1991
1992 ret = ksz_mdio_register(dev);
1993 if (ret < 0) {
1994 dev_err(dev->dev, "failed to register the mdio");
1995 goto out_pirq;
1996 }
1997
1998 /* start switch */
1999 regmap_update_bits(dev->regmap[0], regs[S_START_CTRL],
2000 SW_START, SW_START);
2001
2002 return 0;
2003
2004 out_pirq:
2005 if (dev->irq > 0)
2006 dsa_switch_for_each_user_port(dp, dev->ds)
2007 ksz_irq_free(&dev->ports[dp->index].pirq);
2008 out_girq:
2009 if (dev->irq > 0)
2010 ksz_irq_free(&dev->girq);
2011
2012 return ret;
2013 }
2014
ksz_teardown(struct dsa_switch * ds)2015 static void ksz_teardown(struct dsa_switch *ds)
2016 {
2017 struct ksz_device *dev = ds->priv;
2018 struct dsa_port *dp;
2019
2020 if (dev->irq > 0) {
2021 dsa_switch_for_each_user_port(dp, dev->ds)
2022 ksz_irq_free(&dev->ports[dp->index].pirq);
2023
2024 ksz_irq_free(&dev->girq);
2025 }
2026
2027 if (dev->dev_ops->teardown)
2028 dev->dev_ops->teardown(ds);
2029 }
2030
port_r_cnt(struct ksz_device * dev,int port)2031 static void port_r_cnt(struct ksz_device *dev, int port)
2032 {
2033 struct ksz_port_mib *mib = &dev->ports[port].mib;
2034 u64 *dropped;
2035
2036 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
2037 while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
2038 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
2039 &mib->counters[mib->cnt_ptr]);
2040 ++mib->cnt_ptr;
2041 }
2042
2043 /* last one in storage */
2044 dropped = &mib->counters[dev->info->mib_cnt];
2045
2046 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
2047 while (mib->cnt_ptr < dev->info->mib_cnt) {
2048 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
2049 dropped, &mib->counters[mib->cnt_ptr]);
2050 ++mib->cnt_ptr;
2051 }
2052 mib->cnt_ptr = 0;
2053 }
2054
ksz_mib_read_work(struct work_struct * work)2055 static void ksz_mib_read_work(struct work_struct *work)
2056 {
2057 struct ksz_device *dev = container_of(work, struct ksz_device,
2058 mib_read.work);
2059 struct ksz_port_mib *mib;
2060 struct ksz_port *p;
2061 int i;
2062
2063 for (i = 0; i < dev->info->port_cnt; i++) {
2064 if (dsa_is_unused_port(dev->ds, i))
2065 continue;
2066
2067 p = &dev->ports[i];
2068 mib = &p->mib;
2069 mutex_lock(&mib->cnt_mutex);
2070
2071 /* Only read MIB counters when the port is told to do.
2072 * If not, read only dropped counters when link is not up.
2073 */
2074 if (!p->read) {
2075 const struct dsa_port *dp = dsa_to_port(dev->ds, i);
2076
2077 if (!netif_carrier_ok(dp->slave))
2078 mib->cnt_ptr = dev->info->reg_mib_cnt;
2079 }
2080 port_r_cnt(dev, i);
2081 p->read = false;
2082
2083 if (dev->dev_ops->r_mib_stat64)
2084 dev->dev_ops->r_mib_stat64(dev, i);
2085
2086 mutex_unlock(&mib->cnt_mutex);
2087 }
2088
2089 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval);
2090 }
2091
ksz_init_mib_timer(struct ksz_device * dev)2092 void ksz_init_mib_timer(struct ksz_device *dev)
2093 {
2094 int i;
2095
2096 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work);
2097
2098 for (i = 0; i < dev->info->port_cnt; i++) {
2099 struct ksz_port_mib *mib = &dev->ports[i].mib;
2100
2101 dev->dev_ops->port_init_cnt(dev, i);
2102
2103 mib->cnt_ptr = 0;
2104 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64));
2105 }
2106 }
2107
ksz_phy_read16(struct dsa_switch * ds,int addr,int reg)2108 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg)
2109 {
2110 struct ksz_device *dev = ds->priv;
2111 u16 val = 0xffff;
2112 int ret;
2113
2114 ret = dev->dev_ops->r_phy(dev, addr, reg, &val);
2115 if (ret)
2116 return ret;
2117
2118 return val;
2119 }
2120
ksz_phy_write16(struct dsa_switch * ds,int addr,int reg,u16 val)2121 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
2122 {
2123 struct ksz_device *dev = ds->priv;
2124 int ret;
2125
2126 ret = dev->dev_ops->w_phy(dev, addr, reg, val);
2127 if (ret)
2128 return ret;
2129
2130 return 0;
2131 }
2132
ksz_get_phy_flags(struct dsa_switch * ds,int port)2133 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port)
2134 {
2135 struct ksz_device *dev = ds->priv;
2136
2137 if (dev->chip_id == KSZ8830_CHIP_ID) {
2138 /* Silicon Errata Sheet (DS80000830A):
2139 * Port 1 does not work with LinkMD Cable-Testing.
2140 * Port 1 does not respond to received PAUSE control frames.
2141 */
2142 if (!port)
2143 return MICREL_KSZ8_P1_ERRATA;
2144 }
2145
2146 return 0;
2147 }
2148
ksz_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)2149 static void ksz_mac_link_down(struct dsa_switch *ds, int port,
2150 unsigned int mode, phy_interface_t interface)
2151 {
2152 struct ksz_device *dev = ds->priv;
2153 struct ksz_port *p = &dev->ports[port];
2154
2155 /* Read all MIB counters when the link is going down. */
2156 p->read = true;
2157 /* timer started */
2158 if (dev->mib_read_interval)
2159 schedule_delayed_work(&dev->mib_read, 0);
2160 }
2161
ksz_sset_count(struct dsa_switch * ds,int port,int sset)2162 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset)
2163 {
2164 struct ksz_device *dev = ds->priv;
2165
2166 if (sset != ETH_SS_STATS)
2167 return 0;
2168
2169 return dev->info->mib_cnt;
2170 }
2171
ksz_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * buf)2172 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
2173 uint64_t *buf)
2174 {
2175 const struct dsa_port *dp = dsa_to_port(ds, port);
2176 struct ksz_device *dev = ds->priv;
2177 struct ksz_port_mib *mib;
2178
2179 mib = &dev->ports[port].mib;
2180 mutex_lock(&mib->cnt_mutex);
2181
2182 /* Only read dropped counters if no link. */
2183 if (!netif_carrier_ok(dp->slave))
2184 mib->cnt_ptr = dev->info->reg_mib_cnt;
2185 port_r_cnt(dev, port);
2186 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64));
2187 mutex_unlock(&mib->cnt_mutex);
2188 }
2189
ksz_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)2190 static int ksz_port_bridge_join(struct dsa_switch *ds, int port,
2191 struct dsa_bridge bridge,
2192 bool *tx_fwd_offload,
2193 struct netlink_ext_ack *extack)
2194 {
2195 /* port_stp_state_set() will be called after to put the port in
2196 * appropriate state so there is no need to do anything.
2197 */
2198
2199 return 0;
2200 }
2201
ksz_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)2202 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port,
2203 struct dsa_bridge bridge)
2204 {
2205 /* port_stp_state_set() will be called after to put the port in
2206 * forwarding state so there is no need to do anything.
2207 */
2208 }
2209
ksz_port_fast_age(struct dsa_switch * ds,int port)2210 static void ksz_port_fast_age(struct dsa_switch *ds, int port)
2211 {
2212 struct ksz_device *dev = ds->priv;
2213
2214 dev->dev_ops->flush_dyn_mac_table(dev, port);
2215 }
2216
ksz_set_ageing_time(struct dsa_switch * ds,unsigned int msecs)2217 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
2218 {
2219 struct ksz_device *dev = ds->priv;
2220
2221 if (!dev->dev_ops->set_ageing_time)
2222 return -EOPNOTSUPP;
2223
2224 return dev->dev_ops->set_ageing_time(dev, msecs);
2225 }
2226
ksz_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2227 static int ksz_port_fdb_add(struct dsa_switch *ds, int port,
2228 const unsigned char *addr, u16 vid,
2229 struct dsa_db db)
2230 {
2231 struct ksz_device *dev = ds->priv;
2232
2233 if (!dev->dev_ops->fdb_add)
2234 return -EOPNOTSUPP;
2235
2236 return dev->dev_ops->fdb_add(dev, port, addr, vid, db);
2237 }
2238
ksz_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2239 static int ksz_port_fdb_del(struct dsa_switch *ds, int port,
2240 const unsigned char *addr,
2241 u16 vid, struct dsa_db db)
2242 {
2243 struct ksz_device *dev = ds->priv;
2244
2245 if (!dev->dev_ops->fdb_del)
2246 return -EOPNOTSUPP;
2247
2248 return dev->dev_ops->fdb_del(dev, port, addr, vid, db);
2249 }
2250
ksz_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)2251 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port,
2252 dsa_fdb_dump_cb_t *cb, void *data)
2253 {
2254 struct ksz_device *dev = ds->priv;
2255
2256 if (!dev->dev_ops->fdb_dump)
2257 return -EOPNOTSUPP;
2258
2259 return dev->dev_ops->fdb_dump(dev, port, cb, data);
2260 }
2261
ksz_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)2262 static int ksz_port_mdb_add(struct dsa_switch *ds, int port,
2263 const struct switchdev_obj_port_mdb *mdb,
2264 struct dsa_db db)
2265 {
2266 struct ksz_device *dev = ds->priv;
2267
2268 if (!dev->dev_ops->mdb_add)
2269 return -EOPNOTSUPP;
2270
2271 return dev->dev_ops->mdb_add(dev, port, mdb, db);
2272 }
2273
ksz_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)2274 static int ksz_port_mdb_del(struct dsa_switch *ds, int port,
2275 const struct switchdev_obj_port_mdb *mdb,
2276 struct dsa_db db)
2277 {
2278 struct ksz_device *dev = ds->priv;
2279
2280 if (!dev->dev_ops->mdb_del)
2281 return -EOPNOTSUPP;
2282
2283 return dev->dev_ops->mdb_del(dev, port, mdb, db);
2284 }
2285
ksz_enable_port(struct dsa_switch * ds,int port,struct phy_device * phy)2286 static int ksz_enable_port(struct dsa_switch *ds, int port,
2287 struct phy_device *phy)
2288 {
2289 struct ksz_device *dev = ds->priv;
2290
2291 if (!dsa_is_user_port(ds, port))
2292 return 0;
2293
2294 /* setup slave port */
2295 dev->dev_ops->port_setup(dev, port, false);
2296
2297 /* port_stp_state_set() will be called after to enable the port so
2298 * there is no need to do anything.
2299 */
2300
2301 return 0;
2302 }
2303
ksz_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)2304 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
2305 {
2306 struct ksz_device *dev = ds->priv;
2307 struct ksz_port *p;
2308 const u16 *regs;
2309 u8 data;
2310
2311 regs = dev->info->regs;
2312
2313 ksz_pread8(dev, port, regs[P_STP_CTRL], &data);
2314 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2315
2316 p = &dev->ports[port];
2317
2318 switch (state) {
2319 case BR_STATE_DISABLED:
2320 data |= PORT_LEARN_DISABLE;
2321 break;
2322 case BR_STATE_LISTENING:
2323 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2324 break;
2325 case BR_STATE_LEARNING:
2326 data |= PORT_RX_ENABLE;
2327 if (!p->learning)
2328 data |= PORT_LEARN_DISABLE;
2329 break;
2330 case BR_STATE_FORWARDING:
2331 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2332 if (!p->learning)
2333 data |= PORT_LEARN_DISABLE;
2334 break;
2335 case BR_STATE_BLOCKING:
2336 data |= PORT_LEARN_DISABLE;
2337 break;
2338 default:
2339 dev_err(ds->dev, "invalid STP state: %d\n", state);
2340 return;
2341 }
2342
2343 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data);
2344
2345 p->stp_state = state;
2346
2347 ksz_update_port_member(dev, port);
2348 }
2349
ksz_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)2350 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port,
2351 struct switchdev_brport_flags flags,
2352 struct netlink_ext_ack *extack)
2353 {
2354 if (flags.mask & ~BR_LEARNING)
2355 return -EINVAL;
2356
2357 return 0;
2358 }
2359
ksz_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)2360 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port,
2361 struct switchdev_brport_flags flags,
2362 struct netlink_ext_ack *extack)
2363 {
2364 struct ksz_device *dev = ds->priv;
2365 struct ksz_port *p = &dev->ports[port];
2366
2367 if (flags.mask & BR_LEARNING) {
2368 p->learning = !!(flags.val & BR_LEARNING);
2369
2370 /* Make the change take effect immediately */
2371 ksz_port_stp_state_set(ds, port, p->stp_state);
2372 }
2373
2374 return 0;
2375 }
2376
ksz_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)2377 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,
2378 int port,
2379 enum dsa_tag_protocol mp)
2380 {
2381 struct ksz_device *dev = ds->priv;
2382 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE;
2383
2384 if (dev->chip_id == KSZ8795_CHIP_ID ||
2385 dev->chip_id == KSZ8794_CHIP_ID ||
2386 dev->chip_id == KSZ8765_CHIP_ID)
2387 proto = DSA_TAG_PROTO_KSZ8795;
2388
2389 if (dev->chip_id == KSZ8830_CHIP_ID ||
2390 dev->chip_id == KSZ8563_CHIP_ID ||
2391 dev->chip_id == KSZ9893_CHIP_ID)
2392 proto = DSA_TAG_PROTO_KSZ9893;
2393
2394 if (dev->chip_id == KSZ9477_CHIP_ID ||
2395 dev->chip_id == KSZ9896_CHIP_ID ||
2396 dev->chip_id == KSZ9897_CHIP_ID ||
2397 dev->chip_id == KSZ9567_CHIP_ID)
2398 proto = DSA_TAG_PROTO_KSZ9477;
2399
2400 if (is_lan937x(dev))
2401 proto = DSA_TAG_PROTO_LAN937X_VALUE;
2402
2403 return proto;
2404 }
2405
ksz_port_vlan_filtering(struct dsa_switch * ds,int port,bool flag,struct netlink_ext_ack * extack)2406 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port,
2407 bool flag, struct netlink_ext_ack *extack)
2408 {
2409 struct ksz_device *dev = ds->priv;
2410
2411 if (!dev->dev_ops->vlan_filtering)
2412 return -EOPNOTSUPP;
2413
2414 return dev->dev_ops->vlan_filtering(dev, port, flag, extack);
2415 }
2416
ksz_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)2417 static int ksz_port_vlan_add(struct dsa_switch *ds, int port,
2418 const struct switchdev_obj_port_vlan *vlan,
2419 struct netlink_ext_ack *extack)
2420 {
2421 struct ksz_device *dev = ds->priv;
2422
2423 if (!dev->dev_ops->vlan_add)
2424 return -EOPNOTSUPP;
2425
2426 return dev->dev_ops->vlan_add(dev, port, vlan, extack);
2427 }
2428
ksz_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)2429 static int ksz_port_vlan_del(struct dsa_switch *ds, int port,
2430 const struct switchdev_obj_port_vlan *vlan)
2431 {
2432 struct ksz_device *dev = ds->priv;
2433
2434 if (!dev->dev_ops->vlan_del)
2435 return -EOPNOTSUPP;
2436
2437 return dev->dev_ops->vlan_del(dev, port, vlan);
2438 }
2439
ksz_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)2440 static int ksz_port_mirror_add(struct dsa_switch *ds, int port,
2441 struct dsa_mall_mirror_tc_entry *mirror,
2442 bool ingress, struct netlink_ext_ack *extack)
2443 {
2444 struct ksz_device *dev = ds->priv;
2445
2446 if (!dev->dev_ops->mirror_add)
2447 return -EOPNOTSUPP;
2448
2449 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack);
2450 }
2451
ksz_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)2452 static void ksz_port_mirror_del(struct dsa_switch *ds, int port,
2453 struct dsa_mall_mirror_tc_entry *mirror)
2454 {
2455 struct ksz_device *dev = ds->priv;
2456
2457 if (dev->dev_ops->mirror_del)
2458 dev->dev_ops->mirror_del(dev, port, mirror);
2459 }
2460
ksz_change_mtu(struct dsa_switch * ds,int port,int mtu)2461 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu)
2462 {
2463 struct ksz_device *dev = ds->priv;
2464
2465 if (!dev->dev_ops->change_mtu)
2466 return -EOPNOTSUPP;
2467
2468 return dev->dev_ops->change_mtu(dev, port, mtu);
2469 }
2470
ksz_max_mtu(struct dsa_switch * ds,int port)2471 static int ksz_max_mtu(struct dsa_switch *ds, int port)
2472 {
2473 struct ksz_device *dev = ds->priv;
2474
2475 if (!dev->dev_ops->max_mtu)
2476 return -EOPNOTSUPP;
2477
2478 return dev->dev_ops->max_mtu(dev, port);
2479 }
2480
ksz_set_xmii(struct ksz_device * dev,int port,phy_interface_t interface)2481 static void ksz_set_xmii(struct ksz_device *dev, int port,
2482 phy_interface_t interface)
2483 {
2484 const u8 *bitval = dev->info->xmii_ctrl1;
2485 struct ksz_port *p = &dev->ports[port];
2486 const u16 *regs = dev->info->regs;
2487 u8 data8;
2488
2489 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2490
2491 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
2492 P_RGMII_ID_EG_ENABLE);
2493
2494 switch (interface) {
2495 case PHY_INTERFACE_MODE_MII:
2496 data8 |= bitval[P_MII_SEL];
2497 break;
2498 case PHY_INTERFACE_MODE_RMII:
2499 data8 |= bitval[P_RMII_SEL];
2500 break;
2501 case PHY_INTERFACE_MODE_GMII:
2502 data8 |= bitval[P_GMII_SEL];
2503 break;
2504 case PHY_INTERFACE_MODE_RGMII:
2505 case PHY_INTERFACE_MODE_RGMII_ID:
2506 case PHY_INTERFACE_MODE_RGMII_TXID:
2507 case PHY_INTERFACE_MODE_RGMII_RXID:
2508 data8 |= bitval[P_RGMII_SEL];
2509 /* On KSZ9893, disable RGMII in-band status support */
2510 if (dev->chip_id == KSZ9893_CHIP_ID ||
2511 dev->chip_id == KSZ8563_CHIP_ID)
2512 data8 &= ~P_MII_MAC_MODE;
2513 break;
2514 default:
2515 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
2516 phy_modes(interface), port);
2517 return;
2518 }
2519
2520 if (p->rgmii_tx_val)
2521 data8 |= P_RGMII_ID_EG_ENABLE;
2522
2523 if (p->rgmii_rx_val)
2524 data8 |= P_RGMII_ID_IG_ENABLE;
2525
2526 /* Write the updated value */
2527 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
2528 }
2529
ksz_get_xmii(struct ksz_device * dev,int port,bool gbit)2530 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)
2531 {
2532 const u8 *bitval = dev->info->xmii_ctrl1;
2533 const u16 *regs = dev->info->regs;
2534 phy_interface_t interface;
2535 u8 data8;
2536 u8 val;
2537
2538 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2539
2540 val = FIELD_GET(P_MII_SEL_M, data8);
2541
2542 if (val == bitval[P_MII_SEL]) {
2543 if (gbit)
2544 interface = PHY_INTERFACE_MODE_GMII;
2545 else
2546 interface = PHY_INTERFACE_MODE_MII;
2547 } else if (val == bitval[P_RMII_SEL]) {
2548 interface = PHY_INTERFACE_MODE_RGMII;
2549 } else {
2550 interface = PHY_INTERFACE_MODE_RGMII;
2551 if (data8 & P_RGMII_ID_EG_ENABLE)
2552 interface = PHY_INTERFACE_MODE_RGMII_TXID;
2553 if (data8 & P_RGMII_ID_IG_ENABLE) {
2554 interface = PHY_INTERFACE_MODE_RGMII_RXID;
2555 if (data8 & P_RGMII_ID_EG_ENABLE)
2556 interface = PHY_INTERFACE_MODE_RGMII_ID;
2557 }
2558 }
2559
2560 return interface;
2561 }
2562
ksz_phylink_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)2563 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,
2564 unsigned int mode,
2565 const struct phylink_link_state *state)
2566 {
2567 struct ksz_device *dev = ds->priv;
2568
2569 if (ksz_is_ksz88x3(dev))
2570 return;
2571
2572 /* Internal PHYs */
2573 if (dev->info->internal_phy[port])
2574 return;
2575
2576 if (phylink_autoneg_inband(mode)) {
2577 dev_err(dev->dev, "In-band AN not supported!\n");
2578 return;
2579 }
2580
2581 ksz_set_xmii(dev, port, state->interface);
2582
2583 if (dev->dev_ops->phylink_mac_config)
2584 dev->dev_ops->phylink_mac_config(dev, port, mode, state);
2585
2586 if (dev->dev_ops->setup_rgmii_delay)
2587 dev->dev_ops->setup_rgmii_delay(dev, port);
2588 }
2589
ksz_get_gbit(struct ksz_device * dev,int port)2590 bool ksz_get_gbit(struct ksz_device *dev, int port)
2591 {
2592 const u8 *bitval = dev->info->xmii_ctrl1;
2593 const u16 *regs = dev->info->regs;
2594 bool gbit = false;
2595 u8 data8;
2596 bool val;
2597
2598 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2599
2600 val = FIELD_GET(P_GMII_1GBIT_M, data8);
2601
2602 if (val == bitval[P_GMII_1GBIT])
2603 gbit = true;
2604
2605 return gbit;
2606 }
2607
ksz_set_gbit(struct ksz_device * dev,int port,bool gbit)2608 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
2609 {
2610 const u8 *bitval = dev->info->xmii_ctrl1;
2611 const u16 *regs = dev->info->regs;
2612 u8 data8;
2613
2614 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2615
2616 data8 &= ~P_GMII_1GBIT_M;
2617
2618 if (gbit)
2619 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]);
2620 else
2621 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
2622
2623 /* Write the updated value */
2624 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
2625 }
2626
ksz_set_100_10mbit(struct ksz_device * dev,int port,int speed)2627 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
2628 {
2629 const u8 *bitval = dev->info->xmii_ctrl0;
2630 const u16 *regs = dev->info->regs;
2631 u8 data8;
2632
2633 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
2634
2635 data8 &= ~P_MII_100MBIT_M;
2636
2637 if (speed == SPEED_100)
2638 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);
2639 else
2640 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);
2641
2642 /* Write the updated value */
2643 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
2644 }
2645
ksz_port_set_xmii_speed(struct ksz_device * dev,int port,int speed)2646 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
2647 {
2648 if (speed == SPEED_1000)
2649 ksz_set_gbit(dev, port, true);
2650 else
2651 ksz_set_gbit(dev, port, false);
2652
2653 if (speed == SPEED_100 || speed == SPEED_10)
2654 ksz_set_100_10mbit(dev, port, speed);
2655 }
2656
ksz_duplex_flowctrl(struct ksz_device * dev,int port,int duplex,bool tx_pause,bool rx_pause)2657 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
2658 bool tx_pause, bool rx_pause)
2659 {
2660 const u8 *bitval = dev->info->xmii_ctrl0;
2661 const u32 *masks = dev->info->masks;
2662 const u16 *regs = dev->info->regs;
2663 u8 mask;
2664 u8 val;
2665
2666 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] |
2667 masks[P_MII_RX_FLOW_CTRL];
2668
2669 if (duplex == DUPLEX_FULL)
2670 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]);
2671 else
2672 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]);
2673
2674 if (tx_pause)
2675 val |= masks[P_MII_TX_FLOW_CTRL];
2676
2677 if (rx_pause)
2678 val |= masks[P_MII_RX_FLOW_CTRL];
2679
2680 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val);
2681 }
2682
ksz9477_phylink_mac_link_up(struct ksz_device * dev,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)2683 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port,
2684 unsigned int mode,
2685 phy_interface_t interface,
2686 struct phy_device *phydev, int speed,
2687 int duplex, bool tx_pause,
2688 bool rx_pause)
2689 {
2690 struct ksz_port *p;
2691
2692 p = &dev->ports[port];
2693
2694 /* Internal PHYs */
2695 if (dev->info->internal_phy[port])
2696 return;
2697
2698 p->phydev.speed = speed;
2699
2700 ksz_port_set_xmii_speed(dev, port, speed);
2701
2702 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);
2703 }
2704
ksz_phylink_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)2705 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
2706 unsigned int mode,
2707 phy_interface_t interface,
2708 struct phy_device *phydev, int speed,
2709 int duplex, bool tx_pause, bool rx_pause)
2710 {
2711 struct ksz_device *dev = ds->priv;
2712
2713 if (dev->dev_ops->phylink_mac_link_up)
2714 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface,
2715 phydev, speed, duplex,
2716 tx_pause, rx_pause);
2717 }
2718
ksz_switch_detect(struct ksz_device * dev)2719 static int ksz_switch_detect(struct ksz_device *dev)
2720 {
2721 u8 id1, id2, id4;
2722 u16 id16;
2723 u32 id32;
2724 int ret;
2725
2726 /* read chip id */
2727 ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
2728 if (ret)
2729 return ret;
2730
2731 id1 = FIELD_GET(SW_FAMILY_ID_M, id16);
2732 id2 = FIELD_GET(SW_CHIP_ID_M, id16);
2733
2734 switch (id1) {
2735 case KSZ87_FAMILY_ID:
2736 if (id2 == KSZ87_CHIP_ID_95) {
2737 u8 val;
2738
2739 dev->chip_id = KSZ8795_CHIP_ID;
2740
2741 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val);
2742 if (val & KSZ8_PORT_FIBER_MODE)
2743 dev->chip_id = KSZ8765_CHIP_ID;
2744 } else if (id2 == KSZ87_CHIP_ID_94) {
2745 dev->chip_id = KSZ8794_CHIP_ID;
2746 } else {
2747 return -ENODEV;
2748 }
2749 break;
2750 case KSZ88_FAMILY_ID:
2751 if (id2 == KSZ88_CHIP_ID_63)
2752 dev->chip_id = KSZ8830_CHIP_ID;
2753 else
2754 return -ENODEV;
2755 break;
2756 default:
2757 ret = ksz_read32(dev, REG_CHIP_ID0, &id32);
2758 if (ret)
2759 return ret;
2760
2761 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32);
2762 id32 &= ~0xFF;
2763
2764 switch (id32) {
2765 case KSZ9477_CHIP_ID:
2766 case KSZ9896_CHIP_ID:
2767 case KSZ9897_CHIP_ID:
2768 case KSZ9567_CHIP_ID:
2769 case LAN9370_CHIP_ID:
2770 case LAN9371_CHIP_ID:
2771 case LAN9372_CHIP_ID:
2772 case LAN9373_CHIP_ID:
2773 case LAN9374_CHIP_ID:
2774 dev->chip_id = id32;
2775 break;
2776 case KSZ9893_CHIP_ID:
2777 ret = ksz_read8(dev, REG_CHIP_ID4,
2778 &id4);
2779 if (ret)
2780 return ret;
2781
2782 if (id4 == SKU_ID_KSZ8563)
2783 dev->chip_id = KSZ8563_CHIP_ID;
2784 else
2785 dev->chip_id = KSZ9893_CHIP_ID;
2786
2787 break;
2788 default:
2789 dev_err(dev->dev,
2790 "unsupported switch detected %x)\n", id32);
2791 return -ENODEV;
2792 }
2793 }
2794 return 0;
2795 }
2796
2797 static const struct dsa_switch_ops ksz_switch_ops = {
2798 .get_tag_protocol = ksz_get_tag_protocol,
2799 .get_phy_flags = ksz_get_phy_flags,
2800 .setup = ksz_setup,
2801 .teardown = ksz_teardown,
2802 .phy_read = ksz_phy_read16,
2803 .phy_write = ksz_phy_write16,
2804 .phylink_get_caps = ksz_phylink_get_caps,
2805 .phylink_mac_config = ksz_phylink_mac_config,
2806 .phylink_mac_link_up = ksz_phylink_mac_link_up,
2807 .phylink_mac_link_down = ksz_mac_link_down,
2808 .port_enable = ksz_enable_port,
2809 .set_ageing_time = ksz_set_ageing_time,
2810 .get_strings = ksz_get_strings,
2811 .get_ethtool_stats = ksz_get_ethtool_stats,
2812 .get_sset_count = ksz_sset_count,
2813 .port_bridge_join = ksz_port_bridge_join,
2814 .port_bridge_leave = ksz_port_bridge_leave,
2815 .port_stp_state_set = ksz_port_stp_state_set,
2816 .port_pre_bridge_flags = ksz_port_pre_bridge_flags,
2817 .port_bridge_flags = ksz_port_bridge_flags,
2818 .port_fast_age = ksz_port_fast_age,
2819 .port_vlan_filtering = ksz_port_vlan_filtering,
2820 .port_vlan_add = ksz_port_vlan_add,
2821 .port_vlan_del = ksz_port_vlan_del,
2822 .port_fdb_dump = ksz_port_fdb_dump,
2823 .port_fdb_add = ksz_port_fdb_add,
2824 .port_fdb_del = ksz_port_fdb_del,
2825 .port_mdb_add = ksz_port_mdb_add,
2826 .port_mdb_del = ksz_port_mdb_del,
2827 .port_mirror_add = ksz_port_mirror_add,
2828 .port_mirror_del = ksz_port_mirror_del,
2829 .get_stats64 = ksz_get_stats64,
2830 .get_pause_stats = ksz_get_pause_stats,
2831 .port_change_mtu = ksz_change_mtu,
2832 .port_max_mtu = ksz_max_mtu,
2833 };
2834
ksz_switch_alloc(struct device * base,void * priv)2835 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv)
2836 {
2837 struct dsa_switch *ds;
2838 struct ksz_device *swdev;
2839
2840 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
2841 if (!ds)
2842 return NULL;
2843
2844 ds->dev = base;
2845 ds->num_ports = DSA_MAX_PORTS;
2846 ds->ops = &ksz_switch_ops;
2847
2848 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL);
2849 if (!swdev)
2850 return NULL;
2851
2852 ds->priv = swdev;
2853 swdev->dev = base;
2854
2855 swdev->ds = ds;
2856 swdev->priv = priv;
2857
2858 return swdev;
2859 }
2860 EXPORT_SYMBOL(ksz_switch_alloc);
2861
ksz_parse_rgmii_delay(struct ksz_device * dev,int port_num,struct device_node * port_dn)2862 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num,
2863 struct device_node *port_dn)
2864 {
2865 phy_interface_t phy_mode = dev->ports[port_num].interface;
2866 int rx_delay = -1, tx_delay = -1;
2867
2868 if (!phy_interface_mode_is_rgmii(phy_mode))
2869 return;
2870
2871 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
2872 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
2873
2874 if (rx_delay == -1 && tx_delay == -1) {
2875 dev_warn(dev->dev,
2876 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
2877 "please update device tree to specify \"rx-internal-delay-ps\" and "
2878 "\"tx-internal-delay-ps\"",
2879 port_num);
2880
2881 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
2882 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
2883 rx_delay = 2000;
2884
2885 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
2886 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
2887 tx_delay = 2000;
2888 }
2889
2890 if (rx_delay < 0)
2891 rx_delay = 0;
2892 if (tx_delay < 0)
2893 tx_delay = 0;
2894
2895 dev->ports[port_num].rgmii_rx_val = rx_delay;
2896 dev->ports[port_num].rgmii_tx_val = tx_delay;
2897 }
2898
ksz_switch_register(struct ksz_device * dev)2899 int ksz_switch_register(struct ksz_device *dev)
2900 {
2901 const struct ksz_chip_data *info;
2902 struct device_node *port, *ports;
2903 phy_interface_t interface;
2904 unsigned int port_num;
2905 int ret;
2906 int i;
2907
2908 if (dev->pdata)
2909 dev->chip_id = dev->pdata->chip_id;
2910
2911 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset",
2912 GPIOD_OUT_LOW);
2913 if (IS_ERR(dev->reset_gpio))
2914 return PTR_ERR(dev->reset_gpio);
2915
2916 if (dev->reset_gpio) {
2917 gpiod_set_value_cansleep(dev->reset_gpio, 1);
2918 usleep_range(10000, 12000);
2919 gpiod_set_value_cansleep(dev->reset_gpio, 0);
2920 msleep(100);
2921 }
2922
2923 mutex_init(&dev->dev_mutex);
2924 mutex_init(&dev->regmap_mutex);
2925 mutex_init(&dev->alu_mutex);
2926 mutex_init(&dev->vlan_mutex);
2927
2928 ret = ksz_switch_detect(dev);
2929 if (ret)
2930 return ret;
2931
2932 info = ksz_lookup_info(dev->chip_id);
2933 if (!info)
2934 return -ENODEV;
2935
2936 /* Update the compatible info with the probed one */
2937 dev->info = info;
2938
2939 dev_info(dev->dev, "found switch: %s, rev %i\n",
2940 dev->info->dev_name, dev->chip_rev);
2941
2942 ret = ksz_check_device_id(dev);
2943 if (ret)
2944 return ret;
2945
2946 dev->dev_ops = dev->info->ops;
2947
2948 ret = dev->dev_ops->init(dev);
2949 if (ret)
2950 return ret;
2951
2952 dev->ports = devm_kzalloc(dev->dev,
2953 dev->info->port_cnt * sizeof(struct ksz_port),
2954 GFP_KERNEL);
2955 if (!dev->ports)
2956 return -ENOMEM;
2957
2958 for (i = 0; i < dev->info->port_cnt; i++) {
2959 spin_lock_init(&dev->ports[i].mib.stats64_lock);
2960 mutex_init(&dev->ports[i].mib.cnt_mutex);
2961 dev->ports[i].mib.counters =
2962 devm_kzalloc(dev->dev,
2963 sizeof(u64) * (dev->info->mib_cnt + 1),
2964 GFP_KERNEL);
2965 if (!dev->ports[i].mib.counters)
2966 return -ENOMEM;
2967
2968 dev->ports[i].ksz_dev = dev;
2969 dev->ports[i].num = i;
2970 }
2971
2972 /* set the real number of ports */
2973 dev->ds->num_ports = dev->info->port_cnt;
2974
2975 /* Host port interface will be self detected, or specifically set in
2976 * device tree.
2977 */
2978 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num)
2979 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA;
2980 if (dev->dev->of_node) {
2981 ret = of_get_phy_mode(dev->dev->of_node, &interface);
2982 if (ret == 0)
2983 dev->compat_interface = interface;
2984 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports");
2985 if (!ports)
2986 ports = of_get_child_by_name(dev->dev->of_node, "ports");
2987 if (ports) {
2988 for_each_available_child_of_node(ports, port) {
2989 if (of_property_read_u32(port, "reg",
2990 &port_num))
2991 continue;
2992 if (!(dev->port_mask & BIT(port_num))) {
2993 of_node_put(port);
2994 of_node_put(ports);
2995 return -EINVAL;
2996 }
2997 of_get_phy_mode(port,
2998 &dev->ports[port_num].interface);
2999
3000 ksz_parse_rgmii_delay(dev, port_num, port);
3001 }
3002 of_node_put(ports);
3003 }
3004 dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
3005 "microchip,synclko-125");
3006 dev->synclko_disable = of_property_read_bool(dev->dev->of_node,
3007 "microchip,synclko-disable");
3008 if (dev->synclko_125 && dev->synclko_disable) {
3009 dev_err(dev->dev, "inconsistent synclko settings\n");
3010 return -EINVAL;
3011 }
3012 }
3013
3014 ret = dsa_register_switch(dev->ds);
3015 if (ret) {
3016 dev->dev_ops->exit(dev);
3017 return ret;
3018 }
3019
3020 /* Read MIB counters every 30 seconds to avoid overflow. */
3021 dev->mib_read_interval = msecs_to_jiffies(5000);
3022
3023 /* Start the MIB timer. */
3024 schedule_delayed_work(&dev->mib_read, 0);
3025
3026 return ret;
3027 }
3028 EXPORT_SYMBOL(ksz_switch_register);
3029
ksz_switch_remove(struct ksz_device * dev)3030 void ksz_switch_remove(struct ksz_device *dev)
3031 {
3032 /* timer started */
3033 if (dev->mib_read_interval) {
3034 dev->mib_read_interval = 0;
3035 cancel_delayed_work_sync(&dev->mib_read);
3036 }
3037
3038 dev->dev_ops->exit(dev);
3039 dsa_unregister_switch(dev->ds);
3040
3041 if (dev->reset_gpio)
3042 gpiod_set_value_cansleep(dev->reset_gpio, 1);
3043
3044 }
3045 EXPORT_SYMBOL(ksz_switch_remove);
3046
3047 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
3048 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
3049 MODULE_LICENSE("GPL");
3050