1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright © 2019-2020 Intel Corporation
4 */
5
6 #include <linux/clk.h>
7 #include <linux/delay.h>
8 #include <linux/of_graph.h>
9 #include <linux/mfd/syscon.h>
10 #include <linux/platform_device.h>
11 #include <linux/regmap.h>
12
13 #include <drm/drm_atomic_helper.h>
14 #include <drm/drm_bridge.h>
15 #include <drm/drm_bridge_connector.h>
16 #include <drm/drm_mipi_dsi.h>
17 #include <drm/drm_simple_kms_helper.h>
18 #include <drm/drm_print.h>
19 #include <drm/drm_probe_helper.h>
20
21 #include "kmb_dsi.h"
22 #include "kmb_regs.h"
23
24 static struct mipi_dsi_host *dsi_host;
25 static struct mipi_dsi_device *dsi_device;
26 static struct drm_bridge *adv_bridge;
27
28 /* Default setting is 1080p, 4 lanes */
29 #define IMG_HEIGHT_LINES 1080
30 #define IMG_WIDTH_PX 1920
31 #define MIPI_TX_ACTIVE_LANES 4
32
33 static struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = {
34 .width_pixels = IMG_WIDTH_PX,
35 .height_lines = IMG_HEIGHT_LINES,
36 .data_type = DSI_LP_DT_PPS_RGB888_24B,
37 .data_mode = MIPI_DATA_MODE1,
38 .dma_packed = 0
39 };
40
41 static struct mipi_tx_frame_cfg mipitx_frame0_cfg = {
42 .sections[0] = &mipi_tx_frame0_sect_cfg,
43 .sections[1] = NULL,
44 .sections[2] = NULL,
45 .sections[3] = NULL,
46 .vsync_width = 5,
47 .v_backporch = 36,
48 .v_frontporch = 4,
49 .hsync_width = 44,
50 .h_backporch = 148,
51 .h_frontporch = 88
52 };
53
54 static const struct mipi_tx_dsi_cfg mipitx_dsi_cfg = {
55 .hfp_blank_en = 0,
56 .eotp_en = 0,
57 .lpm_last_vfp_line = 0,
58 .lpm_first_vsa_line = 0,
59 .sync_pulse_eventn = DSI_VIDEO_MODE_NO_BURST_EVENT,
60 .hfp_blanking = SEND_BLANK_PACKET,
61 .hbp_blanking = SEND_BLANK_PACKET,
62 .hsa_blanking = SEND_BLANK_PACKET,
63 .v_blanking = SEND_BLANK_PACKET,
64 };
65
66 static struct mipi_ctrl_cfg mipi_tx_init_cfg = {
67 .active_lanes = MIPI_TX_ACTIVE_LANES,
68 .lane_rate_mbps = MIPI_TX_LANE_DATA_RATE_MBPS,
69 .ref_clk_khz = MIPI_TX_REF_CLK_KHZ,
70 .cfg_clk_khz = MIPI_TX_CFG_CLK_KHZ,
71 .tx_ctrl_cfg = {
72 .frames[0] = &mipitx_frame0_cfg,
73 .frames[1] = NULL,
74 .frames[2] = NULL,
75 .frames[3] = NULL,
76 .tx_dsi_cfg = &mipitx_dsi_cfg,
77 .line_sync_pkt_en = 0,
78 .line_counter_active = 0,
79 .frame_counter_active = 0,
80 .tx_always_use_hact = 1,
81 .tx_hact_wait_stop = 1,
82 }
83 };
84
85 struct mipi_hs_freq_range_cfg {
86 u16 default_bit_rate_mbps;
87 u8 hsfreqrange_code;
88 };
89
90 struct vco_params {
91 u32 freq;
92 u32 range;
93 u32 divider;
94 };
95
96 static const struct vco_params vco_table[] = {
97 {52, 0x3f, 8},
98 {80, 0x39, 8},
99 {105, 0x2f, 4},
100 {160, 0x29, 4},
101 {210, 0x1f, 2},
102 {320, 0x19, 2},
103 {420, 0x0f, 1},
104 {630, 0x09, 1},
105 {1100, 0x03, 1},
106 {0xffff, 0x01, 1},
107 };
108
109 static const struct mipi_hs_freq_range_cfg
110 mipi_hs_freq_range[MIPI_DPHY_DEFAULT_BIT_RATES] = {
111 {.default_bit_rate_mbps = 80, .hsfreqrange_code = 0x00},
112 {.default_bit_rate_mbps = 90, .hsfreqrange_code = 0x10},
113 {.default_bit_rate_mbps = 100, .hsfreqrange_code = 0x20},
114 {.default_bit_rate_mbps = 110, .hsfreqrange_code = 0x30},
115 {.default_bit_rate_mbps = 120, .hsfreqrange_code = 0x01},
116 {.default_bit_rate_mbps = 130, .hsfreqrange_code = 0x11},
117 {.default_bit_rate_mbps = 140, .hsfreqrange_code = 0x21},
118 {.default_bit_rate_mbps = 150, .hsfreqrange_code = 0x31},
119 {.default_bit_rate_mbps = 160, .hsfreqrange_code = 0x02},
120 {.default_bit_rate_mbps = 170, .hsfreqrange_code = 0x12},
121 {.default_bit_rate_mbps = 180, .hsfreqrange_code = 0x22},
122 {.default_bit_rate_mbps = 190, .hsfreqrange_code = 0x32},
123 {.default_bit_rate_mbps = 205, .hsfreqrange_code = 0x03},
124 {.default_bit_rate_mbps = 220, .hsfreqrange_code = 0x13},
125 {.default_bit_rate_mbps = 235, .hsfreqrange_code = 0x23},
126 {.default_bit_rate_mbps = 250, .hsfreqrange_code = 0x33},
127 {.default_bit_rate_mbps = 275, .hsfreqrange_code = 0x04},
128 {.default_bit_rate_mbps = 300, .hsfreqrange_code = 0x14},
129 {.default_bit_rate_mbps = 325, .hsfreqrange_code = 0x25},
130 {.default_bit_rate_mbps = 350, .hsfreqrange_code = 0x35},
131 {.default_bit_rate_mbps = 400, .hsfreqrange_code = 0x05},
132 {.default_bit_rate_mbps = 450, .hsfreqrange_code = 0x16},
133 {.default_bit_rate_mbps = 500, .hsfreqrange_code = 0x26},
134 {.default_bit_rate_mbps = 550, .hsfreqrange_code = 0x37},
135 {.default_bit_rate_mbps = 600, .hsfreqrange_code = 0x07},
136 {.default_bit_rate_mbps = 650, .hsfreqrange_code = 0x18},
137 {.default_bit_rate_mbps = 700, .hsfreqrange_code = 0x28},
138 {.default_bit_rate_mbps = 750, .hsfreqrange_code = 0x39},
139 {.default_bit_rate_mbps = 800, .hsfreqrange_code = 0x09},
140 {.default_bit_rate_mbps = 850, .hsfreqrange_code = 0x19},
141 {.default_bit_rate_mbps = 900, .hsfreqrange_code = 0x29},
142 {.default_bit_rate_mbps = 1000, .hsfreqrange_code = 0x0A},
143 {.default_bit_rate_mbps = 1050, .hsfreqrange_code = 0x1A},
144 {.default_bit_rate_mbps = 1100, .hsfreqrange_code = 0x2A},
145 {.default_bit_rate_mbps = 1150, .hsfreqrange_code = 0x3B},
146 {.default_bit_rate_mbps = 1200, .hsfreqrange_code = 0x0B},
147 {.default_bit_rate_mbps = 1250, .hsfreqrange_code = 0x1B},
148 {.default_bit_rate_mbps = 1300, .hsfreqrange_code = 0x2B},
149 {.default_bit_rate_mbps = 1350, .hsfreqrange_code = 0x3C},
150 {.default_bit_rate_mbps = 1400, .hsfreqrange_code = 0x0C},
151 {.default_bit_rate_mbps = 1450, .hsfreqrange_code = 0x1C},
152 {.default_bit_rate_mbps = 1500, .hsfreqrange_code = 0x2C},
153 {.default_bit_rate_mbps = 1550, .hsfreqrange_code = 0x3D},
154 {.default_bit_rate_mbps = 1600, .hsfreqrange_code = 0x0D},
155 {.default_bit_rate_mbps = 1650, .hsfreqrange_code = 0x1D},
156 {.default_bit_rate_mbps = 1700, .hsfreqrange_code = 0x2E},
157 {.default_bit_rate_mbps = 1750, .hsfreqrange_code = 0x3E},
158 {.default_bit_rate_mbps = 1800, .hsfreqrange_code = 0x0E},
159 {.default_bit_rate_mbps = 1850, .hsfreqrange_code = 0x1E},
160 {.default_bit_rate_mbps = 1900, .hsfreqrange_code = 0x2F},
161 {.default_bit_rate_mbps = 1950, .hsfreqrange_code = 0x3F},
162 {.default_bit_rate_mbps = 2000, .hsfreqrange_code = 0x0F},
163 {.default_bit_rate_mbps = 2050, .hsfreqrange_code = 0x40},
164 {.default_bit_rate_mbps = 2100, .hsfreqrange_code = 0x41},
165 {.default_bit_rate_mbps = 2150, .hsfreqrange_code = 0x42},
166 {.default_bit_rate_mbps = 2200, .hsfreqrange_code = 0x43},
167 {.default_bit_rate_mbps = 2250, .hsfreqrange_code = 0x44},
168 {.default_bit_rate_mbps = 2300, .hsfreqrange_code = 0x45},
169 {.default_bit_rate_mbps = 2350, .hsfreqrange_code = 0x46},
170 {.default_bit_rate_mbps = 2400, .hsfreqrange_code = 0x47},
171 {.default_bit_rate_mbps = 2450, .hsfreqrange_code = 0x48},
172 {.default_bit_rate_mbps = 2500, .hsfreqrange_code = 0x49}
173 };
174
kmb_dsi_clk_disable(struct kmb_dsi * kmb_dsi)175 static void kmb_dsi_clk_disable(struct kmb_dsi *kmb_dsi)
176 {
177 clk_disable_unprepare(kmb_dsi->clk_mipi);
178 clk_disable_unprepare(kmb_dsi->clk_mipi_ecfg);
179 clk_disable_unprepare(kmb_dsi->clk_mipi_cfg);
180 }
181
kmb_dsi_host_unregister(struct kmb_dsi * kmb_dsi)182 void kmb_dsi_host_unregister(struct kmb_dsi *kmb_dsi)
183 {
184 kmb_dsi_clk_disable(kmb_dsi);
185 mipi_dsi_host_unregister(kmb_dsi->host);
186 }
187
188 /*
189 * This DSI can only be paired with bridges that do config through i2c
190 * which is ADV 7535 in the KMB EVM
191 */
kmb_dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)192 static ssize_t kmb_dsi_host_transfer(struct mipi_dsi_host *host,
193 const struct mipi_dsi_msg *msg)
194 {
195 return 0;
196 }
197
kmb_dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * dev)198 static int kmb_dsi_host_attach(struct mipi_dsi_host *host,
199 struct mipi_dsi_device *dev)
200 {
201 return 0;
202 }
203
kmb_dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * dev)204 static int kmb_dsi_host_detach(struct mipi_dsi_host *host,
205 struct mipi_dsi_device *dev)
206 {
207 return 0;
208 }
209
210 static const struct mipi_dsi_host_ops kmb_dsi_host_ops = {
211 .attach = kmb_dsi_host_attach,
212 .detach = kmb_dsi_host_detach,
213 .transfer = kmb_dsi_host_transfer,
214 };
215
kmb_dsi_host_bridge_init(struct device * dev)216 int kmb_dsi_host_bridge_init(struct device *dev)
217 {
218 struct device_node *encoder_node, *dsi_out;
219
220 /* Create and register MIPI DSI host */
221 if (!dsi_host) {
222 dsi_host = kzalloc(sizeof(*dsi_host), GFP_KERNEL);
223 if (!dsi_host)
224 return -ENOMEM;
225
226 dsi_host->ops = &kmb_dsi_host_ops;
227
228 if (!dsi_device) {
229 dsi_device = kzalloc(sizeof(*dsi_device), GFP_KERNEL);
230 if (!dsi_device) {
231 kfree(dsi_host);
232 return -ENOMEM;
233 }
234 }
235
236 dsi_host->dev = dev;
237 mipi_dsi_host_register(dsi_host);
238 }
239
240 /* Find ADV7535 node and initialize it */
241 dsi_out = of_graph_get_endpoint_by_regs(dev->of_node, 0, 1);
242 if (!dsi_out) {
243 DRM_ERROR("Failed to get dsi_out node info from DT\n");
244 return -EINVAL;
245 }
246 encoder_node = of_graph_get_remote_port_parent(dsi_out);
247 if (!encoder_node) {
248 of_node_put(dsi_out);
249 DRM_ERROR("Failed to get bridge info from DT\n");
250 return -EINVAL;
251 }
252 /* Locate drm bridge from the hdmi encoder DT node */
253 adv_bridge = of_drm_find_bridge(encoder_node);
254 of_node_put(dsi_out);
255 of_node_put(encoder_node);
256 if (!adv_bridge) {
257 DRM_DEBUG("Wait for external bridge driver DT\n");
258 return -EPROBE_DEFER;
259 }
260
261 return 0;
262 }
263
mipi_get_datatype_params(u32 data_type,u32 data_mode,struct mipi_data_type_params * params)264 static u32 mipi_get_datatype_params(u32 data_type, u32 data_mode,
265 struct mipi_data_type_params *params)
266 {
267 struct mipi_data_type_params data_type_param;
268
269 switch (data_type) {
270 case DSI_LP_DT_PPS_YCBCR420_12B:
271 data_type_param.size_constraint_pixels = 2;
272 data_type_param.size_constraint_bytes = 3;
273 switch (data_mode) {
274 /* Case 0 not supported according to MDK */
275 case 1:
276 case 2:
277 case 3:
278 data_type_param.pixels_per_pclk = 2;
279 data_type_param.bits_per_pclk = 24;
280 break;
281 default:
282 DRM_ERROR("DSI: Invalid data_mode %d\n", data_mode);
283 return -EINVAL;
284 }
285 break;
286 case DSI_LP_DT_PPS_YCBCR422_16B:
287 data_type_param.size_constraint_pixels = 2;
288 data_type_param.size_constraint_bytes = 4;
289 switch (data_mode) {
290 /* Case 0 and 1 not supported according
291 * to MDK
292 */
293 case 2:
294 data_type_param.pixels_per_pclk = 1;
295 data_type_param.bits_per_pclk = 16;
296 break;
297 case 3:
298 data_type_param.pixels_per_pclk = 2;
299 data_type_param.bits_per_pclk = 32;
300 break;
301 default:
302 DRM_ERROR("DSI: Invalid data_mode %d\n", data_mode);
303 return -EINVAL;
304 }
305 break;
306 case DSI_LP_DT_LPPS_YCBCR422_20B:
307 case DSI_LP_DT_PPS_YCBCR422_24B:
308 data_type_param.size_constraint_pixels = 2;
309 data_type_param.size_constraint_bytes = 6;
310 switch (data_mode) {
311 /* Case 0 not supported according to MDK */
312 case 1:
313 case 2:
314 case 3:
315 data_type_param.pixels_per_pclk = 1;
316 data_type_param.bits_per_pclk = 24;
317 break;
318 default:
319 DRM_ERROR("DSI: Invalid data_mode %d\n", data_mode);
320 return -EINVAL;
321 }
322 break;
323 case DSI_LP_DT_PPS_RGB565_16B:
324 data_type_param.size_constraint_pixels = 1;
325 data_type_param.size_constraint_bytes = 2;
326 switch (data_mode) {
327 case 0:
328 case 1:
329 data_type_param.pixels_per_pclk = 1;
330 data_type_param.bits_per_pclk = 16;
331 break;
332 case 2:
333 case 3:
334 data_type_param.pixels_per_pclk = 2;
335 data_type_param.bits_per_pclk = 32;
336 break;
337 default:
338 DRM_ERROR("DSI: Invalid data_mode %d\n", data_mode);
339 return -EINVAL;
340 }
341 break;
342 case DSI_LP_DT_PPS_RGB666_18B:
343 data_type_param.size_constraint_pixels = 4;
344 data_type_param.size_constraint_bytes = 9;
345 data_type_param.bits_per_pclk = 18;
346 data_type_param.pixels_per_pclk = 1;
347 break;
348 case DSI_LP_DT_LPPS_RGB666_18B:
349 case DSI_LP_DT_PPS_RGB888_24B:
350 data_type_param.size_constraint_pixels = 1;
351 data_type_param.size_constraint_bytes = 3;
352 data_type_param.bits_per_pclk = 24;
353 data_type_param.pixels_per_pclk = 1;
354 break;
355 case DSI_LP_DT_PPS_RGB101010_30B:
356 data_type_param.size_constraint_pixels = 4;
357 data_type_param.size_constraint_bytes = 15;
358 data_type_param.bits_per_pclk = 30;
359 data_type_param.pixels_per_pclk = 1;
360 break;
361 default:
362 DRM_ERROR("DSI: Invalid data_type %d\n", data_type);
363 return -EINVAL;
364 }
365
366 *params = data_type_param;
367 return 0;
368 }
369
compute_wc(u32 width_px,u8 size_constr_p,u8 size_constr_b)370 static u32 compute_wc(u32 width_px, u8 size_constr_p, u8 size_constr_b)
371 {
372 /* Calculate the word count for each long packet */
373 return (((width_px / size_constr_p) * size_constr_b) & 0xffff);
374 }
375
compute_unpacked_bytes(u32 wc,u8 bits_per_pclk)376 static u32 compute_unpacked_bytes(u32 wc, u8 bits_per_pclk)
377 {
378 /* Number of PCLK cycles needed to transfer a line
379 * with each PCLK cycle, 4 Bytes are sent through the PPL module
380 */
381 return ((wc * 8) / bits_per_pclk) * 4;
382 }
383
mipi_tx_fg_section_cfg_regs(struct kmb_dsi * kmb_dsi,u8 frame_id,u8 section,u32 height_lines,u32 unpacked_bytes,struct mipi_tx_frame_sect_phcfg * ph_cfg)384 static u32 mipi_tx_fg_section_cfg_regs(struct kmb_dsi *kmb_dsi,
385 u8 frame_id, u8 section,
386 u32 height_lines, u32 unpacked_bytes,
387 struct mipi_tx_frame_sect_phcfg *ph_cfg)
388 {
389 u32 cfg = 0;
390 u32 ctrl_no = MIPI_CTRL6;
391 u32 reg_adr;
392
393 /* Frame section packet header */
394 /* Word count bits [15:0] */
395 cfg = (ph_cfg->wc & MIPI_TX_SECT_WC_MASK) << 0;
396
397 /* Data type (bits [21:16]) */
398 cfg |= ((ph_cfg->data_type & MIPI_TX_SECT_DT_MASK)
399 << MIPI_TX_SECT_DT_SHIFT);
400
401 /* Virtual channel (bits [23:22]) */
402 cfg |= ((ph_cfg->vchannel & MIPI_TX_SECT_VC_MASK)
403 << MIPI_TX_SECT_VC_SHIFT);
404
405 /* Data mode (bits [24:25]) */
406 cfg |= ((ph_cfg->data_mode & MIPI_TX_SECT_DM_MASK)
407 << MIPI_TX_SECT_DM_SHIFT);
408 if (ph_cfg->dma_packed)
409 cfg |= MIPI_TX_SECT_DMA_PACKED;
410
411 dev_dbg(kmb_dsi->dev,
412 "ctrl=%d frame_id=%d section=%d cfg=%x packed=%d\n",
413 ctrl_no, frame_id, section, cfg, ph_cfg->dma_packed);
414 kmb_write_mipi(kmb_dsi,
415 (MIPI_TXm_HS_FGn_SECTo_PH(ctrl_no, frame_id, section)),
416 cfg);
417
418 /* Unpacked bytes */
419
420 /* There are 4 frame generators and each fg has 4 sections
421 * There are 2 registers for unpacked bytes (# bytes each
422 * section occupies in memory)
423 * REG_UNPACKED_BYTES0: [15:0]-BYTES0, [31:16]-BYTES1
424 * REG_UNPACKED_BYTES1: [15:0]-BYTES2, [31:16]-BYTES3
425 */
426 reg_adr =
427 MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(ctrl_no,
428 frame_id) + (section / 2) * 4;
429 kmb_write_bits_mipi(kmb_dsi, reg_adr, (section % 2) * 16, 16,
430 unpacked_bytes);
431 dev_dbg(kmb_dsi->dev,
432 "unpacked_bytes = %d, wordcount = %d\n", unpacked_bytes,
433 ph_cfg->wc);
434
435 /* Line config */
436 reg_adr = MIPI_TXm_HS_FGn_SECTo_LINE_CFG(ctrl_no, frame_id, section);
437 kmb_write_mipi(kmb_dsi, reg_adr, height_lines);
438 return 0;
439 }
440
mipi_tx_fg_section_cfg(struct kmb_dsi * kmb_dsi,u8 frame_id,u8 section,struct mipi_tx_frame_section_cfg * frame_scfg,u32 * bits_per_pclk,u32 * wc)441 static u32 mipi_tx_fg_section_cfg(struct kmb_dsi *kmb_dsi,
442 u8 frame_id, u8 section,
443 struct mipi_tx_frame_section_cfg *frame_scfg,
444 u32 *bits_per_pclk, u32 *wc)
445 {
446 u32 ret = 0;
447 u32 unpacked_bytes;
448 struct mipi_data_type_params data_type_parameters;
449 struct mipi_tx_frame_sect_phcfg ph_cfg;
450
451 ret = mipi_get_datatype_params(frame_scfg->data_type,
452 frame_scfg->data_mode,
453 &data_type_parameters);
454 if (ret)
455 return ret;
456
457 /* Packet width has to be a multiple of the minimum packet width
458 * (in pixels) set for each data type
459 */
460 if (frame_scfg->width_pixels %
461 data_type_parameters.size_constraint_pixels != 0)
462 return -EINVAL;
463
464 *wc = compute_wc(frame_scfg->width_pixels,
465 data_type_parameters.size_constraint_pixels,
466 data_type_parameters.size_constraint_bytes);
467 unpacked_bytes = compute_unpacked_bytes(*wc,
468 data_type_parameters.bits_per_pclk);
469 ph_cfg.wc = *wc;
470 ph_cfg.data_mode = frame_scfg->data_mode;
471 ph_cfg.data_type = frame_scfg->data_type;
472 ph_cfg.dma_packed = frame_scfg->dma_packed;
473 ph_cfg.vchannel = frame_id;
474
475 mipi_tx_fg_section_cfg_regs(kmb_dsi, frame_id, section,
476 frame_scfg->height_lines,
477 unpacked_bytes, &ph_cfg);
478
479 /* Caller needs bits_per_clk for additional caluclations */
480 *bits_per_pclk = data_type_parameters.bits_per_pclk;
481
482 return 0;
483 }
484
485 #define CLK_DIFF_LOW 50
486 #define CLK_DIFF_HI 60
487 #define SYSCLK_500 500
488
mipi_tx_fg_cfg_regs(struct kmb_dsi * kmb_dsi,u8 frame_gen,struct mipi_tx_frame_timing_cfg * fg_cfg)489 static void mipi_tx_fg_cfg_regs(struct kmb_dsi *kmb_dsi, u8 frame_gen,
490 struct mipi_tx_frame_timing_cfg *fg_cfg)
491 {
492 u32 sysclk;
493 u32 ppl_llp_ratio;
494 u32 ctrl_no = MIPI_CTRL6, reg_adr, val, offset;
495
496 /* 500 Mhz system clock minus 50 to account for the difference in
497 * MIPI clock speed in RTL tests
498 */
499 if (kmb_dsi->sys_clk_mhz == SYSCLK_500) {
500 sysclk = kmb_dsi->sys_clk_mhz - CLK_DIFF_LOW;
501 } else {
502 /* 700 Mhz clk*/
503 sysclk = kmb_dsi->sys_clk_mhz - CLK_DIFF_HI;
504 }
505
506 /* PPL-Pixel Packing Layer, LLP-Low Level Protocol
507 * Frame genartor timing parameters are clocked on the system clock,
508 * whereas as the equivalent parameters in the LLP blocks are clocked
509 * on LLP Tx clock from the D-PHY - BYTE clock
510 */
511
512 /* Multiply by 1000 to maintain precision */
513 ppl_llp_ratio = ((fg_cfg->bpp / 8) * sysclk * 1000) /
514 ((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes);
515
516 dev_dbg(kmb_dsi->dev, "ppl_llp_ratio=%d\n", ppl_llp_ratio);
517 dev_dbg(kmb_dsi->dev, "bpp=%d sysclk=%d lane-rate=%d active-lanes=%d\n",
518 fg_cfg->bpp, sysclk, fg_cfg->lane_rate_mbps,
519 fg_cfg->active_lanes);
520
521 /* Frame generator number of lines */
522 reg_adr = MIPI_TXm_HS_FGn_NUM_LINES(ctrl_no, frame_gen);
523 kmb_write_mipi(kmb_dsi, reg_adr, fg_cfg->v_active);
524
525 /* vsync width
526 * There are 2 registers for vsync width (VSA in lines for
527 * channels 0-3)
528 * REG_VSYNC_WIDTH0: [15:0]-VSA for channel0, [31:16]-VSA for channel1
529 * REG_VSYNC_WIDTH1: [15:0]-VSA for channel2, [31:16]-VSA for channel3
530 */
531 offset = (frame_gen % 2) * 16;
532 reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen / 2);
533 kmb_write_bits_mipi(kmb_dsi, reg_adr, offset, 16, fg_cfg->vsync_width);
534
535 /* vertical backporch (vbp) */
536 reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen / 2);
537 kmb_write_bits_mipi(kmb_dsi, reg_adr, offset, 16, fg_cfg->v_backporch);
538
539 /* vertical frontporch (vfp) */
540 reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen / 2);
541 kmb_write_bits_mipi(kmb_dsi, reg_adr, offset, 16, fg_cfg->v_frontporch);
542
543 /* vertical active (vactive) */
544 reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen / 2);
545 kmb_write_bits_mipi(kmb_dsi, reg_adr, offset, 16, fg_cfg->v_active);
546
547 /* hsync width */
548 reg_adr = MIPI_TXm_HS_HSYNC_WIDTHn(ctrl_no, frame_gen);
549 kmb_write_mipi(kmb_dsi, reg_adr,
550 (fg_cfg->hsync_width * ppl_llp_ratio) / 1000);
551
552 /* horizontal backporch (hbp) */
553 reg_adr = MIPI_TXm_HS_H_BACKPORCHn(ctrl_no, frame_gen);
554 kmb_write_mipi(kmb_dsi, reg_adr,
555 (fg_cfg->h_backporch * ppl_llp_ratio) / 1000);
556
557 /* horizontal frontporch (hfp) */
558 reg_adr = MIPI_TXm_HS_H_FRONTPORCHn(ctrl_no, frame_gen);
559 kmb_write_mipi(kmb_dsi, reg_adr,
560 (fg_cfg->h_frontporch * ppl_llp_ratio) / 1000);
561
562 /* horizontal active (ha) */
563 reg_adr = MIPI_TXm_HS_H_ACTIVEn(ctrl_no, frame_gen);
564
565 /* convert h_active which is wc in bytes to cycles */
566 val = (fg_cfg->h_active * sysclk * 1000) /
567 ((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes);
568 val /= 1000;
569 kmb_write_mipi(kmb_dsi, reg_adr, val);
570
571 /* llp hsync width */
572 reg_adr = MIPI_TXm_HS_LLP_HSYNC_WIDTHn(ctrl_no, frame_gen);
573 kmb_write_mipi(kmb_dsi, reg_adr, fg_cfg->hsync_width * (fg_cfg->bpp / 8));
574
575 /* llp h backporch */
576 reg_adr = MIPI_TXm_HS_LLP_H_BACKPORCHn(ctrl_no, frame_gen);
577 kmb_write_mipi(kmb_dsi, reg_adr, fg_cfg->h_backporch * (fg_cfg->bpp / 8));
578
579 /* llp h frontporch */
580 reg_adr = MIPI_TXm_HS_LLP_H_FRONTPORCHn(ctrl_no, frame_gen);
581 kmb_write_mipi(kmb_dsi, reg_adr,
582 fg_cfg->h_frontporch * (fg_cfg->bpp / 8));
583 }
584
mipi_tx_fg_cfg(struct kmb_dsi * kmb_dsi,u8 frame_gen,u8 active_lanes,u32 bpp,u32 wc,u32 lane_rate_mbps,struct mipi_tx_frame_cfg * fg_cfg)585 static void mipi_tx_fg_cfg(struct kmb_dsi *kmb_dsi, u8 frame_gen,
586 u8 active_lanes, u32 bpp, u32 wc,
587 u32 lane_rate_mbps, struct mipi_tx_frame_cfg *fg_cfg)
588 {
589 u32 i, fg_num_lines = 0;
590 struct mipi_tx_frame_timing_cfg fg_t_cfg;
591
592 /* Calculate the total frame generator number of
593 * lines based on it's active sections
594 */
595 for (i = 0; i < MIPI_TX_FRAME_GEN_SECTIONS; i++) {
596 if (fg_cfg->sections[i])
597 fg_num_lines += fg_cfg->sections[i]->height_lines;
598 }
599
600 fg_t_cfg.bpp = bpp;
601 fg_t_cfg.lane_rate_mbps = lane_rate_mbps;
602 fg_t_cfg.hsync_width = fg_cfg->hsync_width;
603 fg_t_cfg.h_backporch = fg_cfg->h_backporch;
604 fg_t_cfg.h_frontporch = fg_cfg->h_frontporch;
605 fg_t_cfg.h_active = wc;
606 fg_t_cfg.vsync_width = fg_cfg->vsync_width;
607 fg_t_cfg.v_backporch = fg_cfg->v_backporch;
608 fg_t_cfg.v_frontporch = fg_cfg->v_frontporch;
609 fg_t_cfg.v_active = fg_num_lines;
610 fg_t_cfg.active_lanes = active_lanes;
611
612 /* Apply frame generator timing setting */
613 mipi_tx_fg_cfg_regs(kmb_dsi, frame_gen, &fg_t_cfg);
614 }
615
mipi_tx_multichannel_fifo_cfg(struct kmb_dsi * kmb_dsi,u8 active_lanes,u8 vchannel_id)616 static void mipi_tx_multichannel_fifo_cfg(struct kmb_dsi *kmb_dsi,
617 u8 active_lanes, u8 vchannel_id)
618 {
619 u32 fifo_size, fifo_rthreshold;
620 u32 ctrl_no = MIPI_CTRL6;
621
622 /* Clear all mc fifo channel sizes and thresholds */
623 kmb_write_mipi(kmb_dsi, MIPI_TX_HS_MC_FIFO_CTRL_EN, 0);
624 kmb_write_mipi(kmb_dsi, MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0, 0);
625 kmb_write_mipi(kmb_dsi, MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1, 0);
626 kmb_write_mipi(kmb_dsi, MIPI_TX_HS_MC_FIFO_RTHRESHOLD0, 0);
627 kmb_write_mipi(kmb_dsi, MIPI_TX_HS_MC_FIFO_RTHRESHOLD1, 0);
628
629 fifo_size = ((active_lanes > MIPI_D_LANES_PER_DPHY) ?
630 MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC :
631 MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC) - 1;
632
633 /* MC fifo size for virtual channels 0-3
634 * REG_MC_FIFO_CHAN_ALLOC0: [8:0]-channel0, [24:16]-channel1
635 * REG_MC_FIFO_CHAN_ALLOC1: [8:0]-2, [24:16]-channel3
636 */
637 SET_MC_FIFO_CHAN_ALLOC(kmb_dsi, ctrl_no, vchannel_id, fifo_size);
638
639 /* Set threshold to half the fifo size, actual size=size*16 */
640 fifo_rthreshold = ((fifo_size) * 8) & BIT_MASK_16;
641 SET_MC_FIFO_RTHRESHOLD(kmb_dsi, ctrl_no, vchannel_id, fifo_rthreshold);
642
643 /* Enable the MC FIFO channel corresponding to the Virtual Channel */
644 kmb_set_bit_mipi(kmb_dsi, MIPI_TXm_HS_MC_FIFO_CTRL_EN(ctrl_no),
645 vchannel_id);
646 }
647
mipi_tx_ctrl_cfg(struct kmb_dsi * kmb_dsi,u8 fg_id,struct mipi_ctrl_cfg * ctrl_cfg)648 static void mipi_tx_ctrl_cfg(struct kmb_dsi *kmb_dsi, u8 fg_id,
649 struct mipi_ctrl_cfg *ctrl_cfg)
650 {
651 u32 sync_cfg = 0, ctrl = 0, fg_en;
652 u32 ctrl_no = MIPI_CTRL6;
653
654 /* MIPI_TX_HS_SYNC_CFG */
655 if (ctrl_cfg->tx_ctrl_cfg.line_sync_pkt_en)
656 sync_cfg |= LINE_SYNC_PKT_ENABLE;
657 if (ctrl_cfg->tx_ctrl_cfg.frame_counter_active)
658 sync_cfg |= FRAME_COUNTER_ACTIVE;
659 if (ctrl_cfg->tx_ctrl_cfg.line_counter_active)
660 sync_cfg |= LINE_COUNTER_ACTIVE;
661 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->v_blanking)
662 sync_cfg |= DSI_V_BLANKING;
663 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hsa_blanking)
664 sync_cfg |= DSI_HSA_BLANKING;
665 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hbp_blanking)
666 sync_cfg |= DSI_HBP_BLANKING;
667 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blanking)
668 sync_cfg |= DSI_HFP_BLANKING;
669 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->sync_pulse_eventn)
670 sync_cfg |= DSI_SYNC_PULSE_EVENTN;
671 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->lpm_first_vsa_line)
672 sync_cfg |= DSI_LPM_FIRST_VSA_LINE;
673 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->lpm_last_vfp_line)
674 sync_cfg |= DSI_LPM_LAST_VFP_LINE;
675
676 /* Enable frame generator */
677 fg_en = 1 << fg_id;
678 sync_cfg |= FRAME_GEN_EN(fg_en);
679
680 if (ctrl_cfg->tx_ctrl_cfg.tx_always_use_hact)
681 sync_cfg |= ALWAYS_USE_HACT(fg_en);
682 if (ctrl_cfg->tx_ctrl_cfg.tx_hact_wait_stop)
683 sync_cfg |= HACT_WAIT_STOP(fg_en);
684
685 dev_dbg(kmb_dsi->dev, "sync_cfg=%d fg_en=%d\n", sync_cfg, fg_en);
686
687 /* MIPI_TX_HS_CTRL */
688
689 /* type:DSI, source:LCD */
690 ctrl = HS_CTRL_EN | TX_SOURCE;
691 ctrl |= LCD_VC(fg_id);
692 ctrl |= ACTIVE_LANES(ctrl_cfg->active_lanes - 1);
693 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->eotp_en)
694 ctrl |= DSI_EOTP_EN;
695 if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blank_en)
696 ctrl |= DSI_CMD_HFP_EN;
697
698 /*67 ns stop time */
699 ctrl |= HSEXIT_CNT(0x43);
700
701 kmb_write_mipi(kmb_dsi, MIPI_TXm_HS_SYNC_CFG(ctrl_no), sync_cfg);
702 kmb_write_mipi(kmb_dsi, MIPI_TXm_HS_CTRL(ctrl_no), ctrl);
703 }
704
mipi_tx_init_cntrl(struct kmb_dsi * kmb_dsi,struct mipi_ctrl_cfg * ctrl_cfg)705 static u32 mipi_tx_init_cntrl(struct kmb_dsi *kmb_dsi,
706 struct mipi_ctrl_cfg *ctrl_cfg)
707 {
708 u32 ret = 0;
709 u8 active_vchannels = 0;
710 u8 frame_id, sect;
711 u32 bits_per_pclk = 0;
712 u32 word_count = 0;
713 struct mipi_tx_frame_cfg *frame;
714
715 /* This is the order to initialize MIPI TX:
716 * 1. set frame section parameters
717 * 2. set frame specific parameters
718 * 3. connect lcd to mipi
719 * 4. multi channel fifo cfg
720 * 5. set mipitxcctrlcfg
721 */
722
723 for (frame_id = 0; frame_id < 4; frame_id++) {
724 frame = ctrl_cfg->tx_ctrl_cfg.frames[frame_id];
725
726 /* Find valid frame, assume only one valid frame */
727 if (!frame)
728 continue;
729
730 /* Frame Section configuration */
731 /* TODO - assume there is only one valid section in a frame,
732 * so bits_per_pclk and word_count are only set once
733 */
734 for (sect = 0; sect < MIPI_CTRL_VIRTUAL_CHANNELS; sect++) {
735 if (!frame->sections[sect])
736 continue;
737
738 ret = mipi_tx_fg_section_cfg(kmb_dsi, frame_id, sect,
739 frame->sections[sect],
740 &bits_per_pclk,
741 &word_count);
742 if (ret)
743 return ret;
744 }
745
746 /* Set frame specific parameters */
747 mipi_tx_fg_cfg(kmb_dsi, frame_id, ctrl_cfg->active_lanes,
748 bits_per_pclk, word_count,
749 ctrl_cfg->lane_rate_mbps, frame);
750
751 active_vchannels++;
752
753 /* Stop iterating as only one virtual channel
754 * shall be used for LCD connection
755 */
756 break;
757 }
758
759 if (active_vchannels == 0)
760 return -EINVAL;
761 /* Multi-Channel FIFO Configuration */
762 mipi_tx_multichannel_fifo_cfg(kmb_dsi, ctrl_cfg->active_lanes, frame_id);
763
764 /* Frame Generator Enable */
765 mipi_tx_ctrl_cfg(kmb_dsi, frame_id, ctrl_cfg);
766
767 return ret;
768 }
769
test_mode_send(struct kmb_dsi * kmb_dsi,u32 dphy_no,u32 test_code,u32 test_data)770 static void test_mode_send(struct kmb_dsi *kmb_dsi, u32 dphy_no,
771 u32 test_code, u32 test_data)
772 {
773 /* Steps to send test code:
774 * - set testclk HIGH
775 * - set testdin with test code
776 * - set testen HIGH
777 * - set testclk LOW
778 * - set testen LOW
779 */
780
781 /* Set testclk high */
782 SET_DPHY_TEST_CTRL1_CLK(kmb_dsi, dphy_no);
783
784 /* Set testdin */
785 SET_TEST_DIN0_3(kmb_dsi, dphy_no, test_code);
786
787 /* Set testen high */
788 SET_DPHY_TEST_CTRL1_EN(kmb_dsi, dphy_no);
789
790 /* Set testclk low */
791 CLR_DPHY_TEST_CTRL1_CLK(kmb_dsi, dphy_no);
792
793 /* Set testen low */
794 CLR_DPHY_TEST_CTRL1_EN(kmb_dsi, dphy_no);
795
796 if (test_code) {
797 /* Steps to send test data:
798 * - set testen LOW
799 * - set testclk LOW
800 * - set testdin with data
801 * - set testclk HIGH
802 */
803
804 /* Set testen low */
805 CLR_DPHY_TEST_CTRL1_EN(kmb_dsi, dphy_no);
806
807 /* Set testclk low */
808 CLR_DPHY_TEST_CTRL1_CLK(kmb_dsi, dphy_no);
809
810 /* Set data in testdin */
811 kmb_write_mipi(kmb_dsi,
812 DPHY_TEST_DIN0_3 + ((dphy_no / 0x4) * 0x4),
813 test_data << ((dphy_no % 4) * 8));
814
815 /* Set testclk high */
816 SET_DPHY_TEST_CTRL1_CLK(kmb_dsi, dphy_no);
817 }
818 }
819
820 static inline void
set_test_mode_src_osc_freq_target_low_bits(struct kmb_dsi * kmb_dsi,u32 dphy_no,u32 freq)821 set_test_mode_src_osc_freq_target_low_bits(struct kmb_dsi *kmb_dsi,
822 u32 dphy_no,
823 u32 freq)
824 {
825 /* Typical rise/fall time=166, refer Table 1207 databook,
826 * sr_osc_freq_target[7:0]
827 */
828 test_mode_send(kmb_dsi, dphy_no, TEST_CODE_SLEW_RATE_DDL_CYCLES,
829 (freq & 0x7f));
830 }
831
832 static inline void
set_test_mode_src_osc_freq_target_hi_bits(struct kmb_dsi * kmb_dsi,u32 dphy_no,u32 freq)833 set_test_mode_src_osc_freq_target_hi_bits(struct kmb_dsi *kmb_dsi,
834 u32 dphy_no,
835 u32 freq)
836 {
837 u32 data;
838
839 /* Flag this as high nibble */
840 data = ((freq >> 6) & 0x1f) | (1 << 7);
841
842 /* Typical rise/fall time=166, refer Table 1207 databook,
843 * sr_osc_freq_target[11:7]
844 */
845 test_mode_send(kmb_dsi, dphy_no, TEST_CODE_SLEW_RATE_DDL_CYCLES, data);
846 }
847
mipi_tx_get_vco_params(struct vco_params * vco)848 static void mipi_tx_get_vco_params(struct vco_params *vco)
849 {
850 int i;
851
852 for (i = 0; i < ARRAY_SIZE(vco_table); i++) {
853 if (vco->freq < vco_table[i].freq) {
854 *vco = vco_table[i];
855 return;
856 }
857 }
858
859 WARN_ONCE(1, "Invalid vco freq = %u for PLL setup\n", vco->freq);
860 }
861
mipi_tx_pll_setup(struct kmb_dsi * kmb_dsi,u32 dphy_no,u32 ref_clk_mhz,u32 target_freq_mhz)862 static void mipi_tx_pll_setup(struct kmb_dsi *kmb_dsi, u32 dphy_no,
863 u32 ref_clk_mhz, u32 target_freq_mhz)
864 {
865 u32 best_n = 0, best_m = 0;
866 u32 n = 0, m = 0, div = 0, delta, freq = 0, t_freq;
867 u32 best_freq_delta = 3000;
868
869 /* pll_ref_clk: - valid range: 2~64 MHz; Typically 24 MHz
870 * Fvco: - valid range: 320~1250 MHz (Gen3 D-PHY)
871 * Fout: - valid range: 40~1250 MHz (Gen3 D-PHY)
872 * n: - valid range [0 15]
873 * N: - N = n + 1
874 * -valid range: [1 16]
875 * -conditions: - (pll_ref_clk / N) >= 2 MHz
876 * -(pll_ref_clk / N) <= 8 MHz
877 * m: valid range [62 623]
878 * M: - M = m + 2
879 * -valid range [64 625]
880 * -Fvco = (M/N) * pll_ref_clk
881 */
882 struct vco_params vco_p = {
883 .range = 0,
884 .divider = 1,
885 };
886
887 vco_p.freq = target_freq_mhz;
888 mipi_tx_get_vco_params(&vco_p);
889
890 /* Search pll n parameter */
891 for (n = PLL_N_MIN; n <= PLL_N_MAX; n++) {
892 /* Calculate the pll input frequency division ratio
893 * multiply by 1000 for precision -
894 * no floating point, add n for rounding
895 */
896 div = ((ref_clk_mhz * 1000) + n) / (n + 1);
897
898 /* Found a valid n parameter */
899 if ((div < 2000 || div > 8000))
900 continue;
901
902 /* Search pll m parameter */
903 for (m = PLL_M_MIN; m <= PLL_M_MAX; m++) {
904 /* Calculate the Fvco(DPHY PLL output frequency)
905 * using the current n,m params
906 */
907 freq = div * (m + 2);
908 freq /= 1000;
909
910 /* Trim the potential pll freq to max supported */
911 if (freq > PLL_FVCO_MAX)
912 continue;
913
914 delta = abs(freq - target_freq_mhz);
915
916 /* Select the best (closest to target pll freq)
917 * n,m parameters so far
918 */
919 if (delta < best_freq_delta) {
920 best_n = n;
921 best_m = m;
922 best_freq_delta = delta;
923 }
924 }
925 }
926
927 /* Program vco_cntrl parameter
928 * PLL_VCO_Control[5:0] = pll_vco_cntrl_ovr,
929 * PLL_VCO_Control[6] = pll_vco_cntrl_ovr_en
930 */
931 test_mode_send(kmb_dsi, dphy_no, TEST_CODE_PLL_VCO_CTRL, (vco_p.range
932 | (1 << 6)));
933
934 /* Program m, n pll parameters */
935 dev_dbg(kmb_dsi->dev, "m = %d n = %d\n", best_m, best_n);
936
937 /* PLL_Input_Divider_Ratio[3:0] = pll_n_ovr */
938 test_mode_send(kmb_dsi, dphy_no, TEST_CODE_PLL_INPUT_DIVIDER,
939 (best_n & 0x0f));
940
941 /* m - low nibble PLL_Loop_Divider_Ratio[4:0]
942 * pll_m_ovr[4:0]
943 */
944 test_mode_send(kmb_dsi, dphy_no, TEST_CODE_PLL_FEEDBACK_DIVIDER,
945 (best_m & 0x1f));
946
947 /* m - high nibble PLL_Loop_Divider_Ratio[4:0]
948 * pll_m_ovr[9:5]
949 */
950 test_mode_send(kmb_dsi, dphy_no, TEST_CODE_PLL_FEEDBACK_DIVIDER,
951 ((best_m >> 5) & 0x1f) | PLL_FEEDBACK_DIVIDER_HIGH);
952
953 /* Enable overwrite of n,m parameters :pll_n_ovr_en, pll_m_ovr_en */
954 test_mode_send(kmb_dsi, dphy_no, TEST_CODE_PLL_OUTPUT_CLK_SEL,
955 (PLL_N_OVR_EN | PLL_M_OVR_EN));
956
957 /* Program Charge-Pump parameters */
958
959 /* pll_prop_cntrl-fixed values for prop_cntrl from DPHY doc */
960 t_freq = target_freq_mhz * vco_p.divider;
961 test_mode_send(kmb_dsi, dphy_no,
962 TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL,
963 ((t_freq > 1150) ? 0x0C : 0x0B));
964
965 /* pll_int_cntrl-fixed value for int_cntrl from DPHY doc */
966 test_mode_send(kmb_dsi, dphy_no, TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL,
967 0x00);
968
969 /* pll_gmp_cntrl-fixed value for gmp_cntrl from DPHY doci */
970 test_mode_send(kmb_dsi, dphy_no, TEST_CODE_PLL_GMP_CTRL, 0x10);
971
972 /* pll_cpbias_cntrl-fixed value for cpbias_cntrl from DPHY doc */
973 test_mode_send(kmb_dsi, dphy_no, TEST_CODE_PLL_CHARGE_PUMP_BIAS, 0x10);
974
975 /* pll_th1 -Lock Detector Phase error threshold,
976 * document gives fixed value
977 */
978 test_mode_send(kmb_dsi, dphy_no, TEST_CODE_PLL_PHASE_ERR_CTRL, 0x02);
979
980 /* PLL Lock Configuration */
981
982 /* pll_th2 - Lock Filter length, document gives fixed value */
983 test_mode_send(kmb_dsi, dphy_no, TEST_CODE_PLL_LOCK_FILTER, 0x60);
984
985 /* pll_th3- PLL Unlocking filter, document gives fixed value */
986 test_mode_send(kmb_dsi, dphy_no, TEST_CODE_PLL_UNLOCK_FILTER, 0x03);
987
988 /* pll_lock_sel-PLL Lock Detector Selection,
989 * document gives fixed value
990 */
991 test_mode_send(kmb_dsi, dphy_no, TEST_CODE_PLL_LOCK_DETECTOR, 0x02);
992 }
993
set_slewrate_gt_1500(struct kmb_dsi * kmb_dsi,u32 dphy_no)994 static void set_slewrate_gt_1500(struct kmb_dsi *kmb_dsi, u32 dphy_no)
995 {
996 u32 test_code = 0, test_data = 0;
997 /* Bypass slew rate calibration algorithm
998 * bits[1:0} srcal_en_ovr_en, srcal_en_ovr
999 */
1000 test_code = TEST_CODE_SLEW_RATE_OVERRIDE_CTRL;
1001 test_data = 0x02;
1002 test_mode_send(kmb_dsi, dphy_no, test_code, test_data);
1003
1004 /* Disable slew rate calibration */
1005 test_code = TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL;
1006 test_data = 0x00;
1007 test_mode_send(kmb_dsi, dphy_no, test_code, test_data);
1008 }
1009
set_slewrate_gt_1000(struct kmb_dsi * kmb_dsi,u32 dphy_no)1010 static void set_slewrate_gt_1000(struct kmb_dsi *kmb_dsi, u32 dphy_no)
1011 {
1012 u32 test_code = 0, test_data = 0;
1013
1014 /* BitRate: > 1 Gbps && <= 1.5 Gbps: - slew rate control ON
1015 * typical rise/fall times: 166 ps
1016 */
1017
1018 /* Do not bypass slew rate calibration algorithm
1019 * bits[1:0}=srcal_en_ovr_en, srcal_en_ovr, bit[6]=sr_range
1020 */
1021 test_code = TEST_CODE_SLEW_RATE_OVERRIDE_CTRL;
1022 test_data = (0x03 | (1 << 6));
1023 test_mode_send(kmb_dsi, dphy_no, test_code, test_data);
1024
1025 /* Enable slew rate calibration */
1026 test_code = TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL;
1027 test_data = 0x01;
1028 test_mode_send(kmb_dsi, dphy_no, test_code, test_data);
1029
1030 /* Set sr_osc_freq_target[6:0] low nibble
1031 * typical rise/fall time=166, refer Table 1207 databook
1032 */
1033 test_code = TEST_CODE_SLEW_RATE_DDL_CYCLES;
1034 test_data = (0x72f & 0x7f);
1035 test_mode_send(kmb_dsi, dphy_no, test_code, test_data);
1036
1037 /* Set sr_osc_freq_target[11:7] high nibble
1038 * Typical rise/fall time=166, refer Table 1207 databook
1039 */
1040 test_code = TEST_CODE_SLEW_RATE_DDL_CYCLES;
1041 test_data = ((0x72f >> 6) & 0x1f) | (1 << 7);
1042 test_mode_send(kmb_dsi, dphy_no, test_code, test_data);
1043 }
1044
set_slewrate_lt_1000(struct kmb_dsi * kmb_dsi,u32 dphy_no)1045 static void set_slewrate_lt_1000(struct kmb_dsi *kmb_dsi, u32 dphy_no)
1046 {
1047 u32 test_code = 0, test_data = 0;
1048
1049 /* lane_rate_mbps <= 1000 Mbps
1050 * BitRate: <= 1 Gbps:
1051 * - slew rate control ON
1052 * - typical rise/fall times: 225 ps
1053 */
1054
1055 /* Do not bypass slew rate calibration algorithm */
1056 test_code = TEST_CODE_SLEW_RATE_OVERRIDE_CTRL;
1057 test_data = (0x03 | (1 << 6));
1058 test_mode_send(kmb_dsi, dphy_no, test_code, test_data);
1059
1060 /* Enable slew rate calibration */
1061 test_code = TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL;
1062 test_data = 0x01;
1063 test_mode_send(kmb_dsi, dphy_no, test_code, test_data);
1064
1065 /* Typical rise/fall time=255, refer Table 1207 databook */
1066 test_code = TEST_CODE_SLEW_RATE_DDL_CYCLES;
1067 test_data = (0x523 & 0x7f);
1068 test_mode_send(kmb_dsi, dphy_no, test_code, test_data);
1069
1070 /* Set sr_osc_freq_target[11:7] high nibble */
1071 test_code = TEST_CODE_SLEW_RATE_DDL_CYCLES;
1072 test_data = ((0x523 >> 6) & 0x1f) | (1 << 7);
1073 test_mode_send(kmb_dsi, dphy_no, test_code, test_data);
1074 }
1075
setup_pll(struct kmb_dsi * kmb_dsi,u32 dphy_no,struct mipi_ctrl_cfg * cfg)1076 static void setup_pll(struct kmb_dsi *kmb_dsi, u32 dphy_no,
1077 struct mipi_ctrl_cfg *cfg)
1078 {
1079 u32 test_code = 0, test_data = 0;
1080
1081 /* Set PLL regulator in bypass */
1082 test_code = TEST_CODE_PLL_ANALOG_PROG;
1083 test_data = 0x01;
1084 test_mode_send(kmb_dsi, dphy_no, test_code, test_data);
1085
1086 /* PLL Parameters Setup */
1087 mipi_tx_pll_setup(kmb_dsi, dphy_no, cfg->ref_clk_khz / 1000,
1088 cfg->lane_rate_mbps / 2);
1089
1090 /* Set clksel */
1091 kmb_write_bits_mipi(kmb_dsi, DPHY_INIT_CTRL1, PLL_CLKSEL_0, 2, 0x01);
1092
1093 /* Set pll_shadow_control */
1094 kmb_set_bit_mipi(kmb_dsi, DPHY_INIT_CTRL1, PLL_SHADOW_CTRL);
1095 }
1096
set_lane_data_rate(struct kmb_dsi * kmb_dsi,u32 dphy_no,struct mipi_ctrl_cfg * cfg)1097 static void set_lane_data_rate(struct kmb_dsi *kmb_dsi, u32 dphy_no,
1098 struct mipi_ctrl_cfg *cfg)
1099 {
1100 u32 i, test_code = 0, test_data = 0;
1101
1102 for (i = 0; i < MIPI_DPHY_DEFAULT_BIT_RATES; i++) {
1103 if (mipi_hs_freq_range[i].default_bit_rate_mbps <
1104 cfg->lane_rate_mbps)
1105 continue;
1106
1107 /* Send the test code and data */
1108 /* bit[6:0] = hsfreqrange_ovr bit[7] = hsfreqrange_ovr_en */
1109 test_code = TEST_CODE_HS_FREQ_RANGE_CFG;
1110 test_data = (mipi_hs_freq_range[i].hsfreqrange_code & 0x7f) |
1111 (1 << 7);
1112 test_mode_send(kmb_dsi, dphy_no, test_code, test_data);
1113 break;
1114 }
1115 }
1116
dphy_init_sequence(struct kmb_dsi * kmb_dsi,struct mipi_ctrl_cfg * cfg,u32 dphy_no,int active_lanes,enum dphy_mode mode)1117 static void dphy_init_sequence(struct kmb_dsi *kmb_dsi,
1118 struct mipi_ctrl_cfg *cfg, u32 dphy_no,
1119 int active_lanes, enum dphy_mode mode)
1120 {
1121 u32 test_code = 0, test_data = 0, val;
1122
1123 /* Set D-PHY in shutdown mode */
1124 /* Assert RSTZ signal */
1125 CLR_DPHY_INIT_CTRL0(kmb_dsi, dphy_no, RESETZ);
1126
1127 /* Assert SHUTDOWNZ signal */
1128 CLR_DPHY_INIT_CTRL0(kmb_dsi, dphy_no, SHUTDOWNZ);
1129 val = kmb_read_mipi(kmb_dsi, DPHY_INIT_CTRL0);
1130
1131 /* Init D-PHY_n
1132 * Pulse testclear signal to make sure the d-phy configuration
1133 * starts from a clean base
1134 */
1135 CLR_DPHY_TEST_CTRL0(kmb_dsi, dphy_no);
1136 ndelay(15);
1137 SET_DPHY_TEST_CTRL0(kmb_dsi, dphy_no);
1138 ndelay(15);
1139 CLR_DPHY_TEST_CTRL0(kmb_dsi, dphy_no);
1140 ndelay(15);
1141
1142 /* Set mastermacro bit - Master or slave mode */
1143 test_code = TEST_CODE_MULTIPLE_PHY_CTRL;
1144
1145 /* DPHY has its own clock lane enabled (master) */
1146 if (mode == MIPI_DPHY_MASTER)
1147 test_data = 0x01;
1148 else
1149 test_data = 0x00;
1150
1151 /* Send the test code and data */
1152 test_mode_send(kmb_dsi, dphy_no, test_code, test_data);
1153
1154 /* Set the lane data rate */
1155 set_lane_data_rate(kmb_dsi, dphy_no, cfg);
1156
1157 /* High-Speed Tx Slew Rate Calibration
1158 * BitRate: > 1.5 Gbps && <= 2.5 Gbps: slew rate control OFF
1159 */
1160 if (cfg->lane_rate_mbps > 1500)
1161 set_slewrate_gt_1500(kmb_dsi, dphy_no);
1162 else if (cfg->lane_rate_mbps > 1000)
1163 set_slewrate_gt_1000(kmb_dsi, dphy_no);
1164 else
1165 set_slewrate_lt_1000(kmb_dsi, dphy_no);
1166
1167 /* Set cfgclkfreqrange */
1168 val = (((cfg->cfg_clk_khz / 1000) - 17) * 4) & 0x3f;
1169 SET_DPHY_FREQ_CTRL0_3(kmb_dsi, dphy_no, val);
1170
1171 /* Enable config clk for the corresponding d-phy */
1172 kmb_set_bit_mipi(kmb_dsi, DPHY_CFG_CLK_EN, dphy_no);
1173
1174 /* PLL setup */
1175 if (mode == MIPI_DPHY_MASTER)
1176 setup_pll(kmb_dsi, dphy_no, cfg);
1177
1178 /* Send NORMAL OPERATION test code */
1179 test_code = 0x0;
1180 test_data = 0x0;
1181 test_mode_send(kmb_dsi, dphy_no, test_code, test_data);
1182
1183 /* Configure BASEDIR for data lanes
1184 * NOTE: basedir only applies to LANE_0 of each D-PHY.
1185 * The other lanes keep their direction based on the D-PHY type,
1186 * either Rx or Tx.
1187 * bits[5:0] - BaseDir: 1 = Rx
1188 * bits[9:6] - BaseDir: 0 = Tx
1189 */
1190 kmb_write_bits_mipi(kmb_dsi, DPHY_INIT_CTRL2, 0, 9, 0x03f);
1191 ndelay(15);
1192
1193 /* Enable CLOCK LANE
1194 * Clock lane should be enabled regardless of the direction
1195 * set for the D-PHY (Rx/Tx)
1196 */
1197 kmb_set_bit_mipi(kmb_dsi, DPHY_INIT_CTRL2, 12 + dphy_no);
1198
1199 /* Enable DATA LANES */
1200 kmb_write_bits_mipi(kmb_dsi, DPHY_ENABLE, dphy_no * 2, 2,
1201 ((1 << active_lanes) - 1));
1202
1203 ndelay(15);
1204
1205 /* Take D-PHY out of shutdown mode */
1206 /* Deassert SHUTDOWNZ signal */
1207 SET_DPHY_INIT_CTRL0(kmb_dsi, dphy_no, SHUTDOWNZ);
1208 ndelay(15);
1209
1210 /* Deassert RSTZ signal */
1211 SET_DPHY_INIT_CTRL0(kmb_dsi, dphy_no, RESETZ);
1212 }
1213
dphy_wait_fsm(struct kmb_dsi * kmb_dsi,u32 dphy_no,enum dphy_tx_fsm fsm_state)1214 static void dphy_wait_fsm(struct kmb_dsi *kmb_dsi, u32 dphy_no,
1215 enum dphy_tx_fsm fsm_state)
1216 {
1217 enum dphy_tx_fsm val = DPHY_TX_POWERDWN;
1218 int i = 0;
1219 int status = 1;
1220
1221 do {
1222 test_mode_send(kmb_dsi, dphy_no, TEST_CODE_FSM_CONTROL, 0x80);
1223
1224 val = GET_TEST_DOUT4_7(kmb_dsi, dphy_no);
1225 i++;
1226 if (i > TIMEOUT) {
1227 status = 0;
1228 break;
1229 }
1230 } while (val != fsm_state);
1231
1232 dev_dbg(kmb_dsi->dev, "%s: dphy %d val = %x", __func__, dphy_no, val);
1233 dev_dbg(kmb_dsi->dev, "* DPHY %d WAIT_FSM %s *",
1234 dphy_no, status ? "SUCCESS" : "FAILED");
1235 }
1236
wait_init_done(struct kmb_dsi * kmb_dsi,u32 dphy_no,u32 active_lanes)1237 static void wait_init_done(struct kmb_dsi *kmb_dsi, u32 dphy_no,
1238 u32 active_lanes)
1239 {
1240 u32 stopstatedata = 0;
1241 u32 data_lanes = (1 << active_lanes) - 1;
1242 int i = 0;
1243 int status = 1;
1244
1245 do {
1246 stopstatedata = GET_STOPSTATE_DATA(kmb_dsi, dphy_no)
1247 & data_lanes;
1248
1249 /* TODO-need to add a time out and return failure */
1250 i++;
1251
1252 if (i > TIMEOUT) {
1253 status = 0;
1254 dev_dbg(kmb_dsi->dev,
1255 "! WAIT_INIT_DONE: TIMING OUT!(err_stat=%d)",
1256 kmb_read_mipi(kmb_dsi, MIPI_DPHY_ERR_STAT6_7));
1257 break;
1258 }
1259 } while (stopstatedata != data_lanes);
1260
1261 dev_dbg(kmb_dsi->dev, "* DPHY %d INIT - %s *",
1262 dphy_no, status ? "SUCCESS" : "FAILED");
1263 }
1264
wait_pll_lock(struct kmb_dsi * kmb_dsi,u32 dphy_no)1265 static void wait_pll_lock(struct kmb_dsi *kmb_dsi, u32 dphy_no)
1266 {
1267 int i = 0;
1268 int status = 1;
1269
1270 do {
1271 /* TODO-need to add a time out and return failure */
1272 i++;
1273 if (i > TIMEOUT) {
1274 status = 0;
1275 dev_dbg(kmb_dsi->dev, "%s: timing out", __func__);
1276 break;
1277 }
1278 } while (!GET_PLL_LOCK(kmb_dsi, dphy_no));
1279
1280 dev_dbg(kmb_dsi->dev, "* PLL Locked for DPHY %d - %s *",
1281 dphy_no, status ? "SUCCESS" : "FAILED");
1282 }
1283
mipi_tx_init_dphy(struct kmb_dsi * kmb_dsi,struct mipi_ctrl_cfg * cfg)1284 static u32 mipi_tx_init_dphy(struct kmb_dsi *kmb_dsi,
1285 struct mipi_ctrl_cfg *cfg)
1286 {
1287 u32 dphy_no = MIPI_DPHY6;
1288
1289 /* Multiple D-PHYs needed */
1290 if (cfg->active_lanes > MIPI_DPHY_D_LANES) {
1291 /*
1292 *Initialization for Tx aggregation mode is done according to
1293 *a. start init PHY1
1294 *b. poll for PHY1 FSM state LOCK
1295 * b1. reg addr 0x03[3:0] - state_main[3:0] == 5 (LOCK)
1296 *c. poll for PHY1 calibrations done :
1297 * c1. termination calibration lower section: addr 0x22[5]
1298 * - rescal_done
1299 * c2. slewrate calibration (if data rate < = 1500 Mbps):
1300 * addr 0xA7[3:2] - srcal_done, sr_finished
1301 *d. start init PHY0
1302 *e. poll for PHY0 stopstate
1303 *f. poll for PHY1 stopstate
1304 */
1305 /* PHY #N+1 ('slave') */
1306
1307 dphy_init_sequence(kmb_dsi, cfg, dphy_no + 1,
1308 (cfg->active_lanes - MIPI_DPHY_D_LANES),
1309 MIPI_DPHY_SLAVE);
1310 dphy_wait_fsm(kmb_dsi, dphy_no + 1, DPHY_TX_LOCK);
1311
1312 /* PHY #N master */
1313 dphy_init_sequence(kmb_dsi, cfg, dphy_no, MIPI_DPHY_D_LANES,
1314 MIPI_DPHY_MASTER);
1315
1316 /* Wait for DPHY init to complete */
1317 wait_init_done(kmb_dsi, dphy_no, MIPI_DPHY_D_LANES);
1318 wait_init_done(kmb_dsi, dphy_no + 1,
1319 cfg->active_lanes - MIPI_DPHY_D_LANES);
1320 wait_pll_lock(kmb_dsi, dphy_no);
1321 wait_pll_lock(kmb_dsi, dphy_no + 1);
1322 dphy_wait_fsm(kmb_dsi, dphy_no, DPHY_TX_IDLE);
1323 } else { /* Single DPHY */
1324 dphy_init_sequence(kmb_dsi, cfg, dphy_no, cfg->active_lanes,
1325 MIPI_DPHY_MASTER);
1326 dphy_wait_fsm(kmb_dsi, dphy_no, DPHY_TX_IDLE);
1327 wait_init_done(kmb_dsi, dphy_no, cfg->active_lanes);
1328 wait_pll_lock(kmb_dsi, dphy_no);
1329 }
1330
1331 return 0;
1332 }
1333
connect_lcd_to_mipi(struct kmb_dsi * kmb_dsi,struct drm_atomic_state * old_state)1334 static void connect_lcd_to_mipi(struct kmb_dsi *kmb_dsi,
1335 struct drm_atomic_state *old_state)
1336 {
1337 struct regmap *msscam;
1338
1339 msscam = syscon_regmap_lookup_by_compatible("intel,keembay-msscam");
1340 if (IS_ERR(msscam)) {
1341 dev_dbg(kmb_dsi->dev, "failed to get msscam syscon");
1342 return;
1343 }
1344 drm_atomic_bridge_chain_enable(adv_bridge, old_state);
1345 /* DISABLE MIPI->CIF CONNECTION */
1346 regmap_write(msscam, MSS_MIPI_CIF_CFG, 0);
1347
1348 /* ENABLE LCD->MIPI CONNECTION */
1349 regmap_write(msscam, MSS_LCD_MIPI_CFG, 1);
1350 /* DISABLE LCD->CIF LOOPBACK */
1351 regmap_write(msscam, MSS_LOOPBACK_CFG, 1);
1352 }
1353
kmb_dsi_mode_set(struct kmb_dsi * kmb_dsi,struct drm_display_mode * mode,int sys_clk_mhz,struct drm_atomic_state * old_state)1354 int kmb_dsi_mode_set(struct kmb_dsi *kmb_dsi, struct drm_display_mode *mode,
1355 int sys_clk_mhz, struct drm_atomic_state *old_state)
1356 {
1357 u64 data_rate;
1358
1359 kmb_dsi->sys_clk_mhz = sys_clk_mhz;
1360 mipi_tx_init_cfg.active_lanes = MIPI_TX_ACTIVE_LANES;
1361
1362 mipi_tx_frame0_sect_cfg.width_pixels = mode->crtc_hdisplay;
1363 mipi_tx_frame0_sect_cfg.height_lines = mode->crtc_vdisplay;
1364 mipitx_frame0_cfg.vsync_width =
1365 mode->crtc_vsync_end - mode->crtc_vsync_start;
1366 mipitx_frame0_cfg.v_backporch =
1367 mode->crtc_vtotal - mode->crtc_vsync_end;
1368 mipitx_frame0_cfg.v_frontporch =
1369 mode->crtc_vsync_start - mode->crtc_vdisplay;
1370 mipitx_frame0_cfg.hsync_width =
1371 mode->crtc_hsync_end - mode->crtc_hsync_start;
1372 mipitx_frame0_cfg.h_backporch =
1373 mode->crtc_htotal - mode->crtc_hsync_end;
1374 mipitx_frame0_cfg.h_frontporch =
1375 mode->crtc_hsync_start - mode->crtc_hdisplay;
1376
1377 /* Lane rate = (vtotal*htotal*fps*bpp)/4 / 1000000
1378 * to convert to Mbps
1379 */
1380 data_rate = ((((u32)mode->crtc_vtotal * (u32)mode->crtc_htotal) *
1381 (u32)(drm_mode_vrefresh(mode)) *
1382 MIPI_TX_BPP) / mipi_tx_init_cfg.active_lanes) / 1000000;
1383
1384 dev_dbg(kmb_dsi->dev, "data_rate=%u active_lanes=%d\n",
1385 (u32)data_rate, mipi_tx_init_cfg.active_lanes);
1386
1387 /* When late rate < 800, modeset fails with 4 lanes,
1388 * so switch to 2 lanes
1389 */
1390 if (data_rate < 800) {
1391 mipi_tx_init_cfg.active_lanes = 2;
1392 mipi_tx_init_cfg.lane_rate_mbps = data_rate * 2;
1393 } else {
1394 mipi_tx_init_cfg.lane_rate_mbps = data_rate;
1395 }
1396
1397 /* Initialize mipi controller */
1398 mipi_tx_init_cntrl(kmb_dsi, &mipi_tx_init_cfg);
1399
1400 /* Dphy initialization */
1401 mipi_tx_init_dphy(kmb_dsi, &mipi_tx_init_cfg);
1402
1403 connect_lcd_to_mipi(kmb_dsi, old_state);
1404 dev_info(kmb_dsi->dev, "mipi hw initialized");
1405
1406 return 0;
1407 }
1408
kmb_dsi_init(struct platform_device * pdev)1409 struct kmb_dsi *kmb_dsi_init(struct platform_device *pdev)
1410 {
1411 struct kmb_dsi *kmb_dsi;
1412 struct device *dev = get_device(&pdev->dev);
1413
1414 kmb_dsi = devm_kzalloc(dev, sizeof(*kmb_dsi), GFP_KERNEL);
1415 if (!kmb_dsi) {
1416 dev_err(dev, "failed to allocate kmb_dsi\n");
1417 return ERR_PTR(-ENOMEM);
1418 }
1419
1420 kmb_dsi->host = dsi_host;
1421 kmb_dsi->host->ops = &kmb_dsi_host_ops;
1422
1423 dsi_device->host = kmb_dsi->host;
1424 kmb_dsi->device = dsi_device;
1425
1426 return kmb_dsi;
1427 }
1428
kmb_dsi_encoder_init(struct drm_device * dev,struct kmb_dsi * kmb_dsi)1429 int kmb_dsi_encoder_init(struct drm_device *dev, struct kmb_dsi *kmb_dsi)
1430 {
1431 struct drm_encoder *encoder;
1432 struct drm_connector *connector;
1433 int ret = 0;
1434
1435 encoder = &kmb_dsi->base;
1436 encoder->possible_crtcs = 1;
1437 encoder->possible_clones = 0;
1438
1439 ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_DSI);
1440 if (ret) {
1441 dev_err(kmb_dsi->dev, "Failed to init encoder %d\n", ret);
1442 return ret;
1443 }
1444
1445 /* Link drm_bridge to encoder */
1446 ret = drm_bridge_attach(encoder, adv_bridge, NULL,
1447 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
1448 if (ret) {
1449 drm_encoder_cleanup(encoder);
1450 return ret;
1451 }
1452 drm_info(dev, "Bridge attached : SUCCESS");
1453 connector = drm_bridge_connector_init(dev, encoder);
1454 if (IS_ERR(connector)) {
1455 DRM_ERROR("Unable to create bridge connector");
1456 drm_encoder_cleanup(encoder);
1457 return PTR_ERR(connector);
1458 }
1459 drm_connector_attach_encoder(connector, encoder);
1460 return 0;
1461 }
1462
kmb_dsi_map_mmio(struct kmb_dsi * kmb_dsi)1463 int kmb_dsi_map_mmio(struct kmb_dsi *kmb_dsi)
1464 {
1465 struct resource *res;
1466 struct device *dev = kmb_dsi->dev;
1467
1468 res = platform_get_resource_byname(kmb_dsi->pdev, IORESOURCE_MEM,
1469 "mipi");
1470 if (!res) {
1471 dev_err(dev, "failed to get resource for mipi");
1472 return -ENOMEM;
1473 }
1474 kmb_dsi->mipi_mmio = devm_ioremap_resource(dev, res);
1475 if (IS_ERR(kmb_dsi->mipi_mmio)) {
1476 dev_err(dev, "failed to ioremap mipi registers");
1477 return PTR_ERR(kmb_dsi->mipi_mmio);
1478 }
1479 return 0;
1480 }
1481
kmb_dsi_clk_enable(struct kmb_dsi * kmb_dsi)1482 static int kmb_dsi_clk_enable(struct kmb_dsi *kmb_dsi)
1483 {
1484 int ret;
1485 struct device *dev = kmb_dsi->dev;
1486
1487 ret = clk_prepare_enable(kmb_dsi->clk_mipi);
1488 if (ret) {
1489 dev_err(dev, "Failed to enable MIPI clock: %d\n", ret);
1490 return ret;
1491 }
1492
1493 ret = clk_prepare_enable(kmb_dsi->clk_mipi_ecfg);
1494 if (ret) {
1495 dev_err(dev, "Failed to enable MIPI_ECFG clock: %d\n", ret);
1496 return ret;
1497 }
1498
1499 ret = clk_prepare_enable(kmb_dsi->clk_mipi_cfg);
1500 if (ret) {
1501 dev_err(dev, "Failed to enable MIPI_CFG clock: %d\n", ret);
1502 return ret;
1503 }
1504
1505 dev_info(dev, "SUCCESS : enabled MIPI clocks\n");
1506 return 0;
1507 }
1508
kmb_dsi_clk_init(struct kmb_dsi * kmb_dsi)1509 int kmb_dsi_clk_init(struct kmb_dsi *kmb_dsi)
1510 {
1511 struct device *dev = kmb_dsi->dev;
1512 unsigned long clk;
1513
1514 kmb_dsi->clk_mipi = devm_clk_get(dev, "clk_mipi");
1515 if (IS_ERR(kmb_dsi->clk_mipi)) {
1516 dev_err(dev, "devm_clk_get() failed clk_mipi\n");
1517 return PTR_ERR(kmb_dsi->clk_mipi);
1518 }
1519
1520 kmb_dsi->clk_mipi_ecfg = devm_clk_get(dev, "clk_mipi_ecfg");
1521 if (IS_ERR(kmb_dsi->clk_mipi_ecfg)) {
1522 dev_err(dev, "devm_clk_get() failed clk_mipi_ecfg\n");
1523 return PTR_ERR(kmb_dsi->clk_mipi_ecfg);
1524 }
1525
1526 kmb_dsi->clk_mipi_cfg = devm_clk_get(dev, "clk_mipi_cfg");
1527 if (IS_ERR(kmb_dsi->clk_mipi_cfg)) {
1528 dev_err(dev, "devm_clk_get() failed clk_mipi_cfg\n");
1529 return PTR_ERR(kmb_dsi->clk_mipi_cfg);
1530 }
1531 /* Set MIPI clock to 24 Mhz */
1532 clk_set_rate(kmb_dsi->clk_mipi, KMB_MIPI_DEFAULT_CLK);
1533 if (clk_get_rate(kmb_dsi->clk_mipi) != KMB_MIPI_DEFAULT_CLK) {
1534 dev_err(dev, "failed to set to clk_mipi to %d\n",
1535 KMB_MIPI_DEFAULT_CLK);
1536 return -1;
1537 }
1538 dev_dbg(dev, "clk_mipi = %ld\n", clk_get_rate(kmb_dsi->clk_mipi));
1539
1540 clk = clk_get_rate(kmb_dsi->clk_mipi_ecfg);
1541 if (clk != KMB_MIPI_DEFAULT_CFG_CLK) {
1542 /* Set MIPI_ECFG clock to 24 Mhz */
1543 clk_set_rate(kmb_dsi->clk_mipi_ecfg, KMB_MIPI_DEFAULT_CFG_CLK);
1544 clk = clk_get_rate(kmb_dsi->clk_mipi_ecfg);
1545 if (clk != KMB_MIPI_DEFAULT_CFG_CLK) {
1546 dev_err(dev, "failed to set to clk_mipi_ecfg to %d\n",
1547 KMB_MIPI_DEFAULT_CFG_CLK);
1548 return -1;
1549 }
1550 }
1551
1552 clk = clk_get_rate(kmb_dsi->clk_mipi_cfg);
1553 if (clk != KMB_MIPI_DEFAULT_CFG_CLK) {
1554 /* Set MIPI_CFG clock to 24 Mhz */
1555 clk_set_rate(kmb_dsi->clk_mipi_cfg, 24000000);
1556 clk = clk_get_rate(kmb_dsi->clk_mipi_cfg);
1557 if (clk != KMB_MIPI_DEFAULT_CFG_CLK) {
1558 dev_err(dev, "failed to set clk_mipi_cfg to %d\n",
1559 KMB_MIPI_DEFAULT_CFG_CLK);
1560 return -1;
1561 }
1562 }
1563
1564 return kmb_dsi_clk_enable(kmb_dsi);
1565 }
1566