1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3  * Copyright 2014-2022 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  */
23 
24 #include <linux/bsearch.h>
25 #include <linux/pci.h>
26 #include <linux/slab.h>
27 #include "kfd_priv.h"
28 #include "kfd_device_queue_manager.h"
29 #include "kfd_pm4_headers_vi.h"
30 #include "kfd_pm4_headers_aldebaran.h"
31 #include "cwsr_trap_handler.h"
32 #include "amdgpu_amdkfd.h"
33 #include "kfd_smi_events.h"
34 #include "kfd_svm.h"
35 #include "kfd_migrate.h"
36 #include "amdgpu.h"
37 #include "amdgpu_xcp.h"
38 
39 #define MQD_SIZE_ALIGNED 768
40 
41 /*
42  * kfd_locked is used to lock the kfd driver during suspend or reset
43  * once locked, kfd driver will stop any further GPU execution.
44  * create process (open) will return -EAGAIN.
45  */
46 static int kfd_locked;
47 
48 #ifdef CONFIG_DRM_AMDGPU_CIK
49 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd;
50 #endif
51 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd;
52 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd;
53 extern const struct kfd2kgd_calls arcturus_kfd2kgd;
54 extern const struct kfd2kgd_calls aldebaran_kfd2kgd;
55 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd;
56 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd;
57 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd;
58 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd;
59 
60 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
61 				unsigned int chunk_size);
62 static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
63 
64 static int kfd_resume(struct kfd_node *kfd);
65 
kfd_device_info_set_sdma_info(struct kfd_dev * kfd)66 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd)
67 {
68 	uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0];
69 
70 	switch (sdma_version) {
71 	case IP_VERSION(4, 0, 0):/* VEGA10 */
72 	case IP_VERSION(4, 0, 1):/* VEGA12 */
73 	case IP_VERSION(4, 1, 0):/* RAVEN */
74 	case IP_VERSION(4, 1, 1):/* RAVEN */
75 	case IP_VERSION(4, 1, 2):/* RENOIR */
76 	case IP_VERSION(5, 2, 1):/* VANGOGH */
77 	case IP_VERSION(5, 2, 3):/* YELLOW_CARP */
78 	case IP_VERSION(5, 2, 6):/* GC 10.3.6 */
79 	case IP_VERSION(5, 2, 7):/* GC 10.3.7 */
80 		kfd->device_info.num_sdma_queues_per_engine = 2;
81 		break;
82 	case IP_VERSION(4, 2, 0):/* VEGA20 */
83 	case IP_VERSION(4, 2, 2):/* ARCTURUS */
84 	case IP_VERSION(4, 4, 0):/* ALDEBARAN */
85 	case IP_VERSION(4, 4, 2):
86 	case IP_VERSION(5, 0, 0):/* NAVI10 */
87 	case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */
88 	case IP_VERSION(5, 0, 2):/* NAVI14 */
89 	case IP_VERSION(5, 0, 5):/* NAVI12 */
90 	case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */
91 	case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */
92 	case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */
93 	case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */
94 	case IP_VERSION(6, 0, 0):
95 	case IP_VERSION(6, 0, 1):
96 	case IP_VERSION(6, 0, 2):
97 	case IP_VERSION(6, 0, 3):
98 		kfd->device_info.num_sdma_queues_per_engine = 8;
99 		break;
100 	default:
101 		dev_warn(kfd_device,
102 			"Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n",
103 			sdma_version);
104 		kfd->device_info.num_sdma_queues_per_engine = 8;
105 	}
106 
107 	bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES);
108 
109 	switch (sdma_version) {
110 	case IP_VERSION(6, 0, 0):
111 	case IP_VERSION(6, 0, 1):
112 	case IP_VERSION(6, 0, 2):
113 	case IP_VERSION(6, 0, 3):
114 		/* Reserve 1 for paging and 1 for gfx */
115 		kfd->device_info.num_reserved_sdma_queues_per_engine = 2;
116 		/* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */
117 		bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0,
118 			   kfd->adev->sdma.num_instances *
119 			   kfd->device_info.num_reserved_sdma_queues_per_engine);
120 		break;
121 	default:
122 		break;
123 	}
124 }
125 
kfd_device_info_set_event_interrupt_class(struct kfd_dev * kfd)126 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd)
127 {
128 	uint32_t gc_version = KFD_GC_VERSION(kfd);
129 
130 	switch (gc_version) {
131 	case IP_VERSION(9, 0, 1): /* VEGA10 */
132 	case IP_VERSION(9, 1, 0): /* RAVEN */
133 	case IP_VERSION(9, 2, 1): /* VEGA12 */
134 	case IP_VERSION(9, 2, 2): /* RAVEN */
135 	case IP_VERSION(9, 3, 0): /* RENOIR */
136 	case IP_VERSION(9, 4, 0): /* VEGA20 */
137 	case IP_VERSION(9, 4, 1): /* ARCTURUS */
138 	case IP_VERSION(9, 4, 2): /* ALDEBARAN */
139 		kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
140 		break;
141 	case IP_VERSION(9, 4, 3): /* GC 9.4.3 */
142 		kfd->device_info.event_interrupt_class =
143 						&event_interrupt_class_v9_4_3;
144 		break;
145 	case IP_VERSION(10, 3, 1): /* VANGOGH */
146 	case IP_VERSION(10, 3, 3): /* YELLOW_CARP */
147 	case IP_VERSION(10, 3, 6): /* GC 10.3.6 */
148 	case IP_VERSION(10, 3, 7): /* GC 10.3.7 */
149 	case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */
150 	case IP_VERSION(10, 1, 4):
151 	case IP_VERSION(10, 1, 10): /* NAVI10 */
152 	case IP_VERSION(10, 1, 2): /* NAVI12 */
153 	case IP_VERSION(10, 1, 1): /* NAVI14 */
154 	case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */
155 	case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */
156 	case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */
157 	case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */
158 		kfd->device_info.event_interrupt_class = &event_interrupt_class_v10;
159 		break;
160 	case IP_VERSION(11, 0, 0):
161 	case IP_VERSION(11, 0, 1):
162 	case IP_VERSION(11, 0, 2):
163 	case IP_VERSION(11, 0, 3):
164 	case IP_VERSION(11, 0, 4):
165 		kfd->device_info.event_interrupt_class = &event_interrupt_class_v11;
166 		break;
167 	default:
168 		dev_warn(kfd_device, "v9 event interrupt handler is set due to "
169 			"mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version);
170 		kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
171 	}
172 }
173 
kfd_device_info_init(struct kfd_dev * kfd,bool vf,uint32_t gfx_target_version)174 static void kfd_device_info_init(struct kfd_dev *kfd,
175 				 bool vf, uint32_t gfx_target_version)
176 {
177 	uint32_t gc_version = KFD_GC_VERSION(kfd);
178 	uint32_t asic_type = kfd->adev->asic_type;
179 
180 	kfd->device_info.max_pasid_bits = 16;
181 	kfd->device_info.max_no_of_hqd = 24;
182 	kfd->device_info.num_of_watch_points = 4;
183 	kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED;
184 	kfd->device_info.gfx_target_version = gfx_target_version;
185 
186 	if (KFD_IS_SOC15(kfd)) {
187 		kfd->device_info.doorbell_size = 8;
188 		kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t);
189 		kfd->device_info.supports_cwsr = true;
190 
191 		kfd_device_info_set_sdma_info(kfd);
192 
193 		kfd_device_info_set_event_interrupt_class(kfd);
194 
195 		if (gc_version < IP_VERSION(11, 0, 0)) {
196 			/* Navi2x+, Navi1x+ */
197 			if (gc_version == IP_VERSION(10, 3, 6))
198 				kfd->device_info.no_atomic_fw_version = 14;
199 			else if (gc_version == IP_VERSION(10, 3, 7))
200 				kfd->device_info.no_atomic_fw_version = 3;
201 			else if (gc_version >= IP_VERSION(10, 3, 0))
202 				kfd->device_info.no_atomic_fw_version = 92;
203 			else if (gc_version >= IP_VERSION(10, 1, 1))
204 				kfd->device_info.no_atomic_fw_version = 145;
205 
206 			/* Navi1x+ */
207 			if (gc_version >= IP_VERSION(10, 1, 1))
208 				kfd->device_info.needs_pci_atomics = true;
209 		} else if (gc_version < IP_VERSION(12, 0, 0)) {
210 			/*
211 			 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires
212 			 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require
213 			 * PCIe atomics support.
214 			 */
215 			kfd->device_info.needs_pci_atomics = true;
216 			kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0;
217 		}
218 	} else {
219 		kfd->device_info.doorbell_size = 4;
220 		kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t);
221 		kfd->device_info.event_interrupt_class = &event_interrupt_class_cik;
222 		kfd->device_info.num_sdma_queues_per_engine = 2;
223 
224 		if (asic_type != CHIP_KAVERI &&
225 		    asic_type != CHIP_HAWAII &&
226 		    asic_type != CHIP_TONGA)
227 			kfd->device_info.supports_cwsr = true;
228 
229 		if (asic_type != CHIP_HAWAII && !vf)
230 			kfd->device_info.needs_pci_atomics = true;
231 	}
232 }
233 
kgd2kfd_probe(struct amdgpu_device * adev,bool vf)234 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
235 {
236 	struct kfd_dev *kfd = NULL;
237 	const struct kfd2kgd_calls *f2g = NULL;
238 	uint32_t gfx_target_version = 0;
239 
240 	switch (adev->asic_type) {
241 #ifdef CONFIG_DRM_AMDGPU_CIK
242 	case CHIP_KAVERI:
243 		gfx_target_version = 70000;
244 		if (!vf)
245 			f2g = &gfx_v7_kfd2kgd;
246 		break;
247 #endif
248 	case CHIP_CARRIZO:
249 		gfx_target_version = 80001;
250 		if (!vf)
251 			f2g = &gfx_v8_kfd2kgd;
252 		break;
253 #ifdef CONFIG_DRM_AMDGPU_CIK
254 	case CHIP_HAWAII:
255 		gfx_target_version = 70001;
256 		if (!amdgpu_exp_hw_support)
257 			pr_info(
258 	"KFD support on Hawaii is experimental. See modparam exp_hw_support\n"
259 				);
260 		else if (!vf)
261 			f2g = &gfx_v7_kfd2kgd;
262 		break;
263 #endif
264 	case CHIP_TONGA:
265 		gfx_target_version = 80002;
266 		if (!vf)
267 			f2g = &gfx_v8_kfd2kgd;
268 		break;
269 	case CHIP_FIJI:
270 	case CHIP_POLARIS10:
271 		gfx_target_version = 80003;
272 		f2g = &gfx_v8_kfd2kgd;
273 		break;
274 	case CHIP_POLARIS11:
275 	case CHIP_POLARIS12:
276 	case CHIP_VEGAM:
277 		gfx_target_version = 80003;
278 		if (!vf)
279 			f2g = &gfx_v8_kfd2kgd;
280 		break;
281 	default:
282 		switch (adev->ip_versions[GC_HWIP][0]) {
283 		/* Vega 10 */
284 		case IP_VERSION(9, 0, 1):
285 			gfx_target_version = 90000;
286 			f2g = &gfx_v9_kfd2kgd;
287 			break;
288 		/* Raven */
289 		case IP_VERSION(9, 1, 0):
290 		case IP_VERSION(9, 2, 2):
291 			gfx_target_version = 90002;
292 			if (!vf)
293 				f2g = &gfx_v9_kfd2kgd;
294 			break;
295 		/* Vega12 */
296 		case IP_VERSION(9, 2, 1):
297 			gfx_target_version = 90004;
298 			if (!vf)
299 				f2g = &gfx_v9_kfd2kgd;
300 			break;
301 		/* Renoir */
302 		case IP_VERSION(9, 3, 0):
303 			gfx_target_version = 90012;
304 			if (!vf)
305 				f2g = &gfx_v9_kfd2kgd;
306 			break;
307 		/* Vega20 */
308 		case IP_VERSION(9, 4, 0):
309 			gfx_target_version = 90006;
310 			if (!vf)
311 				f2g = &gfx_v9_kfd2kgd;
312 			break;
313 		/* Arcturus */
314 		case IP_VERSION(9, 4, 1):
315 			gfx_target_version = 90008;
316 			f2g = &arcturus_kfd2kgd;
317 			break;
318 		/* Aldebaran */
319 		case IP_VERSION(9, 4, 2):
320 			gfx_target_version = 90010;
321 			f2g = &aldebaran_kfd2kgd;
322 			break;
323 		case IP_VERSION(9, 4, 3):
324 			gfx_target_version = adev->rev_id >= 1 ? 90402
325 					   : adev->flags & AMD_IS_APU ? 90400
326 					   : 90401;
327 			f2g = &gc_9_4_3_kfd2kgd;
328 			break;
329 		/* Navi10 */
330 		case IP_VERSION(10, 1, 10):
331 			gfx_target_version = 100100;
332 			if (!vf)
333 				f2g = &gfx_v10_kfd2kgd;
334 			break;
335 		/* Navi12 */
336 		case IP_VERSION(10, 1, 2):
337 			gfx_target_version = 100101;
338 			f2g = &gfx_v10_kfd2kgd;
339 			break;
340 		/* Navi14 */
341 		case IP_VERSION(10, 1, 1):
342 			gfx_target_version = 100102;
343 			if (!vf)
344 				f2g = &gfx_v10_kfd2kgd;
345 			break;
346 		/* Cyan Skillfish */
347 		case IP_VERSION(10, 1, 3):
348 		case IP_VERSION(10, 1, 4):
349 			gfx_target_version = 100103;
350 			if (!vf)
351 				f2g = &gfx_v10_kfd2kgd;
352 			break;
353 		/* Sienna Cichlid */
354 		case IP_VERSION(10, 3, 0):
355 			gfx_target_version = 100300;
356 			f2g = &gfx_v10_3_kfd2kgd;
357 			break;
358 		/* Navy Flounder */
359 		case IP_VERSION(10, 3, 2):
360 			gfx_target_version = 100301;
361 			f2g = &gfx_v10_3_kfd2kgd;
362 			break;
363 		/* Van Gogh */
364 		case IP_VERSION(10, 3, 1):
365 			gfx_target_version = 100303;
366 			if (!vf)
367 				f2g = &gfx_v10_3_kfd2kgd;
368 			break;
369 		/* Dimgrey Cavefish */
370 		case IP_VERSION(10, 3, 4):
371 			gfx_target_version = 100302;
372 			f2g = &gfx_v10_3_kfd2kgd;
373 			break;
374 		/* Beige Goby */
375 		case IP_VERSION(10, 3, 5):
376 			gfx_target_version = 100304;
377 			f2g = &gfx_v10_3_kfd2kgd;
378 			break;
379 		/* Yellow Carp */
380 		case IP_VERSION(10, 3, 3):
381 			gfx_target_version = 100305;
382 			if (!vf)
383 				f2g = &gfx_v10_3_kfd2kgd;
384 			break;
385 		case IP_VERSION(10, 3, 6):
386 		case IP_VERSION(10, 3, 7):
387 			gfx_target_version = 100306;
388 			if (!vf)
389 				f2g = &gfx_v10_3_kfd2kgd;
390 			break;
391 		case IP_VERSION(11, 0, 0):
392 			gfx_target_version = 110000;
393 			f2g = &gfx_v11_kfd2kgd;
394 			break;
395 		case IP_VERSION(11, 0, 1):
396 		case IP_VERSION(11, 0, 4):
397 			gfx_target_version = 110003;
398 			f2g = &gfx_v11_kfd2kgd;
399 			break;
400 		case IP_VERSION(11, 0, 2):
401 			gfx_target_version = 110002;
402 			f2g = &gfx_v11_kfd2kgd;
403 			break;
404 		case IP_VERSION(11, 0, 3):
405 			if ((adev->pdev->device == 0x7460 &&
406 			     adev->pdev->revision == 0x00) ||
407 			    (adev->pdev->device == 0x7461 &&
408 			     adev->pdev->revision == 0x00))
409 				/* Note: Compiler version is 11.0.5 while HW version is 11.0.3 */
410 				gfx_target_version = 110005;
411 			else
412 				/* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */
413 				gfx_target_version = 110001;
414 			f2g = &gfx_v11_kfd2kgd;
415 			break;
416 		default:
417 			break;
418 		}
419 		break;
420 	}
421 
422 	if (!f2g) {
423 		if (adev->ip_versions[GC_HWIP][0])
424 			dev_err(kfd_device, "GC IP %06x %s not supported in kfd\n",
425 				adev->ip_versions[GC_HWIP][0], vf ? "VF" : "");
426 		else
427 			dev_err(kfd_device, "%s %s not supported in kfd\n",
428 				amdgpu_asic_name[adev->asic_type], vf ? "VF" : "");
429 		return NULL;
430 	}
431 
432 	kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
433 	if (!kfd)
434 		return NULL;
435 
436 	kfd->adev = adev;
437 	kfd_device_info_init(kfd, vf, gfx_target_version);
438 	kfd->init_complete = false;
439 	kfd->kfd2kgd = f2g;
440 	atomic_set(&kfd->compute_profile, 0);
441 
442 	mutex_init(&kfd->doorbell_mutex);
443 
444 	ida_init(&kfd->doorbell_ida);
445 
446 	return kfd;
447 }
448 
kfd_cwsr_init(struct kfd_dev * kfd)449 static void kfd_cwsr_init(struct kfd_dev *kfd)
450 {
451 	if (cwsr_enable && kfd->device_info.supports_cwsr) {
452 		if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) {
453 			BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE);
454 			kfd->cwsr_isa = cwsr_trap_gfx8_hex;
455 			kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
456 		} else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) {
457 			BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE);
458 			kfd->cwsr_isa = cwsr_trap_arcturus_hex;
459 			kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex);
460 		} else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) {
461 			BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE);
462 			kfd->cwsr_isa = cwsr_trap_aldebaran_hex;
463 			kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex);
464 		} else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) {
465 			BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) > PAGE_SIZE);
466 			kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex;
467 			kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex);
468 		} else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) {
469 			BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE);
470 			kfd->cwsr_isa = cwsr_trap_gfx9_hex;
471 			kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
472 		} else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) {
473 			BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE);
474 			kfd->cwsr_isa = cwsr_trap_nv1x_hex;
475 			kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex);
476 		} else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) {
477 			BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE);
478 			kfd->cwsr_isa = cwsr_trap_gfx10_hex;
479 			kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex);
480 		} else {
481 			BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE);
482 			kfd->cwsr_isa = cwsr_trap_gfx11_hex;
483 			kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex);
484 		}
485 
486 		kfd->cwsr_enabled = true;
487 	}
488 }
489 
kfd_gws_init(struct kfd_node * node)490 static int kfd_gws_init(struct kfd_node *node)
491 {
492 	int ret = 0;
493 	struct kfd_dev *kfd = node->kfd;
494 	uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;
495 
496 	if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS)
497 		return 0;
498 
499 	if (hws_gws_support || (KFD_IS_SOC15(node) &&
500 		((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1)
501 			&& kfd->mec2_fw_version >= 0x81b3) ||
502 		(KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0)
503 			&& kfd->mec2_fw_version >= 0x1b3)  ||
504 		(KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1)
505 			&& kfd->mec2_fw_version >= 0x30)   ||
506 		(KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2)
507 			&& kfd->mec2_fw_version >= 0x28) ||
508 		(KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3)) ||
509 		(KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0)
510 			&& KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0)
511 			&& kfd->mec2_fw_version >= 0x6b) ||
512 		(KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0)
513 			&& KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0)
514 			&& mes_rev >= 68))))
515 		ret = amdgpu_amdkfd_alloc_gws(node->adev,
516 				node->adev->gds.gws_size, &node->gws);
517 
518 	return ret;
519 }
520 
kfd_smi_init(struct kfd_node * dev)521 static void kfd_smi_init(struct kfd_node *dev)
522 {
523 	INIT_LIST_HEAD(&dev->smi_clients);
524 	spin_lock_init(&dev->smi_lock);
525 }
526 
kfd_init_node(struct kfd_node * node)527 static int kfd_init_node(struct kfd_node *node)
528 {
529 	int err = -1;
530 
531 	if (kfd_interrupt_init(node)) {
532 		dev_err(kfd_device, "Error initializing interrupts\n");
533 		goto kfd_interrupt_error;
534 	}
535 
536 	node->dqm = device_queue_manager_init(node);
537 	if (!node->dqm) {
538 		dev_err(kfd_device, "Error initializing queue manager\n");
539 		goto device_queue_manager_error;
540 	}
541 
542 	if (kfd_gws_init(node)) {
543 		dev_err(kfd_device, "Could not allocate %d gws\n",
544 			node->adev->gds.gws_size);
545 		goto gws_error;
546 	}
547 
548 	if (kfd_resume(node))
549 		goto kfd_resume_error;
550 
551 	if (kfd_topology_add_device(node)) {
552 		dev_err(kfd_device, "Error adding device to topology\n");
553 		goto kfd_topology_add_device_error;
554 	}
555 
556 	kfd_smi_init(node);
557 
558 	return 0;
559 
560 kfd_topology_add_device_error:
561 kfd_resume_error:
562 gws_error:
563 	device_queue_manager_uninit(node->dqm);
564 device_queue_manager_error:
565 	kfd_interrupt_exit(node);
566 kfd_interrupt_error:
567 	if (node->gws)
568 		amdgpu_amdkfd_free_gws(node->adev, node->gws);
569 
570 	/* Cleanup the node memory here */
571 	kfree(node);
572 	return err;
573 }
574 
kfd_cleanup_nodes(struct kfd_dev * kfd,unsigned int num_nodes)575 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes)
576 {
577 	struct kfd_node *knode;
578 	unsigned int i;
579 
580 	for (i = 0; i < num_nodes; i++) {
581 		knode = kfd->nodes[i];
582 		device_queue_manager_uninit(knode->dqm);
583 		kfd_interrupt_exit(knode);
584 		kfd_topology_remove_device(knode);
585 		if (knode->gws)
586 			amdgpu_amdkfd_free_gws(knode->adev, knode->gws);
587 		kfree(knode);
588 		kfd->nodes[i] = NULL;
589 	}
590 }
591 
kfd_setup_interrupt_bitmap(struct kfd_node * node,unsigned int kfd_node_idx)592 static void kfd_setup_interrupt_bitmap(struct kfd_node *node,
593 				       unsigned int kfd_node_idx)
594 {
595 	struct amdgpu_device *adev = node->adev;
596 	uint32_t xcc_mask = node->xcc_mask;
597 	uint32_t xcc, mapped_xcc;
598 	/*
599 	 * Interrupt bitmap is setup for processing interrupts from
600 	 * different XCDs and AIDs.
601 	 * Interrupt bitmap is defined as follows:
602 	 * 1. Bits 0-15 - correspond to the NodeId field.
603 	 *    Each bit corresponds to NodeId number. For example, if
604 	 *    a KFD node has interrupt bitmap set to 0x7, then this
605 	 *    KFD node will process interrupts with NodeId = 0, 1 and 2
606 	 *    in the IH cookie.
607 	 * 2. Bits 16-31 - unused.
608 	 *
609 	 * Please note that the kfd_node_idx argument passed to this
610 	 * function is not related to NodeId field received in the
611 	 * IH cookie.
612 	 *
613 	 * In CPX mode, a KFD node will process an interrupt if:
614 	 * - the Node Id matches the corresponding bit set in
615 	 *   Bits 0-15.
616 	 * - AND VMID reported in the interrupt lies within the
617 	 *   VMID range of the node.
618 	 */
619 	for_each_inst(xcc, xcc_mask) {
620 		mapped_xcc = GET_INST(GC, xcc);
621 		node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2));
622 	}
623 	dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx,
624 							node->interrupt_bitmap);
625 }
626 
kgd2kfd_device_init(struct kfd_dev * kfd,const struct kgd2kfd_shared_resources * gpu_resources)627 bool kgd2kfd_device_init(struct kfd_dev *kfd,
628 			 const struct kgd2kfd_shared_resources *gpu_resources)
629 {
630 	unsigned int size, map_process_packet_size, i;
631 	struct kfd_node *node;
632 	uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd;
633 	unsigned int max_proc_per_quantum;
634 	int partition_mode;
635 	int xcp_idx;
636 
637 	kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
638 			KGD_ENGINE_MEC1);
639 	kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
640 			KGD_ENGINE_MEC2);
641 	kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
642 			KGD_ENGINE_SDMA1);
643 	kfd->shared_resources = *gpu_resources;
644 
645 	kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr);
646 
647 	if (kfd->num_nodes == 0) {
648 		dev_err(kfd_device,
649 			"KFD num nodes cannot be 0, num_xcc_in_node: %d\n",
650 			kfd->adev->gfx.num_xcc_per_xcp);
651 		goto out;
652 	}
653 
654 	/* Allow BIF to recode atomics to PCIe 3.0 AtomicOps.
655 	 * 32 and 64-bit requests are possible and must be
656 	 * supported.
657 	 */
658 	kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev);
659 	if (!kfd->pci_atomic_requested &&
660 	    kfd->device_info.needs_pci_atomics &&
661 	    (!kfd->device_info.no_atomic_fw_version ||
662 	     kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) {
663 		dev_info(kfd_device,
664 			 "skipped device %x:%x, PCI rejects atomics %d<%d\n",
665 			 kfd->adev->pdev->vendor, kfd->adev->pdev->device,
666 			 kfd->mec_fw_version,
667 			 kfd->device_info.no_atomic_fw_version);
668 		return false;
669 	}
670 
671 	first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1;
672 	last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1;
673 	vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1;
674 
675 	/* For GFX9.4.3, we need special handling for VMIDs depending on
676 	 * partition mode.
677 	 * In CPX mode, the VMID range needs to be shared between XCDs.
678 	 * Additionally, there are 13 VMIDs (3-15) available for KFD. To
679 	 * divide them equally, we change starting VMID to 4 and not use
680 	 * VMID 3.
681 	 * If the VMID range changes for GFX9.4.3, then this code MUST be
682 	 * revisited.
683 	 */
684 	if (kfd->adev->xcp_mgr) {
685 		partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr,
686 								 AMDGPU_XCP_FL_LOCKED);
687 		if (partition_mode == AMDGPU_CPX_PARTITION_MODE &&
688 		    kfd->num_nodes != 1) {
689 			vmid_num_kfd /= 2;
690 			first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2;
691 		}
692 	}
693 
694 	/* Verify module parameters regarding mapped process number*/
695 	if (hws_max_conc_proc >= 0)
696 		max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd);
697 	else
698 		max_proc_per_quantum = vmid_num_kfd;
699 
700 	/* calculate max size of mqds needed for queues */
701 	size = max_num_of_queues_per_device *
702 			kfd->device_info.mqd_size_aligned;
703 
704 	/*
705 	 * calculate max size of runlist packet.
706 	 * There can be only 2 packets at once
707 	 */
708 	map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ?
709 				sizeof(struct pm4_mes_map_process_aldebaran) :
710 				sizeof(struct pm4_mes_map_process);
711 	size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size +
712 		max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues)
713 		+ sizeof(struct pm4_mes_runlist)) * 2;
714 
715 	/* Add size of HIQ & DIQ */
716 	size += KFD_KERNEL_QUEUE_SIZE * 2;
717 
718 	/* add another 512KB for all other allocations on gart (HPD, fences) */
719 	size += 512 * 1024;
720 
721 	if (amdgpu_amdkfd_alloc_gtt_mem(
722 			kfd->adev, size, &kfd->gtt_mem,
723 			&kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
724 			false)) {
725 		dev_err(kfd_device, "Could not allocate %d bytes\n", size);
726 		goto alloc_gtt_mem_failure;
727 	}
728 
729 	dev_info(kfd_device, "Allocated %d bytes on gart\n", size);
730 
731 	/* Initialize GTT sa with 512 byte chunk size */
732 	if (kfd_gtt_sa_init(kfd, size, 512) != 0) {
733 		dev_err(kfd_device, "Error initializing gtt sub-allocator\n");
734 		goto kfd_gtt_sa_init_error;
735 	}
736 
737 	if (kfd_doorbell_init(kfd)) {
738 		dev_err(kfd_device,
739 			"Error initializing doorbell aperture\n");
740 		goto kfd_doorbell_error;
741 	}
742 
743 	if (amdgpu_use_xgmi_p2p)
744 		kfd->hive_id = kfd->adev->gmc.xgmi.hive_id;
745 
746 	/*
747 	 * For GFX9.4.3, the KFD abstracts all partitions within a socket as
748 	 * xGMI connected in the topology so assign a unique hive id per
749 	 * device based on the pci device location if device is in PCIe mode.
750 	 */
751 	if (!kfd->hive_id && (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) && kfd->num_nodes > 1)
752 		kfd->hive_id = pci_dev_id(kfd->adev->pdev);
753 
754 	kfd->noretry = kfd->adev->gmc.noretry;
755 
756 	kfd_cwsr_init(kfd);
757 
758 	dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n",
759 				kfd->num_nodes);
760 
761 	/* Allocate the KFD nodes */
762 	for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) {
763 		node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL);
764 		if (!node)
765 			goto node_alloc_error;
766 
767 		node->node_id = i;
768 		node->adev = kfd->adev;
769 		node->kfd = kfd;
770 		node->kfd2kgd = kfd->kfd2kgd;
771 		node->vm_info.vmid_num_kfd = vmid_num_kfd;
772 		node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx);
773 		/* TODO : Check if error handling is needed */
774 		if (node->xcp) {
775 			amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX,
776 						    &node->xcc_mask);
777 			++xcp_idx;
778 		} else {
779 			node->xcc_mask =
780 				(1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1;
781 		}
782 
783 		if (node->xcp) {
784 			dev_info(kfd_device, "KFD node %d partition %d size %lldM\n",
785 				node->node_id, node->xcp->mem_id,
786 				KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20);
787 		}
788 
789 		if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) &&
790 		    partition_mode == AMDGPU_CPX_PARTITION_MODE &&
791 		    kfd->num_nodes != 1) {
792 			/* For GFX9.4.3 and CPX mode, first XCD gets VMID range
793 			 * 4-9 and second XCD gets VMID range 10-15.
794 			 */
795 
796 			node->vm_info.first_vmid_kfd = (i%2 == 0) ?
797 						first_vmid_kfd :
798 						first_vmid_kfd+vmid_num_kfd;
799 			node->vm_info.last_vmid_kfd = (i%2 == 0) ?
800 						last_vmid_kfd-vmid_num_kfd :
801 						last_vmid_kfd;
802 			node->compute_vmid_bitmap =
803 				((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) -
804 				((0x1 << (node->vm_info.first_vmid_kfd)) - 1);
805 		} else {
806 			node->vm_info.first_vmid_kfd = first_vmid_kfd;
807 			node->vm_info.last_vmid_kfd = last_vmid_kfd;
808 			node->compute_vmid_bitmap =
809 				gpu_resources->compute_vmid_bitmap;
810 		}
811 		node->max_proc_per_quantum = max_proc_per_quantum;
812 		atomic_set(&node->sram_ecc_flag, 0);
813 
814 		amdgpu_amdkfd_get_local_mem_info(kfd->adev,
815 					&node->local_mem_info, node->xcp);
816 
817 		if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3))
818 			kfd_setup_interrupt_bitmap(node, i);
819 
820 		/* Initialize the KFD node */
821 		if (kfd_init_node(node)) {
822 			dev_err(kfd_device, "Error initializing KFD node\n");
823 			goto node_init_error;
824 		}
825 		kfd->nodes[i] = node;
826 	}
827 
828 	svm_range_set_max_pages(kfd->adev);
829 
830 	spin_lock_init(&kfd->watch_points_lock);
831 
832 	kfd->init_complete = true;
833 	dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor,
834 		 kfd->adev->pdev->device);
835 
836 	pr_debug("Starting kfd with the following scheduling policy %d\n",
837 		node->dqm->sched_policy);
838 
839 	goto out;
840 
841 node_init_error:
842 node_alloc_error:
843 	kfd_cleanup_nodes(kfd, i);
844 	kfd_doorbell_fini(kfd);
845 kfd_doorbell_error:
846 	kfd_gtt_sa_fini(kfd);
847 kfd_gtt_sa_init_error:
848 	amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem);
849 alloc_gtt_mem_failure:
850 	dev_err(kfd_device,
851 		"device %x:%x NOT added due to errors\n",
852 		kfd->adev->pdev->vendor, kfd->adev->pdev->device);
853 out:
854 	return kfd->init_complete;
855 }
856 
kgd2kfd_device_exit(struct kfd_dev * kfd)857 void kgd2kfd_device_exit(struct kfd_dev *kfd)
858 {
859 	if (kfd->init_complete) {
860 		/* Cleanup KFD nodes */
861 		kfd_cleanup_nodes(kfd, kfd->num_nodes);
862 		/* Cleanup common/shared resources */
863 		kfd_doorbell_fini(kfd);
864 		ida_destroy(&kfd->doorbell_ida);
865 		kfd_gtt_sa_fini(kfd);
866 		amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem);
867 	}
868 
869 	kfree(kfd);
870 }
871 
kgd2kfd_pre_reset(struct kfd_dev * kfd)872 int kgd2kfd_pre_reset(struct kfd_dev *kfd)
873 {
874 	struct kfd_node *node;
875 	int i;
876 
877 	if (!kfd->init_complete)
878 		return 0;
879 
880 	for (i = 0; i < kfd->num_nodes; i++) {
881 		node = kfd->nodes[i];
882 		kfd_smi_event_update_gpu_reset(node, false);
883 		node->dqm->ops.pre_reset(node->dqm);
884 	}
885 
886 	kgd2kfd_suspend(kfd, false);
887 
888 	for (i = 0; i < kfd->num_nodes; i++)
889 		kfd_signal_reset_event(kfd->nodes[i]);
890 
891 	return 0;
892 }
893 
894 /*
895  * Fix me. KFD won't be able to resume existing process for now.
896  * We will keep all existing process in a evicted state and
897  * wait the process to be terminated.
898  */
899 
kgd2kfd_post_reset(struct kfd_dev * kfd)900 int kgd2kfd_post_reset(struct kfd_dev *kfd)
901 {
902 	int ret;
903 	struct kfd_node *node;
904 	int i;
905 
906 	if (!kfd->init_complete)
907 		return 0;
908 
909 	for (i = 0; i < kfd->num_nodes; i++) {
910 		ret = kfd_resume(kfd->nodes[i]);
911 		if (ret)
912 			return ret;
913 	}
914 
915 	mutex_lock(&kfd_processes_mutex);
916 	--kfd_locked;
917 	mutex_unlock(&kfd_processes_mutex);
918 
919 	for (i = 0; i < kfd->num_nodes; i++) {
920 		node = kfd->nodes[i];
921 		atomic_set(&node->sram_ecc_flag, 0);
922 		kfd_smi_event_update_gpu_reset(node, true);
923 	}
924 
925 	return 0;
926 }
927 
kfd_is_locked(void)928 bool kfd_is_locked(void)
929 {
930 	lockdep_assert_held(&kfd_processes_mutex);
931 	return  (kfd_locked > 0);
932 }
933 
kgd2kfd_suspend(struct kfd_dev * kfd,bool run_pm)934 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
935 {
936 	struct kfd_node *node;
937 	int i;
938 	int count;
939 
940 	if (!kfd->init_complete)
941 		return;
942 
943 	/* for runtime suspend, skip locking kfd */
944 	if (!run_pm) {
945 		mutex_lock(&kfd_processes_mutex);
946 		count = ++kfd_locked;
947 		mutex_unlock(&kfd_processes_mutex);
948 
949 		/* For first KFD device suspend all the KFD processes */
950 		if (count == 1)
951 			kfd_suspend_all_processes();
952 	}
953 
954 	for (i = 0; i < kfd->num_nodes; i++) {
955 		node = kfd->nodes[i];
956 		node->dqm->ops.stop(node->dqm);
957 	}
958 }
959 
kgd2kfd_resume(struct kfd_dev * kfd,bool run_pm)960 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
961 {
962 	int ret, count, i;
963 
964 	if (!kfd->init_complete)
965 		return 0;
966 
967 	for (i = 0; i < kfd->num_nodes; i++) {
968 		ret = kfd_resume(kfd->nodes[i]);
969 		if (ret)
970 			return ret;
971 	}
972 
973 	/* for runtime resume, skip unlocking kfd */
974 	if (!run_pm) {
975 		mutex_lock(&kfd_processes_mutex);
976 		count = --kfd_locked;
977 		mutex_unlock(&kfd_processes_mutex);
978 
979 		WARN_ONCE(count < 0, "KFD suspend / resume ref. error");
980 		if (count == 0)
981 			ret = kfd_resume_all_processes();
982 	}
983 
984 	return ret;
985 }
986 
kfd_resume(struct kfd_node * node)987 static int kfd_resume(struct kfd_node *node)
988 {
989 	int err = 0;
990 
991 	err = node->dqm->ops.start(node->dqm);
992 	if (err)
993 		dev_err(kfd_device,
994 			"Error starting queue manager for device %x:%x\n",
995 			node->adev->pdev->vendor, node->adev->pdev->device);
996 
997 	return err;
998 }
999 
kfd_queue_work(struct workqueue_struct * wq,struct work_struct * work)1000 static inline void kfd_queue_work(struct workqueue_struct *wq,
1001 				  struct work_struct *work)
1002 {
1003 	int cpu, new_cpu;
1004 
1005 	cpu = new_cpu = smp_processor_id();
1006 	do {
1007 		new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids;
1008 		if (cpu_to_node(new_cpu) == numa_node_id())
1009 			break;
1010 	} while (cpu != new_cpu);
1011 
1012 	queue_work_on(new_cpu, wq, work);
1013 }
1014 
1015 /* This is called directly from KGD at ISR. */
kgd2kfd_interrupt(struct kfd_dev * kfd,const void * ih_ring_entry)1016 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
1017 {
1018 	uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i;
1019 	bool is_patched = false;
1020 	unsigned long flags;
1021 	struct kfd_node *node;
1022 
1023 	if (!kfd->init_complete)
1024 		return;
1025 
1026 	if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) {
1027 		dev_err_once(kfd_device, "Ring entry too small\n");
1028 		return;
1029 	}
1030 
1031 	for (i = 0; i < kfd->num_nodes; i++) {
1032 		node = kfd->nodes[i];
1033 		spin_lock_irqsave(&node->interrupt_lock, flags);
1034 
1035 		if (node->interrupts_active
1036 		    && interrupt_is_wanted(node, ih_ring_entry,
1037 			    	patched_ihre, &is_patched)
1038 		    && enqueue_ih_ring_entry(node,
1039 			    	is_patched ? patched_ihre : ih_ring_entry)) {
1040 			kfd_queue_work(node->ih_wq, &node->interrupt_work);
1041 			spin_unlock_irqrestore(&node->interrupt_lock, flags);
1042 			return;
1043 		}
1044 		spin_unlock_irqrestore(&node->interrupt_lock, flags);
1045 	}
1046 
1047 }
1048 
kgd2kfd_quiesce_mm(struct mm_struct * mm,uint32_t trigger)1049 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger)
1050 {
1051 	struct kfd_process *p;
1052 	int r;
1053 
1054 	/* Because we are called from arbitrary context (workqueue) as opposed
1055 	 * to process context, kfd_process could attempt to exit while we are
1056 	 * running so the lookup function increments the process ref count.
1057 	 */
1058 	p = kfd_lookup_process_by_mm(mm);
1059 	if (!p)
1060 		return -ESRCH;
1061 
1062 	WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);
1063 	r = kfd_process_evict_queues(p, trigger);
1064 
1065 	kfd_unref_process(p);
1066 	return r;
1067 }
1068 
kgd2kfd_resume_mm(struct mm_struct * mm)1069 int kgd2kfd_resume_mm(struct mm_struct *mm)
1070 {
1071 	struct kfd_process *p;
1072 	int r;
1073 
1074 	/* Because we are called from arbitrary context (workqueue) as opposed
1075 	 * to process context, kfd_process could attempt to exit while we are
1076 	 * running so the lookup function increments the process ref count.
1077 	 */
1078 	p = kfd_lookup_process_by_mm(mm);
1079 	if (!p)
1080 		return -ESRCH;
1081 
1082 	r = kfd_process_restore_queues(p);
1083 
1084 	kfd_unref_process(p);
1085 	return r;
1086 }
1087 
1088 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will
1089  *   prepare for safe eviction of KFD BOs that belong to the specified
1090  *   process.
1091  *
1092  * @mm: mm_struct that identifies the specified KFD process
1093  * @fence: eviction fence attached to KFD process BOs
1094  *
1095  */
kgd2kfd_schedule_evict_and_restore_process(struct mm_struct * mm,struct dma_fence * fence)1096 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
1097 					       struct dma_fence *fence)
1098 {
1099 	struct kfd_process *p;
1100 	unsigned long active_time;
1101 	unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS);
1102 
1103 	if (!fence)
1104 		return -EINVAL;
1105 
1106 	if (dma_fence_is_signaled(fence))
1107 		return 0;
1108 
1109 	p = kfd_lookup_process_by_mm(mm);
1110 	if (!p)
1111 		return -ENODEV;
1112 
1113 	if (fence->seqno == p->last_eviction_seqno)
1114 		goto out;
1115 
1116 	p->last_eviction_seqno = fence->seqno;
1117 
1118 	/* Avoid KFD process starvation. Wait for at least
1119 	 * PROCESS_ACTIVE_TIME_MS before evicting the process again
1120 	 */
1121 	active_time = get_jiffies_64() - p->last_restore_timestamp;
1122 	if (delay_jiffies > active_time)
1123 		delay_jiffies -= active_time;
1124 	else
1125 		delay_jiffies = 0;
1126 
1127 	/* During process initialization eviction_work.dwork is initialized
1128 	 * to kfd_evict_bo_worker
1129 	 */
1130 	WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies",
1131 	     p->lead_thread->pid, delay_jiffies);
1132 	schedule_delayed_work(&p->eviction_work, delay_jiffies);
1133 out:
1134 	kfd_unref_process(p);
1135 	return 0;
1136 }
1137 
kfd_gtt_sa_init(struct kfd_dev * kfd,unsigned int buf_size,unsigned int chunk_size)1138 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
1139 				unsigned int chunk_size)
1140 {
1141 	if (WARN_ON(buf_size < chunk_size))
1142 		return -EINVAL;
1143 	if (WARN_ON(buf_size == 0))
1144 		return -EINVAL;
1145 	if (WARN_ON(chunk_size == 0))
1146 		return -EINVAL;
1147 
1148 	kfd->gtt_sa_chunk_size = chunk_size;
1149 	kfd->gtt_sa_num_of_chunks = buf_size / chunk_size;
1150 
1151 	kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks,
1152 					   GFP_KERNEL);
1153 	if (!kfd->gtt_sa_bitmap)
1154 		return -ENOMEM;
1155 
1156 	pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n",
1157 			kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap);
1158 
1159 	mutex_init(&kfd->gtt_sa_lock);
1160 
1161 	return 0;
1162 }
1163 
kfd_gtt_sa_fini(struct kfd_dev * kfd)1164 static void kfd_gtt_sa_fini(struct kfd_dev *kfd)
1165 {
1166 	mutex_destroy(&kfd->gtt_sa_lock);
1167 	bitmap_free(kfd->gtt_sa_bitmap);
1168 }
1169 
kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,unsigned int bit_num,unsigned int chunk_size)1170 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,
1171 						unsigned int bit_num,
1172 						unsigned int chunk_size)
1173 {
1174 	return start_addr + bit_num * chunk_size;
1175 }
1176 
kfd_gtt_sa_calc_cpu_addr(void * start_addr,unsigned int bit_num,unsigned int chunk_size)1177 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr,
1178 						unsigned int bit_num,
1179 						unsigned int chunk_size)
1180 {
1181 	return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size);
1182 }
1183 
kfd_gtt_sa_allocate(struct kfd_node * node,unsigned int size,struct kfd_mem_obj ** mem_obj)1184 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size,
1185 			struct kfd_mem_obj **mem_obj)
1186 {
1187 	unsigned int found, start_search, cur_size;
1188 	struct kfd_dev *kfd = node->kfd;
1189 
1190 	if (size == 0)
1191 		return -EINVAL;
1192 
1193 	if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size)
1194 		return -ENOMEM;
1195 
1196 	*mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
1197 	if (!(*mem_obj))
1198 		return -ENOMEM;
1199 
1200 	pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size);
1201 
1202 	start_search = 0;
1203 
1204 	mutex_lock(&kfd->gtt_sa_lock);
1205 
1206 kfd_gtt_restart_search:
1207 	/* Find the first chunk that is free */
1208 	found = find_next_zero_bit(kfd->gtt_sa_bitmap,
1209 					kfd->gtt_sa_num_of_chunks,
1210 					start_search);
1211 
1212 	pr_debug("Found = %d\n", found);
1213 
1214 	/* If there wasn't any free chunk, bail out */
1215 	if (found == kfd->gtt_sa_num_of_chunks)
1216 		goto kfd_gtt_no_free_chunk;
1217 
1218 	/* Update fields of mem_obj */
1219 	(*mem_obj)->range_start = found;
1220 	(*mem_obj)->range_end = found;
1221 	(*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr(
1222 					kfd->gtt_start_gpu_addr,
1223 					found,
1224 					kfd->gtt_sa_chunk_size);
1225 	(*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr(
1226 					kfd->gtt_start_cpu_ptr,
1227 					found,
1228 					kfd->gtt_sa_chunk_size);
1229 
1230 	pr_debug("gpu_addr = %p, cpu_addr = %p\n",
1231 			(uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr);
1232 
1233 	/* If we need only one chunk, mark it as allocated and get out */
1234 	if (size <= kfd->gtt_sa_chunk_size) {
1235 		pr_debug("Single bit\n");
1236 		__set_bit(found, kfd->gtt_sa_bitmap);
1237 		goto kfd_gtt_out;
1238 	}
1239 
1240 	/* Otherwise, try to see if we have enough contiguous chunks */
1241 	cur_size = size - kfd->gtt_sa_chunk_size;
1242 	do {
1243 		(*mem_obj)->range_end =
1244 			find_next_zero_bit(kfd->gtt_sa_bitmap,
1245 					kfd->gtt_sa_num_of_chunks, ++found);
1246 		/*
1247 		 * If next free chunk is not contiguous than we need to
1248 		 * restart our search from the last free chunk we found (which
1249 		 * wasn't contiguous to the previous ones
1250 		 */
1251 		if ((*mem_obj)->range_end != found) {
1252 			start_search = found;
1253 			goto kfd_gtt_restart_search;
1254 		}
1255 
1256 		/*
1257 		 * If we reached end of buffer, bail out with error
1258 		 */
1259 		if (found == kfd->gtt_sa_num_of_chunks)
1260 			goto kfd_gtt_no_free_chunk;
1261 
1262 		/* Check if we don't need another chunk */
1263 		if (cur_size <= kfd->gtt_sa_chunk_size)
1264 			cur_size = 0;
1265 		else
1266 			cur_size -= kfd->gtt_sa_chunk_size;
1267 
1268 	} while (cur_size > 0);
1269 
1270 	pr_debug("range_start = %d, range_end = %d\n",
1271 		(*mem_obj)->range_start, (*mem_obj)->range_end);
1272 
1273 	/* Mark the chunks as allocated */
1274 	bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start,
1275 		   (*mem_obj)->range_end - (*mem_obj)->range_start + 1);
1276 
1277 kfd_gtt_out:
1278 	mutex_unlock(&kfd->gtt_sa_lock);
1279 	return 0;
1280 
1281 kfd_gtt_no_free_chunk:
1282 	pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj);
1283 	mutex_unlock(&kfd->gtt_sa_lock);
1284 	kfree(*mem_obj);
1285 	return -ENOMEM;
1286 }
1287 
kfd_gtt_sa_free(struct kfd_node * node,struct kfd_mem_obj * mem_obj)1288 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj)
1289 {
1290 	struct kfd_dev *kfd = node->kfd;
1291 
1292 	/* Act like kfree when trying to free a NULL object */
1293 	if (!mem_obj)
1294 		return 0;
1295 
1296 	pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n",
1297 			mem_obj, mem_obj->range_start, mem_obj->range_end);
1298 
1299 	mutex_lock(&kfd->gtt_sa_lock);
1300 
1301 	/* Mark the chunks as free */
1302 	bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start,
1303 		     mem_obj->range_end - mem_obj->range_start + 1);
1304 
1305 	mutex_unlock(&kfd->gtt_sa_lock);
1306 
1307 	kfree(mem_obj);
1308 	return 0;
1309 }
1310 
kgd2kfd_set_sram_ecc_flag(struct kfd_dev * kfd)1311 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
1312 {
1313 	/*
1314 	 * TODO: Currently update SRAM ECC flag for first node.
1315 	 * This needs to be updated later when we can
1316 	 * identify SRAM ECC error on other nodes also.
1317 	 */
1318 	if (kfd)
1319 		atomic_inc(&kfd->nodes[0]->sram_ecc_flag);
1320 }
1321 
kfd_inc_compute_active(struct kfd_node * node)1322 void kfd_inc_compute_active(struct kfd_node *node)
1323 {
1324 	if (atomic_inc_return(&node->kfd->compute_profile) == 1)
1325 		amdgpu_amdkfd_set_compute_idle(node->adev, false);
1326 }
1327 
kfd_dec_compute_active(struct kfd_node * node)1328 void kfd_dec_compute_active(struct kfd_node *node)
1329 {
1330 	int count = atomic_dec_return(&node->kfd->compute_profile);
1331 
1332 	if (count == 0)
1333 		amdgpu_amdkfd_set_compute_idle(node->adev, true);
1334 	WARN_ONCE(count < 0, "Compute profile ref. count error");
1335 }
1336 
kgd2kfd_smi_event_throttle(struct kfd_dev * kfd,uint64_t throttle_bitmask)1337 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask)
1338 {
1339 	/*
1340 	 * TODO: For now, raise the throttling event only on first node.
1341 	 * This will need to change after we are able to determine
1342 	 * which node raised the throttling event.
1343 	 */
1344 	if (kfd && kfd->init_complete)
1345 		kfd_smi_event_update_thermal_throttling(kfd->nodes[0],
1346 							throttle_bitmask);
1347 }
1348 
1349 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and
1350  * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA.
1351  * When the device has more than two engines, we reserve two for PCIe to enable
1352  * full-duplex and the rest are used as XGMI.
1353  */
kfd_get_num_sdma_engines(struct kfd_node * node)1354 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node)
1355 {
1356 	/* If XGMI is not supported, all SDMA engines are PCIe */
1357 	if (!node->adev->gmc.xgmi.supported)
1358 		return node->adev->sdma.num_instances/(int)node->kfd->num_nodes;
1359 
1360 	return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2);
1361 }
1362 
kfd_get_num_xgmi_sdma_engines(struct kfd_node * node)1363 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node)
1364 {
1365 	/* After reserved for PCIe, the rest of engines are XGMI */
1366 	return node->adev->sdma.num_instances/(int)node->kfd->num_nodes -
1367 		kfd_get_num_sdma_engines(node);
1368 }
1369 
kgd2kfd_check_and_lock_kfd(void)1370 int kgd2kfd_check_and_lock_kfd(void)
1371 {
1372 	mutex_lock(&kfd_processes_mutex);
1373 	if (!hash_empty(kfd_processes_table) || kfd_is_locked()) {
1374 		mutex_unlock(&kfd_processes_mutex);
1375 		return -EBUSY;
1376 	}
1377 
1378 	++kfd_locked;
1379 	mutex_unlock(&kfd_processes_mutex);
1380 
1381 	return 0;
1382 }
1383 
kgd2kfd_unlock_kfd(void)1384 void kgd2kfd_unlock_kfd(void)
1385 {
1386 	mutex_lock(&kfd_processes_mutex);
1387 	--kfd_locked;
1388 	mutex_unlock(&kfd_processes_mutex);
1389 }
1390 
1391 #if defined(CONFIG_DEBUG_FS)
1392 
1393 /* This function will send a package to HIQ to hang the HWS
1394  * which will trigger a GPU reset and bring the HWS back to normal state
1395  */
kfd_debugfs_hang_hws(struct kfd_node * dev)1396 int kfd_debugfs_hang_hws(struct kfd_node *dev)
1397 {
1398 	if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) {
1399 		pr_err("HWS is not enabled");
1400 		return -EINVAL;
1401 	}
1402 
1403 	return dqm_debugfs_hang_hws(dev->dqm);
1404 }
1405 
1406 #endif
1407