1 /*
2 * arch/arm/mach-ixp4xx/common.c
3 *
4 * Generic code shared across all IXP4XX platforms
5 *
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2002 (c) Intel Corporation
9 * Copyright 2003-2004 (c) MontaVista, Software, Inc.
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/mm.h>
18 #include <linux/init.h>
19 #include <linux/serial.h>
20 #include <linux/tty.h>
21 #include <linux/platform_device.h>
22 #include <linux/serial_core.h>
23 #include <linux/interrupt.h>
24 #include <linux/bitops.h>
25 #include <linux/time.h>
26 #include <linux/timex.h>
27 #include <linux/clocksource.h>
28 #include <linux/clockchips.h>
29 #include <linux/io.h>
30 #include <linux/export.h>
31 #include <linux/gpio.h>
32
33 #include <mach/udc.h>
34 #include <mach/hardware.h>
35 #include <mach/io.h>
36 #include <asm/uaccess.h>
37 #include <asm/pgtable.h>
38 #include <asm/page.h>
39 #include <asm/irq.h>
40 #include <asm/sched_clock.h>
41 #include <asm/system_misc.h>
42
43 #include <asm/mach/map.h>
44 #include <asm/mach/irq.h>
45 #include <asm/mach/time.h>
46
47 static void __init ixp4xx_clocksource_init(void);
48 static void __init ixp4xx_clockevent_init(void);
49 static struct clock_event_device clockevent_ixp4xx;
50
51 /*************************************************************************
52 * IXP4xx chipset I/O mapping
53 *************************************************************************/
54 static struct map_desc ixp4xx_io_desc[] __initdata = {
55 { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
56 .virtual = IXP4XX_PERIPHERAL_BASE_VIRT,
57 .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
58 .length = IXP4XX_PERIPHERAL_REGION_SIZE,
59 .type = MT_DEVICE
60 }, { /* Expansion Bus Config Registers */
61 .virtual = IXP4XX_EXP_CFG_BASE_VIRT,
62 .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
63 .length = IXP4XX_EXP_CFG_REGION_SIZE,
64 .type = MT_DEVICE
65 }, { /* PCI Registers */
66 .virtual = IXP4XX_PCI_CFG_BASE_VIRT,
67 .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
68 .length = IXP4XX_PCI_CFG_REGION_SIZE,
69 .type = MT_DEVICE
70 },
71 #ifdef CONFIG_DEBUG_LL
72 { /* Debug UART mapping */
73 .virtual = IXP4XX_DEBUG_UART_BASE_VIRT,
74 .pfn = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
75 .length = IXP4XX_DEBUG_UART_REGION_SIZE,
76 .type = MT_DEVICE
77 }
78 #endif
79 };
80
ixp4xx_map_io(void)81 void __init ixp4xx_map_io(void)
82 {
83 iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
84 }
85
86
87 /*************************************************************************
88 * IXP4xx chipset IRQ handling
89 *
90 * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
91 * (be it PCI or something else) configures that GPIO line
92 * as an IRQ.
93 **************************************************************************/
94 enum ixp4xx_irq_type {
95 IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
96 };
97
98 /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
99 static unsigned long long ixp4xx_irq_edge = 0;
100
101 /*
102 * IRQ -> GPIO mapping table
103 */
104 static signed char irq2gpio[32] = {
105 -1, -1, -1, -1, -1, -1, 0, 1,
106 -1, -1, -1, -1, -1, -1, -1, -1,
107 -1, -1, -1, 2, 3, 4, 5, 6,
108 7, 8, 9, 10, 11, 12, -1, -1,
109 };
110
ixp4xx_gpio_to_irq(struct gpio_chip * chip,unsigned gpio)111 static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
112 {
113 int irq;
114
115 for (irq = 0; irq < 32; irq++) {
116 if (irq2gpio[irq] == gpio)
117 return irq;
118 }
119 return -EINVAL;
120 }
121
irq_to_gpio(unsigned int irq)122 int irq_to_gpio(unsigned int irq)
123 {
124 int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL;
125
126 if (gpio == -1)
127 return -EINVAL;
128
129 return gpio;
130 }
131 EXPORT_SYMBOL(irq_to_gpio);
132
ixp4xx_set_irq_type(struct irq_data * d,unsigned int type)133 static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
134 {
135 int line = irq2gpio[d->irq];
136 u32 int_style;
137 enum ixp4xx_irq_type irq_type;
138 volatile u32 *int_reg;
139
140 /*
141 * Only for GPIO IRQs
142 */
143 if (line < 0)
144 return -EINVAL;
145
146 switch (type){
147 case IRQ_TYPE_EDGE_BOTH:
148 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
149 irq_type = IXP4XX_IRQ_EDGE;
150 break;
151 case IRQ_TYPE_EDGE_RISING:
152 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
153 irq_type = IXP4XX_IRQ_EDGE;
154 break;
155 case IRQ_TYPE_EDGE_FALLING:
156 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
157 irq_type = IXP4XX_IRQ_EDGE;
158 break;
159 case IRQ_TYPE_LEVEL_HIGH:
160 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
161 irq_type = IXP4XX_IRQ_LEVEL;
162 break;
163 case IRQ_TYPE_LEVEL_LOW:
164 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
165 irq_type = IXP4XX_IRQ_LEVEL;
166 break;
167 default:
168 return -EINVAL;
169 }
170
171 if (irq_type == IXP4XX_IRQ_EDGE)
172 ixp4xx_irq_edge |= (1 << d->irq);
173 else
174 ixp4xx_irq_edge &= ~(1 << d->irq);
175
176 if (line >= 8) { /* pins 8-15 */
177 line -= 8;
178 int_reg = IXP4XX_GPIO_GPIT2R;
179 } else { /* pins 0-7 */
180 int_reg = IXP4XX_GPIO_GPIT1R;
181 }
182
183 /* Clear the style for the appropriate pin */
184 *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
185 (line * IXP4XX_GPIO_STYLE_SIZE));
186
187 *IXP4XX_GPIO_GPISR = (1 << line);
188
189 /* Set the new style */
190 *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
191
192 /* Configure the line as an input */
193 gpio_line_config(irq2gpio[d->irq], IXP4XX_GPIO_IN);
194
195 return 0;
196 }
197
ixp4xx_irq_mask(struct irq_data * d)198 static void ixp4xx_irq_mask(struct irq_data *d)
199 {
200 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
201 *IXP4XX_ICMR2 &= ~(1 << (d->irq - 32));
202 else
203 *IXP4XX_ICMR &= ~(1 << d->irq);
204 }
205
ixp4xx_irq_ack(struct irq_data * d)206 static void ixp4xx_irq_ack(struct irq_data *d)
207 {
208 int line = (d->irq < 32) ? irq2gpio[d->irq] : -1;
209
210 if (line >= 0)
211 *IXP4XX_GPIO_GPISR = (1 << line);
212 }
213
214 /*
215 * Level triggered interrupts on GPIO lines can only be cleared when the
216 * interrupt condition disappears.
217 */
ixp4xx_irq_unmask(struct irq_data * d)218 static void ixp4xx_irq_unmask(struct irq_data *d)
219 {
220 if (!(ixp4xx_irq_edge & (1 << d->irq)))
221 ixp4xx_irq_ack(d);
222
223 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
224 *IXP4XX_ICMR2 |= (1 << (d->irq - 32));
225 else
226 *IXP4XX_ICMR |= (1 << d->irq);
227 }
228
229 static struct irq_chip ixp4xx_irq_chip = {
230 .name = "IXP4xx",
231 .irq_ack = ixp4xx_irq_ack,
232 .irq_mask = ixp4xx_irq_mask,
233 .irq_unmask = ixp4xx_irq_unmask,
234 .irq_set_type = ixp4xx_set_irq_type,
235 };
236
ixp4xx_init_irq(void)237 void __init ixp4xx_init_irq(void)
238 {
239 int i = 0;
240
241 /*
242 * ixp4xx does not implement the XScale PWRMODE register
243 * so it must not call cpu_do_idle().
244 */
245 disable_hlt();
246
247 /* Route all sources to IRQ instead of FIQ */
248 *IXP4XX_ICLR = 0x0;
249
250 /* Disable all interrupt */
251 *IXP4XX_ICMR = 0x0;
252
253 if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
254 /* Route upper 32 sources to IRQ instead of FIQ */
255 *IXP4XX_ICLR2 = 0x00;
256
257 /* Disable upper 32 interrupts */
258 *IXP4XX_ICMR2 = 0x00;
259 }
260
261 /* Default to all level triggered */
262 for(i = 0; i < NR_IRQS; i++) {
263 irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
264 handle_level_irq);
265 set_irq_flags(i, IRQF_VALID);
266 }
267 }
268
269
270 /*************************************************************************
271 * IXP4xx timer tick
272 * We use OS timer1 on the CPU for the timer tick and the timestamp
273 * counter as a source of real clock ticks to account for missed jiffies.
274 *************************************************************************/
275
ixp4xx_timer_interrupt(int irq,void * dev_id)276 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
277 {
278 struct clock_event_device *evt = dev_id;
279
280 /* Clear Pending Interrupt by writing '1' to it */
281 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
282
283 evt->event_handler(evt);
284
285 return IRQ_HANDLED;
286 }
287
288 static struct irqaction ixp4xx_timer_irq = {
289 .name = "timer1",
290 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
291 .handler = ixp4xx_timer_interrupt,
292 .dev_id = &clockevent_ixp4xx,
293 };
294
ixp4xx_timer_init(void)295 void __init ixp4xx_timer_init(void)
296 {
297 /* Reset/disable counter */
298 *IXP4XX_OSRT1 = 0;
299
300 /* Clear Pending Interrupt by writing '1' to it */
301 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
302
303 /* Reset time-stamp counter */
304 *IXP4XX_OSTS = 0;
305
306 /* Connect the interrupt handler and enable the interrupt */
307 setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
308
309 ixp4xx_clocksource_init();
310 ixp4xx_clockevent_init();
311 }
312
313 struct sys_timer ixp4xx_timer = {
314 .init = ixp4xx_timer_init,
315 };
316
317 static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
318
ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info * info)319 void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
320 {
321 memcpy(&ixp4xx_udc_info, info, sizeof *info);
322 }
323
324 static struct resource ixp4xx_udc_resources[] = {
325 [0] = {
326 .start = 0xc800b000,
327 .end = 0xc800bfff,
328 .flags = IORESOURCE_MEM,
329 },
330 [1] = {
331 .start = IRQ_IXP4XX_USB,
332 .end = IRQ_IXP4XX_USB,
333 .flags = IORESOURCE_IRQ,
334 },
335 };
336
337 /*
338 * USB device controller. The IXP4xx uses the same controller as PXA25X,
339 * so we just use the same device.
340 */
341 static struct platform_device ixp4xx_udc_device = {
342 .name = "pxa25x-udc",
343 .id = -1,
344 .num_resources = 2,
345 .resource = ixp4xx_udc_resources,
346 .dev = {
347 .platform_data = &ixp4xx_udc_info,
348 },
349 };
350
351 static struct platform_device *ixp4xx_devices[] __initdata = {
352 &ixp4xx_udc_device,
353 };
354
355 static struct resource ixp46x_i2c_resources[] = {
356 [0] = {
357 .start = 0xc8011000,
358 .end = 0xc801101c,
359 .flags = IORESOURCE_MEM,
360 },
361 [1] = {
362 .start = IRQ_IXP4XX_I2C,
363 .end = IRQ_IXP4XX_I2C,
364 .flags = IORESOURCE_IRQ
365 }
366 };
367
368 /*
369 * I2C controller. The IXP46x uses the same block as the IOP3xx, so
370 * we just use the same device name.
371 */
372 static struct platform_device ixp46x_i2c_controller = {
373 .name = "IOP3xx-I2C",
374 .id = 0,
375 .num_resources = 2,
376 .resource = ixp46x_i2c_resources
377 };
378
379 static struct platform_device *ixp46x_devices[] __initdata = {
380 &ixp46x_i2c_controller
381 };
382
383 unsigned long ixp4xx_exp_bus_size;
384 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
385
ixp4xx_gpio_direction_input(struct gpio_chip * chip,unsigned gpio)386 static int ixp4xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
387 {
388 gpio_line_config(gpio, IXP4XX_GPIO_IN);
389
390 return 0;
391 }
392
ixp4xx_gpio_direction_output(struct gpio_chip * chip,unsigned gpio,int level)393 static int ixp4xx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
394 int level)
395 {
396 gpio_line_set(gpio, level);
397 gpio_line_config(gpio, IXP4XX_GPIO_OUT);
398
399 return 0;
400 }
401
ixp4xx_gpio_get_value(struct gpio_chip * chip,unsigned gpio)402 static int ixp4xx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
403 {
404 int value;
405
406 gpio_line_get(gpio, &value);
407
408 return value;
409 }
410
ixp4xx_gpio_set_value(struct gpio_chip * chip,unsigned gpio,int value)411 static void ixp4xx_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
412 int value)
413 {
414 gpio_line_set(gpio, value);
415 }
416
417 static struct gpio_chip ixp4xx_gpio_chip = {
418 .label = "IXP4XX_GPIO_CHIP",
419 .direction_input = ixp4xx_gpio_direction_input,
420 .direction_output = ixp4xx_gpio_direction_output,
421 .get = ixp4xx_gpio_get_value,
422 .set = ixp4xx_gpio_set_value,
423 .to_irq = ixp4xx_gpio_to_irq,
424 .base = 0,
425 .ngpio = 16,
426 };
427
ixp4xx_sys_init(void)428 void __init ixp4xx_sys_init(void)
429 {
430 ixp4xx_exp_bus_size = SZ_16M;
431
432 platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
433
434 gpiochip_add(&ixp4xx_gpio_chip);
435
436 if (cpu_is_ixp46x()) {
437 int region;
438
439 platform_add_devices(ixp46x_devices,
440 ARRAY_SIZE(ixp46x_devices));
441
442 for (region = 0; region < 7; region++) {
443 if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
444 ixp4xx_exp_bus_size = SZ_32M;
445 break;
446 }
447 }
448 }
449
450 printk("IXP4xx: Using %luMiB expansion bus window size\n",
451 ixp4xx_exp_bus_size >> 20);
452 }
453
454 /*
455 * sched_clock()
456 */
ixp4xx_read_sched_clock(void)457 static u32 notrace ixp4xx_read_sched_clock(void)
458 {
459 return *IXP4XX_OSTS;
460 }
461
462 /*
463 * clocksource
464 */
465
ixp4xx_clocksource_read(struct clocksource * c)466 static cycle_t ixp4xx_clocksource_read(struct clocksource *c)
467 {
468 return *IXP4XX_OSTS;
469 }
470
471 unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
472 EXPORT_SYMBOL(ixp4xx_timer_freq);
ixp4xx_clocksource_init(void)473 static void __init ixp4xx_clocksource_init(void)
474 {
475 setup_sched_clock(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
476
477 clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
478 ixp4xx_clocksource_read);
479 }
480
481 /*
482 * clockevents
483 */
ixp4xx_set_next_event(unsigned long evt,struct clock_event_device * unused)484 static int ixp4xx_set_next_event(unsigned long evt,
485 struct clock_event_device *unused)
486 {
487 unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
488
489 *IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts;
490
491 return 0;
492 }
493
ixp4xx_set_mode(enum clock_event_mode mode,struct clock_event_device * evt)494 static void ixp4xx_set_mode(enum clock_event_mode mode,
495 struct clock_event_device *evt)
496 {
497 unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
498 unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
499
500 switch (mode) {
501 case CLOCK_EVT_MODE_PERIODIC:
502 osrt = LATCH & ~IXP4XX_OST_RELOAD_MASK;
503 opts = IXP4XX_OST_ENABLE;
504 break;
505 case CLOCK_EVT_MODE_ONESHOT:
506 /* period set by 'set next_event' */
507 osrt = 0;
508 opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
509 break;
510 case CLOCK_EVT_MODE_SHUTDOWN:
511 opts &= ~IXP4XX_OST_ENABLE;
512 break;
513 case CLOCK_EVT_MODE_RESUME:
514 opts |= IXP4XX_OST_ENABLE;
515 break;
516 case CLOCK_EVT_MODE_UNUSED:
517 default:
518 osrt = opts = 0;
519 break;
520 }
521
522 *IXP4XX_OSRT1 = osrt | opts;
523 }
524
525 static struct clock_event_device clockevent_ixp4xx = {
526 .name = "ixp4xx timer1",
527 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
528 .rating = 200,
529 .shift = 24,
530 .set_mode = ixp4xx_set_mode,
531 .set_next_event = ixp4xx_set_next_event,
532 };
533
ixp4xx_clockevent_init(void)534 static void __init ixp4xx_clockevent_init(void)
535 {
536 clockevent_ixp4xx.mult = div_sc(IXP4XX_TIMER_FREQ, NSEC_PER_SEC,
537 clockevent_ixp4xx.shift);
538 clockevent_ixp4xx.max_delta_ns =
539 clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx);
540 clockevent_ixp4xx.min_delta_ns =
541 clockevent_delta2ns(0xf, &clockevent_ixp4xx);
542 clockevent_ixp4xx.cpumask = cpumask_of(0);
543
544 clockevents_register_device(&clockevent_ixp4xx);
545 }
546
ixp4xx_restart(char mode,const char * cmd)547 void ixp4xx_restart(char mode, const char *cmd)
548 {
549 if ( 1 && mode == 's') {
550 /* Jump into ROM at address 0 */
551 soft_restart(0);
552 } else {
553 /* Use on-chip reset capability */
554
555 /* set the "key" register to enable access to
556 * "timer" and "enable" registers
557 */
558 *IXP4XX_OSWK = IXP4XX_WDT_KEY;
559
560 /* write 0 to the timer register for an immediate reset */
561 *IXP4XX_OSWT = 0;
562
563 *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
564 }
565 }
566
567 #ifdef CONFIG_IXP4XX_INDIRECT_PCI
568 /*
569 * In the case of using indirect PCI, we simply return the actual PCI
570 * address and our read/write implementation use that to drive the
571 * access registers. If something outside of PCI is ioremap'd, we
572 * fallback to the default.
573 */
574
ixp4xx_ioremap_caller(unsigned long addr,size_t size,unsigned int mtype,void * caller)575 static void __iomem *ixp4xx_ioremap_caller(unsigned long addr, size_t size,
576 unsigned int mtype, void *caller)
577 {
578 if (!is_pci_memory(addr))
579 return __arm_ioremap_caller(addr, size, mtype, caller);
580
581 return (void __iomem *)addr;
582 }
583
ixp4xx_iounmap(void __iomem * addr)584 static void ixp4xx_iounmap(void __iomem *addr)
585 {
586 if (!is_pci_memory((__force u32)addr))
587 __iounmap(addr);
588 }
589
ixp4xx_init_early(void)590 void __init ixp4xx_init_early(void)
591 {
592 arch_ioremap_caller = ixp4xx_ioremap_caller;
593 arch_iounmap = ixp4xx_iounmap;
594 }
595 #else
ixp4xx_init_early(void)596 void __init ixp4xx_init_early(void) {}
597 #endif
598