1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 #include <linux/pci.h>
5 #include <linux/delay.h>
6 #include <linux/iopoll.h>
7 #include <linux/sched.h>
8
9 #include "ixgbe.h"
10 #include "ixgbe_phy.h"
11
12 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
13 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
14 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
15 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
16 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
17 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
18 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
19 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
20 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
21 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
22 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
23 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
24 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
25 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
26 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
27
28 /**
29 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
30 * @hw: pointer to the hardware structure
31 * @byte: byte to send
32 *
33 * Returns an error code on error.
34 **/
ixgbe_out_i2c_byte_ack(struct ixgbe_hw * hw,u8 byte)35 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
36 {
37 s32 status;
38
39 status = ixgbe_clock_out_i2c_byte(hw, byte);
40 if (status)
41 return status;
42 return ixgbe_get_i2c_ack(hw);
43 }
44
45 /**
46 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
47 * @hw: pointer to the hardware structure
48 * @byte: pointer to a u8 to receive the byte
49 *
50 * Returns an error code on error.
51 **/
ixgbe_in_i2c_byte_ack(struct ixgbe_hw * hw,u8 * byte)52 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
53 {
54 s32 status;
55
56 status = ixgbe_clock_in_i2c_byte(hw, byte);
57 if (status)
58 return status;
59 /* ACK */
60 return ixgbe_clock_out_i2c_bit(hw, false);
61 }
62
63 /**
64 * ixgbe_ones_comp_byte_add - Perform one's complement addition
65 * @add1: addend 1
66 * @add2: addend 2
67 *
68 * Returns one's complement 8-bit sum.
69 **/
ixgbe_ones_comp_byte_add(u8 add1,u8 add2)70 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
71 {
72 u16 sum = add1 + add2;
73
74 sum = (sum & 0xFF) + (sum >> 8);
75 return sum & 0xFF;
76 }
77
78 /**
79 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
80 * @hw: pointer to the hardware structure
81 * @addr: I2C bus address to read from
82 * @reg: I2C device register to read from
83 * @val: pointer to location to receive read value
84 * @lock: true if to take and release semaphore
85 *
86 * Returns an error code on error.
87 */
ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 * val,bool lock)88 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
89 u16 reg, u16 *val, bool lock)
90 {
91 u32 swfw_mask = hw->phy.phy_semaphore_mask;
92 int max_retry = 3;
93 int retry = 0;
94 u8 csum_byte;
95 u8 high_bits;
96 u8 low_bits;
97 u8 reg_high;
98 u8 csum;
99
100 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
101 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
102 csum = ~csum;
103 do {
104 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
105 return IXGBE_ERR_SWFW_SYNC;
106 ixgbe_i2c_start(hw);
107 /* Device Address and write indication */
108 if (ixgbe_out_i2c_byte_ack(hw, addr))
109 goto fail;
110 /* Write bits 14:8 */
111 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
112 goto fail;
113 /* Write bits 7:0 */
114 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
115 goto fail;
116 /* Write csum */
117 if (ixgbe_out_i2c_byte_ack(hw, csum))
118 goto fail;
119 /* Re-start condition */
120 ixgbe_i2c_start(hw);
121 /* Device Address and read indication */
122 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
123 goto fail;
124 /* Get upper bits */
125 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
126 goto fail;
127 /* Get low bits */
128 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
129 goto fail;
130 /* Get csum */
131 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
132 goto fail;
133 /* NACK */
134 if (ixgbe_clock_out_i2c_bit(hw, false))
135 goto fail;
136 ixgbe_i2c_stop(hw);
137 if (lock)
138 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
139 *val = (high_bits << 8) | low_bits;
140 return 0;
141
142 fail:
143 ixgbe_i2c_bus_clear(hw);
144 if (lock)
145 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
146 retry++;
147 if (retry < max_retry)
148 hw_dbg(hw, "I2C byte read combined error - Retry.\n");
149 else
150 hw_dbg(hw, "I2C byte read combined error.\n");
151 } while (retry < max_retry);
152
153 return IXGBE_ERR_I2C;
154 }
155
156 /**
157 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
158 * @hw: pointer to the hardware structure
159 * @addr: I2C bus address to write to
160 * @reg: I2C device register to write to
161 * @val: value to write
162 * @lock: true if to take and release semaphore
163 *
164 * Returns an error code on error.
165 */
ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 val,bool lock)166 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
167 u16 reg, u16 val, bool lock)
168 {
169 u32 swfw_mask = hw->phy.phy_semaphore_mask;
170 int max_retry = 1;
171 int retry = 0;
172 u8 reg_high;
173 u8 csum;
174
175 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
176 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
177 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
178 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
179 csum = ~csum;
180 do {
181 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
182 return IXGBE_ERR_SWFW_SYNC;
183 ixgbe_i2c_start(hw);
184 /* Device Address and write indication */
185 if (ixgbe_out_i2c_byte_ack(hw, addr))
186 goto fail;
187 /* Write bits 14:8 */
188 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
189 goto fail;
190 /* Write bits 7:0 */
191 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
192 goto fail;
193 /* Write data 15:8 */
194 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
195 goto fail;
196 /* Write data 7:0 */
197 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
198 goto fail;
199 /* Write csum */
200 if (ixgbe_out_i2c_byte_ack(hw, csum))
201 goto fail;
202 ixgbe_i2c_stop(hw);
203 if (lock)
204 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
205 return 0;
206
207 fail:
208 ixgbe_i2c_bus_clear(hw);
209 if (lock)
210 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
211 retry++;
212 if (retry < max_retry)
213 hw_dbg(hw, "I2C byte write combined error - Retry.\n");
214 else
215 hw_dbg(hw, "I2C byte write combined error.\n");
216 } while (retry < max_retry);
217
218 return IXGBE_ERR_I2C;
219 }
220
221 /**
222 * ixgbe_probe_phy - Probe a single address for a PHY
223 * @hw: pointer to hardware structure
224 * @phy_addr: PHY address to probe
225 *
226 * Returns true if PHY found
227 **/
ixgbe_probe_phy(struct ixgbe_hw * hw,u16 phy_addr)228 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
229 {
230 u16 ext_ability = 0;
231
232 hw->phy.mdio.prtad = phy_addr;
233 if (mdio45_probe(&hw->phy.mdio, phy_addr) != 0)
234 return false;
235
236 if (ixgbe_get_phy_id(hw))
237 return false;
238
239 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
240
241 if (hw->phy.type == ixgbe_phy_unknown) {
242 hw->phy.ops.read_reg(hw,
243 MDIO_PMA_EXTABLE,
244 MDIO_MMD_PMAPMD,
245 &ext_ability);
246 if (ext_ability &
247 (MDIO_PMA_EXTABLE_10GBT |
248 MDIO_PMA_EXTABLE_1000BT))
249 hw->phy.type = ixgbe_phy_cu_unknown;
250 else
251 hw->phy.type = ixgbe_phy_generic;
252 }
253
254 return true;
255 }
256
257 /**
258 * ixgbe_identify_phy_generic - Get physical layer module
259 * @hw: pointer to hardware structure
260 *
261 * Determines the physical layer module found on the current adapter.
262 **/
ixgbe_identify_phy_generic(struct ixgbe_hw * hw)263 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
264 {
265 u32 phy_addr;
266 u32 status = IXGBE_ERR_PHY_ADDR_INVALID;
267
268 if (!hw->phy.phy_semaphore_mask) {
269 if (hw->bus.lan_id)
270 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
271 else
272 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
273 }
274
275 if (hw->phy.type != ixgbe_phy_unknown)
276 return 0;
277
278 if (hw->phy.nw_mng_if_sel) {
279 phy_addr = (hw->phy.nw_mng_if_sel &
280 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
281 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
282 if (ixgbe_probe_phy(hw, phy_addr))
283 return 0;
284 else
285 return IXGBE_ERR_PHY_ADDR_INVALID;
286 }
287
288 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
289 if (ixgbe_probe_phy(hw, phy_addr)) {
290 status = 0;
291 break;
292 }
293 }
294
295 /* Certain media types do not have a phy so an address will not
296 * be found and the code will take this path. Caller has to
297 * decide if it is an error or not.
298 */
299 if (status)
300 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
301
302 return status;
303 }
304
305 /**
306 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
307 * @hw: pointer to the hardware structure
308 *
309 * This function checks the MMNGC.MNG_VETO bit to see if there are
310 * any constraints on link from manageability. For MAC's that don't
311 * have this bit just return false since the link can not be blocked
312 * via this method.
313 **/
ixgbe_check_reset_blocked(struct ixgbe_hw * hw)314 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
315 {
316 u32 mmngc;
317
318 /* If we don't have this bit, it can't be blocking */
319 if (hw->mac.type == ixgbe_mac_82598EB)
320 return false;
321
322 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
323 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
324 hw_dbg(hw, "MNG_VETO bit detected.\n");
325 return true;
326 }
327
328 return false;
329 }
330
331 /**
332 * ixgbe_get_phy_id - Get the phy type
333 * @hw: pointer to hardware structure
334 *
335 **/
ixgbe_get_phy_id(struct ixgbe_hw * hw)336 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
337 {
338 s32 status;
339 u16 phy_id_high = 0;
340 u16 phy_id_low = 0;
341
342 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
343 &phy_id_high);
344
345 if (!status) {
346 hw->phy.id = (u32)(phy_id_high << 16);
347 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
348 &phy_id_low);
349 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
350 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
351 }
352 return status;
353 }
354
355 /**
356 * ixgbe_get_phy_type_from_id - Get the phy type
357 * @phy_id: hardware phy id
358 *
359 **/
ixgbe_get_phy_type_from_id(u32 phy_id)360 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
361 {
362 enum ixgbe_phy_type phy_type;
363
364 switch (phy_id) {
365 case TN1010_PHY_ID:
366 phy_type = ixgbe_phy_tn;
367 break;
368 case X550_PHY_ID2:
369 case X550_PHY_ID3:
370 case X540_PHY_ID:
371 phy_type = ixgbe_phy_aq;
372 break;
373 case QT2022_PHY_ID:
374 phy_type = ixgbe_phy_qt;
375 break;
376 case ATH_PHY_ID:
377 phy_type = ixgbe_phy_nl;
378 break;
379 case X557_PHY_ID:
380 case X557_PHY_ID2:
381 phy_type = ixgbe_phy_x550em_ext_t;
382 break;
383 case BCM54616S_E_PHY_ID:
384 phy_type = ixgbe_phy_ext_1g_t;
385 break;
386 default:
387 phy_type = ixgbe_phy_unknown;
388 break;
389 }
390
391 return phy_type;
392 }
393
394 /**
395 * ixgbe_reset_phy_generic - Performs a PHY reset
396 * @hw: pointer to hardware structure
397 **/
ixgbe_reset_phy_generic(struct ixgbe_hw * hw)398 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
399 {
400 u32 i;
401 u16 ctrl = 0;
402 s32 status = 0;
403
404 if (hw->phy.type == ixgbe_phy_unknown)
405 status = ixgbe_identify_phy_generic(hw);
406
407 if (status != 0 || hw->phy.type == ixgbe_phy_none)
408 return status;
409
410 /* Don't reset PHY if it's shut down due to overtemp. */
411 if (!hw->phy.reset_if_overtemp &&
412 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
413 return 0;
414
415 /* Blocked by MNG FW so bail */
416 if (ixgbe_check_reset_blocked(hw))
417 return 0;
418
419 /*
420 * Perform soft PHY reset to the PHY_XS.
421 * This will cause a soft reset to the PHY
422 */
423 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
424 MDIO_MMD_PHYXS,
425 MDIO_CTRL1_RESET);
426
427 /*
428 * Poll for reset bit to self-clear indicating reset is complete.
429 * Some PHYs could take up to 3 seconds to complete and need about
430 * 1.7 usec delay after the reset is complete.
431 */
432 for (i = 0; i < 30; i++) {
433 msleep(100);
434 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
435 status = hw->phy.ops.read_reg(hw,
436 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
437 MDIO_MMD_PMAPMD, &ctrl);
438 if (status)
439 return status;
440
441 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
442 udelay(2);
443 break;
444 }
445 } else {
446 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1,
447 MDIO_MMD_PHYXS, &ctrl);
448 if (status)
449 return status;
450
451 if (!(ctrl & MDIO_CTRL1_RESET)) {
452 udelay(2);
453 break;
454 }
455 }
456 }
457
458 if (ctrl & MDIO_CTRL1_RESET) {
459 hw_dbg(hw, "PHY reset polling failed to complete.\n");
460 return IXGBE_ERR_RESET_FAILED;
461 }
462
463 return 0;
464 }
465
466 /**
467 * ixgbe_read_phy_reg_mdi - read PHY register
468 * @hw: pointer to hardware structure
469 * @reg_addr: 32 bit address of PHY register to read
470 * @device_type: 5 bit device type
471 * @phy_data: Pointer to read data from PHY register
472 *
473 * Reads a value from a specified PHY register without the SWFW lock
474 **/
ixgbe_read_phy_reg_mdi(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)475 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
476 u16 *phy_data)
477 {
478 u32 i, data, command;
479
480 /* Setup and write the address cycle command */
481 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
482 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
483 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
484 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
485
486 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
487
488 /* Check every 10 usec to see if the address cycle completed.
489 * The MDI Command bit will clear when the operation is
490 * complete
491 */
492 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
493 udelay(10);
494
495 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
496 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
497 break;
498 }
499
500
501 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
502 hw_dbg(hw, "PHY address command did not complete.\n");
503 return IXGBE_ERR_PHY;
504 }
505
506 /* Address cycle complete, setup and write the read
507 * command
508 */
509 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
510 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
511 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
512 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
513
514 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
515
516 /* Check every 10 usec to see if the address cycle
517 * completed. The MDI Command bit will clear when the
518 * operation is complete
519 */
520 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
521 udelay(10);
522
523 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
524 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
525 break;
526 }
527
528 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
529 hw_dbg(hw, "PHY read command didn't complete\n");
530 return IXGBE_ERR_PHY;
531 }
532
533 /* Read operation is complete. Get the data
534 * from MSRWD
535 */
536 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
537 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
538 *phy_data = (u16)(data);
539
540 return 0;
541 }
542
543 /**
544 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
545 * using the SWFW lock - this function is needed in most cases
546 * @hw: pointer to hardware structure
547 * @reg_addr: 32 bit address of PHY register to read
548 * @device_type: 5 bit device type
549 * @phy_data: Pointer to read data from PHY register
550 **/
ixgbe_read_phy_reg_generic(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)551 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
552 u32 device_type, u16 *phy_data)
553 {
554 s32 status;
555 u32 gssr = hw->phy.phy_semaphore_mask;
556
557 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
558 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
559 phy_data);
560 hw->mac.ops.release_swfw_sync(hw, gssr);
561 } else {
562 return IXGBE_ERR_SWFW_SYNC;
563 }
564
565 return status;
566 }
567
568 /**
569 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
570 * without SWFW lock
571 * @hw: pointer to hardware structure
572 * @reg_addr: 32 bit PHY register to write
573 * @device_type: 5 bit device type
574 * @phy_data: Data to write to the PHY register
575 **/
ixgbe_write_phy_reg_mdi(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)576 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
577 u32 device_type, u16 phy_data)
578 {
579 u32 i, command;
580
581 /* Put the data in the MDI single read and write data register*/
582 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
583
584 /* Setup and write the address cycle command */
585 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
586 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
587 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
588 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
589
590 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
591
592 /*
593 * Check every 10 usec to see if the address cycle completed.
594 * The MDI Command bit will clear when the operation is
595 * complete
596 */
597 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
598 udelay(10);
599
600 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
601 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
602 break;
603 }
604
605 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
606 hw_dbg(hw, "PHY address cmd didn't complete\n");
607 return IXGBE_ERR_PHY;
608 }
609
610 /*
611 * Address cycle complete, setup and write the write
612 * command
613 */
614 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
615 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
616 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
617 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
618
619 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
620
621 /* Check every 10 usec to see if the address cycle
622 * completed. The MDI Command bit will clear when the
623 * operation is complete
624 */
625 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
626 udelay(10);
627
628 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
629 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
630 break;
631 }
632
633 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
634 hw_dbg(hw, "PHY write cmd didn't complete\n");
635 return IXGBE_ERR_PHY;
636 }
637
638 return 0;
639 }
640
641 /**
642 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
643 * using SWFW lock- this function is needed in most cases
644 * @hw: pointer to hardware structure
645 * @reg_addr: 32 bit PHY register to write
646 * @device_type: 5 bit device type
647 * @phy_data: Data to write to the PHY register
648 **/
ixgbe_write_phy_reg_generic(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)649 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
650 u32 device_type, u16 phy_data)
651 {
652 s32 status;
653 u32 gssr = hw->phy.phy_semaphore_mask;
654
655 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
656 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
657 phy_data);
658 hw->mac.ops.release_swfw_sync(hw, gssr);
659 } else {
660 return IXGBE_ERR_SWFW_SYNC;
661 }
662
663 return status;
664 }
665
666 #define IXGBE_HW_READ_REG(addr) IXGBE_READ_REG(hw, addr)
667
668 /**
669 * ixgbe_msca_cmd - Write the command register and poll for completion/timeout
670 * @hw: pointer to hardware structure
671 * @cmd: command register value to write
672 **/
ixgbe_msca_cmd(struct ixgbe_hw * hw,u32 cmd)673 static s32 ixgbe_msca_cmd(struct ixgbe_hw *hw, u32 cmd)
674 {
675 IXGBE_WRITE_REG(hw, IXGBE_MSCA, cmd);
676
677 return readx_poll_timeout(IXGBE_HW_READ_REG, IXGBE_MSCA, cmd,
678 !(cmd & IXGBE_MSCA_MDI_COMMAND), 10,
679 10 * IXGBE_MDIO_COMMAND_TIMEOUT);
680 }
681
682 /**
683 * ixgbe_mii_bus_read_generic - Read a clause 22/45 register with gssr flags
684 * @hw: pointer to hardware structure
685 * @addr: address
686 * @regnum: register number
687 * @gssr: semaphore flags to acquire
688 **/
ixgbe_mii_bus_read_generic(struct ixgbe_hw * hw,int addr,int regnum,u32 gssr)689 static s32 ixgbe_mii_bus_read_generic(struct ixgbe_hw *hw, int addr,
690 int regnum, u32 gssr)
691 {
692 u32 hwaddr, cmd;
693 s32 data;
694
695 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
696 return -EBUSY;
697
698 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
699 if (regnum & MII_ADDR_C45) {
700 hwaddr |= regnum & GENMASK(21, 0);
701 cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
702 } else {
703 hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
704 cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL |
705 IXGBE_MSCA_READ_AUTOINC | IXGBE_MSCA_MDI_COMMAND;
706 }
707
708 data = ixgbe_msca_cmd(hw, cmd);
709 if (data < 0)
710 goto mii_bus_read_done;
711
712 /* For a clause 45 access the address cycle just completed, we still
713 * need to do the read command, otherwise just get the data
714 */
715 if (!(regnum & MII_ADDR_C45))
716 goto do_mii_bus_read;
717
718 cmd = hwaddr | IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND;
719 data = ixgbe_msca_cmd(hw, cmd);
720 if (data < 0)
721 goto mii_bus_read_done;
722
723 do_mii_bus_read:
724 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
725 data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0);
726
727 mii_bus_read_done:
728 hw->mac.ops.release_swfw_sync(hw, gssr);
729 return data;
730 }
731
732 /**
733 * ixgbe_mii_bus_write_generic - Write a clause 22/45 register with gssr flags
734 * @hw: pointer to hardware structure
735 * @addr: address
736 * @regnum: register number
737 * @val: value to write
738 * @gssr: semaphore flags to acquire
739 **/
ixgbe_mii_bus_write_generic(struct ixgbe_hw * hw,int addr,int regnum,u16 val,u32 gssr)740 static s32 ixgbe_mii_bus_write_generic(struct ixgbe_hw *hw, int addr,
741 int regnum, u16 val, u32 gssr)
742 {
743 u32 hwaddr, cmd;
744 s32 err;
745
746 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
747 return -EBUSY;
748
749 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val);
750
751 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
752 if (regnum & MII_ADDR_C45) {
753 hwaddr |= regnum & GENMASK(21, 0);
754 cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
755 } else {
756 hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
757 cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
758 IXGBE_MSCA_MDI_COMMAND;
759 }
760
761 /* For clause 45 this is an address cycle, for clause 22 this is the
762 * entire transaction
763 */
764 err = ixgbe_msca_cmd(hw, cmd);
765 if (err < 0 || !(regnum & MII_ADDR_C45))
766 goto mii_bus_write_done;
767
768 cmd = hwaddr | IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND;
769 err = ixgbe_msca_cmd(hw, cmd);
770
771 mii_bus_write_done:
772 hw->mac.ops.release_swfw_sync(hw, gssr);
773 return err;
774 }
775
776 /**
777 * ixgbe_mii_bus_read - Read a clause 22/45 register
778 * @bus: pointer to mii_bus structure which points to our driver private
779 * @addr: address
780 * @regnum: register number
781 **/
ixgbe_mii_bus_read(struct mii_bus * bus,int addr,int regnum)782 static s32 ixgbe_mii_bus_read(struct mii_bus *bus, int addr, int regnum)
783 {
784 struct ixgbe_adapter *adapter = bus->priv;
785 struct ixgbe_hw *hw = &adapter->hw;
786 u32 gssr = hw->phy.phy_semaphore_mask;
787
788 return ixgbe_mii_bus_read_generic(hw, addr, regnum, gssr);
789 }
790
791 /**
792 * ixgbe_mii_bus_write - Write a clause 22/45 register
793 * @bus: pointer to mii_bus structure which points to our driver private
794 * @addr: address
795 * @regnum: register number
796 * @val: value to write
797 **/
ixgbe_mii_bus_write(struct mii_bus * bus,int addr,int regnum,u16 val)798 static s32 ixgbe_mii_bus_write(struct mii_bus *bus, int addr, int regnum,
799 u16 val)
800 {
801 struct ixgbe_adapter *adapter = bus->priv;
802 struct ixgbe_hw *hw = &adapter->hw;
803 u32 gssr = hw->phy.phy_semaphore_mask;
804
805 return ixgbe_mii_bus_write_generic(hw, addr, regnum, val, gssr);
806 }
807
808 /**
809 * ixgbe_x550em_a_mii_bus_read - Read a clause 22/45 register on x550em_a
810 * @bus: pointer to mii_bus structure which points to our driver private
811 * @addr: address
812 * @regnum: register number
813 **/
ixgbe_x550em_a_mii_bus_read(struct mii_bus * bus,int addr,int regnum)814 static s32 ixgbe_x550em_a_mii_bus_read(struct mii_bus *bus, int addr,
815 int regnum)
816 {
817 struct ixgbe_adapter *adapter = bus->priv;
818 struct ixgbe_hw *hw = &adapter->hw;
819 u32 gssr = hw->phy.phy_semaphore_mask;
820
821 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
822 return ixgbe_mii_bus_read_generic(hw, addr, regnum, gssr);
823 }
824
825 /**
826 * ixgbe_x550em_a_mii_bus_write - Write a clause 22/45 register on x550em_a
827 * @bus: pointer to mii_bus structure which points to our driver private
828 * @addr: address
829 * @regnum: register number
830 * @val: value to write
831 **/
ixgbe_x550em_a_mii_bus_write(struct mii_bus * bus,int addr,int regnum,u16 val)832 static s32 ixgbe_x550em_a_mii_bus_write(struct mii_bus *bus, int addr,
833 int regnum, u16 val)
834 {
835 struct ixgbe_adapter *adapter = bus->priv;
836 struct ixgbe_hw *hw = &adapter->hw;
837 u32 gssr = hw->phy.phy_semaphore_mask;
838
839 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
840 return ixgbe_mii_bus_write_generic(hw, addr, regnum, val, gssr);
841 }
842
843 /**
844 * ixgbe_get_first_secondary_devfn - get first device downstream of root port
845 * @devfn: PCI_DEVFN of root port on domain 0, bus 0
846 *
847 * Returns pci_dev pointer to PCI_DEVFN(0, 0) on subordinate side of root
848 * on domain 0, bus 0, devfn = 'devfn'
849 **/
ixgbe_get_first_secondary_devfn(unsigned int devfn)850 static struct pci_dev *ixgbe_get_first_secondary_devfn(unsigned int devfn)
851 {
852 struct pci_dev *rp_pdev;
853 int bus;
854
855 rp_pdev = pci_get_domain_bus_and_slot(0, 0, devfn);
856 if (rp_pdev && rp_pdev->subordinate) {
857 bus = rp_pdev->subordinate->number;
858 pci_dev_put(rp_pdev);
859 return pci_get_domain_bus_and_slot(0, bus, 0);
860 }
861
862 pci_dev_put(rp_pdev);
863 return NULL;
864 }
865
866 /**
867 * ixgbe_x550em_a_has_mii - is this the first ixgbe x550em_a PCI function?
868 * @hw: pointer to hardware structure
869 *
870 * Returns true if hw points to lowest numbered PCI B:D.F x550_em_a device in
871 * the SoC. There are up to 4 MACs sharing a single MDIO bus on the x550em_a,
872 * but we only want to register one MDIO bus.
873 **/
ixgbe_x550em_a_has_mii(struct ixgbe_hw * hw)874 static bool ixgbe_x550em_a_has_mii(struct ixgbe_hw *hw)
875 {
876 struct ixgbe_adapter *adapter = hw->back;
877 struct pci_dev *pdev = adapter->pdev;
878 struct pci_dev *func0_pdev;
879 bool has_mii = false;
880
881 /* For the C3000 family of SoCs (x550em_a) the internal ixgbe devices
882 * are always downstream of root ports @ 0000:00:16.0 & 0000:00:17.0
883 * It's not valid for function 0 to be disabled and function 1 is up,
884 * so the lowest numbered ixgbe dev will be device 0 function 0 on one
885 * of those two root ports
886 */
887 func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x16, 0));
888 if (func0_pdev) {
889 if (func0_pdev == pdev)
890 has_mii = true;
891 goto out;
892 }
893 func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x17, 0));
894 if (func0_pdev == pdev)
895 has_mii = true;
896
897 out:
898 pci_dev_put(func0_pdev);
899 return has_mii;
900 }
901
902 /**
903 * ixgbe_mii_bus_init - mii_bus structure setup
904 * @hw: pointer to hardware structure
905 *
906 * Returns 0 on success, negative on failure
907 *
908 * ixgbe_mii_bus_init initializes a mii_bus structure in adapter
909 **/
ixgbe_mii_bus_init(struct ixgbe_hw * hw)910 s32 ixgbe_mii_bus_init(struct ixgbe_hw *hw)
911 {
912 s32 (*write)(struct mii_bus *bus, int addr, int regnum, u16 val);
913 s32 (*read)(struct mii_bus *bus, int addr, int regnum);
914 struct ixgbe_adapter *adapter = hw->back;
915 struct pci_dev *pdev = adapter->pdev;
916 struct device *dev = &adapter->netdev->dev;
917 struct mii_bus *bus;
918
919 switch (hw->device_id) {
920 /* C3000 SoCs */
921 case IXGBE_DEV_ID_X550EM_A_KR:
922 case IXGBE_DEV_ID_X550EM_A_KR_L:
923 case IXGBE_DEV_ID_X550EM_A_SFP_N:
924 case IXGBE_DEV_ID_X550EM_A_SGMII:
925 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
926 case IXGBE_DEV_ID_X550EM_A_10G_T:
927 case IXGBE_DEV_ID_X550EM_A_SFP:
928 case IXGBE_DEV_ID_X550EM_A_1G_T:
929 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
930 if (!ixgbe_x550em_a_has_mii(hw))
931 return 0;
932 read = &ixgbe_x550em_a_mii_bus_read;
933 write = &ixgbe_x550em_a_mii_bus_write;
934 break;
935 default:
936 read = &ixgbe_mii_bus_read;
937 write = &ixgbe_mii_bus_write;
938 break;
939 }
940
941 bus = devm_mdiobus_alloc(dev);
942 if (!bus)
943 return -ENOMEM;
944
945 bus->read = read;
946 bus->write = write;
947
948 /* Use the position of the device in the PCI hierarchy as the id */
949 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mdio-%s", ixgbe_driver_name,
950 pci_name(pdev));
951
952 bus->name = "ixgbe-mdio";
953 bus->priv = adapter;
954 bus->parent = dev;
955 bus->phy_mask = GENMASK(31, 0);
956
957 /* Support clause 22/45 natively. ixgbe_probe() sets MDIO_EMULATE_C22
958 * unfortunately that causes some clause 22 frames to be sent with
959 * clause 45 addressing. We don't want that.
960 */
961 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_SUPPORTS_C22;
962
963 adapter->mii_bus = bus;
964 return mdiobus_register(bus);
965 }
966
967 /**
968 * ixgbe_setup_phy_link_generic - Set and restart autoneg
969 * @hw: pointer to hardware structure
970 *
971 * Restart autonegotiation and PHY and waits for completion.
972 **/
ixgbe_setup_phy_link_generic(struct ixgbe_hw * hw)973 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
974 {
975 s32 status = 0;
976 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
977 bool autoneg = false;
978 ixgbe_link_speed speed;
979
980 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
981
982 /* Set or unset auto-negotiation 10G advertisement */
983 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg);
984
985 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
986 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
987 (speed & IXGBE_LINK_SPEED_10GB_FULL))
988 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
989
990 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg);
991
992 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
993 MDIO_MMD_AN, &autoneg_reg);
994
995 if (hw->mac.type == ixgbe_mac_X550) {
996 /* Set or unset auto-negotiation 5G advertisement */
997 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
998 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
999 (speed & IXGBE_LINK_SPEED_5GB_FULL))
1000 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
1001
1002 /* Set or unset auto-negotiation 2.5G advertisement */
1003 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
1004 if ((hw->phy.autoneg_advertised &
1005 IXGBE_LINK_SPEED_2_5GB_FULL) &&
1006 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
1007 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
1008 }
1009
1010 /* Set or unset auto-negotiation 1G advertisement */
1011 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
1012 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
1013 (speed & IXGBE_LINK_SPEED_1GB_FULL))
1014 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
1015
1016 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1017 MDIO_MMD_AN, autoneg_reg);
1018
1019 /* Set or unset auto-negotiation 100M advertisement */
1020 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
1021
1022 autoneg_reg &= ~(ADVERTISE_100FULL | ADVERTISE_100HALF);
1023 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
1024 (speed & IXGBE_LINK_SPEED_100_FULL))
1025 autoneg_reg |= ADVERTISE_100FULL;
1026
1027 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
1028
1029 /* Blocked by MNG FW so don't reset PHY */
1030 if (ixgbe_check_reset_blocked(hw))
1031 return 0;
1032
1033 /* Restart PHY autonegotiation and wait for completion */
1034 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1035 MDIO_MMD_AN, &autoneg_reg);
1036
1037 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1038
1039 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1040 MDIO_MMD_AN, autoneg_reg);
1041
1042 return status;
1043 }
1044
1045 /**
1046 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
1047 * @hw: pointer to hardware structure
1048 * @speed: new link speed
1049 * @autoneg_wait_to_complete: unused
1050 **/
ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait_to_complete)1051 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
1052 ixgbe_link_speed speed,
1053 bool autoneg_wait_to_complete)
1054 {
1055 /* Clear autoneg_advertised and set new values based on input link
1056 * speed.
1057 */
1058 hw->phy.autoneg_advertised = 0;
1059
1060 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1061 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
1062
1063 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
1064 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
1065
1066 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
1067 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
1068
1069 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1070 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
1071
1072 if (speed & IXGBE_LINK_SPEED_100_FULL)
1073 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
1074
1075 if (speed & IXGBE_LINK_SPEED_10_FULL)
1076 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
1077
1078 /* Setup link based on the new speed settings */
1079 if (hw->phy.ops.setup_link)
1080 hw->phy.ops.setup_link(hw);
1081
1082 return 0;
1083 }
1084
1085 /**
1086 * ixgbe_get_copper_speeds_supported - Get copper link speed from phy
1087 * @hw: pointer to hardware structure
1088 *
1089 * Determines the supported link capabilities by reading the PHY auto
1090 * negotiation register.
1091 */
ixgbe_get_copper_speeds_supported(struct ixgbe_hw * hw)1092 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
1093 {
1094 u16 speed_ability;
1095 s32 status;
1096
1097 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
1098 &speed_ability);
1099 if (status)
1100 return status;
1101
1102 if (speed_ability & MDIO_SPEED_10G)
1103 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
1104 if (speed_ability & MDIO_PMA_SPEED_1000)
1105 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
1106 if (speed_ability & MDIO_PMA_SPEED_100)
1107 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
1108
1109 switch (hw->mac.type) {
1110 case ixgbe_mac_X550:
1111 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
1112 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
1113 break;
1114 case ixgbe_mac_X550EM_x:
1115 case ixgbe_mac_x550em_a:
1116 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
1117 break;
1118 default:
1119 break;
1120 }
1121
1122 return 0;
1123 }
1124
1125 /**
1126 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
1127 * @hw: pointer to hardware structure
1128 * @speed: pointer to link speed
1129 * @autoneg: boolean auto-negotiation value
1130 */
ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * autoneg)1131 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
1132 ixgbe_link_speed *speed,
1133 bool *autoneg)
1134 {
1135 s32 status = 0;
1136
1137 *autoneg = true;
1138 if (!hw->phy.speeds_supported)
1139 status = ixgbe_get_copper_speeds_supported(hw);
1140
1141 *speed = hw->phy.speeds_supported;
1142 return status;
1143 }
1144
1145 /**
1146 * ixgbe_check_phy_link_tnx - Determine link and speed status
1147 * @hw: pointer to hardware structure
1148 * @speed: link speed
1149 * @link_up: status of link
1150 *
1151 * Reads the VS1 register to determine if link is up and the current speed for
1152 * the PHY.
1153 **/
ixgbe_check_phy_link_tnx(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * link_up)1154 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1155 bool *link_up)
1156 {
1157 s32 status;
1158 u32 time_out;
1159 u32 max_time_out = 10;
1160 u16 phy_link = 0;
1161 u16 phy_speed = 0;
1162 u16 phy_data = 0;
1163
1164 /* Initialize speed and link to default case */
1165 *link_up = false;
1166 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1167
1168 /*
1169 * Check current speed and link status of the PHY register.
1170 * This is a vendor specific register and may have to
1171 * be changed for other copper PHYs.
1172 */
1173 for (time_out = 0; time_out < max_time_out; time_out++) {
1174 udelay(10);
1175 status = hw->phy.ops.read_reg(hw,
1176 MDIO_STAT1,
1177 MDIO_MMD_VEND1,
1178 &phy_data);
1179 phy_link = phy_data &
1180 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1181 phy_speed = phy_data &
1182 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1183 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1184 *link_up = true;
1185 if (phy_speed ==
1186 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1187 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1188 break;
1189 }
1190 }
1191
1192 return status;
1193 }
1194
1195 /**
1196 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
1197 * @hw: pointer to hardware structure
1198 *
1199 * Restart autonegotiation and PHY and waits for completion.
1200 * This function always returns success, this is nessary since
1201 * it is called via a function pointer that could call other
1202 * functions that could return an error.
1203 **/
ixgbe_setup_phy_link_tnx(struct ixgbe_hw * hw)1204 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1205 {
1206 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1207 bool autoneg = false;
1208 ixgbe_link_speed speed;
1209
1210 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1211
1212 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1213 /* Set or unset auto-negotiation 10G advertisement */
1214 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
1215 MDIO_MMD_AN,
1216 &autoneg_reg);
1217
1218 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
1219 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1220 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
1221
1222 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
1223 MDIO_MMD_AN,
1224 autoneg_reg);
1225 }
1226
1227 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1228 /* Set or unset auto-negotiation 1G advertisement */
1229 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1230 MDIO_MMD_AN,
1231 &autoneg_reg);
1232
1233 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1234 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1235 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1236
1237 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1238 MDIO_MMD_AN,
1239 autoneg_reg);
1240 }
1241
1242 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1243 /* Set or unset auto-negotiation 100M advertisement */
1244 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
1245 MDIO_MMD_AN,
1246 &autoneg_reg);
1247
1248 autoneg_reg &= ~(ADVERTISE_100FULL |
1249 ADVERTISE_100HALF);
1250 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1251 autoneg_reg |= ADVERTISE_100FULL;
1252
1253 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
1254 MDIO_MMD_AN,
1255 autoneg_reg);
1256 }
1257
1258 /* Blocked by MNG FW so don't reset PHY */
1259 if (ixgbe_check_reset_blocked(hw))
1260 return 0;
1261
1262 /* Restart PHY autonegotiation and wait for completion */
1263 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1264 MDIO_MMD_AN, &autoneg_reg);
1265
1266 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1267
1268 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1269 MDIO_MMD_AN, autoneg_reg);
1270 return 0;
1271 }
1272
1273 /**
1274 * ixgbe_reset_phy_nl - Performs a PHY reset
1275 * @hw: pointer to hardware structure
1276 **/
ixgbe_reset_phy_nl(struct ixgbe_hw * hw)1277 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1278 {
1279 u16 phy_offset, control, eword, edata, block_crc;
1280 bool end_data = false;
1281 u16 list_offset, data_offset;
1282 u16 phy_data = 0;
1283 s32 ret_val;
1284 u32 i;
1285
1286 /* Blocked by MNG FW so bail */
1287 if (ixgbe_check_reset_blocked(hw))
1288 return 0;
1289
1290 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
1291
1292 /* reset the PHY and poll for completion */
1293 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1294 (phy_data | MDIO_CTRL1_RESET));
1295
1296 for (i = 0; i < 100; i++) {
1297 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1298 &phy_data);
1299 if ((phy_data & MDIO_CTRL1_RESET) == 0)
1300 break;
1301 usleep_range(10000, 20000);
1302 }
1303
1304 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
1305 hw_dbg(hw, "PHY reset did not complete.\n");
1306 return IXGBE_ERR_PHY;
1307 }
1308
1309 /* Get init offsets */
1310 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1311 &data_offset);
1312 if (ret_val)
1313 return ret_val;
1314
1315 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1316 data_offset++;
1317 while (!end_data) {
1318 /*
1319 * Read control word from PHY init contents offset
1320 */
1321 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1322 if (ret_val)
1323 goto err_eeprom;
1324 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1325 IXGBE_CONTROL_SHIFT_NL;
1326 edata = eword & IXGBE_DATA_MASK_NL;
1327 switch (control) {
1328 case IXGBE_DELAY_NL:
1329 data_offset++;
1330 hw_dbg(hw, "DELAY: %d MS\n", edata);
1331 usleep_range(edata * 1000, edata * 2000);
1332 break;
1333 case IXGBE_DATA_NL:
1334 hw_dbg(hw, "DATA:\n");
1335 data_offset++;
1336 ret_val = hw->eeprom.ops.read(hw, data_offset++,
1337 &phy_offset);
1338 if (ret_val)
1339 goto err_eeprom;
1340 for (i = 0; i < edata; i++) {
1341 ret_val = hw->eeprom.ops.read(hw, data_offset,
1342 &eword);
1343 if (ret_val)
1344 goto err_eeprom;
1345 hw->phy.ops.write_reg(hw, phy_offset,
1346 MDIO_MMD_PMAPMD, eword);
1347 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
1348 phy_offset);
1349 data_offset++;
1350 phy_offset++;
1351 }
1352 break;
1353 case IXGBE_CONTROL_NL:
1354 data_offset++;
1355 hw_dbg(hw, "CONTROL:\n");
1356 if (edata == IXGBE_CONTROL_EOL_NL) {
1357 hw_dbg(hw, "EOL\n");
1358 end_data = true;
1359 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1360 hw_dbg(hw, "SOL\n");
1361 } else {
1362 hw_dbg(hw, "Bad control value\n");
1363 return IXGBE_ERR_PHY;
1364 }
1365 break;
1366 default:
1367 hw_dbg(hw, "Bad control type\n");
1368 return IXGBE_ERR_PHY;
1369 }
1370 }
1371
1372 return ret_val;
1373
1374 err_eeprom:
1375 hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
1376 return IXGBE_ERR_PHY;
1377 }
1378
1379 /**
1380 * ixgbe_identify_module_generic - Identifies module type
1381 * @hw: pointer to hardware structure
1382 *
1383 * Determines HW type and calls appropriate function.
1384 **/
ixgbe_identify_module_generic(struct ixgbe_hw * hw)1385 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1386 {
1387 switch (hw->mac.ops.get_media_type(hw)) {
1388 case ixgbe_media_type_fiber:
1389 return ixgbe_identify_sfp_module_generic(hw);
1390 case ixgbe_media_type_fiber_qsfp:
1391 return ixgbe_identify_qsfp_module_generic(hw);
1392 default:
1393 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1394 return IXGBE_ERR_SFP_NOT_PRESENT;
1395 }
1396
1397 return IXGBE_ERR_SFP_NOT_PRESENT;
1398 }
1399
1400 /**
1401 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1402 * @hw: pointer to hardware structure
1403 *
1404 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1405 **/
ixgbe_identify_sfp_module_generic(struct ixgbe_hw * hw)1406 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1407 {
1408 struct ixgbe_adapter *adapter = hw->back;
1409 s32 status;
1410 u32 vendor_oui = 0;
1411 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1412 u8 identifier = 0;
1413 u8 comp_codes_1g = 0;
1414 u8 comp_codes_10g = 0;
1415 u8 oui_bytes[3] = {0, 0, 0};
1416 u8 cable_tech = 0;
1417 u8 cable_spec = 0;
1418 u16 enforce_sfp = 0;
1419
1420 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1421 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1422 return IXGBE_ERR_SFP_NOT_PRESENT;
1423 }
1424
1425 /* LAN ID is needed for sfp_type determination */
1426 hw->mac.ops.set_lan_id(hw);
1427
1428 status = hw->phy.ops.read_i2c_eeprom(hw,
1429 IXGBE_SFF_IDENTIFIER,
1430 &identifier);
1431
1432 if (status)
1433 goto err_read_i2c_eeprom;
1434
1435 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1436 hw->phy.type = ixgbe_phy_sfp_unsupported;
1437 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1438 }
1439 status = hw->phy.ops.read_i2c_eeprom(hw,
1440 IXGBE_SFF_1GBE_COMP_CODES,
1441 &comp_codes_1g);
1442
1443 if (status)
1444 goto err_read_i2c_eeprom;
1445
1446 status = hw->phy.ops.read_i2c_eeprom(hw,
1447 IXGBE_SFF_10GBE_COMP_CODES,
1448 &comp_codes_10g);
1449
1450 if (status)
1451 goto err_read_i2c_eeprom;
1452 status = hw->phy.ops.read_i2c_eeprom(hw,
1453 IXGBE_SFF_CABLE_TECHNOLOGY,
1454 &cable_tech);
1455
1456 if (status)
1457 goto err_read_i2c_eeprom;
1458
1459 /* ID Module
1460 * =========
1461 * 0 SFP_DA_CU
1462 * 1 SFP_SR
1463 * 2 SFP_LR
1464 * 3 SFP_DA_CORE0 - 82599-specific
1465 * 4 SFP_DA_CORE1 - 82599-specific
1466 * 5 SFP_SR/LR_CORE0 - 82599-specific
1467 * 6 SFP_SR/LR_CORE1 - 82599-specific
1468 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1469 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1470 * 9 SFP_1g_cu_CORE0 - 82599-specific
1471 * 10 SFP_1g_cu_CORE1 - 82599-specific
1472 * 11 SFP_1g_sx_CORE0 - 82599-specific
1473 * 12 SFP_1g_sx_CORE1 - 82599-specific
1474 */
1475 if (hw->mac.type == ixgbe_mac_82598EB) {
1476 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1477 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1478 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1479 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1480 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1481 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1482 else
1483 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1484 } else {
1485 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1486 if (hw->bus.lan_id == 0)
1487 hw->phy.sfp_type =
1488 ixgbe_sfp_type_da_cu_core0;
1489 else
1490 hw->phy.sfp_type =
1491 ixgbe_sfp_type_da_cu_core1;
1492 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1493 hw->phy.ops.read_i2c_eeprom(
1494 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1495 &cable_spec);
1496 if (cable_spec &
1497 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1498 if (hw->bus.lan_id == 0)
1499 hw->phy.sfp_type =
1500 ixgbe_sfp_type_da_act_lmt_core0;
1501 else
1502 hw->phy.sfp_type =
1503 ixgbe_sfp_type_da_act_lmt_core1;
1504 } else {
1505 hw->phy.sfp_type =
1506 ixgbe_sfp_type_unknown;
1507 }
1508 } else if (comp_codes_10g &
1509 (IXGBE_SFF_10GBASESR_CAPABLE |
1510 IXGBE_SFF_10GBASELR_CAPABLE)) {
1511 if (hw->bus.lan_id == 0)
1512 hw->phy.sfp_type =
1513 ixgbe_sfp_type_srlr_core0;
1514 else
1515 hw->phy.sfp_type =
1516 ixgbe_sfp_type_srlr_core1;
1517 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1518 if (hw->bus.lan_id == 0)
1519 hw->phy.sfp_type =
1520 ixgbe_sfp_type_1g_cu_core0;
1521 else
1522 hw->phy.sfp_type =
1523 ixgbe_sfp_type_1g_cu_core1;
1524 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1525 if (hw->bus.lan_id == 0)
1526 hw->phy.sfp_type =
1527 ixgbe_sfp_type_1g_sx_core0;
1528 else
1529 hw->phy.sfp_type =
1530 ixgbe_sfp_type_1g_sx_core1;
1531 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1532 if (hw->bus.lan_id == 0)
1533 hw->phy.sfp_type =
1534 ixgbe_sfp_type_1g_lx_core0;
1535 else
1536 hw->phy.sfp_type =
1537 ixgbe_sfp_type_1g_lx_core1;
1538 } else {
1539 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1540 }
1541 }
1542
1543 if (hw->phy.sfp_type != stored_sfp_type)
1544 hw->phy.sfp_setup_needed = true;
1545
1546 /* Determine if the SFP+ PHY is dual speed or not. */
1547 hw->phy.multispeed_fiber = false;
1548 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1549 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1550 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1551 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1552 hw->phy.multispeed_fiber = true;
1553
1554 /* Determine PHY vendor */
1555 if (hw->phy.type != ixgbe_phy_nl) {
1556 hw->phy.id = identifier;
1557 status = hw->phy.ops.read_i2c_eeprom(hw,
1558 IXGBE_SFF_VENDOR_OUI_BYTE0,
1559 &oui_bytes[0]);
1560
1561 if (status != 0)
1562 goto err_read_i2c_eeprom;
1563
1564 status = hw->phy.ops.read_i2c_eeprom(hw,
1565 IXGBE_SFF_VENDOR_OUI_BYTE1,
1566 &oui_bytes[1]);
1567
1568 if (status != 0)
1569 goto err_read_i2c_eeprom;
1570
1571 status = hw->phy.ops.read_i2c_eeprom(hw,
1572 IXGBE_SFF_VENDOR_OUI_BYTE2,
1573 &oui_bytes[2]);
1574
1575 if (status != 0)
1576 goto err_read_i2c_eeprom;
1577
1578 vendor_oui =
1579 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1580 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1581 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1582
1583 switch (vendor_oui) {
1584 case IXGBE_SFF_VENDOR_OUI_TYCO:
1585 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1586 hw->phy.type =
1587 ixgbe_phy_sfp_passive_tyco;
1588 break;
1589 case IXGBE_SFF_VENDOR_OUI_FTL:
1590 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1591 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1592 else
1593 hw->phy.type = ixgbe_phy_sfp_ftl;
1594 break;
1595 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1596 hw->phy.type = ixgbe_phy_sfp_avago;
1597 break;
1598 case IXGBE_SFF_VENDOR_OUI_INTEL:
1599 hw->phy.type = ixgbe_phy_sfp_intel;
1600 break;
1601 default:
1602 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1603 hw->phy.type =
1604 ixgbe_phy_sfp_passive_unknown;
1605 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1606 hw->phy.type =
1607 ixgbe_phy_sfp_active_unknown;
1608 else
1609 hw->phy.type = ixgbe_phy_sfp_unknown;
1610 break;
1611 }
1612 }
1613
1614 /* Allow any DA cable vendor */
1615 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1616 IXGBE_SFF_DA_ACTIVE_CABLE))
1617 return 0;
1618
1619 /* Verify supported 1G SFP modules */
1620 if (comp_codes_10g == 0 &&
1621 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1622 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1623 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1624 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1625 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1626 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1627 hw->phy.type = ixgbe_phy_sfp_unsupported;
1628 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1629 }
1630
1631 /* Anything else 82598-based is supported */
1632 if (hw->mac.type == ixgbe_mac_82598EB)
1633 return 0;
1634
1635 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1636 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1637 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1638 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1639 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1640 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1641 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1642 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1643 /* Make sure we're a supported PHY type */
1644 if (hw->phy.type == ixgbe_phy_sfp_intel)
1645 return 0;
1646 if (hw->allow_unsupported_sfp) {
1647 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1648 return 0;
1649 }
1650 hw_dbg(hw, "SFP+ module not supported\n");
1651 hw->phy.type = ixgbe_phy_sfp_unsupported;
1652 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1653 }
1654 return 0;
1655
1656 err_read_i2c_eeprom:
1657 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1658 if (hw->phy.type != ixgbe_phy_nl) {
1659 hw->phy.id = 0;
1660 hw->phy.type = ixgbe_phy_unknown;
1661 }
1662 return IXGBE_ERR_SFP_NOT_PRESENT;
1663 }
1664
1665 /**
1666 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1667 * @hw: pointer to hardware structure
1668 *
1669 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1670 **/
ixgbe_identify_qsfp_module_generic(struct ixgbe_hw * hw)1671 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1672 {
1673 struct ixgbe_adapter *adapter = hw->back;
1674 s32 status;
1675 u32 vendor_oui = 0;
1676 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1677 u8 identifier = 0;
1678 u8 comp_codes_1g = 0;
1679 u8 comp_codes_10g = 0;
1680 u8 oui_bytes[3] = {0, 0, 0};
1681 u16 enforce_sfp = 0;
1682 u8 connector = 0;
1683 u8 cable_length = 0;
1684 u8 device_tech = 0;
1685 bool active_cable = false;
1686
1687 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1688 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1689 return IXGBE_ERR_SFP_NOT_PRESENT;
1690 }
1691
1692 /* LAN ID is needed for sfp_type determination */
1693 hw->mac.ops.set_lan_id(hw);
1694
1695 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1696 &identifier);
1697
1698 if (status != 0)
1699 goto err_read_i2c_eeprom;
1700
1701 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1702 hw->phy.type = ixgbe_phy_sfp_unsupported;
1703 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1704 }
1705
1706 hw->phy.id = identifier;
1707
1708 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1709 &comp_codes_10g);
1710
1711 if (status != 0)
1712 goto err_read_i2c_eeprom;
1713
1714 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1715 &comp_codes_1g);
1716
1717 if (status != 0)
1718 goto err_read_i2c_eeprom;
1719
1720 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1721 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1722 if (hw->bus.lan_id == 0)
1723 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1724 else
1725 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1726 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1727 IXGBE_SFF_10GBASELR_CAPABLE)) {
1728 if (hw->bus.lan_id == 0)
1729 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1730 else
1731 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1732 } else {
1733 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1734 active_cable = true;
1735
1736 if (!active_cable) {
1737 /* check for active DA cables that pre-date
1738 * SFF-8436 v3.6
1739 */
1740 hw->phy.ops.read_i2c_eeprom(hw,
1741 IXGBE_SFF_QSFP_CONNECTOR,
1742 &connector);
1743
1744 hw->phy.ops.read_i2c_eeprom(hw,
1745 IXGBE_SFF_QSFP_CABLE_LENGTH,
1746 &cable_length);
1747
1748 hw->phy.ops.read_i2c_eeprom(hw,
1749 IXGBE_SFF_QSFP_DEVICE_TECH,
1750 &device_tech);
1751
1752 if ((connector ==
1753 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1754 (cable_length > 0) &&
1755 ((device_tech >> 4) ==
1756 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1757 active_cable = true;
1758 }
1759
1760 if (active_cable) {
1761 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1762 if (hw->bus.lan_id == 0)
1763 hw->phy.sfp_type =
1764 ixgbe_sfp_type_da_act_lmt_core0;
1765 else
1766 hw->phy.sfp_type =
1767 ixgbe_sfp_type_da_act_lmt_core1;
1768 } else {
1769 /* unsupported module type */
1770 hw->phy.type = ixgbe_phy_sfp_unsupported;
1771 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1772 }
1773 }
1774
1775 if (hw->phy.sfp_type != stored_sfp_type)
1776 hw->phy.sfp_setup_needed = true;
1777
1778 /* Determine if the QSFP+ PHY is dual speed or not. */
1779 hw->phy.multispeed_fiber = false;
1780 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1781 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1782 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1783 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1784 hw->phy.multispeed_fiber = true;
1785
1786 /* Determine PHY vendor for optical modules */
1787 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1788 IXGBE_SFF_10GBASELR_CAPABLE)) {
1789 status = hw->phy.ops.read_i2c_eeprom(hw,
1790 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1791 &oui_bytes[0]);
1792
1793 if (status != 0)
1794 goto err_read_i2c_eeprom;
1795
1796 status = hw->phy.ops.read_i2c_eeprom(hw,
1797 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1798 &oui_bytes[1]);
1799
1800 if (status != 0)
1801 goto err_read_i2c_eeprom;
1802
1803 status = hw->phy.ops.read_i2c_eeprom(hw,
1804 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1805 &oui_bytes[2]);
1806
1807 if (status != 0)
1808 goto err_read_i2c_eeprom;
1809
1810 vendor_oui =
1811 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1812 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1813 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1814
1815 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1816 hw->phy.type = ixgbe_phy_qsfp_intel;
1817 else
1818 hw->phy.type = ixgbe_phy_qsfp_unknown;
1819
1820 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1821 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1822 /* Make sure we're a supported PHY type */
1823 if (hw->phy.type == ixgbe_phy_qsfp_intel)
1824 return 0;
1825 if (hw->allow_unsupported_sfp) {
1826 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1827 return 0;
1828 }
1829 hw_dbg(hw, "QSFP module not supported\n");
1830 hw->phy.type = ixgbe_phy_sfp_unsupported;
1831 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1832 }
1833 return 0;
1834 }
1835 return 0;
1836
1837 err_read_i2c_eeprom:
1838 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1839 hw->phy.id = 0;
1840 hw->phy.type = ixgbe_phy_unknown;
1841
1842 return IXGBE_ERR_SFP_NOT_PRESENT;
1843 }
1844
1845 /**
1846 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1847 * @hw: pointer to hardware structure
1848 * @list_offset: offset to the SFP ID list
1849 * @data_offset: offset to the SFP data block
1850 *
1851 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1852 * so it returns the offsets to the phy init sequence block.
1853 **/
ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw * hw,u16 * list_offset,u16 * data_offset)1854 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1855 u16 *list_offset,
1856 u16 *data_offset)
1857 {
1858 u16 sfp_id;
1859 u16 sfp_type = hw->phy.sfp_type;
1860
1861 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1862 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1863
1864 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1865 return IXGBE_ERR_SFP_NOT_PRESENT;
1866
1867 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1868 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1869 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1870
1871 /*
1872 * Limiting active cables and 1G Phys must be initialized as
1873 * SR modules
1874 */
1875 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1876 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1877 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1878 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1879 sfp_type = ixgbe_sfp_type_srlr_core0;
1880 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1881 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1882 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1883 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1884 sfp_type = ixgbe_sfp_type_srlr_core1;
1885
1886 /* Read offset to PHY init contents */
1887 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1888 hw_err(hw, "eeprom read at %d failed\n",
1889 IXGBE_PHY_INIT_OFFSET_NL);
1890 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1891 }
1892
1893 if ((!*list_offset) || (*list_offset == 0xFFFF))
1894 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1895
1896 /* Shift offset to first ID word */
1897 (*list_offset)++;
1898
1899 /*
1900 * Find the matching SFP ID in the EEPROM
1901 * and program the init sequence
1902 */
1903 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1904 goto err_phy;
1905
1906 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1907 if (sfp_id == sfp_type) {
1908 (*list_offset)++;
1909 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1910 goto err_phy;
1911 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1912 hw_dbg(hw, "SFP+ module not supported\n");
1913 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1914 } else {
1915 break;
1916 }
1917 } else {
1918 (*list_offset) += 2;
1919 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1920 goto err_phy;
1921 }
1922 }
1923
1924 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1925 hw_dbg(hw, "No matching SFP+ module found\n");
1926 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1927 }
1928
1929 return 0;
1930
1931 err_phy:
1932 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
1933 return IXGBE_ERR_PHY;
1934 }
1935
1936 /**
1937 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1938 * @hw: pointer to hardware structure
1939 * @byte_offset: EEPROM byte offset to read
1940 * @eeprom_data: value read
1941 *
1942 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1943 **/
ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 * eeprom_data)1944 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1945 u8 *eeprom_data)
1946 {
1947 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1948 IXGBE_I2C_EEPROM_DEV_ADDR,
1949 eeprom_data);
1950 }
1951
1952 /**
1953 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1954 * @hw: pointer to hardware structure
1955 * @byte_offset: byte offset at address 0xA2
1956 * @sff8472_data: value read
1957 *
1958 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1959 **/
ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 * sff8472_data)1960 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1961 u8 *sff8472_data)
1962 {
1963 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1964 IXGBE_I2C_EEPROM_DEV_ADDR2,
1965 sff8472_data);
1966 }
1967
1968 /**
1969 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1970 * @hw: pointer to hardware structure
1971 * @byte_offset: EEPROM byte offset to write
1972 * @eeprom_data: value to write
1973 *
1974 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1975 **/
ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 eeprom_data)1976 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1977 u8 eeprom_data)
1978 {
1979 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1980 IXGBE_I2C_EEPROM_DEV_ADDR,
1981 eeprom_data);
1982 }
1983
1984 /**
1985 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1986 * @hw: pointer to hardware structure
1987 * @offset: eeprom offset to be read
1988 * @addr: I2C address to be read
1989 */
ixgbe_is_sfp_probe(struct ixgbe_hw * hw,u8 offset,u8 addr)1990 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1991 {
1992 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1993 offset == IXGBE_SFF_IDENTIFIER &&
1994 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1995 return true;
1996 return false;
1997 }
1998
1999 /**
2000 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2001 * @hw: pointer to hardware structure
2002 * @byte_offset: byte offset to read
2003 * @dev_addr: device address
2004 * @data: value read
2005 * @lock: true if to take and release semaphore
2006 *
2007 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2008 * a specified device address.
2009 */
ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data,bool lock)2010 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2011 u8 dev_addr, u8 *data, bool lock)
2012 {
2013 s32 status;
2014 u32 max_retry = 10;
2015 u32 retry = 0;
2016 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2017 bool nack = true;
2018
2019 if (hw->mac.type >= ixgbe_mac_X550)
2020 max_retry = 3;
2021 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2022 max_retry = IXGBE_SFP_DETECT_RETRIES;
2023
2024 *data = 0;
2025
2026 do {
2027 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2028 return IXGBE_ERR_SWFW_SYNC;
2029
2030 ixgbe_i2c_start(hw);
2031
2032 /* Device Address and write indication */
2033 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2034 if (status != 0)
2035 goto fail;
2036
2037 status = ixgbe_get_i2c_ack(hw);
2038 if (status != 0)
2039 goto fail;
2040
2041 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2042 if (status != 0)
2043 goto fail;
2044
2045 status = ixgbe_get_i2c_ack(hw);
2046 if (status != 0)
2047 goto fail;
2048
2049 ixgbe_i2c_start(hw);
2050
2051 /* Device Address and read indication */
2052 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2053 if (status != 0)
2054 goto fail;
2055
2056 status = ixgbe_get_i2c_ack(hw);
2057 if (status != 0)
2058 goto fail;
2059
2060 status = ixgbe_clock_in_i2c_byte(hw, data);
2061 if (status != 0)
2062 goto fail;
2063
2064 status = ixgbe_clock_out_i2c_bit(hw, nack);
2065 if (status != 0)
2066 goto fail;
2067
2068 ixgbe_i2c_stop(hw);
2069 if (lock)
2070 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2071 return 0;
2072
2073 fail:
2074 ixgbe_i2c_bus_clear(hw);
2075 if (lock) {
2076 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2077 msleep(100);
2078 }
2079 retry++;
2080 if (retry < max_retry)
2081 hw_dbg(hw, "I2C byte read error - Retrying.\n");
2082 else
2083 hw_dbg(hw, "I2C byte read error.\n");
2084
2085 } while (retry < max_retry);
2086
2087 return status;
2088 }
2089
2090 /**
2091 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2092 * @hw: pointer to hardware structure
2093 * @byte_offset: byte offset to read
2094 * @dev_addr: device address
2095 * @data: value read
2096 *
2097 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2098 * a specified device address.
2099 */
ixgbe_read_i2c_byte_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)2100 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2101 u8 dev_addr, u8 *data)
2102 {
2103 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2104 data, true);
2105 }
2106
2107 /**
2108 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2109 * @hw: pointer to hardware structure
2110 * @byte_offset: byte offset to read
2111 * @dev_addr: device address
2112 * @data: value read
2113 *
2114 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2115 * a specified device address.
2116 */
ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)2117 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2118 u8 dev_addr, u8 *data)
2119 {
2120 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2121 data, false);
2122 }
2123
2124 /**
2125 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2126 * @hw: pointer to hardware structure
2127 * @byte_offset: byte offset to write
2128 * @dev_addr: device address
2129 * @data: value to write
2130 * @lock: true if to take and release semaphore
2131 *
2132 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2133 * a specified device address.
2134 */
ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data,bool lock)2135 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2136 u8 dev_addr, u8 data, bool lock)
2137 {
2138 s32 status;
2139 u32 max_retry = 1;
2140 u32 retry = 0;
2141 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2142
2143 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2144 return IXGBE_ERR_SWFW_SYNC;
2145
2146 do {
2147 ixgbe_i2c_start(hw);
2148
2149 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2150 if (status != 0)
2151 goto fail;
2152
2153 status = ixgbe_get_i2c_ack(hw);
2154 if (status != 0)
2155 goto fail;
2156
2157 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2158 if (status != 0)
2159 goto fail;
2160
2161 status = ixgbe_get_i2c_ack(hw);
2162 if (status != 0)
2163 goto fail;
2164
2165 status = ixgbe_clock_out_i2c_byte(hw, data);
2166 if (status != 0)
2167 goto fail;
2168
2169 status = ixgbe_get_i2c_ack(hw);
2170 if (status != 0)
2171 goto fail;
2172
2173 ixgbe_i2c_stop(hw);
2174 if (lock)
2175 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2176 return 0;
2177
2178 fail:
2179 ixgbe_i2c_bus_clear(hw);
2180 retry++;
2181 if (retry < max_retry)
2182 hw_dbg(hw, "I2C byte write error - Retrying.\n");
2183 else
2184 hw_dbg(hw, "I2C byte write error.\n");
2185 } while (retry < max_retry);
2186
2187 if (lock)
2188 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2189
2190 return status;
2191 }
2192
2193 /**
2194 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2195 * @hw: pointer to hardware structure
2196 * @byte_offset: byte offset to write
2197 * @dev_addr: device address
2198 * @data: value to write
2199 *
2200 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2201 * a specified device address.
2202 */
ixgbe_write_i2c_byte_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)2203 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2204 u8 dev_addr, u8 data)
2205 {
2206 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2207 data, true);
2208 }
2209
2210 /**
2211 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2212 * @hw: pointer to hardware structure
2213 * @byte_offset: byte offset to write
2214 * @dev_addr: device address
2215 * @data: value to write
2216 *
2217 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2218 * a specified device address.
2219 */
ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)2220 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2221 u8 dev_addr, u8 data)
2222 {
2223 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2224 data, false);
2225 }
2226
2227 /**
2228 * ixgbe_i2c_start - Sets I2C start condition
2229 * @hw: pointer to hardware structure
2230 *
2231 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2232 * Set bit-bang mode on X550 hardware.
2233 **/
ixgbe_i2c_start(struct ixgbe_hw * hw)2234 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2235 {
2236 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2237
2238 i2cctl |= IXGBE_I2C_BB_EN(hw);
2239
2240 /* Start condition must begin with data and clock high */
2241 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2242 ixgbe_raise_i2c_clk(hw, &i2cctl);
2243
2244 /* Setup time for start condition (4.7us) */
2245 udelay(IXGBE_I2C_T_SU_STA);
2246
2247 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2248
2249 /* Hold time for start condition (4us) */
2250 udelay(IXGBE_I2C_T_HD_STA);
2251
2252 ixgbe_lower_i2c_clk(hw, &i2cctl);
2253
2254 /* Minimum low period of clock is 4.7 us */
2255 udelay(IXGBE_I2C_T_LOW);
2256
2257 }
2258
2259 /**
2260 * ixgbe_i2c_stop - Sets I2C stop condition
2261 * @hw: pointer to hardware structure
2262 *
2263 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2264 * Disables bit-bang mode and negates data output enable on X550
2265 * hardware.
2266 **/
ixgbe_i2c_stop(struct ixgbe_hw * hw)2267 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2268 {
2269 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2270 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2271 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2272 u32 bb_en_bit = IXGBE_I2C_BB_EN(hw);
2273
2274 /* Stop condition must begin with data low and clock high */
2275 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2276 ixgbe_raise_i2c_clk(hw, &i2cctl);
2277
2278 /* Setup time for stop condition (4us) */
2279 udelay(IXGBE_I2C_T_SU_STO);
2280
2281 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2282
2283 /* bus free time between stop and start (4.7us)*/
2284 udelay(IXGBE_I2C_T_BUF);
2285
2286 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2287 i2cctl &= ~bb_en_bit;
2288 i2cctl |= data_oe_bit | clk_oe_bit;
2289 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2290 IXGBE_WRITE_FLUSH(hw);
2291 }
2292 }
2293
2294 /**
2295 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2296 * @hw: pointer to hardware structure
2297 * @data: data byte to clock in
2298 *
2299 * Clocks in one byte data via I2C data/clock
2300 **/
ixgbe_clock_in_i2c_byte(struct ixgbe_hw * hw,u8 * data)2301 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2302 {
2303 s32 i;
2304 bool bit = false;
2305
2306 *data = 0;
2307 for (i = 7; i >= 0; i--) {
2308 ixgbe_clock_in_i2c_bit(hw, &bit);
2309 *data |= bit << i;
2310 }
2311
2312 return 0;
2313 }
2314
2315 /**
2316 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2317 * @hw: pointer to hardware structure
2318 * @data: data byte clocked out
2319 *
2320 * Clocks out one byte data via I2C data/clock
2321 **/
ixgbe_clock_out_i2c_byte(struct ixgbe_hw * hw,u8 data)2322 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2323 {
2324 s32 status;
2325 s32 i;
2326 u32 i2cctl;
2327 bool bit = false;
2328
2329 for (i = 7; i >= 0; i--) {
2330 bit = (data >> i) & 0x1;
2331 status = ixgbe_clock_out_i2c_bit(hw, bit);
2332
2333 if (status != 0)
2334 break;
2335 }
2336
2337 /* Release SDA line (set high) */
2338 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2339 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2340 i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw);
2341 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2342 IXGBE_WRITE_FLUSH(hw);
2343
2344 return status;
2345 }
2346
2347 /**
2348 * ixgbe_get_i2c_ack - Polls for I2C ACK
2349 * @hw: pointer to hardware structure
2350 *
2351 * Clocks in/out one bit via I2C data/clock
2352 **/
ixgbe_get_i2c_ack(struct ixgbe_hw * hw)2353 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2354 {
2355 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2356 s32 status = 0;
2357 u32 i = 0;
2358 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2359 u32 timeout = 10;
2360 bool ack = true;
2361
2362 if (data_oe_bit) {
2363 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2364 i2cctl |= data_oe_bit;
2365 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2366 IXGBE_WRITE_FLUSH(hw);
2367 }
2368 ixgbe_raise_i2c_clk(hw, &i2cctl);
2369
2370 /* Minimum high period of clock is 4us */
2371 udelay(IXGBE_I2C_T_HIGH);
2372
2373 /* Poll for ACK. Note that ACK in I2C spec is
2374 * transition from 1 to 0 */
2375 for (i = 0; i < timeout; i++) {
2376 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2377 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2378
2379 udelay(1);
2380 if (ack == 0)
2381 break;
2382 }
2383
2384 if (ack == 1) {
2385 hw_dbg(hw, "I2C ack was not received.\n");
2386 status = IXGBE_ERR_I2C;
2387 }
2388
2389 ixgbe_lower_i2c_clk(hw, &i2cctl);
2390
2391 /* Minimum low period of clock is 4.7 us */
2392 udelay(IXGBE_I2C_T_LOW);
2393
2394 return status;
2395 }
2396
2397 /**
2398 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2399 * @hw: pointer to hardware structure
2400 * @data: read data value
2401 *
2402 * Clocks in one bit via I2C data/clock
2403 **/
ixgbe_clock_in_i2c_bit(struct ixgbe_hw * hw,bool * data)2404 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2405 {
2406 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2407 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2408
2409 if (data_oe_bit) {
2410 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2411 i2cctl |= data_oe_bit;
2412 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2413 IXGBE_WRITE_FLUSH(hw);
2414 }
2415 ixgbe_raise_i2c_clk(hw, &i2cctl);
2416
2417 /* Minimum high period of clock is 4us */
2418 udelay(IXGBE_I2C_T_HIGH);
2419
2420 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2421 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2422
2423 ixgbe_lower_i2c_clk(hw, &i2cctl);
2424
2425 /* Minimum low period of clock is 4.7 us */
2426 udelay(IXGBE_I2C_T_LOW);
2427
2428 return 0;
2429 }
2430
2431 /**
2432 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2433 * @hw: pointer to hardware structure
2434 * @data: data value to write
2435 *
2436 * Clocks out one bit via I2C data/clock
2437 **/
ixgbe_clock_out_i2c_bit(struct ixgbe_hw * hw,bool data)2438 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2439 {
2440 s32 status;
2441 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2442
2443 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2444 if (status == 0) {
2445 ixgbe_raise_i2c_clk(hw, &i2cctl);
2446
2447 /* Minimum high period of clock is 4us */
2448 udelay(IXGBE_I2C_T_HIGH);
2449
2450 ixgbe_lower_i2c_clk(hw, &i2cctl);
2451
2452 /* Minimum low period of clock is 4.7 us.
2453 * This also takes care of the data hold time.
2454 */
2455 udelay(IXGBE_I2C_T_LOW);
2456 } else {
2457 hw_dbg(hw, "I2C data was not set to %X\n", data);
2458 return IXGBE_ERR_I2C;
2459 }
2460
2461 return 0;
2462 }
2463 /**
2464 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2465 * @hw: pointer to hardware structure
2466 * @i2cctl: Current value of I2CCTL register
2467 *
2468 * Raises the I2C clock line '0'->'1'
2469 * Negates the I2C clock output enable on X550 hardware.
2470 **/
ixgbe_raise_i2c_clk(struct ixgbe_hw * hw,u32 * i2cctl)2471 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2472 {
2473 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2474 u32 i = 0;
2475 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2476 u32 i2cctl_r = 0;
2477
2478 if (clk_oe_bit) {
2479 *i2cctl |= clk_oe_bit;
2480 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2481 }
2482
2483 for (i = 0; i < timeout; i++) {
2484 *i2cctl |= IXGBE_I2C_CLK_OUT(hw);
2485 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2486 IXGBE_WRITE_FLUSH(hw);
2487 /* SCL rise time (1000ns) */
2488 udelay(IXGBE_I2C_T_RISE);
2489
2490 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2491 if (i2cctl_r & IXGBE_I2C_CLK_IN(hw))
2492 break;
2493 }
2494 }
2495
2496 /**
2497 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2498 * @hw: pointer to hardware structure
2499 * @i2cctl: Current value of I2CCTL register
2500 *
2501 * Lowers the I2C clock line '1'->'0'
2502 * Asserts the I2C clock output enable on X550 hardware.
2503 **/
ixgbe_lower_i2c_clk(struct ixgbe_hw * hw,u32 * i2cctl)2504 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2505 {
2506
2507 *i2cctl &= ~IXGBE_I2C_CLK_OUT(hw);
2508 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw);
2509
2510 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2511 IXGBE_WRITE_FLUSH(hw);
2512
2513 /* SCL fall time (300ns) */
2514 udelay(IXGBE_I2C_T_FALL);
2515 }
2516
2517 /**
2518 * ixgbe_set_i2c_data - Sets the I2C data bit
2519 * @hw: pointer to hardware structure
2520 * @i2cctl: Current value of I2CCTL register
2521 * @data: I2C data value (0 or 1) to set
2522 *
2523 * Sets the I2C data bit
2524 * Asserts the I2C data output enable on X550 hardware.
2525 **/
ixgbe_set_i2c_data(struct ixgbe_hw * hw,u32 * i2cctl,bool data)2526 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2527 {
2528 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2529
2530 if (data)
2531 *i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2532 else
2533 *i2cctl &= ~IXGBE_I2C_DATA_OUT(hw);
2534 *i2cctl &= ~data_oe_bit;
2535
2536 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2537 IXGBE_WRITE_FLUSH(hw);
2538
2539 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2540 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2541
2542 if (!data) /* Can't verify data in this case */
2543 return 0;
2544 if (data_oe_bit) {
2545 *i2cctl |= data_oe_bit;
2546 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2547 IXGBE_WRITE_FLUSH(hw);
2548 }
2549
2550 /* Verify data was set correctly */
2551 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2552 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2553 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
2554 return IXGBE_ERR_I2C;
2555 }
2556
2557 return 0;
2558 }
2559
2560 /**
2561 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2562 * @hw: pointer to hardware structure
2563 * @i2cctl: Current value of I2CCTL register
2564 *
2565 * Returns the I2C data bit value
2566 * Negates the I2C data output enable on X550 hardware.
2567 **/
ixgbe_get_i2c_data(struct ixgbe_hw * hw,u32 * i2cctl)2568 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2569 {
2570 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2571
2572 if (data_oe_bit) {
2573 *i2cctl |= data_oe_bit;
2574 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2575 IXGBE_WRITE_FLUSH(hw);
2576 udelay(IXGBE_I2C_T_FALL);
2577 }
2578
2579 if (*i2cctl & IXGBE_I2C_DATA_IN(hw))
2580 return true;
2581 return false;
2582 }
2583
2584 /**
2585 * ixgbe_i2c_bus_clear - Clears the I2C bus
2586 * @hw: pointer to hardware structure
2587 *
2588 * Clears the I2C bus by sending nine clock pulses.
2589 * Used when data line is stuck low.
2590 **/
ixgbe_i2c_bus_clear(struct ixgbe_hw * hw)2591 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2592 {
2593 u32 i2cctl;
2594 u32 i;
2595
2596 ixgbe_i2c_start(hw);
2597 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2598
2599 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2600
2601 for (i = 0; i < 9; i++) {
2602 ixgbe_raise_i2c_clk(hw, &i2cctl);
2603
2604 /* Min high period of clock is 4us */
2605 udelay(IXGBE_I2C_T_HIGH);
2606
2607 ixgbe_lower_i2c_clk(hw, &i2cctl);
2608
2609 /* Min low period of clock is 4.7us*/
2610 udelay(IXGBE_I2C_T_LOW);
2611 }
2612
2613 ixgbe_i2c_start(hw);
2614
2615 /* Put the i2c bus back to default state */
2616 ixgbe_i2c_stop(hw);
2617 }
2618
2619 /**
2620 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2621 * @hw: pointer to hardware structure
2622 *
2623 * Checks if the LASI temp alarm status was triggered due to overtemp
2624 **/
ixgbe_tn_check_overtemp(struct ixgbe_hw * hw)2625 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2626 {
2627 u16 phy_data = 0;
2628
2629 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2630 return 0;
2631
2632 /* Check that the LASI temp alarm status was triggered */
2633 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2634 MDIO_MMD_PMAPMD, &phy_data);
2635
2636 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2637 return 0;
2638
2639 return IXGBE_ERR_OVERTEMP;
2640 }
2641
2642 /** ixgbe_set_copper_phy_power - Control power for copper phy
2643 * @hw: pointer to hardware structure
2644 * @on: true for on, false for off
2645 **/
ixgbe_set_copper_phy_power(struct ixgbe_hw * hw,bool on)2646 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2647 {
2648 u32 status;
2649 u16 reg;
2650
2651 /* Bail if we don't have copper phy */
2652 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2653 return 0;
2654
2655 if (!on && ixgbe_mng_present(hw))
2656 return 0;
2657
2658 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, ®);
2659 if (status)
2660 return status;
2661
2662 if (on) {
2663 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2664 } else {
2665 if (ixgbe_check_reset_blocked(hw))
2666 return 0;
2667 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2668 }
2669
2670 status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg);
2671 return status;
2672 }
2673