1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 #include <linux/pci.h>
5 #include <linux/delay.h>
6 #include <linux/sched.h>
7 #include <linux/netdevice.h>
8
9 #include "ixgbe.h"
10 #include "ixgbe_common.h"
11 #include "ixgbe_phy.h"
12
13 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
14 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
15 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
16 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
17 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
18 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
19 u16 count);
20 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
21 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
22 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
23 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
24
25 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
26 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
27 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
28 u16 words, u16 *data);
29 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
30 u16 words, u16 *data);
31 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
32 u16 offset);
33 static s32 ixgbe_disable_pcie_primary(struct ixgbe_hw *hw);
34
35 /* Base table for registers values that change by MAC */
36 const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT] = {
37 IXGBE_MVALS_INIT(8259X)
38 };
39
40 /**
41 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
42 * control
43 * @hw: pointer to hardware structure
44 *
45 * There are several phys that do not support autoneg flow control. This
46 * function check the device id to see if the associated phy supports
47 * autoneg flow control.
48 **/
ixgbe_device_supports_autoneg_fc(struct ixgbe_hw * hw)49 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
50 {
51 bool supported = false;
52 ixgbe_link_speed speed;
53 bool link_up;
54
55 switch (hw->phy.media_type) {
56 case ixgbe_media_type_fiber:
57 /* flow control autoneg black list */
58 switch (hw->device_id) {
59 case IXGBE_DEV_ID_X550EM_A_SFP:
60 case IXGBE_DEV_ID_X550EM_A_SFP_N:
61 supported = false;
62 break;
63 default:
64 hw->mac.ops.check_link(hw, &speed, &link_up, false);
65 /* if link is down, assume supported */
66 if (link_up)
67 supported = speed == IXGBE_LINK_SPEED_1GB_FULL;
68 else
69 supported = true;
70 }
71
72 break;
73 case ixgbe_media_type_backplane:
74 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI)
75 supported = false;
76 else
77 supported = true;
78 break;
79 case ixgbe_media_type_copper:
80 /* only some copper devices support flow control autoneg */
81 switch (hw->device_id) {
82 case IXGBE_DEV_ID_82599_T3_LOM:
83 case IXGBE_DEV_ID_X540T:
84 case IXGBE_DEV_ID_X540T1:
85 case IXGBE_DEV_ID_X550T:
86 case IXGBE_DEV_ID_X550T1:
87 case IXGBE_DEV_ID_X550EM_X_10G_T:
88 case IXGBE_DEV_ID_X550EM_A_10G_T:
89 case IXGBE_DEV_ID_X550EM_A_1G_T:
90 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
91 supported = true;
92 break;
93 default:
94 break;
95 }
96 break;
97 default:
98 break;
99 }
100
101 if (!supported)
102 hw_dbg(hw, "Device %x does not support flow control autoneg\n",
103 hw->device_id);
104
105 return supported;
106 }
107
108 /**
109 * ixgbe_setup_fc_generic - Set up flow control
110 * @hw: pointer to hardware structure
111 *
112 * Called at init time to set up flow control.
113 **/
ixgbe_setup_fc_generic(struct ixgbe_hw * hw)114 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
115 {
116 s32 ret_val = 0;
117 u32 reg = 0, reg_bp = 0;
118 u16 reg_cu = 0;
119 bool locked = false;
120
121 /*
122 * Validate the requested mode. Strict IEEE mode does not allow
123 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
124 */
125 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
126 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
127 return IXGBE_ERR_INVALID_LINK_SETTINGS;
128 }
129
130 /*
131 * 10gig parts do not have a word in the EEPROM to determine the
132 * default flow control setting, so we explicitly set it to full.
133 */
134 if (hw->fc.requested_mode == ixgbe_fc_default)
135 hw->fc.requested_mode = ixgbe_fc_full;
136
137 /*
138 * Set up the 1G and 10G flow control advertisement registers so the
139 * HW will be able to do fc autoneg once the cable is plugged in. If
140 * we link at 10G, the 1G advertisement is harmless and vice versa.
141 */
142 switch (hw->phy.media_type) {
143 case ixgbe_media_type_backplane:
144 /* some MAC's need RMW protection on AUTOC */
145 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
146 if (ret_val)
147 return ret_val;
148
149 fallthrough; /* only backplane uses autoc */
150 case ixgbe_media_type_fiber:
151 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
152
153 break;
154 case ixgbe_media_type_copper:
155 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
156 MDIO_MMD_AN, ®_cu);
157 break;
158 default:
159 break;
160 }
161
162 /*
163 * The possible values of fc.requested_mode are:
164 * 0: Flow control is completely disabled
165 * 1: Rx flow control is enabled (we can receive pause frames,
166 * but not send pause frames).
167 * 2: Tx flow control is enabled (we can send pause frames but
168 * we do not support receiving pause frames).
169 * 3: Both Rx and Tx flow control (symmetric) are enabled.
170 * other: Invalid.
171 */
172 switch (hw->fc.requested_mode) {
173 case ixgbe_fc_none:
174 /* Flow control completely disabled by software override. */
175 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
176 if (hw->phy.media_type == ixgbe_media_type_backplane)
177 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
178 IXGBE_AUTOC_ASM_PAUSE);
179 else if (hw->phy.media_type == ixgbe_media_type_copper)
180 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
181 break;
182 case ixgbe_fc_tx_pause:
183 /*
184 * Tx Flow control is enabled, and Rx Flow control is
185 * disabled by software override.
186 */
187 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
188 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
189 if (hw->phy.media_type == ixgbe_media_type_backplane) {
190 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
191 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
192 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
193 reg_cu |= IXGBE_TAF_ASM_PAUSE;
194 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
195 }
196 break;
197 case ixgbe_fc_rx_pause:
198 /*
199 * Rx Flow control is enabled and Tx Flow control is
200 * disabled by software override. Since there really
201 * isn't a way to advertise that we are capable of RX
202 * Pause ONLY, we will advertise that we support both
203 * symmetric and asymmetric Rx PAUSE, as such we fall
204 * through to the fc_full statement. Later, we will
205 * disable the adapter's ability to send PAUSE frames.
206 */
207 case ixgbe_fc_full:
208 /* Flow control (both Rx and Tx) is enabled by SW override. */
209 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
210 if (hw->phy.media_type == ixgbe_media_type_backplane)
211 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
212 IXGBE_AUTOC_ASM_PAUSE;
213 else if (hw->phy.media_type == ixgbe_media_type_copper)
214 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
215 break;
216 default:
217 hw_dbg(hw, "Flow control param set incorrectly\n");
218 return IXGBE_ERR_CONFIG;
219 }
220
221 if (hw->mac.type != ixgbe_mac_X540) {
222 /*
223 * Enable auto-negotiation between the MAC & PHY;
224 * the MAC will advertise clause 37 flow control.
225 */
226 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
227 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
228
229 /* Disable AN timeout */
230 if (hw->fc.strict_ieee)
231 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
232
233 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
234 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
235 }
236
237 /*
238 * AUTOC restart handles negotiation of 1G and 10G on backplane
239 * and copper. There is no need to set the PCS1GCTL register.
240 *
241 */
242 if (hw->phy.media_type == ixgbe_media_type_backplane) {
243 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
244 * LESM is on, likewise reset_pipeline requries the lock as
245 * it also writes AUTOC.
246 */
247 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
248 if (ret_val)
249 return ret_val;
250
251 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
252 ixgbe_device_supports_autoneg_fc(hw)) {
253 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
254 MDIO_MMD_AN, reg_cu);
255 }
256
257 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
258 return ret_val;
259 }
260
261 /**
262 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
263 * @hw: pointer to hardware structure
264 *
265 * Starts the hardware by filling the bus info structure and media type, clears
266 * all on chip counters, initializes receive address registers, multicast
267 * table, VLAN filter table, calls routine to set up link and flow control
268 * settings, and leaves transmit and receive units disabled and uninitialized
269 **/
ixgbe_start_hw_generic(struct ixgbe_hw * hw)270 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
271 {
272 s32 ret_val;
273 u32 ctrl_ext;
274 u16 device_caps;
275
276 /* Set the media type */
277 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
278
279 /* Identify the PHY */
280 hw->phy.ops.identify(hw);
281
282 /* Clear the VLAN filter table */
283 hw->mac.ops.clear_vfta(hw);
284
285 /* Clear statistics registers */
286 hw->mac.ops.clear_hw_cntrs(hw);
287
288 /* Set No Snoop Disable */
289 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
290 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
291 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
292 IXGBE_WRITE_FLUSH(hw);
293
294 /* Setup flow control if method for doing so */
295 if (hw->mac.ops.setup_fc) {
296 ret_val = hw->mac.ops.setup_fc(hw);
297 if (ret_val)
298 return ret_val;
299 }
300
301 /* Cashe bit indicating need for crosstalk fix */
302 switch (hw->mac.type) {
303 case ixgbe_mac_82599EB:
304 case ixgbe_mac_X550EM_x:
305 case ixgbe_mac_x550em_a:
306 hw->mac.ops.get_device_caps(hw, &device_caps);
307 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
308 hw->need_crosstalk_fix = false;
309 else
310 hw->need_crosstalk_fix = true;
311 break;
312 default:
313 hw->need_crosstalk_fix = false;
314 break;
315 }
316
317 /* Clear adapter stopped flag */
318 hw->adapter_stopped = false;
319
320 return 0;
321 }
322
323 /**
324 * ixgbe_start_hw_gen2 - Init sequence for common device family
325 * @hw: pointer to hw structure
326 *
327 * Performs the init sequence common to the second generation
328 * of 10 GbE devices.
329 * Devices in the second generation:
330 * 82599
331 * X540
332 **/
ixgbe_start_hw_gen2(struct ixgbe_hw * hw)333 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
334 {
335 u32 i;
336
337 /* Clear the rate limiters */
338 for (i = 0; i < hw->mac.max_tx_queues; i++) {
339 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
340 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
341 }
342 IXGBE_WRITE_FLUSH(hw);
343
344 return 0;
345 }
346
347 /**
348 * ixgbe_init_hw_generic - Generic hardware initialization
349 * @hw: pointer to hardware structure
350 *
351 * Initialize the hardware by resetting the hardware, filling the bus info
352 * structure and media type, clears all on chip counters, initializes receive
353 * address registers, multicast table, VLAN filter table, calls routine to set
354 * up link and flow control settings, and leaves transmit and receive units
355 * disabled and uninitialized
356 **/
ixgbe_init_hw_generic(struct ixgbe_hw * hw)357 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
358 {
359 s32 status;
360
361 /* Reset the hardware */
362 status = hw->mac.ops.reset_hw(hw);
363
364 if (status == 0) {
365 /* Start the HW */
366 status = hw->mac.ops.start_hw(hw);
367 }
368
369 /* Initialize the LED link active for LED blink support */
370 if (hw->mac.ops.init_led_link_act)
371 hw->mac.ops.init_led_link_act(hw);
372
373 return status;
374 }
375
376 /**
377 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
378 * @hw: pointer to hardware structure
379 *
380 * Clears all hardware statistics counters by reading them from the hardware
381 * Statistics counters are clear on read.
382 **/
ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw * hw)383 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
384 {
385 u16 i = 0;
386
387 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
388 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
389 IXGBE_READ_REG(hw, IXGBE_ERRBC);
390 IXGBE_READ_REG(hw, IXGBE_MSPDC);
391 for (i = 0; i < 8; i++)
392 IXGBE_READ_REG(hw, IXGBE_MPC(i));
393
394 IXGBE_READ_REG(hw, IXGBE_MLFC);
395 IXGBE_READ_REG(hw, IXGBE_MRFC);
396 IXGBE_READ_REG(hw, IXGBE_RLEC);
397 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
398 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
399 if (hw->mac.type >= ixgbe_mac_82599EB) {
400 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
401 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
402 } else {
403 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
404 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
405 }
406
407 for (i = 0; i < 8; i++) {
408 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
409 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
410 if (hw->mac.type >= ixgbe_mac_82599EB) {
411 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
412 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
413 } else {
414 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
415 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
416 }
417 }
418 if (hw->mac.type >= ixgbe_mac_82599EB)
419 for (i = 0; i < 8; i++)
420 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
421 IXGBE_READ_REG(hw, IXGBE_PRC64);
422 IXGBE_READ_REG(hw, IXGBE_PRC127);
423 IXGBE_READ_REG(hw, IXGBE_PRC255);
424 IXGBE_READ_REG(hw, IXGBE_PRC511);
425 IXGBE_READ_REG(hw, IXGBE_PRC1023);
426 IXGBE_READ_REG(hw, IXGBE_PRC1522);
427 IXGBE_READ_REG(hw, IXGBE_GPRC);
428 IXGBE_READ_REG(hw, IXGBE_BPRC);
429 IXGBE_READ_REG(hw, IXGBE_MPRC);
430 IXGBE_READ_REG(hw, IXGBE_GPTC);
431 IXGBE_READ_REG(hw, IXGBE_GORCL);
432 IXGBE_READ_REG(hw, IXGBE_GORCH);
433 IXGBE_READ_REG(hw, IXGBE_GOTCL);
434 IXGBE_READ_REG(hw, IXGBE_GOTCH);
435 if (hw->mac.type == ixgbe_mac_82598EB)
436 for (i = 0; i < 8; i++)
437 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
438 IXGBE_READ_REG(hw, IXGBE_RUC);
439 IXGBE_READ_REG(hw, IXGBE_RFC);
440 IXGBE_READ_REG(hw, IXGBE_ROC);
441 IXGBE_READ_REG(hw, IXGBE_RJC);
442 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
443 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
444 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
445 IXGBE_READ_REG(hw, IXGBE_TORL);
446 IXGBE_READ_REG(hw, IXGBE_TORH);
447 IXGBE_READ_REG(hw, IXGBE_TPR);
448 IXGBE_READ_REG(hw, IXGBE_TPT);
449 IXGBE_READ_REG(hw, IXGBE_PTC64);
450 IXGBE_READ_REG(hw, IXGBE_PTC127);
451 IXGBE_READ_REG(hw, IXGBE_PTC255);
452 IXGBE_READ_REG(hw, IXGBE_PTC511);
453 IXGBE_READ_REG(hw, IXGBE_PTC1023);
454 IXGBE_READ_REG(hw, IXGBE_PTC1522);
455 IXGBE_READ_REG(hw, IXGBE_MPTC);
456 IXGBE_READ_REG(hw, IXGBE_BPTC);
457 for (i = 0; i < 16; i++) {
458 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
459 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
460 if (hw->mac.type >= ixgbe_mac_82599EB) {
461 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
462 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
463 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
464 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
465 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
466 } else {
467 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
468 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
469 }
470 }
471
472 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
473 if (hw->phy.id == 0)
474 hw->phy.ops.identify(hw);
475 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i);
476 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i);
477 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i);
478 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i);
479 }
480
481 return 0;
482 }
483
484 /**
485 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
486 * @hw: pointer to hardware structure
487 * @pba_num: stores the part number string from the EEPROM
488 * @pba_num_size: part number string buffer length
489 *
490 * Reads the part number string from the EEPROM.
491 **/
ixgbe_read_pba_string_generic(struct ixgbe_hw * hw,u8 * pba_num,u32 pba_num_size)492 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
493 u32 pba_num_size)
494 {
495 s32 ret_val;
496 u16 data;
497 u16 pba_ptr;
498 u16 offset;
499 u16 length;
500
501 if (pba_num == NULL) {
502 hw_dbg(hw, "PBA string buffer was null\n");
503 return IXGBE_ERR_INVALID_ARGUMENT;
504 }
505
506 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
507 if (ret_val) {
508 hw_dbg(hw, "NVM Read Error\n");
509 return ret_val;
510 }
511
512 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
513 if (ret_val) {
514 hw_dbg(hw, "NVM Read Error\n");
515 return ret_val;
516 }
517
518 /*
519 * if data is not ptr guard the PBA must be in legacy format which
520 * means pba_ptr is actually our second data word for the PBA number
521 * and we can decode it into an ascii string
522 */
523 if (data != IXGBE_PBANUM_PTR_GUARD) {
524 hw_dbg(hw, "NVM PBA number is not stored as string\n");
525
526 /* we will need 11 characters to store the PBA */
527 if (pba_num_size < 11) {
528 hw_dbg(hw, "PBA string buffer too small\n");
529 return IXGBE_ERR_NO_SPACE;
530 }
531
532 /* extract hex string from data and pba_ptr */
533 pba_num[0] = (data >> 12) & 0xF;
534 pba_num[1] = (data >> 8) & 0xF;
535 pba_num[2] = (data >> 4) & 0xF;
536 pba_num[3] = data & 0xF;
537 pba_num[4] = (pba_ptr >> 12) & 0xF;
538 pba_num[5] = (pba_ptr >> 8) & 0xF;
539 pba_num[6] = '-';
540 pba_num[7] = 0;
541 pba_num[8] = (pba_ptr >> 4) & 0xF;
542 pba_num[9] = pba_ptr & 0xF;
543
544 /* put a null character on the end of our string */
545 pba_num[10] = '\0';
546
547 /* switch all the data but the '-' to hex char */
548 for (offset = 0; offset < 10; offset++) {
549 if (pba_num[offset] < 0xA)
550 pba_num[offset] += '0';
551 else if (pba_num[offset] < 0x10)
552 pba_num[offset] += 'A' - 0xA;
553 }
554
555 return 0;
556 }
557
558 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
559 if (ret_val) {
560 hw_dbg(hw, "NVM Read Error\n");
561 return ret_val;
562 }
563
564 if (length == 0xFFFF || length == 0) {
565 hw_dbg(hw, "NVM PBA number section invalid length\n");
566 return IXGBE_ERR_PBA_SECTION;
567 }
568
569 /* check if pba_num buffer is big enough */
570 if (pba_num_size < (((u32)length * 2) - 1)) {
571 hw_dbg(hw, "PBA string buffer too small\n");
572 return IXGBE_ERR_NO_SPACE;
573 }
574
575 /* trim pba length from start of string */
576 pba_ptr++;
577 length--;
578
579 for (offset = 0; offset < length; offset++) {
580 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
581 if (ret_val) {
582 hw_dbg(hw, "NVM Read Error\n");
583 return ret_val;
584 }
585 pba_num[offset * 2] = (u8)(data >> 8);
586 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
587 }
588 pba_num[offset * 2] = '\0';
589
590 return 0;
591 }
592
593 /**
594 * ixgbe_get_mac_addr_generic - Generic get MAC address
595 * @hw: pointer to hardware structure
596 * @mac_addr: Adapter MAC address
597 *
598 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
599 * A reset of the adapter must be performed prior to calling this function
600 * in order for the MAC address to have been loaded from the EEPROM into RAR0
601 **/
ixgbe_get_mac_addr_generic(struct ixgbe_hw * hw,u8 * mac_addr)602 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
603 {
604 u32 rar_high;
605 u32 rar_low;
606 u16 i;
607
608 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
609 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
610
611 for (i = 0; i < 4; i++)
612 mac_addr[i] = (u8)(rar_low >> (i*8));
613
614 for (i = 0; i < 2; i++)
615 mac_addr[i+4] = (u8)(rar_high >> (i*8));
616
617 return 0;
618 }
619
ixgbe_convert_bus_width(u16 link_status)620 enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status)
621 {
622 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
623 case IXGBE_PCI_LINK_WIDTH_1:
624 return ixgbe_bus_width_pcie_x1;
625 case IXGBE_PCI_LINK_WIDTH_2:
626 return ixgbe_bus_width_pcie_x2;
627 case IXGBE_PCI_LINK_WIDTH_4:
628 return ixgbe_bus_width_pcie_x4;
629 case IXGBE_PCI_LINK_WIDTH_8:
630 return ixgbe_bus_width_pcie_x8;
631 default:
632 return ixgbe_bus_width_unknown;
633 }
634 }
635
ixgbe_convert_bus_speed(u16 link_status)636 enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status)
637 {
638 switch (link_status & IXGBE_PCI_LINK_SPEED) {
639 case IXGBE_PCI_LINK_SPEED_2500:
640 return ixgbe_bus_speed_2500;
641 case IXGBE_PCI_LINK_SPEED_5000:
642 return ixgbe_bus_speed_5000;
643 case IXGBE_PCI_LINK_SPEED_8000:
644 return ixgbe_bus_speed_8000;
645 default:
646 return ixgbe_bus_speed_unknown;
647 }
648 }
649
650 /**
651 * ixgbe_get_bus_info_generic - Generic set PCI bus info
652 * @hw: pointer to hardware structure
653 *
654 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
655 **/
ixgbe_get_bus_info_generic(struct ixgbe_hw * hw)656 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
657 {
658 u16 link_status;
659
660 hw->bus.type = ixgbe_bus_type_pci_express;
661
662 /* Get the negotiated link width and speed from PCI config space */
663 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS);
664
665 hw->bus.width = ixgbe_convert_bus_width(link_status);
666 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
667
668 hw->mac.ops.set_lan_id(hw);
669
670 return 0;
671 }
672
673 /**
674 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
675 * @hw: pointer to the HW structure
676 *
677 * Determines the LAN function id by reading memory-mapped registers
678 * and swaps the port value if requested.
679 **/
ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw * hw)680 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
681 {
682 struct ixgbe_bus_info *bus = &hw->bus;
683 u16 ee_ctrl_4;
684 u32 reg;
685
686 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
687 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
688 bus->lan_id = bus->func;
689
690 /* check for a port swap */
691 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw));
692 if (reg & IXGBE_FACTPS_LFS)
693 bus->func ^= 0x1;
694
695 /* Get MAC instance from EEPROM for configuring CS4227 */
696 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
697 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
698 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>
699 IXGBE_EE_CTRL_4_INST_ID_SHIFT;
700 }
701 }
702
703 /**
704 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
705 * @hw: pointer to hardware structure
706 *
707 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
708 * disables transmit and receive units. The adapter_stopped flag is used by
709 * the shared code and drivers to determine if the adapter is in a stopped
710 * state and should not touch the hardware.
711 **/
ixgbe_stop_adapter_generic(struct ixgbe_hw * hw)712 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
713 {
714 u32 reg_val;
715 u16 i;
716
717 /*
718 * Set the adapter_stopped flag so other driver functions stop touching
719 * the hardware
720 */
721 hw->adapter_stopped = true;
722
723 /* Disable the receive unit */
724 hw->mac.ops.disable_rx(hw);
725
726 /* Clear interrupt mask to stop interrupts from being generated */
727 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
728
729 /* Clear any pending interrupts, flush previous writes */
730 IXGBE_READ_REG(hw, IXGBE_EICR);
731
732 /* Disable the transmit unit. Each queue must be disabled. */
733 for (i = 0; i < hw->mac.max_tx_queues; i++)
734 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
735
736 /* Disable the receive unit by stopping each queue */
737 for (i = 0; i < hw->mac.max_rx_queues; i++) {
738 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
739 reg_val &= ~IXGBE_RXDCTL_ENABLE;
740 reg_val |= IXGBE_RXDCTL_SWFLSH;
741 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
742 }
743
744 /* flush all queues disables */
745 IXGBE_WRITE_FLUSH(hw);
746 usleep_range(1000, 2000);
747
748 /*
749 * Prevent the PCI-E bus from hanging by disabling PCI-E primary
750 * access and verify no pending requests
751 */
752 return ixgbe_disable_pcie_primary(hw);
753 }
754
755 /**
756 * ixgbe_init_led_link_act_generic - Store the LED index link/activity.
757 * @hw: pointer to hardware structure
758 *
759 * Store the index for the link active LED. This will be used to support
760 * blinking the LED.
761 **/
ixgbe_init_led_link_act_generic(struct ixgbe_hw * hw)762 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw)
763 {
764 struct ixgbe_mac_info *mac = &hw->mac;
765 u32 led_reg, led_mode;
766 u16 i;
767
768 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
769
770 /* Get LED link active from the LEDCTL register */
771 for (i = 0; i < 4; i++) {
772 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i);
773
774 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) ==
775 IXGBE_LED_LINK_ACTIVE) {
776 mac->led_link_act = i;
777 return 0;
778 }
779 }
780
781 /* If LEDCTL register does not have the LED link active set, then use
782 * known MAC defaults.
783 */
784 switch (hw->mac.type) {
785 case ixgbe_mac_x550em_a:
786 mac->led_link_act = 0;
787 break;
788 case ixgbe_mac_X550EM_x:
789 mac->led_link_act = 1;
790 break;
791 default:
792 mac->led_link_act = 2;
793 }
794
795 return 0;
796 }
797
798 /**
799 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
800 * @hw: pointer to hardware structure
801 * @index: led number to turn on
802 **/
ixgbe_led_on_generic(struct ixgbe_hw * hw,u32 index)803 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
804 {
805 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
806
807 if (index > 3)
808 return IXGBE_ERR_PARAM;
809
810 /* To turn on the LED, set mode to ON. */
811 led_reg &= ~IXGBE_LED_MODE_MASK(index);
812 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
813 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
814 IXGBE_WRITE_FLUSH(hw);
815
816 return 0;
817 }
818
819 /**
820 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
821 * @hw: pointer to hardware structure
822 * @index: led number to turn off
823 **/
ixgbe_led_off_generic(struct ixgbe_hw * hw,u32 index)824 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
825 {
826 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
827
828 if (index > 3)
829 return IXGBE_ERR_PARAM;
830
831 /* To turn off the LED, set mode to OFF. */
832 led_reg &= ~IXGBE_LED_MODE_MASK(index);
833 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
834 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
835 IXGBE_WRITE_FLUSH(hw);
836
837 return 0;
838 }
839
840 /**
841 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
842 * @hw: pointer to hardware structure
843 *
844 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
845 * ixgbe_hw struct in order to set up EEPROM access.
846 **/
ixgbe_init_eeprom_params_generic(struct ixgbe_hw * hw)847 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
848 {
849 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
850 u32 eec;
851 u16 eeprom_size;
852
853 if (eeprom->type == ixgbe_eeprom_uninitialized) {
854 eeprom->type = ixgbe_eeprom_none;
855 /* Set default semaphore delay to 10ms which is a well
856 * tested value */
857 eeprom->semaphore_delay = 10;
858 /* Clear EEPROM page size, it will be initialized as needed */
859 eeprom->word_page_size = 0;
860
861 /*
862 * Check for EEPROM present first.
863 * If not present leave as none
864 */
865 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
866 if (eec & IXGBE_EEC_PRES) {
867 eeprom->type = ixgbe_eeprom_spi;
868
869 /*
870 * SPI EEPROM is assumed here. This code would need to
871 * change if a future EEPROM is not SPI.
872 */
873 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
874 IXGBE_EEC_SIZE_SHIFT);
875 eeprom->word_size = BIT(eeprom_size +
876 IXGBE_EEPROM_WORD_SIZE_SHIFT);
877 }
878
879 if (eec & IXGBE_EEC_ADDR_SIZE)
880 eeprom->address_bits = 16;
881 else
882 eeprom->address_bits = 8;
883 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n",
884 eeprom->type, eeprom->word_size, eeprom->address_bits);
885 }
886
887 return 0;
888 }
889
890 /**
891 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
892 * @hw: pointer to hardware structure
893 * @offset: offset within the EEPROM to write
894 * @words: number of words
895 * @data: 16 bit word(s) to write to EEPROM
896 *
897 * Reads 16 bit word(s) from EEPROM through bit-bang method
898 **/
ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)899 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
900 u16 words, u16 *data)
901 {
902 s32 status;
903 u16 i, count;
904
905 hw->eeprom.ops.init_params(hw);
906
907 if (words == 0)
908 return IXGBE_ERR_INVALID_ARGUMENT;
909
910 if (offset + words > hw->eeprom.word_size)
911 return IXGBE_ERR_EEPROM;
912
913 /*
914 * The EEPROM page size cannot be queried from the chip. We do lazy
915 * initialization. It is worth to do that when we write large buffer.
916 */
917 if ((hw->eeprom.word_page_size == 0) &&
918 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
919 ixgbe_detect_eeprom_page_size_generic(hw, offset);
920
921 /*
922 * We cannot hold synchronization semaphores for too long
923 * to avoid other entity starvation. However it is more efficient
924 * to read in bursts than synchronizing access for each word.
925 */
926 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
927 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
928 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
929 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
930 count, &data[i]);
931
932 if (status != 0)
933 break;
934 }
935
936 return status;
937 }
938
939 /**
940 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
941 * @hw: pointer to hardware structure
942 * @offset: offset within the EEPROM to be written to
943 * @words: number of word(s)
944 * @data: 16 bit word(s) to be written to the EEPROM
945 *
946 * If ixgbe_eeprom_update_checksum is not called after this function, the
947 * EEPROM will most likely contain an invalid checksum.
948 **/
ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)949 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
950 u16 words, u16 *data)
951 {
952 s32 status;
953 u16 word;
954 u16 page_size;
955 u16 i;
956 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
957
958 /* Prepare the EEPROM for writing */
959 status = ixgbe_acquire_eeprom(hw);
960 if (status)
961 return status;
962
963 if (ixgbe_ready_eeprom(hw) != 0) {
964 ixgbe_release_eeprom(hw);
965 return IXGBE_ERR_EEPROM;
966 }
967
968 for (i = 0; i < words; i++) {
969 ixgbe_standby_eeprom(hw);
970
971 /* Send the WRITE ENABLE command (8 bit opcode) */
972 ixgbe_shift_out_eeprom_bits(hw,
973 IXGBE_EEPROM_WREN_OPCODE_SPI,
974 IXGBE_EEPROM_OPCODE_BITS);
975
976 ixgbe_standby_eeprom(hw);
977
978 /* Some SPI eeproms use the 8th address bit embedded
979 * in the opcode
980 */
981 if ((hw->eeprom.address_bits == 8) &&
982 ((offset + i) >= 128))
983 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
984
985 /* Send the Write command (8-bit opcode + addr) */
986 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
987 IXGBE_EEPROM_OPCODE_BITS);
988 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
989 hw->eeprom.address_bits);
990
991 page_size = hw->eeprom.word_page_size;
992
993 /* Send the data in burst via SPI */
994 do {
995 word = data[i];
996 word = (word >> 8) | (word << 8);
997 ixgbe_shift_out_eeprom_bits(hw, word, 16);
998
999 if (page_size == 0)
1000 break;
1001
1002 /* do not wrap around page */
1003 if (((offset + i) & (page_size - 1)) ==
1004 (page_size - 1))
1005 break;
1006 } while (++i < words);
1007
1008 ixgbe_standby_eeprom(hw);
1009 usleep_range(10000, 20000);
1010 }
1011 /* Done with writing - release the EEPROM */
1012 ixgbe_release_eeprom(hw);
1013
1014 return 0;
1015 }
1016
1017 /**
1018 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1019 * @hw: pointer to hardware structure
1020 * @offset: offset within the EEPROM to be written to
1021 * @data: 16 bit word to be written to the EEPROM
1022 *
1023 * If ixgbe_eeprom_update_checksum is not called after this function, the
1024 * EEPROM will most likely contain an invalid checksum.
1025 **/
ixgbe_write_eeprom_generic(struct ixgbe_hw * hw,u16 offset,u16 data)1026 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1027 {
1028 hw->eeprom.ops.init_params(hw);
1029
1030 if (offset >= hw->eeprom.word_size)
1031 return IXGBE_ERR_EEPROM;
1032
1033 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1034 }
1035
1036 /**
1037 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1038 * @hw: pointer to hardware structure
1039 * @offset: offset within the EEPROM to be read
1040 * @words: number of word(s)
1041 * @data: read 16 bit words(s) from EEPROM
1042 *
1043 * Reads 16 bit word(s) from EEPROM through bit-bang method
1044 **/
ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1045 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1046 u16 words, u16 *data)
1047 {
1048 s32 status;
1049 u16 i, count;
1050
1051 hw->eeprom.ops.init_params(hw);
1052
1053 if (words == 0)
1054 return IXGBE_ERR_INVALID_ARGUMENT;
1055
1056 if (offset + words > hw->eeprom.word_size)
1057 return IXGBE_ERR_EEPROM;
1058
1059 /*
1060 * We cannot hold synchronization semaphores for too long
1061 * to avoid other entity starvation. However it is more efficient
1062 * to read in bursts than synchronizing access for each word.
1063 */
1064 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1065 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1066 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1067
1068 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1069 count, &data[i]);
1070
1071 if (status)
1072 return status;
1073 }
1074
1075 return 0;
1076 }
1077
1078 /**
1079 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1080 * @hw: pointer to hardware structure
1081 * @offset: offset within the EEPROM to be read
1082 * @words: number of word(s)
1083 * @data: read 16 bit word(s) from EEPROM
1084 *
1085 * Reads 16 bit word(s) from EEPROM through bit-bang method
1086 **/
ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1087 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1088 u16 words, u16 *data)
1089 {
1090 s32 status;
1091 u16 word_in;
1092 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1093 u16 i;
1094
1095 /* Prepare the EEPROM for reading */
1096 status = ixgbe_acquire_eeprom(hw);
1097 if (status)
1098 return status;
1099
1100 if (ixgbe_ready_eeprom(hw) != 0) {
1101 ixgbe_release_eeprom(hw);
1102 return IXGBE_ERR_EEPROM;
1103 }
1104
1105 for (i = 0; i < words; i++) {
1106 ixgbe_standby_eeprom(hw);
1107 /* Some SPI eeproms use the 8th address bit embedded
1108 * in the opcode
1109 */
1110 if ((hw->eeprom.address_bits == 8) &&
1111 ((offset + i) >= 128))
1112 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1113
1114 /* Send the READ command (opcode + addr) */
1115 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1116 IXGBE_EEPROM_OPCODE_BITS);
1117 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1118 hw->eeprom.address_bits);
1119
1120 /* Read the data. */
1121 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1122 data[i] = (word_in >> 8) | (word_in << 8);
1123 }
1124
1125 /* End this read operation */
1126 ixgbe_release_eeprom(hw);
1127
1128 return 0;
1129 }
1130
1131 /**
1132 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1133 * @hw: pointer to hardware structure
1134 * @offset: offset within the EEPROM to be read
1135 * @data: read 16 bit value from EEPROM
1136 *
1137 * Reads 16 bit value from EEPROM through bit-bang method
1138 **/
ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw * hw,u16 offset,u16 * data)1139 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1140 u16 *data)
1141 {
1142 hw->eeprom.ops.init_params(hw);
1143
1144 if (offset >= hw->eeprom.word_size)
1145 return IXGBE_ERR_EEPROM;
1146
1147 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1148 }
1149
1150 /**
1151 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1152 * @hw: pointer to hardware structure
1153 * @offset: offset of word in the EEPROM to read
1154 * @words: number of word(s)
1155 * @data: 16 bit word(s) from the EEPROM
1156 *
1157 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1158 **/
ixgbe_read_eerd_buffer_generic(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1159 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1160 u16 words, u16 *data)
1161 {
1162 u32 eerd;
1163 s32 status;
1164 u32 i;
1165
1166 hw->eeprom.ops.init_params(hw);
1167
1168 if (words == 0)
1169 return IXGBE_ERR_INVALID_ARGUMENT;
1170
1171 if (offset >= hw->eeprom.word_size)
1172 return IXGBE_ERR_EEPROM;
1173
1174 for (i = 0; i < words; i++) {
1175 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1176 IXGBE_EEPROM_RW_REG_START;
1177
1178 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1179 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1180
1181 if (status == 0) {
1182 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1183 IXGBE_EEPROM_RW_REG_DATA);
1184 } else {
1185 hw_dbg(hw, "Eeprom read timed out\n");
1186 return status;
1187 }
1188 }
1189
1190 return 0;
1191 }
1192
1193 /**
1194 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1195 * @hw: pointer to hardware structure
1196 * @offset: offset within the EEPROM to be used as a scratch pad
1197 *
1198 * Discover EEPROM page size by writing marching data at given offset.
1199 * This function is called only when we are writing a new large buffer
1200 * at given offset so the data would be overwritten anyway.
1201 **/
ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw * hw,u16 offset)1202 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1203 u16 offset)
1204 {
1205 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1206 s32 status;
1207 u16 i;
1208
1209 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1210 data[i] = i;
1211
1212 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1213 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1214 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1215 hw->eeprom.word_page_size = 0;
1216 if (status)
1217 return status;
1218
1219 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1220 if (status)
1221 return status;
1222
1223 /*
1224 * When writing in burst more than the actual page size
1225 * EEPROM address wraps around current page.
1226 */
1227 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1228
1229 hw_dbg(hw, "Detected EEPROM page size = %d words.\n",
1230 hw->eeprom.word_page_size);
1231 return 0;
1232 }
1233
1234 /**
1235 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1236 * @hw: pointer to hardware structure
1237 * @offset: offset of word in the EEPROM to read
1238 * @data: word read from the EEPROM
1239 *
1240 * Reads a 16 bit word from the EEPROM using the EERD register.
1241 **/
ixgbe_read_eerd_generic(struct ixgbe_hw * hw,u16 offset,u16 * data)1242 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1243 {
1244 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1245 }
1246
1247 /**
1248 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1249 * @hw: pointer to hardware structure
1250 * @offset: offset of word in the EEPROM to write
1251 * @words: number of words
1252 * @data: word(s) write to the EEPROM
1253 *
1254 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1255 **/
ixgbe_write_eewr_buffer_generic(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1256 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1257 u16 words, u16 *data)
1258 {
1259 u32 eewr;
1260 s32 status;
1261 u16 i;
1262
1263 hw->eeprom.ops.init_params(hw);
1264
1265 if (words == 0)
1266 return IXGBE_ERR_INVALID_ARGUMENT;
1267
1268 if (offset >= hw->eeprom.word_size)
1269 return IXGBE_ERR_EEPROM;
1270
1271 for (i = 0; i < words; i++) {
1272 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1273 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1274 IXGBE_EEPROM_RW_REG_START;
1275
1276 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1277 if (status) {
1278 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1279 return status;
1280 }
1281
1282 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1283
1284 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1285 if (status) {
1286 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1287 return status;
1288 }
1289 }
1290
1291 return 0;
1292 }
1293
1294 /**
1295 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1296 * @hw: pointer to hardware structure
1297 * @offset: offset of word in the EEPROM to write
1298 * @data: word write to the EEPROM
1299 *
1300 * Write a 16 bit word to the EEPROM using the EEWR register.
1301 **/
ixgbe_write_eewr_generic(struct ixgbe_hw * hw,u16 offset,u16 data)1302 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1303 {
1304 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1305 }
1306
1307 /**
1308 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1309 * @hw: pointer to hardware structure
1310 * @ee_reg: EEPROM flag for polling
1311 *
1312 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1313 * read or write is done respectively.
1314 **/
ixgbe_poll_eerd_eewr_done(struct ixgbe_hw * hw,u32 ee_reg)1315 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1316 {
1317 u32 i;
1318 u32 reg;
1319
1320 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1321 if (ee_reg == IXGBE_NVM_POLL_READ)
1322 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1323 else
1324 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1325
1326 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1327 return 0;
1328 }
1329 udelay(5);
1330 }
1331 return IXGBE_ERR_EEPROM;
1332 }
1333
1334 /**
1335 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1336 * @hw: pointer to hardware structure
1337 *
1338 * Prepares EEPROM for access using bit-bang method. This function should
1339 * be called before issuing a command to the EEPROM.
1340 **/
ixgbe_acquire_eeprom(struct ixgbe_hw * hw)1341 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1342 {
1343 u32 eec;
1344 u32 i;
1345
1346 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
1347 return IXGBE_ERR_SWFW_SYNC;
1348
1349 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
1350
1351 /* Request EEPROM Access */
1352 eec |= IXGBE_EEC_REQ;
1353 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1354
1355 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1356 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
1357 if (eec & IXGBE_EEC_GNT)
1358 break;
1359 udelay(5);
1360 }
1361
1362 /* Release if grant not acquired */
1363 if (!(eec & IXGBE_EEC_GNT)) {
1364 eec &= ~IXGBE_EEC_REQ;
1365 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1366 hw_dbg(hw, "Could not acquire EEPROM grant\n");
1367
1368 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1369 return IXGBE_ERR_EEPROM;
1370 }
1371
1372 /* Setup EEPROM for Read/Write */
1373 /* Clear CS and SK */
1374 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1375 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1376 IXGBE_WRITE_FLUSH(hw);
1377 udelay(1);
1378 return 0;
1379 }
1380
1381 /**
1382 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1383 * @hw: pointer to hardware structure
1384 *
1385 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1386 **/
ixgbe_get_eeprom_semaphore(struct ixgbe_hw * hw)1387 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1388 {
1389 u32 timeout = 2000;
1390 u32 i;
1391 u32 swsm;
1392
1393 /* Get SMBI software semaphore between device drivers first */
1394 for (i = 0; i < timeout; i++) {
1395 /*
1396 * If the SMBI bit is 0 when we read it, then the bit will be
1397 * set and we have the semaphore
1398 */
1399 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
1400 if (!(swsm & IXGBE_SWSM_SMBI))
1401 break;
1402 usleep_range(50, 100);
1403 }
1404
1405 if (i == timeout) {
1406 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n");
1407 /* this release is particularly important because our attempts
1408 * above to get the semaphore may have succeeded, and if there
1409 * was a timeout, we should unconditionally clear the semaphore
1410 * bits to free the driver to make progress
1411 */
1412 ixgbe_release_eeprom_semaphore(hw);
1413
1414 usleep_range(50, 100);
1415 /* one last try
1416 * If the SMBI bit is 0 when we read it, then the bit will be
1417 * set and we have the semaphore
1418 */
1419 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
1420 if (swsm & IXGBE_SWSM_SMBI) {
1421 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n");
1422 return IXGBE_ERR_EEPROM;
1423 }
1424 }
1425
1426 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1427 for (i = 0; i < timeout; i++) {
1428 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
1429
1430 /* Set the SW EEPROM semaphore bit to request access */
1431 swsm |= IXGBE_SWSM_SWESMBI;
1432 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
1433
1434 /* If we set the bit successfully then we got the
1435 * semaphore.
1436 */
1437 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
1438 if (swsm & IXGBE_SWSM_SWESMBI)
1439 break;
1440
1441 usleep_range(50, 100);
1442 }
1443
1444 /* Release semaphores and return error if SW EEPROM semaphore
1445 * was not granted because we don't have access to the EEPROM
1446 */
1447 if (i >= timeout) {
1448 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n");
1449 ixgbe_release_eeprom_semaphore(hw);
1450 return IXGBE_ERR_EEPROM;
1451 }
1452
1453 return 0;
1454 }
1455
1456 /**
1457 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1458 * @hw: pointer to hardware structure
1459 *
1460 * This function clears hardware semaphore bits.
1461 **/
ixgbe_release_eeprom_semaphore(struct ixgbe_hw * hw)1462 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1463 {
1464 u32 swsm;
1465
1466 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
1467
1468 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1469 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1470 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
1471 IXGBE_WRITE_FLUSH(hw);
1472 }
1473
1474 /**
1475 * ixgbe_ready_eeprom - Polls for EEPROM ready
1476 * @hw: pointer to hardware structure
1477 **/
ixgbe_ready_eeprom(struct ixgbe_hw * hw)1478 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1479 {
1480 u16 i;
1481 u8 spi_stat_reg;
1482
1483 /*
1484 * Read "Status Register" repeatedly until the LSB is cleared. The
1485 * EEPROM will signal that the command has been completed by clearing
1486 * bit 0 of the internal status register. If it's not cleared within
1487 * 5 milliseconds, then error out.
1488 */
1489 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1490 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1491 IXGBE_EEPROM_OPCODE_BITS);
1492 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1493 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1494 break;
1495
1496 udelay(5);
1497 ixgbe_standby_eeprom(hw);
1498 }
1499
1500 /*
1501 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1502 * devices (and only 0-5mSec on 5V devices)
1503 */
1504 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1505 hw_dbg(hw, "SPI EEPROM Status error\n");
1506 return IXGBE_ERR_EEPROM;
1507 }
1508
1509 return 0;
1510 }
1511
1512 /**
1513 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1514 * @hw: pointer to hardware structure
1515 **/
ixgbe_standby_eeprom(struct ixgbe_hw * hw)1516 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1517 {
1518 u32 eec;
1519
1520 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
1521
1522 /* Toggle CS to flush commands */
1523 eec |= IXGBE_EEC_CS;
1524 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1525 IXGBE_WRITE_FLUSH(hw);
1526 udelay(1);
1527 eec &= ~IXGBE_EEC_CS;
1528 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1529 IXGBE_WRITE_FLUSH(hw);
1530 udelay(1);
1531 }
1532
1533 /**
1534 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1535 * @hw: pointer to hardware structure
1536 * @data: data to send to the EEPROM
1537 * @count: number of bits to shift out
1538 **/
ixgbe_shift_out_eeprom_bits(struct ixgbe_hw * hw,u16 data,u16 count)1539 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1540 u16 count)
1541 {
1542 u32 eec;
1543 u32 mask;
1544 u32 i;
1545
1546 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
1547
1548 /*
1549 * Mask is used to shift "count" bits of "data" out to the EEPROM
1550 * one bit at a time. Determine the starting bit based on count
1551 */
1552 mask = BIT(count - 1);
1553
1554 for (i = 0; i < count; i++) {
1555 /*
1556 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1557 * "1", and then raising and then lowering the clock (the SK
1558 * bit controls the clock input to the EEPROM). A "0" is
1559 * shifted out to the EEPROM by setting "DI" to "0" and then
1560 * raising and then lowering the clock.
1561 */
1562 if (data & mask)
1563 eec |= IXGBE_EEC_DI;
1564 else
1565 eec &= ~IXGBE_EEC_DI;
1566
1567 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1568 IXGBE_WRITE_FLUSH(hw);
1569
1570 udelay(1);
1571
1572 ixgbe_raise_eeprom_clk(hw, &eec);
1573 ixgbe_lower_eeprom_clk(hw, &eec);
1574
1575 /*
1576 * Shift mask to signify next bit of data to shift in to the
1577 * EEPROM
1578 */
1579 mask = mask >> 1;
1580 }
1581
1582 /* We leave the "DI" bit set to "0" when we leave this routine. */
1583 eec &= ~IXGBE_EEC_DI;
1584 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1585 IXGBE_WRITE_FLUSH(hw);
1586 }
1587
1588 /**
1589 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1590 * @hw: pointer to hardware structure
1591 * @count: number of bits to shift
1592 **/
ixgbe_shift_in_eeprom_bits(struct ixgbe_hw * hw,u16 count)1593 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1594 {
1595 u32 eec;
1596 u32 i;
1597 u16 data = 0;
1598
1599 /*
1600 * In order to read a register from the EEPROM, we need to shift
1601 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1602 * the clock input to the EEPROM (setting the SK bit), and then reading
1603 * the value of the "DO" bit. During this "shifting in" process the
1604 * "DI" bit should always be clear.
1605 */
1606 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
1607
1608 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1609
1610 for (i = 0; i < count; i++) {
1611 data = data << 1;
1612 ixgbe_raise_eeprom_clk(hw, &eec);
1613
1614 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
1615
1616 eec &= ~(IXGBE_EEC_DI);
1617 if (eec & IXGBE_EEC_DO)
1618 data |= 1;
1619
1620 ixgbe_lower_eeprom_clk(hw, &eec);
1621 }
1622
1623 return data;
1624 }
1625
1626 /**
1627 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1628 * @hw: pointer to hardware structure
1629 * @eec: EEC register's current value
1630 **/
ixgbe_raise_eeprom_clk(struct ixgbe_hw * hw,u32 * eec)1631 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1632 {
1633 /*
1634 * Raise the clock input to the EEPROM
1635 * (setting the SK bit), then delay
1636 */
1637 *eec = *eec | IXGBE_EEC_SK;
1638 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec);
1639 IXGBE_WRITE_FLUSH(hw);
1640 udelay(1);
1641 }
1642
1643 /**
1644 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1645 * @hw: pointer to hardware structure
1646 * @eec: EEC's current value
1647 **/
ixgbe_lower_eeprom_clk(struct ixgbe_hw * hw,u32 * eec)1648 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1649 {
1650 /*
1651 * Lower the clock input to the EEPROM (clearing the SK bit), then
1652 * delay
1653 */
1654 *eec = *eec & ~IXGBE_EEC_SK;
1655 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec);
1656 IXGBE_WRITE_FLUSH(hw);
1657 udelay(1);
1658 }
1659
1660 /**
1661 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1662 * @hw: pointer to hardware structure
1663 **/
ixgbe_release_eeprom(struct ixgbe_hw * hw)1664 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1665 {
1666 u32 eec;
1667
1668 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
1669
1670 eec |= IXGBE_EEC_CS; /* Pull CS high */
1671 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1672
1673 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1674 IXGBE_WRITE_FLUSH(hw);
1675
1676 udelay(1);
1677
1678 /* Stop requesting EEPROM access */
1679 eec &= ~IXGBE_EEC_REQ;
1680 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1681
1682 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1683
1684 /*
1685 * Delay before attempt to obtain semaphore again to allow FW
1686 * access. semaphore_delay is in ms we need us for usleep_range
1687 */
1688 usleep_range(hw->eeprom.semaphore_delay * 1000,
1689 hw->eeprom.semaphore_delay * 2000);
1690 }
1691
1692 /**
1693 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1694 * @hw: pointer to hardware structure
1695 **/
ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw * hw)1696 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
1697 {
1698 u16 i;
1699 u16 j;
1700 u16 checksum = 0;
1701 u16 length = 0;
1702 u16 pointer = 0;
1703 u16 word = 0;
1704
1705 /* Include 0x0-0x3F in the checksum */
1706 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1707 if (hw->eeprom.ops.read(hw, i, &word)) {
1708 hw_dbg(hw, "EEPROM read failed\n");
1709 break;
1710 }
1711 checksum += word;
1712 }
1713
1714 /* Include all data from pointers except for the fw pointer */
1715 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1716 if (hw->eeprom.ops.read(hw, i, &pointer)) {
1717 hw_dbg(hw, "EEPROM read failed\n");
1718 return IXGBE_ERR_EEPROM;
1719 }
1720
1721 /* If the pointer seems invalid */
1722 if (pointer == 0xFFFF || pointer == 0)
1723 continue;
1724
1725 if (hw->eeprom.ops.read(hw, pointer, &length)) {
1726 hw_dbg(hw, "EEPROM read failed\n");
1727 return IXGBE_ERR_EEPROM;
1728 }
1729
1730 if (length == 0xFFFF || length == 0)
1731 continue;
1732
1733 for (j = pointer + 1; j <= pointer + length; j++) {
1734 if (hw->eeprom.ops.read(hw, j, &word)) {
1735 hw_dbg(hw, "EEPROM read failed\n");
1736 return IXGBE_ERR_EEPROM;
1737 }
1738 checksum += word;
1739 }
1740 }
1741
1742 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1743
1744 return (s32)checksum;
1745 }
1746
1747 /**
1748 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1749 * @hw: pointer to hardware structure
1750 * @checksum_val: calculated checksum
1751 *
1752 * Performs checksum calculation and validates the EEPROM checksum. If the
1753 * caller does not need checksum_val, the value can be NULL.
1754 **/
ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw * hw,u16 * checksum_val)1755 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1756 u16 *checksum_val)
1757 {
1758 s32 status;
1759 u16 checksum;
1760 u16 read_checksum = 0;
1761
1762 /*
1763 * Read the first word from the EEPROM. If this times out or fails, do
1764 * not continue or we could be in for a very long wait while every
1765 * EEPROM read fails
1766 */
1767 status = hw->eeprom.ops.read(hw, 0, &checksum);
1768 if (status) {
1769 hw_dbg(hw, "EEPROM read failed\n");
1770 return status;
1771 }
1772
1773 status = hw->eeprom.ops.calc_checksum(hw);
1774 if (status < 0)
1775 return status;
1776
1777 checksum = (u16)(status & 0xffff);
1778
1779 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1780 if (status) {
1781 hw_dbg(hw, "EEPROM read failed\n");
1782 return status;
1783 }
1784
1785 /* Verify read checksum from EEPROM is the same as
1786 * calculated checksum
1787 */
1788 if (read_checksum != checksum)
1789 status = IXGBE_ERR_EEPROM_CHECKSUM;
1790
1791 /* If the user cares, return the calculated checksum */
1792 if (checksum_val)
1793 *checksum_val = checksum;
1794
1795 return status;
1796 }
1797
1798 /**
1799 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1800 * @hw: pointer to hardware structure
1801 **/
ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw * hw)1802 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1803 {
1804 s32 status;
1805 u16 checksum;
1806
1807 /*
1808 * Read the first word from the EEPROM. If this times out or fails, do
1809 * not continue or we could be in for a very long wait while every
1810 * EEPROM read fails
1811 */
1812 status = hw->eeprom.ops.read(hw, 0, &checksum);
1813 if (status) {
1814 hw_dbg(hw, "EEPROM read failed\n");
1815 return status;
1816 }
1817
1818 status = hw->eeprom.ops.calc_checksum(hw);
1819 if (status < 0)
1820 return status;
1821
1822 checksum = (u16)(status & 0xffff);
1823
1824 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
1825
1826 return status;
1827 }
1828
1829 /**
1830 * ixgbe_set_rar_generic - Set Rx address register
1831 * @hw: pointer to hardware structure
1832 * @index: Receive address register to write
1833 * @addr: Address to put into receive address register
1834 * @vmdq: VMDq "set" or "pool" index
1835 * @enable_addr: set flag that address is active
1836 *
1837 * Puts an ethernet address into a receive address register.
1838 **/
ixgbe_set_rar_generic(struct ixgbe_hw * hw,u32 index,u8 * addr,u32 vmdq,u32 enable_addr)1839 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1840 u32 enable_addr)
1841 {
1842 u32 rar_low, rar_high;
1843 u32 rar_entries = hw->mac.num_rar_entries;
1844
1845 /* Make sure we are using a valid rar index range */
1846 if (index >= rar_entries) {
1847 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1848 return IXGBE_ERR_INVALID_ARGUMENT;
1849 }
1850
1851 /* setup VMDq pool selection before this RAR gets enabled */
1852 hw->mac.ops.set_vmdq(hw, index, vmdq);
1853
1854 /*
1855 * HW expects these in little endian so we reverse the byte
1856 * order from network order (big endian) to little endian
1857 */
1858 rar_low = ((u32)addr[0] |
1859 ((u32)addr[1] << 8) |
1860 ((u32)addr[2] << 16) |
1861 ((u32)addr[3] << 24));
1862 /*
1863 * Some parts put the VMDq setting in the extra RAH bits,
1864 * so save everything except the lower 16 bits that hold part
1865 * of the address and the address valid bit.
1866 */
1867 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1868 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1869 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
1870
1871 if (enable_addr != 0)
1872 rar_high |= IXGBE_RAH_AV;
1873
1874 /* Record lower 32 bits of MAC address and then make
1875 * sure that write is flushed to hardware before writing
1876 * the upper 16 bits and setting the valid bit.
1877 */
1878 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1879 IXGBE_WRITE_FLUSH(hw);
1880 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1881
1882 return 0;
1883 }
1884
1885 /**
1886 * ixgbe_clear_rar_generic - Remove Rx address register
1887 * @hw: pointer to hardware structure
1888 * @index: Receive address register to write
1889 *
1890 * Clears an ethernet address from a receive address register.
1891 **/
ixgbe_clear_rar_generic(struct ixgbe_hw * hw,u32 index)1892 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1893 {
1894 u32 rar_high;
1895 u32 rar_entries = hw->mac.num_rar_entries;
1896
1897 /* Make sure we are using a valid rar index range */
1898 if (index >= rar_entries) {
1899 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1900 return IXGBE_ERR_INVALID_ARGUMENT;
1901 }
1902
1903 /*
1904 * Some parts put the VMDq setting in the extra RAH bits,
1905 * so save everything except the lower 16 bits that hold part
1906 * of the address and the address valid bit.
1907 */
1908 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1909 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1910
1911 /* Clear the address valid bit and upper 16 bits of the address
1912 * before clearing the lower bits. This way we aren't updating
1913 * a live filter.
1914 */
1915 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1916 IXGBE_WRITE_FLUSH(hw);
1917 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1918
1919 /* clear VMDq pool/queue selection for this RAR */
1920 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
1921
1922 return 0;
1923 }
1924
1925 /**
1926 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1927 * @hw: pointer to hardware structure
1928 *
1929 * Places the MAC address in receive address register 0 and clears the rest
1930 * of the receive address registers. Clears the multicast table. Assumes
1931 * the receiver is in reset when the routine is called.
1932 **/
ixgbe_init_rx_addrs_generic(struct ixgbe_hw * hw)1933 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1934 {
1935 u32 i;
1936 u32 rar_entries = hw->mac.num_rar_entries;
1937
1938 /*
1939 * If the current mac address is valid, assume it is a software override
1940 * to the permanent address.
1941 * Otherwise, use the permanent address from the eeprom.
1942 */
1943 if (!is_valid_ether_addr(hw->mac.addr)) {
1944 /* Get the MAC address from the RAR0 for later reference */
1945 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
1946
1947 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
1948 } else {
1949 /* Setup the receive address. */
1950 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
1951 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
1952
1953 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1954 }
1955
1956 /* clear VMDq pool/queue selection for RAR 0 */
1957 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
1958
1959 hw->addr_ctrl.overflow_promisc = 0;
1960
1961 hw->addr_ctrl.rar_used_count = 1;
1962
1963 /* Zero out the other receive addresses. */
1964 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
1965 for (i = 1; i < rar_entries; i++) {
1966 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1967 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1968 }
1969
1970 /* Clear the MTA */
1971 hw->addr_ctrl.mta_in_use = 0;
1972 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1973
1974 hw_dbg(hw, " Clearing MTA\n");
1975 for (i = 0; i < hw->mac.mcft_size; i++)
1976 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1977
1978 if (hw->mac.ops.init_uta_tables)
1979 hw->mac.ops.init_uta_tables(hw);
1980
1981 return 0;
1982 }
1983
1984 /**
1985 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1986 * @hw: pointer to hardware structure
1987 * @mc_addr: the multicast address
1988 *
1989 * Extracts the 12 bits, from a multicast address, to determine which
1990 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1991 * incoming rx multicast addresses, to determine the bit-vector to check in
1992 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1993 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1994 * to mc_filter_type.
1995 **/
ixgbe_mta_vector(struct ixgbe_hw * hw,u8 * mc_addr)1996 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1997 {
1998 u32 vector = 0;
1999
2000 switch (hw->mac.mc_filter_type) {
2001 case 0: /* use bits [47:36] of the address */
2002 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2003 break;
2004 case 1: /* use bits [46:35] of the address */
2005 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2006 break;
2007 case 2: /* use bits [45:34] of the address */
2008 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2009 break;
2010 case 3: /* use bits [43:32] of the address */
2011 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2012 break;
2013 default: /* Invalid mc_filter_type */
2014 hw_dbg(hw, "MC filter type param set incorrectly\n");
2015 break;
2016 }
2017
2018 /* vector can only be 12-bits or boundary will be exceeded */
2019 vector &= 0xFFF;
2020 return vector;
2021 }
2022
2023 /**
2024 * ixgbe_set_mta - Set bit-vector in multicast table
2025 * @hw: pointer to hardware structure
2026 * @mc_addr: Multicast address
2027 *
2028 * Sets the bit-vector in the multicast table.
2029 **/
ixgbe_set_mta(struct ixgbe_hw * hw,u8 * mc_addr)2030 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2031 {
2032 u32 vector;
2033 u32 vector_bit;
2034 u32 vector_reg;
2035
2036 hw->addr_ctrl.mta_in_use++;
2037
2038 vector = ixgbe_mta_vector(hw, mc_addr);
2039 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
2040
2041 /*
2042 * The MTA is a register array of 128 32-bit registers. It is treated
2043 * like an array of 4096 bits. We want to set bit
2044 * BitArray[vector_value]. So we figure out what register the bit is
2045 * in, read it, OR in the new bit, then write back the new value. The
2046 * register is determined by the upper 7 bits of the vector value and
2047 * the bit within that register are determined by the lower 5 bits of
2048 * the value.
2049 */
2050 vector_reg = (vector >> 5) & 0x7F;
2051 vector_bit = vector & 0x1F;
2052 hw->mac.mta_shadow[vector_reg] |= BIT(vector_bit);
2053 }
2054
2055 /**
2056 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2057 * @hw: pointer to hardware structure
2058 * @netdev: pointer to net device structure
2059 *
2060 * The given list replaces any existing list. Clears the MC addrs from receive
2061 * address registers and the multicast table. Uses unused receive address
2062 * registers for the first multicast addresses, and hashes the rest into the
2063 * multicast table.
2064 **/
ixgbe_update_mc_addr_list_generic(struct ixgbe_hw * hw,struct net_device * netdev)2065 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
2066 struct net_device *netdev)
2067 {
2068 struct netdev_hw_addr *ha;
2069 u32 i;
2070
2071 /*
2072 * Set the new number of MC addresses that we are being requested to
2073 * use.
2074 */
2075 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
2076 hw->addr_ctrl.mta_in_use = 0;
2077
2078 /* Clear mta_shadow */
2079 hw_dbg(hw, " Clearing MTA\n");
2080 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2081
2082 /* Update mta shadow */
2083 netdev_for_each_mc_addr(ha, netdev) {
2084 hw_dbg(hw, " Adding the multicast addresses:\n");
2085 ixgbe_set_mta(hw, ha->addr);
2086 }
2087
2088 /* Enable mta */
2089 for (i = 0; i < hw->mac.mcft_size; i++)
2090 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2091 hw->mac.mta_shadow[i]);
2092
2093 if (hw->addr_ctrl.mta_in_use > 0)
2094 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2095 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2096
2097 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
2098 return 0;
2099 }
2100
2101 /**
2102 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2103 * @hw: pointer to hardware structure
2104 *
2105 * Enables multicast address in RAR and the use of the multicast hash table.
2106 **/
ixgbe_enable_mc_generic(struct ixgbe_hw * hw)2107 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2108 {
2109 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2110
2111 if (a->mta_in_use > 0)
2112 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2113 hw->mac.mc_filter_type);
2114
2115 return 0;
2116 }
2117
2118 /**
2119 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2120 * @hw: pointer to hardware structure
2121 *
2122 * Disables multicast address in RAR and the use of the multicast hash table.
2123 **/
ixgbe_disable_mc_generic(struct ixgbe_hw * hw)2124 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2125 {
2126 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2127
2128 if (a->mta_in_use > 0)
2129 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2130
2131 return 0;
2132 }
2133
2134 /**
2135 * ixgbe_fc_enable_generic - Enable flow control
2136 * @hw: pointer to hardware structure
2137 *
2138 * Enable flow control according to the current settings.
2139 **/
ixgbe_fc_enable_generic(struct ixgbe_hw * hw)2140 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2141 {
2142 u32 mflcn_reg, fccfg_reg;
2143 u32 reg;
2144 u32 fcrtl, fcrth;
2145 int i;
2146
2147 /* Validate the water mark configuration. */
2148 if (!hw->fc.pause_time)
2149 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2150
2151 /* Low water mark of zero causes XOFF floods */
2152 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2153 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2154 hw->fc.high_water[i]) {
2155 if (!hw->fc.low_water[i] ||
2156 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2157 hw_dbg(hw, "Invalid water mark configuration\n");
2158 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2159 }
2160 }
2161 }
2162
2163 /* Negotiate the fc mode to use */
2164 hw->mac.ops.fc_autoneg(hw);
2165
2166 /* Disable any previous flow control settings */
2167 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2168 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2169
2170 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2171 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2172
2173 /*
2174 * The possible values of fc.current_mode are:
2175 * 0: Flow control is completely disabled
2176 * 1: Rx flow control is enabled (we can receive pause frames,
2177 * but not send pause frames).
2178 * 2: Tx flow control is enabled (we can send pause frames but
2179 * we do not support receiving pause frames).
2180 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2181 * other: Invalid.
2182 */
2183 switch (hw->fc.current_mode) {
2184 case ixgbe_fc_none:
2185 /*
2186 * Flow control is disabled by software override or autoneg.
2187 * The code below will actually disable it in the HW.
2188 */
2189 break;
2190 case ixgbe_fc_rx_pause:
2191 /*
2192 * Rx Flow control is enabled and Tx Flow control is
2193 * disabled by software override. Since there really
2194 * isn't a way to advertise that we are capable of RX
2195 * Pause ONLY, we will advertise that we support both
2196 * symmetric and asymmetric Rx PAUSE. Later, we will
2197 * disable the adapter's ability to send PAUSE frames.
2198 */
2199 mflcn_reg |= IXGBE_MFLCN_RFCE;
2200 break;
2201 case ixgbe_fc_tx_pause:
2202 /*
2203 * Tx Flow control is enabled, and Rx Flow control is
2204 * disabled by software override.
2205 */
2206 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2207 break;
2208 case ixgbe_fc_full:
2209 /* Flow control (both Rx and Tx) is enabled by SW override. */
2210 mflcn_reg |= IXGBE_MFLCN_RFCE;
2211 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2212 break;
2213 default:
2214 hw_dbg(hw, "Flow control param set incorrectly\n");
2215 return IXGBE_ERR_CONFIG;
2216 }
2217
2218 /* Set 802.3x based flow control settings. */
2219 mflcn_reg |= IXGBE_MFLCN_DPF;
2220 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2221 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2222
2223 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2224 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2225 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2226 hw->fc.high_water[i]) {
2227 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2228 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2229 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2230 } else {
2231 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2232 /*
2233 * In order to prevent Tx hangs when the internal Tx
2234 * switch is enabled we must set the high water mark
2235 * to the Rx packet buffer size - 24KB. This allows
2236 * the Tx switch to function even under heavy Rx
2237 * workloads.
2238 */
2239 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2240 }
2241
2242 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2243 }
2244
2245 /* Configure pause time (2 TCs per register) */
2246 reg = hw->fc.pause_time * 0x00010001U;
2247 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
2248 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2249
2250 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2251
2252 return 0;
2253 }
2254
2255 /**
2256 * ixgbe_negotiate_fc - Negotiate flow control
2257 * @hw: pointer to hardware structure
2258 * @adv_reg: flow control advertised settings
2259 * @lp_reg: link partner's flow control settings
2260 * @adv_sym: symmetric pause bit in advertisement
2261 * @adv_asm: asymmetric pause bit in advertisement
2262 * @lp_sym: symmetric pause bit in link partner advertisement
2263 * @lp_asm: asymmetric pause bit in link partner advertisement
2264 *
2265 * Find the intersection between advertised settings and link partner's
2266 * advertised settings
2267 **/
ixgbe_negotiate_fc(struct ixgbe_hw * hw,u32 adv_reg,u32 lp_reg,u32 adv_sym,u32 adv_asm,u32 lp_sym,u32 lp_asm)2268 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2269 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2270 {
2271 if ((!(adv_reg)) || (!(lp_reg)))
2272 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2273
2274 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2275 /*
2276 * Now we need to check if the user selected Rx ONLY
2277 * of pause frames. In this case, we had to advertise
2278 * FULL flow control because we could not advertise RX
2279 * ONLY. Hence, we must now check to see if we need to
2280 * turn OFF the TRANSMISSION of PAUSE frames.
2281 */
2282 if (hw->fc.requested_mode == ixgbe_fc_full) {
2283 hw->fc.current_mode = ixgbe_fc_full;
2284 hw_dbg(hw, "Flow Control = FULL.\n");
2285 } else {
2286 hw->fc.current_mode = ixgbe_fc_rx_pause;
2287 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
2288 }
2289 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2290 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2291 hw->fc.current_mode = ixgbe_fc_tx_pause;
2292 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
2293 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2294 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2295 hw->fc.current_mode = ixgbe_fc_rx_pause;
2296 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
2297 } else {
2298 hw->fc.current_mode = ixgbe_fc_none;
2299 hw_dbg(hw, "Flow Control = NONE.\n");
2300 }
2301 return 0;
2302 }
2303
2304 /**
2305 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2306 * @hw: pointer to hardware structure
2307 *
2308 * Enable flow control according on 1 gig fiber.
2309 **/
ixgbe_fc_autoneg_fiber(struct ixgbe_hw * hw)2310 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2311 {
2312 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2313 s32 ret_val;
2314
2315 /*
2316 * On multispeed fiber at 1g, bail out if
2317 * - link is up but AN did not complete, or if
2318 * - link is up and AN completed but timed out
2319 */
2320
2321 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2322 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2323 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
2324 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2325
2326 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2327 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2328
2329 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2330 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2331 IXGBE_PCS1GANA_ASM_PAUSE,
2332 IXGBE_PCS1GANA_SYM_PAUSE,
2333 IXGBE_PCS1GANA_ASM_PAUSE);
2334
2335 return ret_val;
2336 }
2337
2338 /**
2339 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2340 * @hw: pointer to hardware structure
2341 *
2342 * Enable flow control according to IEEE clause 37.
2343 **/
ixgbe_fc_autoneg_backplane(struct ixgbe_hw * hw)2344 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2345 {
2346 u32 links2, anlp1_reg, autoc_reg, links;
2347 s32 ret_val;
2348
2349 /*
2350 * On backplane, bail out if
2351 * - backplane autoneg was not completed, or if
2352 * - we are 82599 and link partner is not AN enabled
2353 */
2354 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2355 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
2356 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2357
2358 if (hw->mac.type == ixgbe_mac_82599EB) {
2359 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2360 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
2361 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2362 }
2363 /*
2364 * Read the 10g AN autoc and LP ability registers and resolve
2365 * local flow control settings accordingly
2366 */
2367 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2368 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2369
2370 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2371 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2372 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2373
2374 return ret_val;
2375 }
2376
2377 /**
2378 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2379 * @hw: pointer to hardware structure
2380 *
2381 * Enable flow control according to IEEE clause 37.
2382 **/
ixgbe_fc_autoneg_copper(struct ixgbe_hw * hw)2383 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2384 {
2385 u16 technology_ability_reg = 0;
2386 u16 lp_technology_ability_reg = 0;
2387
2388 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2389 MDIO_MMD_AN,
2390 &technology_ability_reg);
2391 hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
2392 MDIO_MMD_AN,
2393 &lp_technology_ability_reg);
2394
2395 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2396 (u32)lp_technology_ability_reg,
2397 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2398 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2399 }
2400
2401 /**
2402 * ixgbe_fc_autoneg - Configure flow control
2403 * @hw: pointer to hardware structure
2404 *
2405 * Compares our advertised flow control capabilities to those advertised by
2406 * our link partner, and determines the proper flow control mode to use.
2407 **/
ixgbe_fc_autoneg(struct ixgbe_hw * hw)2408 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2409 {
2410 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2411 ixgbe_link_speed speed;
2412 bool link_up;
2413
2414 /*
2415 * AN should have completed when the cable was plugged in.
2416 * Look for reasons to bail out. Bail out if:
2417 * - FC autoneg is disabled, or if
2418 * - link is not up.
2419 *
2420 * Since we're being called from an LSC, link is already known to be up.
2421 * So use link_up_wait_to_complete=false.
2422 */
2423 if (hw->fc.disable_fc_autoneg)
2424 goto out;
2425
2426 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2427 if (!link_up)
2428 goto out;
2429
2430 switch (hw->phy.media_type) {
2431 /* Autoneg flow control on fiber adapters */
2432 case ixgbe_media_type_fiber:
2433 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2434 ret_val = ixgbe_fc_autoneg_fiber(hw);
2435 break;
2436
2437 /* Autoneg flow control on backplane adapters */
2438 case ixgbe_media_type_backplane:
2439 ret_val = ixgbe_fc_autoneg_backplane(hw);
2440 break;
2441
2442 /* Autoneg flow control on copper adapters */
2443 case ixgbe_media_type_copper:
2444 if (ixgbe_device_supports_autoneg_fc(hw))
2445 ret_val = ixgbe_fc_autoneg_copper(hw);
2446 break;
2447
2448 default:
2449 break;
2450 }
2451
2452 out:
2453 if (ret_val == 0) {
2454 hw->fc.fc_was_autonegged = true;
2455 } else {
2456 hw->fc.fc_was_autonegged = false;
2457 hw->fc.current_mode = hw->fc.requested_mode;
2458 }
2459 }
2460
2461 /**
2462 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
2463 * @hw: pointer to hardware structure
2464 *
2465 * System-wide timeout range is encoded in PCIe Device Control2 register.
2466 *
2467 * Add 10% to specified maximum and return the number of times to poll for
2468 * completion timeout, in units of 100 microsec. Never return less than
2469 * 800 = 80 millisec.
2470 **/
ixgbe_pcie_timeout_poll(struct ixgbe_hw * hw)2471 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
2472 {
2473 s16 devctl2;
2474 u32 pollcnt;
2475
2476 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2);
2477 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
2478
2479 switch (devctl2) {
2480 case IXGBE_PCIDEVCTRL2_65_130ms:
2481 pollcnt = 1300; /* 130 millisec */
2482 break;
2483 case IXGBE_PCIDEVCTRL2_260_520ms:
2484 pollcnt = 5200; /* 520 millisec */
2485 break;
2486 case IXGBE_PCIDEVCTRL2_1_2s:
2487 pollcnt = 20000; /* 2 sec */
2488 break;
2489 case IXGBE_PCIDEVCTRL2_4_8s:
2490 pollcnt = 80000; /* 8 sec */
2491 break;
2492 case IXGBE_PCIDEVCTRL2_17_34s:
2493 pollcnt = 34000; /* 34 sec */
2494 break;
2495 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
2496 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
2497 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
2498 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
2499 default:
2500 pollcnt = 800; /* 80 millisec minimum */
2501 break;
2502 }
2503
2504 /* add 10% to spec maximum */
2505 return (pollcnt * 11) / 10;
2506 }
2507
2508 /**
2509 * ixgbe_disable_pcie_primary - Disable PCI-express primary access
2510 * @hw: pointer to hardware structure
2511 *
2512 * Disables PCI-Express primary access and verifies there are no pending
2513 * requests. IXGBE_ERR_PRIMARY_REQUESTS_PENDING is returned if primary disable
2514 * bit hasn't caused the primary requests to be disabled, else 0
2515 * is returned signifying primary requests disabled.
2516 **/
ixgbe_disable_pcie_primary(struct ixgbe_hw * hw)2517 static s32 ixgbe_disable_pcie_primary(struct ixgbe_hw *hw)
2518 {
2519 u32 i, poll;
2520 u16 value;
2521
2522 /* Always set this bit to ensure any future transactions are blocked */
2523 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
2524
2525 /* Poll for bit to read as set */
2526 for (i = 0; i < IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT; i++) {
2527 if (IXGBE_READ_REG(hw, IXGBE_CTRL) & IXGBE_CTRL_GIO_DIS)
2528 break;
2529 usleep_range(100, 120);
2530 }
2531 if (i >= IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT) {
2532 hw_dbg(hw, "GIO disable did not set - requesting resets\n");
2533 goto gio_disable_fail;
2534 }
2535
2536 /* Exit if primary requests are blocked */
2537 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
2538 ixgbe_removed(hw->hw_addr))
2539 return 0;
2540
2541 /* Poll for primary request bit to clear */
2542 for (i = 0; i < IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT; i++) {
2543 udelay(100);
2544 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2545 return 0;
2546 }
2547
2548 /*
2549 * Two consecutive resets are required via CTRL.RST per datasheet
2550 * 5.2.5.3.2 Primary Disable. We set a flag to inform the reset routine
2551 * of this need. The first reset prevents new primary requests from
2552 * being issued by our device. We then must wait 1usec or more for any
2553 * remaining completions from the PCIe bus to trickle in, and then reset
2554 * again to clear out any effects they may have had on our device.
2555 */
2556 hw_dbg(hw, "GIO Primary Disable bit didn't clear - requesting resets\n");
2557 gio_disable_fail:
2558 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2559
2560 if (hw->mac.type >= ixgbe_mac_X550)
2561 return 0;
2562
2563 /*
2564 * Before proceeding, make sure that the PCIe block does not have
2565 * transactions pending.
2566 */
2567 poll = ixgbe_pcie_timeout_poll(hw);
2568 for (i = 0; i < poll; i++) {
2569 udelay(100);
2570 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
2571 if (ixgbe_removed(hw->hw_addr))
2572 return 0;
2573 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2574 return 0;
2575 }
2576
2577 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
2578 return IXGBE_ERR_PRIMARY_REQUESTS_PENDING;
2579 }
2580
2581 /**
2582 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2583 * @hw: pointer to hardware structure
2584 * @mask: Mask to specify which semaphore to acquire
2585 *
2586 * Acquires the SWFW semaphore through the GSSR register for the specified
2587 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2588 **/
ixgbe_acquire_swfw_sync(struct ixgbe_hw * hw,u32 mask)2589 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
2590 {
2591 u32 gssr = 0;
2592 u32 swmask = mask;
2593 u32 fwmask = mask << 5;
2594 u32 timeout = 200;
2595 u32 i;
2596
2597 for (i = 0; i < timeout; i++) {
2598 /*
2599 * SW NVM semaphore bit is used for access to all
2600 * SW_FW_SYNC bits (not just NVM)
2601 */
2602 if (ixgbe_get_eeprom_semaphore(hw))
2603 return IXGBE_ERR_SWFW_SYNC;
2604
2605 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2606 if (!(gssr & (fwmask | swmask))) {
2607 gssr |= swmask;
2608 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2609 ixgbe_release_eeprom_semaphore(hw);
2610 return 0;
2611 } else {
2612 /* Resource is currently in use by FW or SW */
2613 ixgbe_release_eeprom_semaphore(hw);
2614 usleep_range(5000, 10000);
2615 }
2616 }
2617
2618 /* If time expired clear the bits holding the lock and retry */
2619 if (gssr & (fwmask | swmask))
2620 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
2621
2622 usleep_range(5000, 10000);
2623 return IXGBE_ERR_SWFW_SYNC;
2624 }
2625
2626 /**
2627 * ixgbe_release_swfw_sync - Release SWFW semaphore
2628 * @hw: pointer to hardware structure
2629 * @mask: Mask to specify which semaphore to release
2630 *
2631 * Releases the SWFW semaphore through the GSSR register for the specified
2632 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2633 **/
ixgbe_release_swfw_sync(struct ixgbe_hw * hw,u32 mask)2634 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
2635 {
2636 u32 gssr;
2637 u32 swmask = mask;
2638
2639 ixgbe_get_eeprom_semaphore(hw);
2640
2641 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2642 gssr &= ~swmask;
2643 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2644
2645 ixgbe_release_eeprom_semaphore(hw);
2646 }
2647
2648 /**
2649 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
2650 * @hw: pointer to hardware structure
2651 * @reg_val: Value we read from AUTOC
2652 * @locked: bool to indicate whether the SW/FW lock should be taken. Never
2653 * true in this the generic case.
2654 *
2655 * The default case requires no protection so just to the register read.
2656 **/
prot_autoc_read_generic(struct ixgbe_hw * hw,bool * locked,u32 * reg_val)2657 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
2658 {
2659 *locked = false;
2660 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2661 return 0;
2662 }
2663
2664 /**
2665 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
2666 * @hw: pointer to hardware structure
2667 * @reg_val: value to write to AUTOC
2668 * @locked: bool to indicate whether the SW/FW lock was already taken by
2669 * previous read.
2670 **/
prot_autoc_write_generic(struct ixgbe_hw * hw,u32 reg_val,bool locked)2671 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
2672 {
2673 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
2674 return 0;
2675 }
2676
2677 /**
2678 * ixgbe_disable_rx_buff_generic - Stops the receive data path
2679 * @hw: pointer to hardware structure
2680 *
2681 * Stops the receive data path and waits for the HW to internally
2682 * empty the Rx security block.
2683 **/
ixgbe_disable_rx_buff_generic(struct ixgbe_hw * hw)2684 s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw)
2685 {
2686 #define IXGBE_MAX_SECRX_POLL 40
2687 int i;
2688 int secrxreg;
2689
2690 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2691 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2692 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2693 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2694 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2695 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2696 break;
2697 else
2698 /* Use interrupt-safe sleep just in case */
2699 udelay(1000);
2700 }
2701
2702 /* For informational purposes only */
2703 if (i >= IXGBE_MAX_SECRX_POLL)
2704 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n");
2705
2706 return 0;
2707
2708 }
2709
2710 /**
2711 * ixgbe_enable_rx_buff_generic - Enables the receive data path
2712 * @hw: pointer to hardware structure
2713 *
2714 * Enables the receive data path
2715 **/
ixgbe_enable_rx_buff_generic(struct ixgbe_hw * hw)2716 s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw)
2717 {
2718 u32 secrxreg;
2719
2720 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2721 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2722 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2723 IXGBE_WRITE_FLUSH(hw);
2724
2725 return 0;
2726 }
2727
2728 /**
2729 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2730 * @hw: pointer to hardware structure
2731 * @regval: register value to write to RXCTRL
2732 *
2733 * Enables the Rx DMA unit
2734 **/
ixgbe_enable_rx_dma_generic(struct ixgbe_hw * hw,u32 regval)2735 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2736 {
2737 if (regval & IXGBE_RXCTRL_RXEN)
2738 hw->mac.ops.enable_rx(hw);
2739 else
2740 hw->mac.ops.disable_rx(hw);
2741
2742 return 0;
2743 }
2744
2745 /**
2746 * ixgbe_blink_led_start_generic - Blink LED based on index.
2747 * @hw: pointer to hardware structure
2748 * @index: led number to blink
2749 **/
ixgbe_blink_led_start_generic(struct ixgbe_hw * hw,u32 index)2750 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2751 {
2752 ixgbe_link_speed speed = 0;
2753 bool link_up = false;
2754 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2755 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2756 bool locked = false;
2757 s32 ret_val;
2758
2759 if (index > 3)
2760 return IXGBE_ERR_PARAM;
2761
2762 /*
2763 * Link must be up to auto-blink the LEDs;
2764 * Force it if link is down.
2765 */
2766 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2767
2768 if (!link_up) {
2769 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
2770 if (ret_val)
2771 return ret_val;
2772
2773 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2774 autoc_reg |= IXGBE_AUTOC_FLU;
2775
2776 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
2777 if (ret_val)
2778 return ret_val;
2779
2780 IXGBE_WRITE_FLUSH(hw);
2781
2782 usleep_range(10000, 20000);
2783 }
2784
2785 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2786 led_reg |= IXGBE_LED_BLINK(index);
2787 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2788 IXGBE_WRITE_FLUSH(hw);
2789
2790 return 0;
2791 }
2792
2793 /**
2794 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2795 * @hw: pointer to hardware structure
2796 * @index: led number to stop blinking
2797 **/
ixgbe_blink_led_stop_generic(struct ixgbe_hw * hw,u32 index)2798 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2799 {
2800 u32 autoc_reg = 0;
2801 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2802 bool locked = false;
2803 s32 ret_val;
2804
2805 if (index > 3)
2806 return IXGBE_ERR_PARAM;
2807
2808 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
2809 if (ret_val)
2810 return ret_val;
2811
2812 autoc_reg &= ~IXGBE_AUTOC_FLU;
2813 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2814
2815 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
2816 if (ret_val)
2817 return ret_val;
2818
2819 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2820 led_reg &= ~IXGBE_LED_BLINK(index);
2821 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2822 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2823 IXGBE_WRITE_FLUSH(hw);
2824
2825 return 0;
2826 }
2827
2828 /**
2829 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2830 * @hw: pointer to hardware structure
2831 * @san_mac_offset: SAN MAC address offset
2832 *
2833 * This function will read the EEPROM location for the SAN MAC address
2834 * pointer, and returns the value at that location. This is used in both
2835 * get and set mac_addr routines.
2836 **/
ixgbe_get_san_mac_addr_offset(struct ixgbe_hw * hw,u16 * san_mac_offset)2837 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2838 u16 *san_mac_offset)
2839 {
2840 s32 ret_val;
2841
2842 /*
2843 * First read the EEPROM pointer to see if the MAC addresses are
2844 * available.
2845 */
2846 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
2847 san_mac_offset);
2848 if (ret_val)
2849 hw_err(hw, "eeprom read at offset %d failed\n",
2850 IXGBE_SAN_MAC_ADDR_PTR);
2851
2852 return ret_val;
2853 }
2854
2855 /**
2856 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2857 * @hw: pointer to hardware structure
2858 * @san_mac_addr: SAN MAC address
2859 *
2860 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2861 * per-port, so set_lan_id() must be called before reading the addresses.
2862 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2863 * upon for non-SFP connections, so we must call it here.
2864 **/
ixgbe_get_san_mac_addr_generic(struct ixgbe_hw * hw,u8 * san_mac_addr)2865 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2866 {
2867 u16 san_mac_data, san_mac_offset;
2868 u8 i;
2869 s32 ret_val;
2870
2871 /*
2872 * First read the EEPROM pointer to see if the MAC addresses are
2873 * available. If they're not, no point in calling set_lan_id() here.
2874 */
2875 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2876 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
2877
2878 goto san_mac_addr_clr;
2879
2880 /* make sure we know which port we need to program */
2881 hw->mac.ops.set_lan_id(hw);
2882 /* apply the port offset to the address offset */
2883 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2884 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2885 for (i = 0; i < 3; i++) {
2886 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
2887 &san_mac_data);
2888 if (ret_val) {
2889 hw_err(hw, "eeprom read at offset %d failed\n",
2890 san_mac_offset);
2891 goto san_mac_addr_clr;
2892 }
2893 san_mac_addr[i * 2] = (u8)(san_mac_data);
2894 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2895 san_mac_offset++;
2896 }
2897 return 0;
2898
2899 san_mac_addr_clr:
2900 /* No addresses available in this EEPROM. It's not necessarily an
2901 * error though, so just wipe the local address and return.
2902 */
2903 for (i = 0; i < 6; i++)
2904 san_mac_addr[i] = 0xFF;
2905 return ret_val;
2906 }
2907
2908 /**
2909 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2910 * @hw: pointer to hardware structure
2911 *
2912 * Read PCIe configuration space, and get the MSI-X vector count from
2913 * the capabilities table.
2914 **/
ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw * hw)2915 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2916 {
2917 u16 msix_count;
2918 u16 max_msix_count;
2919 u16 pcie_offset;
2920
2921 switch (hw->mac.type) {
2922 case ixgbe_mac_82598EB:
2923 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
2924 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
2925 break;
2926 case ixgbe_mac_82599EB:
2927 case ixgbe_mac_X540:
2928 case ixgbe_mac_X550:
2929 case ixgbe_mac_X550EM_x:
2930 case ixgbe_mac_x550em_a:
2931 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
2932 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
2933 break;
2934 default:
2935 return 1;
2936 }
2937
2938 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset);
2939 if (ixgbe_removed(hw->hw_addr))
2940 msix_count = 0;
2941 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2942
2943 /* MSI-X count is zero-based in HW */
2944 msix_count++;
2945
2946 if (msix_count > max_msix_count)
2947 msix_count = max_msix_count;
2948
2949 return msix_count;
2950 }
2951
2952 /**
2953 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2954 * @hw: pointer to hardware struct
2955 * @rar: receive address register index to disassociate
2956 * @vmdq: VMDq pool index to remove from the rar
2957 **/
ixgbe_clear_vmdq_generic(struct ixgbe_hw * hw,u32 rar,u32 vmdq)2958 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2959 {
2960 u32 mpsar_lo, mpsar_hi;
2961 u32 rar_entries = hw->mac.num_rar_entries;
2962
2963 /* Make sure we are using a valid rar index range */
2964 if (rar >= rar_entries) {
2965 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2966 return IXGBE_ERR_INVALID_ARGUMENT;
2967 }
2968
2969 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2970 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2971
2972 if (ixgbe_removed(hw->hw_addr))
2973 return 0;
2974
2975 if (!mpsar_lo && !mpsar_hi)
2976 return 0;
2977
2978 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2979 if (mpsar_lo) {
2980 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2981 mpsar_lo = 0;
2982 }
2983 if (mpsar_hi) {
2984 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2985 mpsar_hi = 0;
2986 }
2987 } else if (vmdq < 32) {
2988 mpsar_lo &= ~BIT(vmdq);
2989 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
2990 } else {
2991 mpsar_hi &= ~BIT(vmdq - 32);
2992 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
2993 }
2994
2995 /* was that the last pool using this rar? */
2996 if (mpsar_lo == 0 && mpsar_hi == 0 &&
2997 rar != 0 && rar != hw->mac.san_mac_rar_index)
2998 hw->mac.ops.clear_rar(hw, rar);
2999
3000 return 0;
3001 }
3002
3003 /**
3004 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3005 * @hw: pointer to hardware struct
3006 * @rar: receive address register index to associate with a VMDq index
3007 * @vmdq: VMDq pool index
3008 **/
ixgbe_set_vmdq_generic(struct ixgbe_hw * hw,u32 rar,u32 vmdq)3009 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3010 {
3011 u32 mpsar;
3012 u32 rar_entries = hw->mac.num_rar_entries;
3013
3014 /* Make sure we are using a valid rar index range */
3015 if (rar >= rar_entries) {
3016 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
3017 return IXGBE_ERR_INVALID_ARGUMENT;
3018 }
3019
3020 if (vmdq < 32) {
3021 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3022 mpsar |= BIT(vmdq);
3023 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3024 } else {
3025 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3026 mpsar |= BIT(vmdq - 32);
3027 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3028 }
3029 return 0;
3030 }
3031
3032 /**
3033 * ixgbe_set_vmdq_san_mac_generic - Associate VMDq pool index with a rx address
3034 * @hw: pointer to hardware struct
3035 * @vmdq: VMDq pool index
3036 *
3037 * This function should only be involved in the IOV mode.
3038 * In IOV mode, Default pool is next pool after the number of
3039 * VFs advertized and not 0.
3040 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3041 **/
ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw * hw,u32 vmdq)3042 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3043 {
3044 u32 rar = hw->mac.san_mac_rar_index;
3045
3046 if (vmdq < 32) {
3047 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), BIT(vmdq));
3048 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3049 } else {
3050 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3051 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), BIT(vmdq - 32));
3052 }
3053
3054 return 0;
3055 }
3056
3057 /**
3058 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3059 * @hw: pointer to hardware structure
3060 **/
ixgbe_init_uta_tables_generic(struct ixgbe_hw * hw)3061 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3062 {
3063 int i;
3064
3065 for (i = 0; i < 128; i++)
3066 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3067
3068 return 0;
3069 }
3070
3071 /**
3072 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3073 * @hw: pointer to hardware structure
3074 * @vlan: VLAN id to write to VLAN filter
3075 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if
3076 * vlanid not found
3077 *
3078 * return the VLVF index where this VLAN id should be placed
3079 *
3080 **/
ixgbe_find_vlvf_slot(struct ixgbe_hw * hw,u32 vlan,bool vlvf_bypass)3081 static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
3082 {
3083 s32 regindex, first_empty_slot;
3084 u32 bits;
3085
3086 /* short cut the special case */
3087 if (vlan == 0)
3088 return 0;
3089
3090 /* if vlvf_bypass is set we don't want to use an empty slot, we
3091 * will simply bypass the VLVF if there are no entries present in the
3092 * VLVF that contain our VLAN
3093 */
3094 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0;
3095
3096 /* add VLAN enable bit for comparison */
3097 vlan |= IXGBE_VLVF_VIEN;
3098
3099 /* Search for the vlan id in the VLVF entries. Save off the first empty
3100 * slot found along the way.
3101 *
3102 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
3103 */
3104 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) {
3105 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3106 if (bits == vlan)
3107 return regindex;
3108 if (!first_empty_slot && !bits)
3109 first_empty_slot = regindex;
3110 }
3111
3112 /* If we are here then we didn't find the VLAN. Return first empty
3113 * slot we found during our search, else error.
3114 */
3115 if (!first_empty_slot)
3116 hw_dbg(hw, "No space in VLVF.\n");
3117
3118 return first_empty_slot ? : IXGBE_ERR_NO_SPACE;
3119 }
3120
3121 /**
3122 * ixgbe_set_vfta_generic - Set VLAN filter table
3123 * @hw: pointer to hardware structure
3124 * @vlan: VLAN id to write to VLAN filter
3125 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3126 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3127 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3128 *
3129 * Turn on/off specified VLAN in the VLAN filter table.
3130 **/
ixgbe_set_vfta_generic(struct ixgbe_hw * hw,u32 vlan,u32 vind,bool vlan_on,bool vlvf_bypass)3131 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3132 bool vlan_on, bool vlvf_bypass)
3133 {
3134 u32 regidx, vfta_delta, vfta, bits;
3135 s32 vlvf_index;
3136
3137 if ((vlan > 4095) || (vind > 63))
3138 return IXGBE_ERR_PARAM;
3139
3140 /*
3141 * this is a 2 part operation - first the VFTA, then the
3142 * VLVF and VLVFB if VT Mode is set
3143 * We don't write the VFTA until we know the VLVF part succeeded.
3144 */
3145
3146 /* Part 1
3147 * The VFTA is a bitstring made up of 128 32-bit registers
3148 * that enable the particular VLAN id, much like the MTA:
3149 * bits[11-5]: which register
3150 * bits[4-0]: which bit in the register
3151 */
3152 regidx = vlan / 32;
3153 vfta_delta = BIT(vlan % 32);
3154 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
3155
3156 /* vfta_delta represents the difference between the current value
3157 * of vfta and the value we want in the register. Since the diff
3158 * is an XOR mask we can just update vfta using an XOR.
3159 */
3160 vfta_delta &= vlan_on ? ~vfta : vfta;
3161 vfta ^= vfta_delta;
3162
3163 /* Part 2
3164 * If VT Mode is set
3165 * Either vlan_on
3166 * make sure the vlan is in VLVF
3167 * set the vind bit in the matching VLVFB
3168 * Or !vlan_on
3169 * clear the pool bit and possibly the vind
3170 */
3171 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE))
3172 goto vfta_update;
3173
3174 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
3175 if (vlvf_index < 0) {
3176 if (vlvf_bypass)
3177 goto vfta_update;
3178 return vlvf_index;
3179 }
3180
3181 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
3182
3183 /* set the pool bit */
3184 bits |= BIT(vind % 32);
3185 if (vlan_on)
3186 goto vlvf_update;
3187
3188 /* clear the pool bit */
3189 bits ^= BIT(vind % 32);
3190
3191 if (!bits &&
3192 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
3193 /* Clear VFTA first, then disable VLVF. Otherwise
3194 * we run the risk of stray packets leaking into
3195 * the PF via the default pool
3196 */
3197 if (vfta_delta)
3198 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
3199
3200 /* disable VLVF and clear remaining bit from pool */
3201 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3202 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0);
3203
3204 return 0;
3205 }
3206
3207 /* If there are still bits set in the VLVFB registers
3208 * for the VLAN ID indicated we need to see if the
3209 * caller is requesting that we clear the VFTA entry bit.
3210 * If the caller has requested that we clear the VFTA
3211 * entry bit but there are still pools/VFs using this VLAN
3212 * ID entry then ignore the request. We're not worried
3213 * about the case where we're turning the VFTA VLAN ID
3214 * entry bit on, only when requested to turn it off as
3215 * there may be multiple pools and/or VFs using the
3216 * VLAN ID entry. In that case we cannot clear the
3217 * VFTA bit until all pools/VFs using that VLAN ID have also
3218 * been cleared. This will be indicated by "bits" being
3219 * zero.
3220 */
3221 vfta_delta = 0;
3222
3223 vlvf_update:
3224 /* record pool change and enable VLAN ID if not already enabled */
3225 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);
3226 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan);
3227
3228 vfta_update:
3229 /* Update VFTA now that we are ready for traffic */
3230 if (vfta_delta)
3231 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
3232
3233 return 0;
3234 }
3235
3236 /**
3237 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3238 * @hw: pointer to hardware structure
3239 *
3240 * Clears the VLAN filter table, and the VMDq index associated with the filter
3241 **/
ixgbe_clear_vfta_generic(struct ixgbe_hw * hw)3242 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3243 {
3244 u32 offset;
3245
3246 for (offset = 0; offset < hw->mac.vft_size; offset++)
3247 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3248
3249 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3250 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3251 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
3252 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0);
3253 }
3254
3255 return 0;
3256 }
3257
3258 /**
3259 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
3260 * @hw: pointer to hardware structure
3261 *
3262 * Contains the logic to identify if we need to verify link for the
3263 * crosstalk fix
3264 **/
ixgbe_need_crosstalk_fix(struct ixgbe_hw * hw)3265 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
3266 {
3267 /* Does FW say we need the fix */
3268 if (!hw->need_crosstalk_fix)
3269 return false;
3270
3271 /* Only consider SFP+ PHYs i.e. media type fiber */
3272 switch (hw->mac.ops.get_media_type(hw)) {
3273 case ixgbe_media_type_fiber:
3274 case ixgbe_media_type_fiber_qsfp:
3275 break;
3276 default:
3277 return false;
3278 }
3279
3280 return true;
3281 }
3282
3283 /**
3284 * ixgbe_check_mac_link_generic - Determine link and speed status
3285 * @hw: pointer to hardware structure
3286 * @speed: pointer to link speed
3287 * @link_up: true when link is up
3288 * @link_up_wait_to_complete: bool used to wait for link up or not
3289 *
3290 * Reads the links register to determine if link is up and the current speed
3291 **/
ixgbe_check_mac_link_generic(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * link_up,bool link_up_wait_to_complete)3292 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3293 bool *link_up, bool link_up_wait_to_complete)
3294 {
3295 u32 links_reg, links_orig;
3296 u32 i;
3297
3298 /* If Crosstalk fix enabled do the sanity check of making sure
3299 * the SFP+ cage is full.
3300 */
3301 if (ixgbe_need_crosstalk_fix(hw)) {
3302 u32 sfp_cage_full;
3303
3304 switch (hw->mac.type) {
3305 case ixgbe_mac_82599EB:
3306 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
3307 IXGBE_ESDP_SDP2;
3308 break;
3309 case ixgbe_mac_X550EM_x:
3310 case ixgbe_mac_x550em_a:
3311 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
3312 IXGBE_ESDP_SDP0;
3313 break;
3314 default:
3315 /* sanity check - No SFP+ devices here */
3316 sfp_cage_full = false;
3317 break;
3318 }
3319
3320 if (!sfp_cage_full) {
3321 *link_up = false;
3322 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3323 return 0;
3324 }
3325 }
3326
3327 /* clear the old state */
3328 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3329
3330 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3331
3332 if (links_orig != links_reg) {
3333 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
3334 links_orig, links_reg);
3335 }
3336
3337 if (link_up_wait_to_complete) {
3338 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3339 if (links_reg & IXGBE_LINKS_UP) {
3340 *link_up = true;
3341 break;
3342 } else {
3343 *link_up = false;
3344 }
3345 msleep(100);
3346 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3347 }
3348 } else {
3349 if (links_reg & IXGBE_LINKS_UP)
3350 *link_up = true;
3351 else
3352 *link_up = false;
3353 }
3354
3355 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3356 case IXGBE_LINKS_SPEED_10G_82599:
3357 if ((hw->mac.type >= ixgbe_mac_X550) &&
3358 (links_reg & IXGBE_LINKS_SPEED_NON_STD))
3359 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3360 else
3361 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3362 break;
3363 case IXGBE_LINKS_SPEED_1G_82599:
3364 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3365 break;
3366 case IXGBE_LINKS_SPEED_100_82599:
3367 if ((hw->mac.type >= ixgbe_mac_X550) &&
3368 (links_reg & IXGBE_LINKS_SPEED_NON_STD))
3369 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3370 else
3371 *speed = IXGBE_LINK_SPEED_100_FULL;
3372 break;
3373 case IXGBE_LINKS_SPEED_10_X550EM_A:
3374 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3375 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3376 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
3377 *speed = IXGBE_LINK_SPEED_10_FULL;
3378 }
3379 break;
3380 default:
3381 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3382 }
3383
3384 return 0;
3385 }
3386
3387 /**
3388 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
3389 * the EEPROM
3390 * @hw: pointer to hardware structure
3391 * @wwnn_prefix: the alternative WWNN prefix
3392 * @wwpn_prefix: the alternative WWPN prefix
3393 *
3394 * This function will read the EEPROM from the alternative SAN MAC address
3395 * block to check the support for the alternative WWNN/WWPN prefix support.
3396 **/
ixgbe_get_wwn_prefix_generic(struct ixgbe_hw * hw,u16 * wwnn_prefix,u16 * wwpn_prefix)3397 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
3398 u16 *wwpn_prefix)
3399 {
3400 u16 offset, caps;
3401 u16 alt_san_mac_blk_offset;
3402
3403 /* clear output first */
3404 *wwnn_prefix = 0xFFFF;
3405 *wwpn_prefix = 0xFFFF;
3406
3407 /* check if alternative SAN MAC is supported */
3408 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
3409 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
3410 goto wwn_prefix_err;
3411
3412 if ((alt_san_mac_blk_offset == 0) ||
3413 (alt_san_mac_blk_offset == 0xFFFF))
3414 return 0;
3415
3416 /* check capability in alternative san mac address block */
3417 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
3418 if (hw->eeprom.ops.read(hw, offset, &caps))
3419 goto wwn_prefix_err;
3420 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
3421 return 0;
3422
3423 /* get the corresponding prefix for WWNN/WWPN */
3424 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
3425 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix))
3426 hw_err(hw, "eeprom read at offset %d failed\n", offset);
3427
3428 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
3429 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
3430 goto wwn_prefix_err;
3431
3432 return 0;
3433
3434 wwn_prefix_err:
3435 hw_err(hw, "eeprom read at offset %d failed\n", offset);
3436 return 0;
3437 }
3438
3439 /**
3440 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3441 * @hw: pointer to hardware structure
3442 * @enable: enable or disable switch for MAC anti-spoofing
3443 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
3444 *
3445 **/
ixgbe_set_mac_anti_spoofing(struct ixgbe_hw * hw,bool enable,int vf)3446 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3447 {
3448 int vf_target_reg = vf >> 3;
3449 int vf_target_shift = vf % 8;
3450 u32 pfvfspoof;
3451
3452 if (hw->mac.type == ixgbe_mac_82598EB)
3453 return;
3454
3455 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3456 if (enable)
3457 pfvfspoof |= BIT(vf_target_shift);
3458 else
3459 pfvfspoof &= ~BIT(vf_target_shift);
3460 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3461 }
3462
3463 /**
3464 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3465 * @hw: pointer to hardware structure
3466 * @enable: enable or disable switch for VLAN anti-spoofing
3467 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3468 *
3469 **/
ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw * hw,bool enable,int vf)3470 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3471 {
3472 int vf_target_reg = vf >> 3;
3473 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3474 u32 pfvfspoof;
3475
3476 if (hw->mac.type == ixgbe_mac_82598EB)
3477 return;
3478
3479 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3480 if (enable)
3481 pfvfspoof |= BIT(vf_target_shift);
3482 else
3483 pfvfspoof &= ~BIT(vf_target_shift);
3484 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3485 }
3486
3487 /**
3488 * ixgbe_get_device_caps_generic - Get additional device capabilities
3489 * @hw: pointer to hardware structure
3490 * @device_caps: the EEPROM word with the extra device capabilities
3491 *
3492 * This function will read the EEPROM location for the device capabilities,
3493 * and return the word through device_caps.
3494 **/
ixgbe_get_device_caps_generic(struct ixgbe_hw * hw,u16 * device_caps)3495 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3496 {
3497 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3498
3499 return 0;
3500 }
3501
3502 /**
3503 * ixgbe_set_rxpba_generic - Initialize RX packet buffer
3504 * @hw: pointer to hardware structure
3505 * @num_pb: number of packet buffers to allocate
3506 * @headroom: reserve n KB of headroom
3507 * @strategy: packet buffer allocation strategy
3508 **/
ixgbe_set_rxpba_generic(struct ixgbe_hw * hw,int num_pb,u32 headroom,int strategy)3509 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
3510 int num_pb,
3511 u32 headroom,
3512 int strategy)
3513 {
3514 u32 pbsize = hw->mac.rx_pb_size;
3515 int i = 0;
3516 u32 rxpktsize, txpktsize, txpbthresh;
3517
3518 /* Reserve headroom */
3519 pbsize -= headroom;
3520
3521 if (!num_pb)
3522 num_pb = 1;
3523
3524 /* Divide remaining packet buffer space amongst the number
3525 * of packet buffers requested using supplied strategy.
3526 */
3527 switch (strategy) {
3528 case (PBA_STRATEGY_WEIGHTED):
3529 /* pba_80_48 strategy weight first half of packet buffer with
3530 * 5/8 of the packet buffer space.
3531 */
3532 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
3533 pbsize -= rxpktsize * (num_pb / 2);
3534 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
3535 for (; i < (num_pb / 2); i++)
3536 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3537 fallthrough; /* configure remaining packet buffers */
3538 case (PBA_STRATEGY_EQUAL):
3539 /* Divide the remaining Rx packet buffer evenly among the TCs */
3540 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
3541 for (; i < num_pb; i++)
3542 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3543 break;
3544 default:
3545 break;
3546 }
3547
3548 /*
3549 * Setup Tx packet buffer and threshold equally for all TCs
3550 * TXPBTHRESH register is set in K so divide by 1024 and subtract
3551 * 10 since the largest packet we support is just over 9K.
3552 */
3553 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
3554 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
3555 for (i = 0; i < num_pb; i++) {
3556 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3557 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3558 }
3559
3560 /* Clear unused TCs, if any, to zero buffer size*/
3561 for (; i < IXGBE_MAX_PB; i++) {
3562 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3563 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3564 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3565 }
3566 }
3567
3568 /**
3569 * ixgbe_calculate_checksum - Calculate checksum for buffer
3570 * @buffer: pointer to EEPROM
3571 * @length: size of EEPROM to calculate a checksum for
3572 *
3573 * Calculates the checksum for some buffer on a specified length. The
3574 * checksum calculated is returned.
3575 **/
ixgbe_calculate_checksum(u8 * buffer,u32 length)3576 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3577 {
3578 u32 i;
3579 u8 sum = 0;
3580
3581 if (!buffer)
3582 return 0;
3583
3584 for (i = 0; i < length; i++)
3585 sum += buffer[i];
3586
3587 return (u8) (0 - sum);
3588 }
3589
3590 /**
3591 * ixgbe_hic_unlocked - Issue command to manageability block unlocked
3592 * @hw: pointer to the HW structure
3593 * @buffer: command to write and where the return status will be placed
3594 * @length: length of buffer, must be multiple of 4 bytes
3595 * @timeout: time in ms to wait for command completion
3596 *
3597 * Communicates with the manageability block. On success return 0
3598 * else returns semaphore error when encountering an error acquiring
3599 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3600 *
3601 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held
3602 * by the caller.
3603 **/
ixgbe_hic_unlocked(struct ixgbe_hw * hw,u32 * buffer,u32 length,u32 timeout)3604 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,
3605 u32 timeout)
3606 {
3607 u32 hicr, i, fwsts;
3608 u16 dword_len;
3609
3610 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3611 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length);
3612 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
3613 }
3614
3615 /* Set bit 9 of FWSTS clearing FW reset indication */
3616 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
3617 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
3618
3619 /* Check that the host interface is enabled. */
3620 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3621 if (!(hicr & IXGBE_HICR_EN)) {
3622 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
3623 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
3624 }
3625
3626 /* Calculate length in DWORDs. We must be DWORD aligned */
3627 if (length % sizeof(u32)) {
3628 hw_dbg(hw, "Buffer length failure, not aligned to dword");
3629 return IXGBE_ERR_INVALID_ARGUMENT;
3630 }
3631
3632 dword_len = length >> 2;
3633
3634 /* The device driver writes the relevant command block
3635 * into the ram area.
3636 */
3637 for (i = 0; i < dword_len; i++)
3638 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3639 i, (__force u32)cpu_to_le32(buffer[i]));
3640
3641 /* Setting this bit tells the ARC that a new command is pending. */
3642 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3643
3644 for (i = 0; i < timeout; i++) {
3645 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3646 if (!(hicr & IXGBE_HICR_C))
3647 break;
3648 usleep_range(1000, 2000);
3649 }
3650
3651 /* Check command successful completion. */
3652 if ((timeout && i == timeout) ||
3653 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))
3654 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
3655
3656 return 0;
3657 }
3658
3659 /**
3660 * ixgbe_host_interface_command - Issue command to manageability block
3661 * @hw: pointer to the HW structure
3662 * @buffer: contains the command to write and where the return status will
3663 * be placed
3664 * @length: length of buffer, must be multiple of 4 bytes
3665 * @timeout: time in ms to wait for command completion
3666 * @return_data: read and return data from the buffer (true) or not (false)
3667 * Needed because FW structures are big endian and decoding of
3668 * these fields can be 8 bit or 16 bit based on command. Decoding
3669 * is not easily understood without making a table of commands.
3670 * So we will leave this up to the caller to read back the data
3671 * in these cases.
3672 *
3673 * Communicates with the manageability block. On success return 0
3674 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3675 **/
ixgbe_host_interface_command(struct ixgbe_hw * hw,void * buffer,u32 length,u32 timeout,bool return_data)3676 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *buffer,
3677 u32 length, u32 timeout,
3678 bool return_data)
3679 {
3680 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3681 struct ixgbe_hic_hdr *hdr = buffer;
3682 u32 *u32arr = buffer;
3683 u16 buf_len, dword_len;
3684 s32 status;
3685 u32 bi;
3686
3687 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3688 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length);
3689 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
3690 }
3691 /* Take management host interface semaphore */
3692 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
3693 if (status)
3694 return status;
3695
3696 status = ixgbe_hic_unlocked(hw, buffer, length, timeout);
3697 if (status)
3698 goto rel_out;
3699
3700 if (!return_data)
3701 goto rel_out;
3702
3703 /* Calculate length in DWORDs */
3704 dword_len = hdr_size >> 2;
3705
3706 /* first pull in the header so we know the buffer length */
3707 for (bi = 0; bi < dword_len; bi++) {
3708 u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3709 le32_to_cpus(&u32arr[bi]);
3710 }
3711
3712 /* If there is any thing in data position pull it in */
3713 buf_len = hdr->buf_len;
3714 if (!buf_len)
3715 goto rel_out;
3716
3717 if (length < round_up(buf_len, 4) + hdr_size) {
3718 hw_dbg(hw, "Buffer not large enough for reply message.\n");
3719 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3720 goto rel_out;
3721 }
3722
3723 /* Calculate length in DWORDs, add 3 for odd lengths */
3724 dword_len = (buf_len + 3) >> 2;
3725
3726 /* Pull in the rest of the buffer (bi is where we left off) */
3727 for (; bi <= dword_len; bi++) {
3728 u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3729 le32_to_cpus(&u32arr[bi]);
3730 }
3731
3732 rel_out:
3733 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
3734
3735 return status;
3736 }
3737
3738 /**
3739 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3740 * @hw: pointer to the HW structure
3741 * @maj: driver version major number
3742 * @min: driver version minor number
3743 * @build: driver version build number
3744 * @sub: driver version sub build number
3745 * @len: length of driver_ver string
3746 * @driver_ver: driver string
3747 *
3748 * Sends driver version number to firmware through the manageability
3749 * block. On success return 0
3750 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3751 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3752 **/
ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw * hw,u8 maj,u8 min,u8 build,u8 sub,__always_unused u16 len,__always_unused const char * driver_ver)3753 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
3754 u8 build, u8 sub, __always_unused u16 len,
3755 __always_unused const char *driver_ver)
3756 {
3757 struct ixgbe_hic_drv_info fw_cmd;
3758 int i;
3759 s32 ret_val;
3760
3761 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
3762 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
3763 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
3764 fw_cmd.port_num = hw->bus.func;
3765 fw_cmd.ver_maj = maj;
3766 fw_cmd.ver_min = min;
3767 fw_cmd.ver_build = build;
3768 fw_cmd.ver_sub = sub;
3769 fw_cmd.hdr.checksum = 0;
3770 fw_cmd.pad = 0;
3771 fw_cmd.pad2 = 0;
3772 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
3773 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
3774
3775 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
3776 ret_val = ixgbe_host_interface_command(hw, &fw_cmd,
3777 sizeof(fw_cmd),
3778 IXGBE_HI_COMMAND_TIMEOUT,
3779 true);
3780 if (ret_val != 0)
3781 continue;
3782
3783 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
3784 FW_CEM_RESP_STATUS_SUCCESS)
3785 ret_val = 0;
3786 else
3787 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3788
3789 break;
3790 }
3791
3792 return ret_val;
3793 }
3794
3795 /**
3796 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
3797 * @hw: pointer to the hardware structure
3798 *
3799 * The 82599 and x540 MACs can experience issues if TX work is still pending
3800 * when a reset occurs. This function prevents this by flushing the PCIe
3801 * buffers on the system.
3802 **/
ixgbe_clear_tx_pending(struct ixgbe_hw * hw)3803 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
3804 {
3805 u32 gcr_ext, hlreg0, i, poll;
3806 u16 value;
3807
3808 /*
3809 * If double reset is not requested then all transactions should
3810 * already be clear and as such there is no work to do
3811 */
3812 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
3813 return;
3814
3815 /*
3816 * Set loopback enable to prevent any transmits from being sent
3817 * should the link come up. This assumes that the RXCTRL.RXEN bit
3818 * has already been cleared.
3819 */
3820 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3821 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
3822
3823 /* wait for a last completion before clearing buffers */
3824 IXGBE_WRITE_FLUSH(hw);
3825 usleep_range(3000, 6000);
3826
3827 /* Before proceeding, make sure that the PCIe block does not have
3828 * transactions pending.
3829 */
3830 poll = ixgbe_pcie_timeout_poll(hw);
3831 for (i = 0; i < poll; i++) {
3832 usleep_range(100, 200);
3833 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
3834 if (ixgbe_removed(hw->hw_addr))
3835 break;
3836 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3837 break;
3838 }
3839
3840 /* initiate cleaning flow for buffers in the PCIe transaction layer */
3841 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3842 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
3843 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
3844
3845 /* Flush all writes and allow 20usec for all transactions to clear */
3846 IXGBE_WRITE_FLUSH(hw);
3847 udelay(20);
3848
3849 /* restore previous register values */
3850 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3851 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3852 }
3853
3854 static const u8 ixgbe_emc_temp_data[4] = {
3855 IXGBE_EMC_INTERNAL_DATA,
3856 IXGBE_EMC_DIODE1_DATA,
3857 IXGBE_EMC_DIODE2_DATA,
3858 IXGBE_EMC_DIODE3_DATA
3859 };
3860 static const u8 ixgbe_emc_therm_limit[4] = {
3861 IXGBE_EMC_INTERNAL_THERM_LIMIT,
3862 IXGBE_EMC_DIODE1_THERM_LIMIT,
3863 IXGBE_EMC_DIODE2_THERM_LIMIT,
3864 IXGBE_EMC_DIODE3_THERM_LIMIT
3865 };
3866
3867 /**
3868 * ixgbe_get_ets_data - Extracts the ETS bit data
3869 * @hw: pointer to hardware structure
3870 * @ets_cfg: extected ETS data
3871 * @ets_offset: offset of ETS data
3872 *
3873 * Returns error code.
3874 **/
ixgbe_get_ets_data(struct ixgbe_hw * hw,u16 * ets_cfg,u16 * ets_offset)3875 static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg,
3876 u16 *ets_offset)
3877 {
3878 s32 status;
3879
3880 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset);
3881 if (status)
3882 return status;
3883
3884 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF))
3885 return IXGBE_NOT_IMPLEMENTED;
3886
3887 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg);
3888 if (status)
3889 return status;
3890
3891 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED)
3892 return IXGBE_NOT_IMPLEMENTED;
3893
3894 return 0;
3895 }
3896
3897 /**
3898 * ixgbe_get_thermal_sensor_data_generic - Gathers thermal sensor data
3899 * @hw: pointer to hardware structure
3900 *
3901 * Returns the thermal sensor data structure
3902 **/
ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw * hw)3903 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
3904 {
3905 s32 status;
3906 u16 ets_offset;
3907 u16 ets_cfg;
3908 u16 ets_sensor;
3909 u8 num_sensors;
3910 u8 i;
3911 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3912
3913 /* Only support thermal sensors attached to physical port 0 */
3914 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
3915 return IXGBE_NOT_IMPLEMENTED;
3916
3917 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3918 if (status)
3919 return status;
3920
3921 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3922 if (num_sensors > IXGBE_MAX_SENSORS)
3923 num_sensors = IXGBE_MAX_SENSORS;
3924
3925 for (i = 0; i < num_sensors; i++) {
3926 u8 sensor_index;
3927 u8 sensor_location;
3928
3929 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
3930 &ets_sensor);
3931 if (status)
3932 return status;
3933
3934 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3935 IXGBE_ETS_DATA_INDEX_SHIFT);
3936 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3937 IXGBE_ETS_DATA_LOC_SHIFT);
3938
3939 if (sensor_location != 0) {
3940 status = hw->phy.ops.read_i2c_byte(hw,
3941 ixgbe_emc_temp_data[sensor_index],
3942 IXGBE_I2C_THERMAL_SENSOR_ADDR,
3943 &data->sensor[i].temp);
3944 if (status)
3945 return status;
3946 }
3947 }
3948
3949 return 0;
3950 }
3951
3952 /**
3953 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
3954 * @hw: pointer to hardware structure
3955 *
3956 * Inits the thermal sensor thresholds according to the NVM map
3957 * and save off the threshold and location values into mac.thermal_sensor_data
3958 **/
ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw * hw)3959 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
3960 {
3961 s32 status;
3962 u16 ets_offset;
3963 u16 ets_cfg;
3964 u16 ets_sensor;
3965 u8 low_thresh_delta;
3966 u8 num_sensors;
3967 u8 therm_limit;
3968 u8 i;
3969 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3970
3971 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
3972
3973 /* Only support thermal sensors attached to physical port 0 */
3974 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
3975 return IXGBE_NOT_IMPLEMENTED;
3976
3977 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3978 if (status)
3979 return status;
3980
3981 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
3982 IXGBE_ETS_LTHRES_DELTA_SHIFT);
3983 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3984 if (num_sensors > IXGBE_MAX_SENSORS)
3985 num_sensors = IXGBE_MAX_SENSORS;
3986
3987 for (i = 0; i < num_sensors; i++) {
3988 u8 sensor_index;
3989 u8 sensor_location;
3990
3991 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) {
3992 hw_err(hw, "eeprom read at offset %d failed\n",
3993 ets_offset + 1 + i);
3994 continue;
3995 }
3996 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3997 IXGBE_ETS_DATA_INDEX_SHIFT);
3998 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3999 IXGBE_ETS_DATA_LOC_SHIFT);
4000 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
4001
4002 hw->phy.ops.write_i2c_byte(hw,
4003 ixgbe_emc_therm_limit[sensor_index],
4004 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
4005
4006 if (sensor_location == 0)
4007 continue;
4008
4009 data->sensor[i].location = sensor_location;
4010 data->sensor[i].caution_thresh = therm_limit;
4011 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta;
4012 }
4013
4014 return 0;
4015 }
4016
4017 /**
4018 * ixgbe_get_orom_version - Return option ROM from EEPROM
4019 *
4020 * @hw: pointer to hardware structure
4021 * @nvm_ver: pointer to output structure
4022 *
4023 * if valid option ROM version, nvm_ver->or_valid set to true
4024 * else nvm_ver->or_valid is false.
4025 **/
ixgbe_get_orom_version(struct ixgbe_hw * hw,struct ixgbe_nvm_version * nvm_ver)4026 void ixgbe_get_orom_version(struct ixgbe_hw *hw,
4027 struct ixgbe_nvm_version *nvm_ver)
4028 {
4029 u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl;
4030
4031 nvm_ver->or_valid = false;
4032 /* Option Rom may or may not be present. Start with pointer */
4033 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset);
4034
4035 /* make sure offset is valid */
4036 if (offset == 0x0 || offset == NVM_INVALID_PTR)
4037 return;
4038
4039 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh);
4040 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl);
4041
4042 /* option rom exists and is valid */
4043 if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 ||
4044 eeprom_cfg_blkl == NVM_VER_INVALID ||
4045 eeprom_cfg_blkh == NVM_VER_INVALID)
4046 return;
4047
4048 nvm_ver->or_valid = true;
4049 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT;
4050 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) |
4051 (eeprom_cfg_blkh >> NVM_OROM_SHIFT);
4052 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK;
4053 }
4054
4055 /**
4056 * ixgbe_get_oem_prod_version - Etrack ID from EEPROM
4057 * @hw: pointer to hardware structure
4058 * @nvm_ver: pointer to output structure
4059 *
4060 * if valid OEM product version, nvm_ver->oem_valid set to true
4061 * else nvm_ver->oem_valid is false.
4062 **/
ixgbe_get_oem_prod_version(struct ixgbe_hw * hw,struct ixgbe_nvm_version * nvm_ver)4063 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,
4064 struct ixgbe_nvm_version *nvm_ver)
4065 {
4066 u16 rel_num, prod_ver, mod_len, cap, offset;
4067
4068 nvm_ver->oem_valid = false;
4069 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset);
4070
4071 /* Return is offset to OEM Product Version block is invalid */
4072 if (offset == 0x0 || offset == NVM_INVALID_PTR)
4073 return;
4074
4075 /* Read product version block */
4076 hw->eeprom.ops.read(hw, offset, &mod_len);
4077 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap);
4078
4079 /* Return if OEM product version block is invalid */
4080 if (mod_len != NVM_OEM_PROD_VER_MOD_LEN ||
4081 (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0)
4082 return;
4083
4084 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver);
4085 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num);
4086
4087 /* Return if version is invalid */
4088 if ((rel_num | prod_ver) == 0x0 ||
4089 rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID)
4090 return;
4091
4092 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT;
4093 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK;
4094 nvm_ver->oem_release = rel_num;
4095 nvm_ver->oem_valid = true;
4096 }
4097
4098 /**
4099 * ixgbe_get_etk_id - Return Etrack ID from EEPROM
4100 *
4101 * @hw: pointer to hardware structure
4102 * @nvm_ver: pointer to output structure
4103 *
4104 * word read errors will return 0xFFFF
4105 **/
ixgbe_get_etk_id(struct ixgbe_hw * hw,struct ixgbe_nvm_version * nvm_ver)4106 void ixgbe_get_etk_id(struct ixgbe_hw *hw,
4107 struct ixgbe_nvm_version *nvm_ver)
4108 {
4109 u16 etk_id_l, etk_id_h;
4110
4111 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l))
4112 etk_id_l = NVM_VER_INVALID;
4113 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h))
4114 etk_id_h = NVM_VER_INVALID;
4115
4116 /* The word order for the version format is determined by high order
4117 * word bit 15.
4118 */
4119 if ((etk_id_h & NVM_ETK_VALID) == 0) {
4120 nvm_ver->etk_id = etk_id_h;
4121 nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT);
4122 } else {
4123 nvm_ver->etk_id = etk_id_l;
4124 nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT);
4125 }
4126 }
4127
ixgbe_disable_rx_generic(struct ixgbe_hw * hw)4128 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
4129 {
4130 u32 rxctrl;
4131
4132 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4133 if (rxctrl & IXGBE_RXCTRL_RXEN) {
4134 if (hw->mac.type != ixgbe_mac_82598EB) {
4135 u32 pfdtxgswc;
4136
4137 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4138 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
4139 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4140 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4141 hw->mac.set_lben = true;
4142 } else {
4143 hw->mac.set_lben = false;
4144 }
4145 }
4146 rxctrl &= ~IXGBE_RXCTRL_RXEN;
4147 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
4148 }
4149 }
4150
ixgbe_enable_rx_generic(struct ixgbe_hw * hw)4151 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
4152 {
4153 u32 rxctrl;
4154
4155 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4156 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
4157
4158 if (hw->mac.type != ixgbe_mac_82598EB) {
4159 if (hw->mac.set_lben) {
4160 u32 pfdtxgswc;
4161
4162 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4163 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
4164 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4165 hw->mac.set_lben = false;
4166 }
4167 }
4168 }
4169
4170 /** ixgbe_mng_present - returns true when management capability is present
4171 * @hw: pointer to hardware structure
4172 **/
ixgbe_mng_present(struct ixgbe_hw * hw)4173 bool ixgbe_mng_present(struct ixgbe_hw *hw)
4174 {
4175 u32 fwsm;
4176
4177 if (hw->mac.type < ixgbe_mac_82599EB)
4178 return false;
4179
4180 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
4181
4182 return !!(fwsm & IXGBE_FWSM_FW_MODE_PT);
4183 }
4184
4185 /**
4186 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
4187 * @hw: pointer to hardware structure
4188 * @speed: new link speed
4189 * @autoneg_wait_to_complete: true when waiting for completion is needed
4190 *
4191 * Set the link speed in the MAC and/or PHY register and restarts link.
4192 */
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait_to_complete)4193 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
4194 ixgbe_link_speed speed,
4195 bool autoneg_wait_to_complete)
4196 {
4197 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4198 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4199 s32 status = 0;
4200 u32 speedcnt = 0;
4201 u32 i = 0;
4202 bool autoneg, link_up = false;
4203
4204 /* Mask off requested but non-supported speeds */
4205 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, &autoneg);
4206 if (status)
4207 return status;
4208
4209 speed &= link_speed;
4210
4211 /* Try each speed one by one, highest priority first. We do this in
4212 * software because 10Gb fiber doesn't support speed autonegotiation.
4213 */
4214 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
4215 speedcnt++;
4216 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
4217
4218 /* Set the module link speed */
4219 switch (hw->phy.media_type) {
4220 case ixgbe_media_type_fiber:
4221 hw->mac.ops.set_rate_select_speed(hw,
4222 IXGBE_LINK_SPEED_10GB_FULL);
4223 break;
4224 case ixgbe_media_type_fiber_qsfp:
4225 /* QSFP module automatically detects MAC link speed */
4226 break;
4227 default:
4228 hw_dbg(hw, "Unexpected media type\n");
4229 break;
4230 }
4231
4232 /* Allow module to change analog characteristics (1G->10G) */
4233 msleep(40);
4234
4235 status = hw->mac.ops.setup_mac_link(hw,
4236 IXGBE_LINK_SPEED_10GB_FULL,
4237 autoneg_wait_to_complete);
4238 if (status)
4239 return status;
4240
4241 /* Flap the Tx laser if it has not already been done */
4242 if (hw->mac.ops.flap_tx_laser)
4243 hw->mac.ops.flap_tx_laser(hw);
4244
4245 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
4246 * Section 73.10.2, we may have to wait up to 500ms if KR is
4247 * attempted. 82599 uses the same timing for 10g SFI.
4248 */
4249 for (i = 0; i < 5; i++) {
4250 /* Wait for the link partner to also set speed */
4251 msleep(100);
4252
4253 /* If we have link, just jump out */
4254 status = hw->mac.ops.check_link(hw, &link_speed,
4255 &link_up, false);
4256 if (status)
4257 return status;
4258
4259 if (link_up)
4260 goto out;
4261 }
4262 }
4263
4264 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
4265 speedcnt++;
4266 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
4267 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
4268
4269 /* Set the module link speed */
4270 switch (hw->phy.media_type) {
4271 case ixgbe_media_type_fiber:
4272 hw->mac.ops.set_rate_select_speed(hw,
4273 IXGBE_LINK_SPEED_1GB_FULL);
4274 break;
4275 case ixgbe_media_type_fiber_qsfp:
4276 /* QSFP module automatically detects link speed */
4277 break;
4278 default:
4279 hw_dbg(hw, "Unexpected media type\n");
4280 break;
4281 }
4282
4283 /* Allow module to change analog characteristics (10G->1G) */
4284 msleep(40);
4285
4286 status = hw->mac.ops.setup_mac_link(hw,
4287 IXGBE_LINK_SPEED_1GB_FULL,
4288 autoneg_wait_to_complete);
4289 if (status)
4290 return status;
4291
4292 /* Flap the Tx laser if it has not already been done */
4293 if (hw->mac.ops.flap_tx_laser)
4294 hw->mac.ops.flap_tx_laser(hw);
4295
4296 /* Wait for the link partner to also set speed */
4297 msleep(100);
4298
4299 /* If we have link, just jump out */
4300 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
4301 false);
4302 if (status)
4303 return status;
4304
4305 if (link_up)
4306 goto out;
4307 }
4308
4309 /* We didn't get link. Configure back to the highest speed we tried,
4310 * (if there was more than one). We call ourselves back with just the
4311 * single highest speed that the user requested.
4312 */
4313 if (speedcnt > 1)
4314 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
4315 highest_link_speed,
4316 autoneg_wait_to_complete);
4317
4318 out:
4319 /* Set autoneg_advertised value based on input link speed */
4320 hw->phy.autoneg_advertised = 0;
4321
4322 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4323 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
4324
4325 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
4326 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
4327
4328 return status;
4329 }
4330
4331 /**
4332 * ixgbe_set_soft_rate_select_speed - Set module link speed
4333 * @hw: pointer to hardware structure
4334 * @speed: link speed to set
4335 *
4336 * Set module link speed via the soft rate select.
4337 */
ixgbe_set_soft_rate_select_speed(struct ixgbe_hw * hw,ixgbe_link_speed speed)4338 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
4339 ixgbe_link_speed speed)
4340 {
4341 s32 status;
4342 u8 rs, eeprom_data;
4343
4344 switch (speed) {
4345 case IXGBE_LINK_SPEED_10GB_FULL:
4346 /* one bit mask same as setting on */
4347 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
4348 break;
4349 case IXGBE_LINK_SPEED_1GB_FULL:
4350 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
4351 break;
4352 default:
4353 hw_dbg(hw, "Invalid fixed module speed\n");
4354 return;
4355 }
4356
4357 /* Set RS0 */
4358 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
4359 IXGBE_I2C_EEPROM_DEV_ADDR2,
4360 &eeprom_data);
4361 if (status) {
4362 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n");
4363 return;
4364 }
4365
4366 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
4367
4368 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
4369 IXGBE_I2C_EEPROM_DEV_ADDR2,
4370 eeprom_data);
4371 if (status) {
4372 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n");
4373 return;
4374 }
4375
4376 /* Set RS1 */
4377 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
4378 IXGBE_I2C_EEPROM_DEV_ADDR2,
4379 &eeprom_data);
4380 if (status) {
4381 hw_dbg(hw, "Failed to read Rx Rate Select RS1\n");
4382 return;
4383 }
4384
4385 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
4386
4387 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
4388 IXGBE_I2C_EEPROM_DEV_ADDR2,
4389 eeprom_data);
4390 if (status) {
4391 hw_dbg(hw, "Failed to write Rx Rate Select RS1\n");
4392 return;
4393 }
4394 }
4395