1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/sched.h>
30 #include <linux/wait.h>
31 #include <linux/gfp.h>
32
33 #include "iwl-prph.h"
34 #include "iwl-io.h"
35 #include "iwl-trans-pcie-int.h"
36 #include "iwl-op-mode.h"
37
38 #ifdef CONFIG_IWLWIFI_IDI
39 #include "iwl-amfh.h"
40 #endif
41
42 /******************************************************************************
43 *
44 * RX path functions
45 *
46 ******************************************************************************/
47
48 /*
49 * Rx theory of operation
50 *
51 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
52 * each of which point to Receive Buffers to be filled by the NIC. These get
53 * used not only for Rx frames, but for any command response or notification
54 * from the NIC. The driver and NIC manage the Rx buffers by means
55 * of indexes into the circular buffer.
56 *
57 * Rx Queue Indexes
58 * The host/firmware share two index registers for managing the Rx buffers.
59 *
60 * The READ index maps to the first position that the firmware may be writing
61 * to -- the driver can read up to (but not including) this position and get
62 * good data.
63 * The READ index is managed by the firmware once the card is enabled.
64 *
65 * The WRITE index maps to the last position the driver has read from -- the
66 * position preceding WRITE is the last slot the firmware can place a packet.
67 *
68 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
69 * WRITE = READ.
70 *
71 * During initialization, the host sets up the READ queue position to the first
72 * INDEX position, and WRITE to the last (READ - 1 wrapped)
73 *
74 * When the firmware places a packet in a buffer, it will advance the READ index
75 * and fire the RX interrupt. The driver can then query the READ index and
76 * process as many packets as possible, moving the WRITE index forward as it
77 * resets the Rx queue buffers with new memory.
78 *
79 * The management in the driver is as follows:
80 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
81 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
82 * to replenish the iwl->rxq->rx_free.
83 * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
84 * iwl->rxq is replenished and the READ INDEX is updated (updating the
85 * 'processed' and 'read' driver indexes as well)
86 * + A received packet is processed and handed to the kernel network stack,
87 * detached from the iwl->rxq. The driver 'processed' index is updated.
88 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
89 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
90 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
91 * were enough free buffers and RX_STALLED is set it is cleared.
92 *
93 *
94 * Driver sequence:
95 *
96 * iwl_rx_queue_alloc() Allocates rx_free
97 * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls
98 * iwl_rx_queue_restock
99 * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
100 * queue, updates firmware pointers, and updates
101 * the WRITE index. If insufficient rx_free buffers
102 * are available, schedules iwl_rx_replenish
103 *
104 * -- enable interrupts --
105 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
106 * READ INDEX, detaching the SKB from the pool.
107 * Moves the packet buffer from queue to rx_used.
108 * Calls iwl_rx_queue_restock to refill any empty
109 * slots.
110 * ...
111 *
112 */
113
114 /**
115 * iwl_rx_queue_space - Return number of free slots available in queue.
116 */
iwl_rx_queue_space(const struct iwl_rx_queue * q)117 static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
118 {
119 int s = q->read - q->write;
120 if (s <= 0)
121 s += RX_QUEUE_SIZE;
122 /* keep some buffer to not confuse full and empty queue */
123 s -= 2;
124 if (s < 0)
125 s = 0;
126 return s;
127 }
128
129 /**
130 * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
131 */
iwl_rx_queue_update_write_ptr(struct iwl_trans * trans,struct iwl_rx_queue * q)132 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
133 struct iwl_rx_queue *q)
134 {
135 unsigned long flags;
136 u32 reg;
137
138 spin_lock_irqsave(&q->lock, flags);
139
140 if (q->need_update == 0)
141 goto exit_unlock;
142
143 if (cfg(trans)->base_params->shadow_reg_enable) {
144 /* shadow register enabled */
145 /* Device expects a multiple of 8 */
146 q->write_actual = (q->write & ~0x7);
147 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, q->write_actual);
148 } else {
149 /* If power-saving is in use, make sure device is awake */
150 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
151 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
152
153 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
154 IWL_DEBUG_INFO(trans,
155 "Rx queue requesting wakeup,"
156 " GP1 = 0x%x\n", reg);
157 iwl_set_bit(trans, CSR_GP_CNTRL,
158 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
159 goto exit_unlock;
160 }
161
162 q->write_actual = (q->write & ~0x7);
163 iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
164 q->write_actual);
165
166 /* Else device is assumed to be awake */
167 } else {
168 /* Device expects a multiple of 8 */
169 q->write_actual = (q->write & ~0x7);
170 iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
171 q->write_actual);
172 }
173 }
174 q->need_update = 0;
175
176 exit_unlock:
177 spin_unlock_irqrestore(&q->lock, flags);
178 }
179
180 /**
181 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
182 */
iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr)183 static inline __le32 iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr)
184 {
185 return cpu_to_le32((u32)(dma_addr >> 8));
186 }
187
188 /**
189 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
190 *
191 * If there are slots in the RX queue that need to be restocked,
192 * and we have free pre-allocated buffers, fill the ranks as much
193 * as we can, pulling from rx_free.
194 *
195 * This moves the 'write' index forward to catch up with 'processed', and
196 * also updates the memory address in the firmware to reference the new
197 * target buffer.
198 */
iwlagn_rx_queue_restock(struct iwl_trans * trans)199 static void iwlagn_rx_queue_restock(struct iwl_trans *trans)
200 {
201 struct iwl_trans_pcie *trans_pcie =
202 IWL_TRANS_GET_PCIE_TRANS(trans);
203
204 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
205 struct list_head *element;
206 struct iwl_rx_mem_buffer *rxb;
207 unsigned long flags;
208
209 spin_lock_irqsave(&rxq->lock, flags);
210 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
211 /* The overwritten rxb must be a used one */
212 rxb = rxq->queue[rxq->write];
213 BUG_ON(rxb && rxb->page);
214
215 /* Get next free Rx buffer, remove from free list */
216 element = rxq->rx_free.next;
217 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
218 list_del(element);
219
220 /* Point to Rx buffer via next RBD in circular buffer */
221 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(rxb->page_dma);
222 rxq->queue[rxq->write] = rxb;
223 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
224 rxq->free_count--;
225 }
226 spin_unlock_irqrestore(&rxq->lock, flags);
227 /* If the pre-allocated buffer pool is dropping low, schedule to
228 * refill it */
229 if (rxq->free_count <= RX_LOW_WATERMARK)
230 schedule_work(&trans_pcie->rx_replenish);
231
232
233 /* If we've added more space for the firmware to place data, tell it.
234 * Increment device's write pointer in multiples of 8. */
235 if (rxq->write_actual != (rxq->write & ~0x7)) {
236 spin_lock_irqsave(&rxq->lock, flags);
237 rxq->need_update = 1;
238 spin_unlock_irqrestore(&rxq->lock, flags);
239 iwl_rx_queue_update_write_ptr(trans, rxq);
240 }
241 }
242
243 /**
244 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
245 *
246 * When moving to rx_free an SKB is allocated for the slot.
247 *
248 * Also restock the Rx queue via iwl_rx_queue_restock.
249 * This is called as a scheduled work item (except for during initialization)
250 */
iwlagn_rx_allocate(struct iwl_trans * trans,gfp_t priority)251 static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority)
252 {
253 struct iwl_trans_pcie *trans_pcie =
254 IWL_TRANS_GET_PCIE_TRANS(trans);
255
256 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
257 struct list_head *element;
258 struct iwl_rx_mem_buffer *rxb;
259 struct page *page;
260 unsigned long flags;
261 gfp_t gfp_mask = priority;
262
263 while (1) {
264 spin_lock_irqsave(&rxq->lock, flags);
265 if (list_empty(&rxq->rx_used)) {
266 spin_unlock_irqrestore(&rxq->lock, flags);
267 return;
268 }
269 spin_unlock_irqrestore(&rxq->lock, flags);
270
271 if (rxq->free_count > RX_LOW_WATERMARK)
272 gfp_mask |= __GFP_NOWARN;
273
274 if (hw_params(trans).rx_page_order > 0)
275 gfp_mask |= __GFP_COMP;
276
277 /* Alloc a new receive buffer */
278 page = alloc_pages(gfp_mask,
279 hw_params(trans).rx_page_order);
280 if (!page) {
281 if (net_ratelimit())
282 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
283 "order: %d\n",
284 hw_params(trans).rx_page_order);
285
286 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
287 net_ratelimit())
288 IWL_CRIT(trans, "Failed to alloc_pages with %s."
289 "Only %u free buffers remaining.\n",
290 priority == GFP_ATOMIC ?
291 "GFP_ATOMIC" : "GFP_KERNEL",
292 rxq->free_count);
293 /* We don't reschedule replenish work here -- we will
294 * call the restock method and if it still needs
295 * more buffers it will schedule replenish */
296 return;
297 }
298
299 spin_lock_irqsave(&rxq->lock, flags);
300
301 if (list_empty(&rxq->rx_used)) {
302 spin_unlock_irqrestore(&rxq->lock, flags);
303 __free_pages(page, hw_params(trans).rx_page_order);
304 return;
305 }
306 element = rxq->rx_used.next;
307 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
308 list_del(element);
309
310 spin_unlock_irqrestore(&rxq->lock, flags);
311
312 BUG_ON(rxb->page);
313 rxb->page = page;
314 /* Get physical address of the RB */
315 rxb->page_dma = dma_map_page(trans->dev, page, 0,
316 PAGE_SIZE << hw_params(trans).rx_page_order,
317 DMA_FROM_DEVICE);
318 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
319 rxb->page = NULL;
320 spin_lock_irqsave(&rxq->lock, flags);
321 list_add(&rxb->list, &rxq->rx_used);
322 spin_unlock_irqrestore(&rxq->lock, flags);
323 __free_pages(page, hw_params(trans).rx_page_order);
324 return;
325 }
326 /* dma address must be no more than 36 bits */
327 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
328 /* and also 256 byte aligned! */
329 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
330
331 spin_lock_irqsave(&rxq->lock, flags);
332
333 list_add_tail(&rxb->list, &rxq->rx_free);
334 rxq->free_count++;
335
336 spin_unlock_irqrestore(&rxq->lock, flags);
337 }
338 }
339
iwlagn_rx_replenish(struct iwl_trans * trans)340 void iwlagn_rx_replenish(struct iwl_trans *trans)
341 {
342 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
343 unsigned long flags;
344
345 iwlagn_rx_allocate(trans, GFP_KERNEL);
346
347 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
348 iwlagn_rx_queue_restock(trans);
349 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
350 }
351
iwlagn_rx_replenish_now(struct iwl_trans * trans)352 static void iwlagn_rx_replenish_now(struct iwl_trans *trans)
353 {
354 iwlagn_rx_allocate(trans, GFP_ATOMIC);
355
356 iwlagn_rx_queue_restock(trans);
357 }
358
iwl_bg_rx_replenish(struct work_struct * data)359 void iwl_bg_rx_replenish(struct work_struct *data)
360 {
361 struct iwl_trans_pcie *trans_pcie =
362 container_of(data, struct iwl_trans_pcie, rx_replenish);
363
364 iwlagn_rx_replenish(trans_pcie->trans);
365 }
366
iwl_rx_handle_rxbuf(struct iwl_trans * trans,struct iwl_rx_mem_buffer * rxb)367 static void iwl_rx_handle_rxbuf(struct iwl_trans *trans,
368 struct iwl_rx_mem_buffer *rxb)
369 {
370 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
371 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
372 struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
373 struct iwl_device_cmd *cmd;
374 unsigned long flags;
375 int len, err;
376 u16 sequence;
377 struct iwl_rx_cmd_buffer rxcb;
378 struct iwl_rx_packet *pkt;
379 bool reclaim;
380 int index, cmd_index;
381
382 if (WARN_ON(!rxb))
383 return;
384
385 rxcb.truesize = PAGE_SIZE << hw_params(trans).rx_page_order;
386 dma_unmap_page(trans->dev, rxb->page_dma,
387 rxcb.truesize,
388 DMA_FROM_DEVICE);
389
390 rxcb._page = rxb->page;
391 pkt = rxb_addr(&rxcb);
392
393 IWL_DEBUG_RX(trans, "%s, 0x%02x\n",
394 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
395
396
397 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
398 len += sizeof(u32); /* account for status word */
399 trace_iwlwifi_dev_rx(trans->dev, pkt, len);
400
401 /* Reclaim a command buffer only if this packet is a response
402 * to a (driver-originated) command.
403 * If the packet (e.g. Rx frame) originated from uCode,
404 * there is no command buffer to reclaim.
405 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
406 * but apparently a few don't get set; catch them here. */
407 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
408 if (reclaim) {
409 int i;
410
411 for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
412 if (trans_pcie->no_reclaim_cmds[i] == pkt->hdr.cmd) {
413 reclaim = false;
414 break;
415 }
416 }
417 }
418
419 sequence = le16_to_cpu(pkt->hdr.sequence);
420 index = SEQ_TO_INDEX(sequence);
421 cmd_index = get_cmd_index(&txq->q, index);
422
423 if (reclaim)
424 cmd = txq->cmd[cmd_index];
425 else
426 cmd = NULL;
427
428 err = iwl_op_mode_rx(trans->op_mode, &rxcb, cmd);
429
430 /*
431 * XXX: After here, we should always check rxcb._page
432 * against NULL before touching it or its virtual
433 * memory (pkt). Because some rx_handler might have
434 * already taken or freed the pages.
435 */
436
437 if (reclaim) {
438 /* Invoke any callbacks, transfer the buffer to caller,
439 * and fire off the (possibly) blocking
440 * iwl_trans_send_cmd()
441 * as we reclaim the driver command queue */
442 if (rxcb._page)
443 iwl_tx_cmd_complete(trans, &rxcb, err);
444 else
445 IWL_WARN(trans, "Claim null rxb?\n");
446 }
447
448 /* page was stolen from us */
449 if (rxcb._page == NULL)
450 rxb->page = NULL;
451
452 /* Reuse the page if possible. For notification packets and
453 * SKBs that fail to Rx correctly, add them back into the
454 * rx_free list for reuse later. */
455 spin_lock_irqsave(&rxq->lock, flags);
456 if (rxb->page != NULL) {
457 rxb->page_dma =
458 dma_map_page(trans->dev, rxb->page, 0,
459 PAGE_SIZE << hw_params(trans).rx_page_order,
460 DMA_FROM_DEVICE);
461 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
462 /*
463 * free the page(s) as well to not break
464 * the invariant that the items on the used
465 * list have no page(s)
466 */
467 __free_pages(rxb->page, hw_params(trans).rx_page_order);
468 rxb->page = NULL;
469 list_add_tail(&rxb->list, &rxq->rx_used);
470 } else {
471 list_add_tail(&rxb->list, &rxq->rx_free);
472 rxq->free_count++;
473 }
474 } else
475 list_add_tail(&rxb->list, &rxq->rx_used);
476 spin_unlock_irqrestore(&rxq->lock, flags);
477 }
478
479 /**
480 * iwl_rx_handle - Main entry function for receiving responses from uCode
481 *
482 * Uses the priv->rx_handlers callback function array to invoke
483 * the appropriate handlers, including command responses,
484 * frame-received notifications, and other notifications.
485 */
iwl_rx_handle(struct iwl_trans * trans)486 static void iwl_rx_handle(struct iwl_trans *trans)
487 {
488 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
489 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
490 u32 r, i;
491 u8 fill_rx = 0;
492 u32 count = 8;
493 int total_empty;
494
495 /* uCode's read index (stored in shared DRAM) indicates the last Rx
496 * buffer that the driver may process (last buffer filled by ucode). */
497 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
498 i = rxq->read;
499
500 /* Rx interrupt, but nothing sent from uCode */
501 if (i == r)
502 IWL_DEBUG_RX(trans, "r = %d, i = %d\n", r, i);
503
504 /* calculate total frames need to be restock after handling RX */
505 total_empty = r - rxq->write_actual;
506 if (total_empty < 0)
507 total_empty += RX_QUEUE_SIZE;
508
509 if (total_empty > (RX_QUEUE_SIZE / 2))
510 fill_rx = 1;
511
512 while (i != r) {
513 struct iwl_rx_mem_buffer *rxb;
514
515 rxb = rxq->queue[i];
516 rxq->queue[i] = NULL;
517
518 IWL_DEBUG_RX(trans, "rxbuf: r = %d, i = %d (%p)\n", rxb);
519
520 iwl_rx_handle_rxbuf(trans, rxb);
521
522 i = (i + 1) & RX_QUEUE_MASK;
523 /* If there are a lot of unused frames,
524 * restock the Rx queue so ucode wont assert. */
525 if (fill_rx) {
526 count++;
527 if (count >= 8) {
528 rxq->read = i;
529 iwlagn_rx_replenish_now(trans);
530 count = 0;
531 }
532 }
533 }
534
535 /* Backtrack one entry */
536 rxq->read = i;
537 if (fill_rx)
538 iwlagn_rx_replenish_now(trans);
539 else
540 iwlagn_rx_queue_restock(trans);
541 }
542
543 static const char * const desc_lookup_text[] = {
544 "OK",
545 "FAIL",
546 "BAD_PARAM",
547 "BAD_CHECKSUM",
548 "NMI_INTERRUPT_WDG",
549 "SYSASSERT",
550 "FATAL_ERROR",
551 "BAD_COMMAND",
552 "HW_ERROR_TUNE_LOCK",
553 "HW_ERROR_TEMPERATURE",
554 "ILLEGAL_CHAN_FREQ",
555 "VCC_NOT_STABLE",
556 "FH_ERROR",
557 "NMI_INTERRUPT_HOST",
558 "NMI_INTERRUPT_ACTION_PT",
559 "NMI_INTERRUPT_UNKNOWN",
560 "UCODE_VERSION_MISMATCH",
561 "HW_ERROR_ABS_LOCK",
562 "HW_ERROR_CAL_LOCK_FAIL",
563 "NMI_INTERRUPT_INST_ACTION_PT",
564 "NMI_INTERRUPT_DATA_ACTION_PT",
565 "NMI_TRM_HW_ER",
566 "NMI_INTERRUPT_TRM",
567 "NMI_INTERRUPT_BREAK_POINT",
568 "DEBUG_0",
569 "DEBUG_1",
570 "DEBUG_2",
571 "DEBUG_3",
572 };
573
574 static struct { char *name; u8 num; } advanced_lookup[] = {
575 { "NMI_INTERRUPT_WDG", 0x34 },
576 { "SYSASSERT", 0x35 },
577 { "UCODE_VERSION_MISMATCH", 0x37 },
578 { "BAD_COMMAND", 0x38 },
579 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
580 { "FATAL_ERROR", 0x3D },
581 { "NMI_TRM_HW_ERR", 0x46 },
582 { "NMI_INTERRUPT_TRM", 0x4C },
583 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
584 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
585 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
586 { "NMI_INTERRUPT_HOST", 0x66 },
587 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
588 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
589 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
590 { "ADVANCED_SYSASSERT", 0 },
591 };
592
desc_lookup(u32 num)593 static const char *desc_lookup(u32 num)
594 {
595 int i;
596 int max = ARRAY_SIZE(desc_lookup_text);
597
598 if (num < max)
599 return desc_lookup_text[num];
600
601 max = ARRAY_SIZE(advanced_lookup) - 1;
602 for (i = 0; i < max; i++) {
603 if (advanced_lookup[i].num == num)
604 break;
605 }
606 return advanced_lookup[i].name;
607 }
608
609 #define ERROR_START_OFFSET (1 * sizeof(u32))
610 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
611
iwl_dump_nic_error_log(struct iwl_trans * trans)612 static void iwl_dump_nic_error_log(struct iwl_trans *trans)
613 {
614 u32 base;
615 struct iwl_error_event_table table;
616 struct iwl_trans_pcie *trans_pcie =
617 IWL_TRANS_GET_PCIE_TRANS(trans);
618
619 base = trans->shrd->device_pointers.error_event_table;
620 if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
621 if (!base)
622 base = trans->shrd->fw->init_errlog_ptr;
623 } else {
624 if (!base)
625 base = trans->shrd->fw->inst_errlog_ptr;
626 }
627
628 if (!iwlagn_hw_valid_rtc_data_addr(base)) {
629 IWL_ERR(trans,
630 "Not valid error log pointer 0x%08X for %s uCode\n",
631 base,
632 (trans->shrd->ucode_type == IWL_UCODE_INIT)
633 ? "Init" : "RT");
634 return;
635 }
636
637 iwl_read_targ_mem_words(trans, base, &table, sizeof(table));
638
639 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
640 IWL_ERR(trans, "Start IWL Error Log Dump:\n");
641 IWL_ERR(trans, "Status: 0x%08lX, count: %d\n",
642 trans->shrd->status, table.valid);
643 }
644
645 trans_pcie->isr_stats.err_code = table.error_id;
646
647 trace_iwlwifi_dev_ucode_error(trans->dev, table.error_id, table.tsf_low,
648 table.data1, table.data2, table.line,
649 table.blink1, table.blink2, table.ilink1,
650 table.ilink2, table.bcon_time, table.gp1,
651 table.gp2, table.gp3, table.ucode_ver,
652 table.hw_ver, table.brd_ver);
653 IWL_ERR(trans, "0x%08X | %-28s\n", table.error_id,
654 desc_lookup(table.error_id));
655 IWL_ERR(trans, "0x%08X | uPc\n", table.pc);
656 IWL_ERR(trans, "0x%08X | branchlink1\n", table.blink1);
657 IWL_ERR(trans, "0x%08X | branchlink2\n", table.blink2);
658 IWL_ERR(trans, "0x%08X | interruptlink1\n", table.ilink1);
659 IWL_ERR(trans, "0x%08X | interruptlink2\n", table.ilink2);
660 IWL_ERR(trans, "0x%08X | data1\n", table.data1);
661 IWL_ERR(trans, "0x%08X | data2\n", table.data2);
662 IWL_ERR(trans, "0x%08X | line\n", table.line);
663 IWL_ERR(trans, "0x%08X | beacon time\n", table.bcon_time);
664 IWL_ERR(trans, "0x%08X | tsf low\n", table.tsf_low);
665 IWL_ERR(trans, "0x%08X | tsf hi\n", table.tsf_hi);
666 IWL_ERR(trans, "0x%08X | time gp1\n", table.gp1);
667 IWL_ERR(trans, "0x%08X | time gp2\n", table.gp2);
668 IWL_ERR(trans, "0x%08X | time gp3\n", table.gp3);
669 IWL_ERR(trans, "0x%08X | uCode version\n", table.ucode_ver);
670 IWL_ERR(trans, "0x%08X | hw version\n", table.hw_ver);
671 IWL_ERR(trans, "0x%08X | board version\n", table.brd_ver);
672 IWL_ERR(trans, "0x%08X | hcmd\n", table.hcmd);
673
674 IWL_ERR(trans, "0x%08X | isr0\n", table.isr0);
675 IWL_ERR(trans, "0x%08X | isr1\n", table.isr1);
676 IWL_ERR(trans, "0x%08X | isr2\n", table.isr2);
677 IWL_ERR(trans, "0x%08X | isr3\n", table.isr3);
678 IWL_ERR(trans, "0x%08X | isr4\n", table.isr4);
679 IWL_ERR(trans, "0x%08X | isr_pref\n", table.isr_pref);
680 IWL_ERR(trans, "0x%08X | wait_event\n", table.wait_event);
681 IWL_ERR(trans, "0x%08X | l2p_control\n", table.l2p_control);
682 IWL_ERR(trans, "0x%08X | l2p_duration\n", table.l2p_duration);
683 IWL_ERR(trans, "0x%08X | l2p_mhvalid\n", table.l2p_mhvalid);
684 IWL_ERR(trans, "0x%08X | l2p_addr_match\n", table.l2p_addr_match);
685 IWL_ERR(trans, "0x%08X | lmpm_pmg_sel\n", table.lmpm_pmg_sel);
686 IWL_ERR(trans, "0x%08X | timestamp\n", table.u_timestamp);
687 IWL_ERR(trans, "0x%08X | flow_handler\n", table.flow_handler);
688 }
689
690 /**
691 * iwl_irq_handle_error - called for HW or SW error interrupt from card
692 */
iwl_irq_handle_error(struct iwl_trans * trans)693 static void iwl_irq_handle_error(struct iwl_trans *trans)
694 {
695 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
696 if (cfg(trans)->internal_wimax_coex &&
697 (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
698 APMS_CLK_VAL_MRB_FUNC_MODE) ||
699 (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
700 APMG_PS_CTRL_VAL_RESET_REQ))) {
701 /*
702 * Keep the restart process from trying to send host
703 * commands by clearing the ready bit.
704 */
705 clear_bit(STATUS_READY, &trans->shrd->status);
706 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
707 wake_up(&trans->wait_command_queue);
708 IWL_ERR(trans, "RF is used by WiMAX\n");
709 return;
710 }
711
712 IWL_ERR(trans, "Loaded firmware version: %s\n",
713 trans->shrd->fw->fw_version);
714
715 iwl_dump_nic_error_log(trans);
716 iwl_dump_csr(trans);
717 iwl_dump_fh(trans, NULL);
718 iwl_dump_nic_event_log(trans, false, NULL, false);
719
720 iwl_op_mode_nic_error(trans->op_mode);
721 }
722
723 #define EVENT_START_OFFSET (4 * sizeof(u32))
724
725 /**
726 * iwl_print_event_log - Dump error event log to syslog
727 *
728 */
iwl_print_event_log(struct iwl_trans * trans,u32 start_idx,u32 num_events,u32 mode,int pos,char ** buf,size_t bufsz)729 static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
730 u32 num_events, u32 mode,
731 int pos, char **buf, size_t bufsz)
732 {
733 u32 i;
734 u32 base; /* SRAM byte address of event log header */
735 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
736 u32 ptr; /* SRAM byte address of log data */
737 u32 ev, time, data; /* event log data */
738 unsigned long reg_flags;
739
740 if (num_events == 0)
741 return pos;
742
743 base = trans->shrd->device_pointers.log_event_table;
744 if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
745 if (!base)
746 base = trans->shrd->fw->init_evtlog_ptr;
747 } else {
748 if (!base)
749 base = trans->shrd->fw->inst_evtlog_ptr;
750 }
751
752 if (mode == 0)
753 event_size = 2 * sizeof(u32);
754 else
755 event_size = 3 * sizeof(u32);
756
757 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
758
759 /* Make sure device is powered up for SRAM reads */
760 spin_lock_irqsave(&trans->reg_lock, reg_flags);
761 if (unlikely(!iwl_grab_nic_access(trans)))
762 goto out_unlock;
763
764 /* Set starting address; reads will auto-increment */
765 iwl_write32(trans, HBUS_TARG_MEM_RADDR, ptr);
766
767 /* "time" is actually "data" for mode 0 (no timestamp).
768 * place event id # at far right for easier visual parsing. */
769 for (i = 0; i < num_events; i++) {
770 ev = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
771 time = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
772 if (mode == 0) {
773 /* data, ev */
774 if (bufsz) {
775 pos += scnprintf(*buf + pos, bufsz - pos,
776 "EVT_LOG:0x%08x:%04u\n",
777 time, ev);
778 } else {
779 trace_iwlwifi_dev_ucode_event(trans->dev, 0,
780 time, ev);
781 IWL_ERR(trans, "EVT_LOG:0x%08x:%04u\n",
782 time, ev);
783 }
784 } else {
785 data = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
786 if (bufsz) {
787 pos += scnprintf(*buf + pos, bufsz - pos,
788 "EVT_LOGT:%010u:0x%08x:%04u\n",
789 time, data, ev);
790 } else {
791 IWL_ERR(trans, "EVT_LOGT:%010u:0x%08x:%04u\n",
792 time, data, ev);
793 trace_iwlwifi_dev_ucode_event(trans->dev, time,
794 data, ev);
795 }
796 }
797 }
798
799 /* Allow device to power down */
800 iwl_release_nic_access(trans);
801 out_unlock:
802 spin_unlock_irqrestore(&trans->reg_lock, reg_flags);
803 return pos;
804 }
805
806 /**
807 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
808 */
iwl_print_last_event_logs(struct iwl_trans * trans,u32 capacity,u32 num_wraps,u32 next_entry,u32 size,u32 mode,int pos,char ** buf,size_t bufsz)809 static int iwl_print_last_event_logs(struct iwl_trans *trans, u32 capacity,
810 u32 num_wraps, u32 next_entry,
811 u32 size, u32 mode,
812 int pos, char **buf, size_t bufsz)
813 {
814 /*
815 * display the newest DEFAULT_LOG_ENTRIES entries
816 * i.e the entries just before the next ont that uCode would fill.
817 */
818 if (num_wraps) {
819 if (next_entry < size) {
820 pos = iwl_print_event_log(trans,
821 capacity - (size - next_entry),
822 size - next_entry, mode,
823 pos, buf, bufsz);
824 pos = iwl_print_event_log(trans, 0,
825 next_entry, mode,
826 pos, buf, bufsz);
827 } else
828 pos = iwl_print_event_log(trans, next_entry - size,
829 size, mode, pos, buf, bufsz);
830 } else {
831 if (next_entry < size) {
832 pos = iwl_print_event_log(trans, 0, next_entry,
833 mode, pos, buf, bufsz);
834 } else {
835 pos = iwl_print_event_log(trans, next_entry - size,
836 size, mode, pos, buf, bufsz);
837 }
838 }
839 return pos;
840 }
841
842 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
843
iwl_dump_nic_event_log(struct iwl_trans * trans,bool full_log,char ** buf,bool display)844 int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
845 char **buf, bool display)
846 {
847 u32 base; /* SRAM byte address of event log header */
848 u32 capacity; /* event log capacity in # entries */
849 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
850 u32 num_wraps; /* # times uCode wrapped to top of log */
851 u32 next_entry; /* index of next entry to be written by uCode */
852 u32 size; /* # entries that we'll print */
853 u32 logsize;
854 int pos = 0;
855 size_t bufsz = 0;
856
857 base = trans->shrd->device_pointers.log_event_table;
858 if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
859 logsize = trans->shrd->fw->init_evtlog_size;
860 if (!base)
861 base = trans->shrd->fw->init_evtlog_ptr;
862 } else {
863 logsize = trans->shrd->fw->inst_evtlog_size;
864 if (!base)
865 base = trans->shrd->fw->inst_evtlog_ptr;
866 }
867
868 if (!iwlagn_hw_valid_rtc_data_addr(base)) {
869 IWL_ERR(trans,
870 "Invalid event log pointer 0x%08X for %s uCode\n",
871 base,
872 (trans->shrd->ucode_type == IWL_UCODE_INIT)
873 ? "Init" : "RT");
874 return -EINVAL;
875 }
876
877 /* event log header */
878 capacity = iwl_read_targ_mem(trans, base);
879 mode = iwl_read_targ_mem(trans, base + (1 * sizeof(u32)));
880 num_wraps = iwl_read_targ_mem(trans, base + (2 * sizeof(u32)));
881 next_entry = iwl_read_targ_mem(trans, base + (3 * sizeof(u32)));
882
883 if (capacity > logsize) {
884 IWL_ERR(trans, "Log capacity %d is bogus, limit to %d "
885 "entries\n", capacity, logsize);
886 capacity = logsize;
887 }
888
889 if (next_entry > logsize) {
890 IWL_ERR(trans, "Log write index %d is bogus, limit to %d\n",
891 next_entry, logsize);
892 next_entry = logsize;
893 }
894
895 size = num_wraps ? capacity : next_entry;
896
897 /* bail out if nothing in log */
898 if (size == 0) {
899 IWL_ERR(trans, "Start IWL Event Log Dump: nothing in log\n");
900 return pos;
901 }
902
903 #ifdef CONFIG_IWLWIFI_DEBUG
904 if (!(iwl_have_debug_level(IWL_DL_FW_ERRORS)) && !full_log)
905 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
906 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
907 #else
908 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
909 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
910 #endif
911 IWL_ERR(trans, "Start IWL Event Log Dump: display last %u entries\n",
912 size);
913
914 #ifdef CONFIG_IWLWIFI_DEBUG
915 if (display) {
916 if (full_log)
917 bufsz = capacity * 48;
918 else
919 bufsz = size * 48;
920 *buf = kmalloc(bufsz, GFP_KERNEL);
921 if (!*buf)
922 return -ENOMEM;
923 }
924 if (iwl_have_debug_level(IWL_DL_FW_ERRORS) || full_log) {
925 /*
926 * if uCode has wrapped back to top of log,
927 * start at the oldest entry,
928 * i.e the next one that uCode would fill.
929 */
930 if (num_wraps)
931 pos = iwl_print_event_log(trans, next_entry,
932 capacity - next_entry, mode,
933 pos, buf, bufsz);
934 /* (then/else) start at top of log */
935 pos = iwl_print_event_log(trans, 0,
936 next_entry, mode, pos, buf, bufsz);
937 } else
938 pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
939 next_entry, size, mode,
940 pos, buf, bufsz);
941 #else
942 pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
943 next_entry, size, mode,
944 pos, buf, bufsz);
945 #endif
946 return pos;
947 }
948
949 /* tasklet for iwlagn interrupt */
iwl_irq_tasklet(struct iwl_trans * trans)950 void iwl_irq_tasklet(struct iwl_trans *trans)
951 {
952 u32 inta = 0;
953 u32 handled = 0;
954 unsigned long flags;
955 u32 i;
956 #ifdef CONFIG_IWLWIFI_DEBUG
957 u32 inta_mask;
958 #endif
959
960 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
961 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
962
963
964 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
965
966 /* Ack/clear/reset pending uCode interrupts.
967 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
968 */
969 /* There is a hardware bug in the interrupt mask function that some
970 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
971 * they are disabled in the CSR_INT_MASK register. Furthermore the
972 * ICT interrupt handling mechanism has another bug that might cause
973 * these unmasked interrupts fail to be detected. We workaround the
974 * hardware bugs here by ACKing all the possible interrupts so that
975 * interrupt coalescing can still be achieved.
976 */
977 iwl_write32(trans, CSR_INT,
978 trans_pcie->inta | ~trans_pcie->inta_mask);
979
980 inta = trans_pcie->inta;
981
982 #ifdef CONFIG_IWLWIFI_DEBUG
983 if (iwl_have_debug_level(IWL_DL_ISR)) {
984 /* just for debug */
985 inta_mask = iwl_read32(trans, CSR_INT_MASK);
986 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n ",
987 inta, inta_mask);
988 }
989 #endif
990
991 /* saved interrupt in inta variable now we can reset trans_pcie->inta */
992 trans_pcie->inta = 0;
993
994 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
995
996 /* Now service all interrupt bits discovered above. */
997 if (inta & CSR_INT_BIT_HW_ERR) {
998 IWL_ERR(trans, "Hardware error detected. Restarting.\n");
999
1000 /* Tell the device to stop sending interrupts */
1001 iwl_disable_interrupts(trans);
1002
1003 isr_stats->hw++;
1004 iwl_irq_handle_error(trans);
1005
1006 handled |= CSR_INT_BIT_HW_ERR;
1007
1008 return;
1009 }
1010
1011 #ifdef CONFIG_IWLWIFI_DEBUG
1012 if (iwl_have_debug_level(IWL_DL_ISR)) {
1013 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1014 if (inta & CSR_INT_BIT_SCD) {
1015 IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
1016 "the frame/frames.\n");
1017 isr_stats->sch++;
1018 }
1019
1020 /* Alive notification via Rx interrupt will do the real work */
1021 if (inta & CSR_INT_BIT_ALIVE) {
1022 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1023 isr_stats->alive++;
1024 }
1025 }
1026 #endif
1027 /* Safely ignore these bits for debug checks below */
1028 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1029
1030 /* HW RF KILL switch toggled */
1031 if (inta & CSR_INT_BIT_RF_KILL) {
1032 bool hw_rfkill;
1033
1034 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1035 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1036 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1037 hw_rfkill ? "disable radio" : "enable radio");
1038
1039 isr_stats->rfkill++;
1040
1041 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1042
1043 handled |= CSR_INT_BIT_RF_KILL;
1044 }
1045
1046 /* Chip got too hot and stopped itself */
1047 if (inta & CSR_INT_BIT_CT_KILL) {
1048 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1049 isr_stats->ctkill++;
1050 handled |= CSR_INT_BIT_CT_KILL;
1051 }
1052
1053 /* Error detected by uCode */
1054 if (inta & CSR_INT_BIT_SW_ERR) {
1055 IWL_ERR(trans, "Microcode SW error detected. "
1056 " Restarting 0x%X.\n", inta);
1057 isr_stats->sw++;
1058 iwl_irq_handle_error(trans);
1059 handled |= CSR_INT_BIT_SW_ERR;
1060 }
1061
1062 /* uCode wakes up after power-down sleep */
1063 if (inta & CSR_INT_BIT_WAKEUP) {
1064 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1065 iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
1066 for (i = 0; i < cfg(trans)->base_params->num_of_queues; i++)
1067 iwl_txq_update_write_ptr(trans,
1068 &trans_pcie->txq[i]);
1069
1070 isr_stats->wakeup++;
1071
1072 handled |= CSR_INT_BIT_WAKEUP;
1073 }
1074
1075 /* All uCode command responses, including Tx command responses,
1076 * Rx "responses" (frame-received notification), and other
1077 * notifications from uCode come through here*/
1078 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1079 CSR_INT_BIT_RX_PERIODIC)) {
1080 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1081 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1082 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1083 iwl_write32(trans, CSR_FH_INT_STATUS,
1084 CSR_FH_INT_RX_MASK);
1085 }
1086 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1087 handled |= CSR_INT_BIT_RX_PERIODIC;
1088 iwl_write32(trans,
1089 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1090 }
1091 /* Sending RX interrupt require many steps to be done in the
1092 * the device:
1093 * 1- write interrupt to current index in ICT table.
1094 * 2- dma RX frame.
1095 * 3- update RX shared data to indicate last write index.
1096 * 4- send interrupt.
1097 * This could lead to RX race, driver could receive RX interrupt
1098 * but the shared data changes does not reflect this;
1099 * periodic interrupt will detect any dangling Rx activity.
1100 */
1101
1102 /* Disable periodic interrupt; we use it as just a one-shot. */
1103 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1104 CSR_INT_PERIODIC_DIS);
1105 #ifdef CONFIG_IWLWIFI_IDI
1106 iwl_amfh_rx_handler();
1107 #else
1108 iwl_rx_handle(trans);
1109 #endif
1110 /*
1111 * Enable periodic interrupt in 8 msec only if we received
1112 * real RX interrupt (instead of just periodic int), to catch
1113 * any dangling Rx interrupt. If it was just the periodic
1114 * interrupt, there was no dangling Rx activity, and no need
1115 * to extend the periodic interrupt; one-shot is enough.
1116 */
1117 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1118 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1119 CSR_INT_PERIODIC_ENA);
1120
1121 isr_stats->rx++;
1122 }
1123
1124 /* This "Tx" DMA channel is used only for loading uCode */
1125 if (inta & CSR_INT_BIT_FH_TX) {
1126 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1127 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1128 isr_stats->tx++;
1129 handled |= CSR_INT_BIT_FH_TX;
1130 /* Wake up uCode load routine, now that load is complete */
1131 trans_pcie->ucode_write_complete = true;
1132 wake_up(&trans_pcie->ucode_write_waitq);
1133 }
1134
1135 if (inta & ~handled) {
1136 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1137 isr_stats->unhandled++;
1138 }
1139
1140 if (inta & ~(trans_pcie->inta_mask)) {
1141 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1142 inta & ~trans_pcie->inta_mask);
1143 }
1144
1145 /* Re-enable all interrupts */
1146 /* only Re-enable if disabled by irq */
1147 if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status))
1148 iwl_enable_interrupts(trans);
1149 /* Re-enable RF_KILL if it occurred */
1150 else if (handled & CSR_INT_BIT_RF_KILL)
1151 iwl_enable_rfkill_int(trans);
1152 }
1153
1154 /******************************************************************************
1155 *
1156 * ICT functions
1157 *
1158 ******************************************************************************/
1159
1160 /* a device (PCI-E) page is 4096 bytes long */
1161 #define ICT_SHIFT 12
1162 #define ICT_SIZE (1 << ICT_SHIFT)
1163 #define ICT_COUNT (ICT_SIZE / sizeof(u32))
1164
1165 /* Free dram table */
iwl_free_isr_ict(struct iwl_trans * trans)1166 void iwl_free_isr_ict(struct iwl_trans *trans)
1167 {
1168 struct iwl_trans_pcie *trans_pcie =
1169 IWL_TRANS_GET_PCIE_TRANS(trans);
1170
1171 if (trans_pcie->ict_tbl) {
1172 dma_free_coherent(trans->dev, ICT_SIZE,
1173 trans_pcie->ict_tbl,
1174 trans_pcie->ict_tbl_dma);
1175 trans_pcie->ict_tbl = NULL;
1176 trans_pcie->ict_tbl_dma = 0;
1177 }
1178 }
1179
1180
1181 /*
1182 * allocate dram shared table, it is an aligned memory
1183 * block of ICT_SIZE.
1184 * also reset all data related to ICT table interrupt.
1185 */
iwl_alloc_isr_ict(struct iwl_trans * trans)1186 int iwl_alloc_isr_ict(struct iwl_trans *trans)
1187 {
1188 struct iwl_trans_pcie *trans_pcie =
1189 IWL_TRANS_GET_PCIE_TRANS(trans);
1190
1191 trans_pcie->ict_tbl =
1192 dma_alloc_coherent(trans->dev, ICT_SIZE,
1193 &trans_pcie->ict_tbl_dma,
1194 GFP_KERNEL);
1195 if (!trans_pcie->ict_tbl)
1196 return -ENOMEM;
1197
1198 /* just an API sanity check ... it is guaranteed to be aligned */
1199 if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1200 iwl_free_isr_ict(trans);
1201 return -EINVAL;
1202 }
1203
1204 IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
1205 (unsigned long long)trans_pcie->ict_tbl_dma);
1206
1207 IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);
1208
1209 /* reset table and index to all 0 */
1210 memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1211 trans_pcie->ict_index = 0;
1212
1213 /* add periodic RX interrupt */
1214 trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
1215 return 0;
1216 }
1217
1218 /* Device is going up inform it about using ICT interrupt table,
1219 * also we need to tell the driver to start using ICT interrupt.
1220 */
iwl_reset_ict(struct iwl_trans * trans)1221 void iwl_reset_ict(struct iwl_trans *trans)
1222 {
1223 u32 val;
1224 unsigned long flags;
1225 struct iwl_trans_pcie *trans_pcie =
1226 IWL_TRANS_GET_PCIE_TRANS(trans);
1227
1228 if (!trans_pcie->ict_tbl)
1229 return;
1230
1231 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1232 iwl_disable_interrupts(trans);
1233
1234 memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1235
1236 val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1237
1238 val |= CSR_DRAM_INT_TBL_ENABLE;
1239 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1240
1241 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1242
1243 iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
1244 trans_pcie->use_ict = true;
1245 trans_pcie->ict_index = 0;
1246 iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
1247 iwl_enable_interrupts(trans);
1248 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1249 }
1250
1251 /* Device is going down disable ict interrupt usage */
iwl_disable_ict(struct iwl_trans * trans)1252 void iwl_disable_ict(struct iwl_trans *trans)
1253 {
1254 struct iwl_trans_pcie *trans_pcie =
1255 IWL_TRANS_GET_PCIE_TRANS(trans);
1256
1257 unsigned long flags;
1258
1259 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1260 trans_pcie->use_ict = false;
1261 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1262 }
1263
iwl_isr(int irq,void * data)1264 static irqreturn_t iwl_isr(int irq, void *data)
1265 {
1266 struct iwl_trans *trans = data;
1267 struct iwl_trans_pcie *trans_pcie;
1268 u32 inta, inta_mask;
1269 unsigned long flags;
1270 #ifdef CONFIG_IWLWIFI_DEBUG
1271 u32 inta_fh;
1272 #endif
1273 if (!trans)
1274 return IRQ_NONE;
1275
1276 trace_iwlwifi_dev_irq(trans->dev);
1277
1278 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1279
1280 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1281
1282 /* Disable (but don't clear!) interrupts here to avoid
1283 * back-to-back ISRs and sporadic interrupts from our NIC.
1284 * If we have something to service, the tasklet will re-enable ints.
1285 * If we *don't* have something, we'll re-enable before leaving here. */
1286 inta_mask = iwl_read32(trans, CSR_INT_MASK);
1287 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1288
1289 /* Discover which interrupts are active/pending */
1290 inta = iwl_read32(trans, CSR_INT);
1291
1292 if (inta & (~inta_mask)) {
1293 IWL_DEBUG_ISR(trans,
1294 "We got a masked interrupt (0x%08x)...Ack and ignore\n",
1295 inta & (~inta_mask));
1296 iwl_write32(trans, CSR_INT, inta & (~inta_mask));
1297 inta &= inta_mask;
1298 }
1299
1300 /* Ignore interrupt if there's nothing in NIC to service.
1301 * This may be due to IRQ shared with another device,
1302 * or due to sporadic interrupts thrown from our NIC. */
1303 if (!inta) {
1304 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1305 goto none;
1306 }
1307
1308 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1309 /* Hardware disappeared. It might have already raised
1310 * an interrupt */
1311 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1312 goto unplugged;
1313 }
1314
1315 #ifdef CONFIG_IWLWIFI_DEBUG
1316 if (iwl_have_debug_level(IWL_DL_ISR)) {
1317 inta_fh = iwl_read32(trans, CSR_FH_INT_STATUS);
1318 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
1319 "fh 0x%08x\n", inta, inta_mask, inta_fh);
1320 }
1321 #endif
1322
1323 trans_pcie->inta |= inta;
1324 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1325 if (likely(inta))
1326 tasklet_schedule(&trans_pcie->irq_tasklet);
1327 else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1328 !trans_pcie->inta)
1329 iwl_enable_interrupts(trans);
1330
1331 unplugged:
1332 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1333 return IRQ_HANDLED;
1334
1335 none:
1336 /* re-enable interrupts here since we don't have anything to service. */
1337 /* only Re-enable if disabled by irq and no schedules tasklet. */
1338 if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1339 !trans_pcie->inta)
1340 iwl_enable_interrupts(trans);
1341
1342 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1343 return IRQ_NONE;
1344 }
1345
1346 /* interrupt handler using ict table, with this interrupt driver will
1347 * stop using INTA register to get device's interrupt, reading this register
1348 * is expensive, device will write interrupts in ICT dram table, increment
1349 * index then will fire interrupt to driver, driver will OR all ICT table
1350 * entries from current index up to table entry with 0 value. the result is
1351 * the interrupt we need to service, driver will set the entries back to 0 and
1352 * set index.
1353 */
iwl_isr_ict(int irq,void * data)1354 irqreturn_t iwl_isr_ict(int irq, void *data)
1355 {
1356 struct iwl_trans *trans = data;
1357 struct iwl_trans_pcie *trans_pcie;
1358 u32 inta, inta_mask;
1359 u32 val = 0;
1360 u32 read;
1361 unsigned long flags;
1362
1363 if (!trans)
1364 return IRQ_NONE;
1365
1366 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1367
1368 /* dram interrupt table not set yet,
1369 * use legacy interrupt.
1370 */
1371 if (!trans_pcie->use_ict)
1372 return iwl_isr(irq, data);
1373
1374 trace_iwlwifi_dev_irq(trans->dev);
1375
1376 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1377
1378 /* Disable (but don't clear!) interrupts here to avoid
1379 * back-to-back ISRs and sporadic interrupts from our NIC.
1380 * If we have something to service, the tasklet will re-enable ints.
1381 * If we *don't* have something, we'll re-enable before leaving here.
1382 */
1383 inta_mask = iwl_read32(trans, CSR_INT_MASK);
1384 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1385
1386
1387 /* Ignore interrupt if there's nothing in NIC to service.
1388 * This may be due to IRQ shared with another device,
1389 * or due to sporadic interrupts thrown from our NIC. */
1390 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1391 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1392 if (!read) {
1393 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1394 goto none;
1395 }
1396
1397 /*
1398 * Collect all entries up to the first 0, starting from ict_index;
1399 * note we already read at ict_index.
1400 */
1401 do {
1402 val |= read;
1403 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1404 trans_pcie->ict_index, read);
1405 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1406 trans_pcie->ict_index =
1407 iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1408
1409 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1410 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1411 read);
1412 } while (read);
1413
1414 /* We should not get this value, just ignore it. */
1415 if (val == 0xffffffff)
1416 val = 0;
1417
1418 /*
1419 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1420 * (bit 15 before shifting it to 31) to clear when using interrupt
1421 * coalescing. fortunately, bits 18 and 19 stay set when this happens
1422 * so we use them to decide on the real state of the Rx bit.
1423 * In order words, bit 15 is set if bit 18 or bit 19 are set.
1424 */
1425 if (val & 0xC0000)
1426 val |= 0x8000;
1427
1428 inta = (0xff & val) | ((0xff00 & val) << 16);
1429 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1430 inta, inta_mask, val);
1431
1432 inta &= trans_pcie->inta_mask;
1433 trans_pcie->inta |= inta;
1434
1435 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1436 if (likely(inta))
1437 tasklet_schedule(&trans_pcie->irq_tasklet);
1438 else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1439 !trans_pcie->inta) {
1440 /* Allow interrupt if was disabled by this handler and
1441 * no tasklet was schedules, We should not enable interrupt,
1442 * tasklet will enable it.
1443 */
1444 iwl_enable_interrupts(trans);
1445 }
1446
1447 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1448 return IRQ_HANDLED;
1449
1450 none:
1451 /* re-enable interrupts here since we don't have anything to service.
1452 * only Re-enable if disabled by irq.
1453 */
1454 if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1455 !trans_pcie->inta)
1456 iwl_enable_interrupts(trans);
1457
1458 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1459 return IRQ_NONE;
1460 }
1461