1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/slab.h>
31 #include <linux/sched.h>
32
33 #include "iwl-debug.h"
34 #include "iwl-csr.h"
35 #include "iwl-prph.h"
36 #include "iwl-io.h"
37 #include "iwl-agn-hw.h"
38 #include "iwl-op-mode.h"
39 #include "iwl-trans-pcie-int.h"
40
41 #define IWL_TX_CRC_SIZE 4
42 #define IWL_TX_DELIMITER_SIZE 4
43
44 /*
45 * mac80211 queues, ACs, hardware queues, FIFOs.
46 *
47 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
48 *
49 * Mac80211 uses the following numbers, which we get as from it
50 * by way of skb_get_queue_mapping(skb):
51 *
52 * VO 0
53 * VI 1
54 * BE 2
55 * BK 3
56 *
57 *
58 * Regular (not A-MPDU) frames are put into hardware queues corresponding
59 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
60 * own queue per aggregation session (RA/TID combination), such queues are
61 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
62 * order to map frames to the right queue, we also need an AC->hw queue
63 * mapping. This is implemented here.
64 *
65 * Due to the way hw queues are set up (by the hw specific code), the AC->hw
66 * queue mapping is the identity mapping.
67 */
68
69 static const u8 tid_to_ac[] = {
70 IEEE80211_AC_BE,
71 IEEE80211_AC_BK,
72 IEEE80211_AC_BK,
73 IEEE80211_AC_BE,
74 IEEE80211_AC_VI,
75 IEEE80211_AC_VI,
76 IEEE80211_AC_VO,
77 IEEE80211_AC_VO
78 };
79
80
81 /**
82 * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
83 */
iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans * trans,struct iwl_tx_queue * txq,u16 byte_cnt)84 void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
85 struct iwl_tx_queue *txq,
86 u16 byte_cnt)
87 {
88 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
89 struct iwl_trans_pcie *trans_pcie =
90 IWL_TRANS_GET_PCIE_TRANS(trans);
91 int write_ptr = txq->q.write_ptr;
92 int txq_id = txq->q.id;
93 u8 sec_ctl = 0;
94 u8 sta_id = 0;
95 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
96 __le16 bc_ent;
97 struct iwl_tx_cmd *tx_cmd =
98 (struct iwl_tx_cmd *) txq->cmd[txq->q.write_ptr]->payload;
99
100 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
101
102 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
103
104 sta_id = tx_cmd->sta_id;
105 sec_ctl = tx_cmd->sec_ctl;
106
107 switch (sec_ctl & TX_CMD_SEC_MSK) {
108 case TX_CMD_SEC_CCM:
109 len += CCMP_MIC_LEN;
110 break;
111 case TX_CMD_SEC_TKIP:
112 len += TKIP_ICV_LEN;
113 break;
114 case TX_CMD_SEC_WEP:
115 len += WEP_IV_LEN + WEP_ICV_LEN;
116 break;
117 }
118
119 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
120
121 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
122
123 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
124 scd_bc_tbl[txq_id].
125 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
126 }
127
128 /**
129 * iwl_txq_update_write_ptr - Send new write index to hardware
130 */
iwl_txq_update_write_ptr(struct iwl_trans * trans,struct iwl_tx_queue * txq)131 void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq)
132 {
133 u32 reg = 0;
134 int txq_id = txq->q.id;
135
136 if (txq->need_update == 0)
137 return;
138
139 if (cfg(trans)->base_params->shadow_reg_enable) {
140 /* shadow register enabled */
141 iwl_write32(trans, HBUS_TARG_WRPTR,
142 txq->q.write_ptr | (txq_id << 8));
143 } else {
144 /* if we're trying to save power */
145 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
146 /* wake up nic if it's powered down ...
147 * uCode will wake up, and interrupt us again, so next
148 * time we'll skip this part. */
149 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
150
151 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
152 IWL_DEBUG_INFO(trans,
153 "Tx queue %d requesting wakeup,"
154 " GP1 = 0x%x\n", txq_id, reg);
155 iwl_set_bit(trans, CSR_GP_CNTRL,
156 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
157 return;
158 }
159
160 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
161 txq->q.write_ptr | (txq_id << 8));
162
163 /*
164 * else not in power-save mode,
165 * uCode will never sleep when we're
166 * trying to tx (during RFKILL, we're not trying to tx).
167 */
168 } else
169 iwl_write32(trans, HBUS_TARG_WRPTR,
170 txq->q.write_ptr | (txq_id << 8));
171 }
172 txq->need_update = 0;
173 }
174
iwl_tfd_tb_get_addr(struct iwl_tfd * tfd,u8 idx)175 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
176 {
177 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
178
179 dma_addr_t addr = get_unaligned_le32(&tb->lo);
180 if (sizeof(dma_addr_t) > sizeof(u32))
181 addr |=
182 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
183
184 return addr;
185 }
186
iwl_tfd_tb_get_len(struct iwl_tfd * tfd,u8 idx)187 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
188 {
189 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
190
191 return le16_to_cpu(tb->hi_n_len) >> 4;
192 }
193
iwl_tfd_set_tb(struct iwl_tfd * tfd,u8 idx,dma_addr_t addr,u16 len)194 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
195 dma_addr_t addr, u16 len)
196 {
197 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
198 u16 hi_n_len = len << 4;
199
200 put_unaligned_le32(addr, &tb->lo);
201 if (sizeof(dma_addr_t) > sizeof(u32))
202 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
203
204 tb->hi_n_len = cpu_to_le16(hi_n_len);
205
206 tfd->num_tbs = idx + 1;
207 }
208
iwl_tfd_get_num_tbs(struct iwl_tfd * tfd)209 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
210 {
211 return tfd->num_tbs & 0x1f;
212 }
213
iwlagn_unmap_tfd(struct iwl_trans * trans,struct iwl_cmd_meta * meta,struct iwl_tfd * tfd,enum dma_data_direction dma_dir)214 static void iwlagn_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta,
215 struct iwl_tfd *tfd, enum dma_data_direction dma_dir)
216 {
217 int i;
218 int num_tbs;
219
220 /* Sanity check on number of chunks */
221 num_tbs = iwl_tfd_get_num_tbs(tfd);
222
223 if (num_tbs >= IWL_NUM_OF_TBS) {
224 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
225 /* @todo issue fatal error, it is quite serious situation */
226 return;
227 }
228
229 /* Unmap tx_cmd */
230 if (num_tbs)
231 dma_unmap_single(trans->dev,
232 dma_unmap_addr(meta, mapping),
233 dma_unmap_len(meta, len),
234 DMA_BIDIRECTIONAL);
235
236 /* Unmap chunks, if any. */
237 for (i = 1; i < num_tbs; i++)
238 dma_unmap_single(trans->dev, iwl_tfd_tb_get_addr(tfd, i),
239 iwl_tfd_tb_get_len(tfd, i), dma_dir);
240
241 tfd->num_tbs = 0;
242 }
243
244 /**
245 * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
246 * @trans - transport private data
247 * @txq - tx queue
248 * @dma_dir - the direction of the DMA mapping
249 *
250 * Does NOT advance any TFD circular buffer read/write indexes
251 * Does NOT free the TFD itself (which is within circular buffer)
252 */
iwlagn_txq_free_tfd(struct iwl_trans * trans,struct iwl_tx_queue * txq,enum dma_data_direction dma_dir)253 void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
254 enum dma_data_direction dma_dir)
255 {
256 struct iwl_tfd *tfd_tmp = txq->tfds;
257
258 /* rd_ptr is bounded by n_bd and idx is bounded by n_window */
259 int rd_ptr = txq->q.read_ptr;
260 int idx = get_cmd_index(&txq->q, rd_ptr);
261
262 lockdep_assert_held(&txq->lock);
263
264 /* We have only q->n_window txq->entries, but we use q->n_bd tfds */
265 iwlagn_unmap_tfd(trans, &txq->meta[idx], &tfd_tmp[rd_ptr], dma_dir);
266
267 /* free SKB */
268 if (txq->skbs) {
269 struct sk_buff *skb;
270
271 skb = txq->skbs[idx];
272
273 /* Can be called from irqs-disabled context
274 * If skb is not NULL, it means that the whole queue is being
275 * freed and that the queue is not empty - free the skb
276 */
277 if (skb) {
278 iwl_op_mode_free_skb(trans->op_mode, skb);
279 txq->skbs[idx] = NULL;
280 }
281 }
282 }
283
iwlagn_txq_attach_buf_to_tfd(struct iwl_trans * trans,struct iwl_tx_queue * txq,dma_addr_t addr,u16 len,u8 reset)284 int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
285 struct iwl_tx_queue *txq,
286 dma_addr_t addr, u16 len,
287 u8 reset)
288 {
289 struct iwl_queue *q;
290 struct iwl_tfd *tfd, *tfd_tmp;
291 u32 num_tbs;
292
293 q = &txq->q;
294 tfd_tmp = txq->tfds;
295 tfd = &tfd_tmp[q->write_ptr];
296
297 if (reset)
298 memset(tfd, 0, sizeof(*tfd));
299
300 num_tbs = iwl_tfd_get_num_tbs(tfd);
301
302 /* Each TFD can point to a maximum 20 Tx buffers */
303 if (num_tbs >= IWL_NUM_OF_TBS) {
304 IWL_ERR(trans, "Error can not send more than %d chunks\n",
305 IWL_NUM_OF_TBS);
306 return -EINVAL;
307 }
308
309 if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
310 return -EINVAL;
311
312 if (unlikely(addr & ~IWL_TX_DMA_MASK))
313 IWL_ERR(trans, "Unaligned address = %llx\n",
314 (unsigned long long)addr);
315
316 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
317
318 return 0;
319 }
320
321 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
322 * DMA services
323 *
324 * Theory of operation
325 *
326 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
327 * of buffer descriptors, each of which points to one or more data buffers for
328 * the device to read from or fill. Driver and device exchange status of each
329 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
330 * entries in each circular buffer, to protect against confusing empty and full
331 * queue states.
332 *
333 * The device reads or writes the data in the queues via the device's several
334 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
335 *
336 * For Tx queue, there are low mark and high mark limits. If, after queuing
337 * the packet for Tx, free space become < low mark, Tx queue stopped. When
338 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
339 * Tx queue resumed.
340 *
341 ***************************************************/
342
iwl_queue_space(const struct iwl_queue * q)343 int iwl_queue_space(const struct iwl_queue *q)
344 {
345 int s = q->read_ptr - q->write_ptr;
346
347 if (q->read_ptr > q->write_ptr)
348 s -= q->n_bd;
349
350 if (s <= 0)
351 s += q->n_window;
352 /* keep some reserve to not confuse empty and full situations */
353 s -= 2;
354 if (s < 0)
355 s = 0;
356 return s;
357 }
358
359 /**
360 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
361 */
iwl_queue_init(struct iwl_queue * q,int count,int slots_num,u32 id)362 int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id)
363 {
364 q->n_bd = count;
365 q->n_window = slots_num;
366 q->id = id;
367
368 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
369 * and iwl_queue_dec_wrap are broken. */
370 if (WARN_ON(!is_power_of_2(count)))
371 return -EINVAL;
372
373 /* slots_num must be power-of-two size, otherwise
374 * get_cmd_index is broken. */
375 if (WARN_ON(!is_power_of_2(slots_num)))
376 return -EINVAL;
377
378 q->low_mark = q->n_window / 4;
379 if (q->low_mark < 4)
380 q->low_mark = 4;
381
382 q->high_mark = q->n_window / 8;
383 if (q->high_mark < 2)
384 q->high_mark = 2;
385
386 q->write_ptr = q->read_ptr = 0;
387
388 return 0;
389 }
390
iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans * trans,struct iwl_tx_queue * txq)391 static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
392 struct iwl_tx_queue *txq)
393 {
394 struct iwl_trans_pcie *trans_pcie =
395 IWL_TRANS_GET_PCIE_TRANS(trans);
396 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
397 int txq_id = txq->q.id;
398 int read_ptr = txq->q.read_ptr;
399 u8 sta_id = 0;
400 __le16 bc_ent;
401 struct iwl_tx_cmd *tx_cmd =
402 (struct iwl_tx_cmd *) txq->cmd[txq->q.read_ptr]->payload;
403
404 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
405
406 if (txq_id != trans_pcie->cmd_queue)
407 sta_id = tx_cmd->sta_id;
408
409 bc_ent = cpu_to_le16(1 | (sta_id << 12));
410 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
411
412 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
413 scd_bc_tbl[txq_id].
414 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
415 }
416
iwlagn_tx_queue_set_q2ratid(struct iwl_trans * trans,u16 ra_tid,u16 txq_id)417 static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid,
418 u16 txq_id)
419 {
420 u32 tbl_dw_addr;
421 u32 tbl_dw;
422 u16 scd_q2ratid;
423
424 struct iwl_trans_pcie *trans_pcie =
425 IWL_TRANS_GET_PCIE_TRANS(trans);
426
427 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
428
429 tbl_dw_addr = trans_pcie->scd_base_addr +
430 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
431
432 tbl_dw = iwl_read_targ_mem(trans, tbl_dw_addr);
433
434 if (txq_id & 0x1)
435 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
436 else
437 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
438
439 iwl_write_targ_mem(trans, tbl_dw_addr, tbl_dw);
440
441 return 0;
442 }
443
iwlagn_tx_queue_stop_scheduler(struct iwl_trans * trans,u16 txq_id)444 static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id)
445 {
446 /* Simply stop the queue, but don't change any configuration;
447 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
448 iwl_write_prph(trans,
449 SCD_QUEUE_STATUS_BITS(txq_id),
450 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
451 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
452 }
453
iwl_trans_set_wr_ptrs(struct iwl_trans * trans,int txq_id,u32 index)454 void iwl_trans_set_wr_ptrs(struct iwl_trans *trans,
455 int txq_id, u32 index)
456 {
457 IWL_DEBUG_TX_QUEUES(trans, "Q %d WrPtr: %d", txq_id, index & 0xff);
458 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
459 (index & 0xff) | (txq_id << 8));
460 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), index);
461 }
462
iwl_trans_tx_queue_set_status(struct iwl_trans * trans,struct iwl_tx_queue * txq,int tx_fifo_id,int scd_retry)463 void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
464 struct iwl_tx_queue *txq,
465 int tx_fifo_id, int scd_retry)
466 {
467 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
468 int txq_id = txq->q.id;
469 int active =
470 test_bit(txq_id, &trans_pcie->txq_ctx_active_msk) ? 1 : 0;
471
472 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
473 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
474 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
475 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
476 SCD_QUEUE_STTS_REG_MSK);
477
478 txq->sched_retry = scd_retry;
479
480 if (active)
481 IWL_DEBUG_TX_QUEUES(trans, "Activate %s Queue %d on FIFO %d\n",
482 scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
483 else
484 IWL_DEBUG_TX_QUEUES(trans, "Deactivate %s Queue %d\n",
485 scd_retry ? "BA" : "AC/CMD", txq_id);
486 }
487
get_ac_from_tid(u16 tid)488 static inline int get_ac_from_tid(u16 tid)
489 {
490 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
491 return tid_to_ac[tid];
492
493 /* no support for TIDs 8-15 yet */
494 return -EINVAL;
495 }
496
get_fifo_from_tid(struct iwl_trans_pcie * trans_pcie,u8 ctx,u16 tid)497 static inline int get_fifo_from_tid(struct iwl_trans_pcie *trans_pcie,
498 u8 ctx, u16 tid)
499 {
500 const u8 *ac_to_fifo = trans_pcie->ac_to_fifo[ctx];
501 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
502 return ac_to_fifo[tid_to_ac[tid]];
503
504 /* no support for TIDs 8-15 yet */
505 return -EINVAL;
506 }
507
is_agg_txqid_valid(struct iwl_trans * trans,int txq_id)508 static inline bool is_agg_txqid_valid(struct iwl_trans *trans, int txq_id)
509 {
510 if (txq_id < IWLAGN_FIRST_AMPDU_QUEUE)
511 return false;
512 return txq_id < (IWLAGN_FIRST_AMPDU_QUEUE +
513 hw_params(trans).num_ampdu_queues);
514 }
515
iwl_trans_pcie_tx_agg_setup(struct iwl_trans * trans,enum iwl_rxon_context_id ctx,int sta_id,int tid,int frame_limit,u16 ssn)516 void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans,
517 enum iwl_rxon_context_id ctx, int sta_id,
518 int tid, int frame_limit, u16 ssn)
519 {
520 int tx_fifo, txq_id;
521 u16 ra_tid;
522 unsigned long flags;
523
524 struct iwl_trans_pcie *trans_pcie =
525 IWL_TRANS_GET_PCIE_TRANS(trans);
526
527 if (WARN_ON(sta_id == IWL_INVALID_STATION))
528 return;
529 if (WARN_ON(tid >= IWL_MAX_TID_COUNT))
530 return;
531
532 tx_fifo = get_fifo_from_tid(trans_pcie, ctx, tid);
533 if (WARN_ON(tx_fifo < 0)) {
534 IWL_ERR(trans, "txq_agg_setup, bad fifo: %d\n", tx_fifo);
535 return;
536 }
537
538 txq_id = trans_pcie->agg_txq[sta_id][tid];
539 if (WARN_ON_ONCE(!is_agg_txqid_valid(trans, txq_id))) {
540 IWL_ERR(trans,
541 "queue number out of range: %d, must be %d to %d\n",
542 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
543 IWLAGN_FIRST_AMPDU_QUEUE +
544 hw_params(trans).num_ampdu_queues - 1);
545 return;
546 }
547
548 ra_tid = BUILD_RAxTID(sta_id, tid);
549
550 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
551
552 /* Stop this Tx queue before configuring it */
553 iwlagn_tx_queue_stop_scheduler(trans, txq_id);
554
555 /* Map receiver-address / traffic-ID to this queue */
556 iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id);
557
558 /* Set this queue as a chain-building queue */
559 iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, (1<<txq_id));
560
561 /* enable aggregations for the queue */
562 iwl_set_bits_prph(trans, SCD_AGGR_SEL, (1<<txq_id));
563
564 /* Place first TFD at index corresponding to start sequence number.
565 * Assumes that ssn_idx is valid (!= 0xFFF) */
566 trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff);
567 trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff);
568 iwl_trans_set_wr_ptrs(trans, txq_id, ssn);
569
570 /* Set up Tx window size and frame limit for this queue */
571 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
572 SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
573 sizeof(u32),
574 ((frame_limit <<
575 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
576 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
577 ((frame_limit <<
578 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
579 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
580
581 iwl_set_bits_prph(trans, SCD_INTERRUPT_MASK, (1 << txq_id));
582
583 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
584 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id],
585 tx_fifo, 1);
586
587 trans_pcie->txq[txq_id].sta_id = sta_id;
588 trans_pcie->txq[txq_id].tid = tid;
589
590 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
591 }
592
593 /*
594 * Find first available (lowest unused) Tx Queue, mark it "active".
595 * Called only when finding queue for aggregation.
596 * Should never return anything < 7, because they should already
597 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
598 */
iwlagn_txq_ctx_activate_free(struct iwl_trans * trans)599 static int iwlagn_txq_ctx_activate_free(struct iwl_trans *trans)
600 {
601 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
602 int txq_id;
603
604 for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
605 txq_id++)
606 if (!test_and_set_bit(txq_id,
607 &trans_pcie->txq_ctx_active_msk))
608 return txq_id;
609 return -1;
610 }
611
iwl_trans_pcie_tx_agg_alloc(struct iwl_trans * trans,int sta_id,int tid)612 int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans,
613 int sta_id, int tid)
614 {
615 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
616 int txq_id;
617
618 txq_id = iwlagn_txq_ctx_activate_free(trans);
619 if (txq_id == -1) {
620 IWL_ERR(trans, "No free aggregation queue available\n");
621 return -ENXIO;
622 }
623
624 trans_pcie->agg_txq[sta_id][tid] = txq_id;
625 iwl_set_swq_id(&trans_pcie->txq[txq_id], get_ac_from_tid(tid), txq_id);
626
627 return 0;
628 }
629
iwl_trans_pcie_tx_agg_disable(struct iwl_trans * trans,int sta_id,int tid)630 int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans, int sta_id, int tid)
631 {
632 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
633 u8 txq_id = trans_pcie->agg_txq[sta_id][tid];
634
635 if (WARN_ON_ONCE(!is_agg_txqid_valid(trans, txq_id))) {
636 IWL_ERR(trans,
637 "queue number out of range: %d, must be %d to %d\n",
638 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
639 IWLAGN_FIRST_AMPDU_QUEUE +
640 hw_params(trans).num_ampdu_queues - 1);
641 return -EINVAL;
642 }
643
644 iwlagn_tx_queue_stop_scheduler(trans, txq_id);
645
646 iwl_clear_bits_prph(trans, SCD_AGGR_SEL, (1 << txq_id));
647
648 trans_pcie->agg_txq[sta_id][tid] = 0;
649 trans_pcie->txq[txq_id].q.read_ptr = 0;
650 trans_pcie->txq[txq_id].q.write_ptr = 0;
651 /* supposes that ssn_idx is valid (!= 0xFFF) */
652 iwl_trans_set_wr_ptrs(trans, txq_id, 0);
653
654 iwl_clear_bits_prph(trans, SCD_INTERRUPT_MASK, (1 << txq_id));
655 iwl_txq_ctx_deactivate(trans_pcie, txq_id);
656 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], 0, 0);
657 return 0;
658 }
659
660 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
661
662 /**
663 * iwl_enqueue_hcmd - enqueue a uCode command
664 * @priv: device private data point
665 * @cmd: a point to the ucode command structure
666 *
667 * The function returns < 0 values to indicate the operation is
668 * failed. On success, it turns the index (> 0) of command in the
669 * command queue.
670 */
iwl_enqueue_hcmd(struct iwl_trans * trans,struct iwl_host_cmd * cmd)671 static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
672 {
673 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
674 struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
675 struct iwl_queue *q = &txq->q;
676 struct iwl_device_cmd *out_cmd;
677 struct iwl_cmd_meta *out_meta;
678 dma_addr_t phys_addr;
679 u32 idx;
680 u16 copy_size, cmd_size, dma_size;
681 bool had_nocopy = false;
682 int i;
683 u8 *cmd_dest;
684 const u8 *cmddata[IWL_MAX_CMD_TFDS];
685 u16 cmdlen[IWL_MAX_CMD_TFDS];
686 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
687 const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {};
688 int trace_lens[IWL_MAX_CMD_TFDS + 1] = {};
689 int trace_idx;
690 #endif
691
692 if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) {
693 IWL_WARN(trans, "fw recovery, no hcmd send\n");
694 return -EIO;
695 }
696
697 copy_size = sizeof(out_cmd->hdr);
698 cmd_size = sizeof(out_cmd->hdr);
699
700 /* need one for the header if the first is NOCOPY */
701 BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1);
702
703 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
704 cmddata[i] = cmd->data[i];
705 cmdlen[i] = cmd->len[i];
706
707 if (!cmd->len[i])
708 continue;
709
710 /* need at least IWL_HCMD_MIN_COPY_SIZE copied */
711 if (copy_size < IWL_HCMD_MIN_COPY_SIZE) {
712 int copy = IWL_HCMD_MIN_COPY_SIZE - copy_size;
713
714 if (copy > cmdlen[i])
715 copy = cmdlen[i];
716 cmdlen[i] -= copy;
717 cmddata[i] += copy;
718 copy_size += copy;
719 }
720
721 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
722 had_nocopy = true;
723 } else {
724 /* NOCOPY must not be followed by normal! */
725 if (WARN_ON(had_nocopy))
726 return -EINVAL;
727 copy_size += cmdlen[i];
728 }
729 cmd_size += cmd->len[i];
730 }
731
732 /*
733 * If any of the command structures end up being larger than
734 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
735 * allocated into separate TFDs, then we will need to
736 * increase the size of the buffers.
737 */
738 if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE))
739 return -EINVAL;
740
741 spin_lock_bh(&txq->lock);
742
743 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
744 spin_unlock_bh(&txq->lock);
745
746 IWL_ERR(trans, "No space in command queue\n");
747 iwl_op_mode_cmd_queue_full(trans->op_mode);
748 return -ENOSPC;
749 }
750
751 idx = get_cmd_index(q, q->write_ptr);
752 out_cmd = txq->cmd[idx];
753 out_meta = &txq->meta[idx];
754
755 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
756 if (cmd->flags & CMD_WANT_SKB)
757 out_meta->source = cmd;
758
759 /* set up the header */
760
761 out_cmd->hdr.cmd = cmd->id;
762 out_cmd->hdr.flags = 0;
763 out_cmd->hdr.sequence =
764 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
765 INDEX_TO_SEQ(q->write_ptr));
766
767 /* and copy the data that needs to be copied */
768
769 cmd_dest = out_cmd->payload;
770 copy_size = sizeof(out_cmd->hdr);
771 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
772 int copy = 0;
773
774 if (!cmd->len)
775 continue;
776
777 /* need at least IWL_HCMD_MIN_COPY_SIZE copied */
778 if (copy_size < IWL_HCMD_MIN_COPY_SIZE) {
779 copy = IWL_HCMD_MIN_COPY_SIZE - copy_size;
780
781 if (copy > cmd->len[i])
782 copy = cmd->len[i];
783 }
784
785 /* copy everything if not nocopy/dup */
786 if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
787 copy = cmd->len[i];
788
789 if (copy) {
790 memcpy(cmd_dest, cmd->data[i], copy);
791 cmd_dest += copy;
792 copy_size += copy;
793 }
794 }
795
796 IWL_DEBUG_HC(trans, "Sending command %s (#%x), seq: 0x%04X, "
797 "%d bytes at %d[%d]:%d\n",
798 get_cmd_string(out_cmd->hdr.cmd),
799 out_cmd->hdr.cmd,
800 le16_to_cpu(out_cmd->hdr.sequence), cmd_size,
801 q->write_ptr, idx, trans_pcie->cmd_queue);
802
803 /*
804 * If the entire command is smaller than IWL_HCMD_MIN_COPY_SIZE, we must
805 * still map at least that many bytes for the hardware to write back to.
806 * We have enough space, so that's not a problem.
807 */
808 dma_size = max_t(u16, copy_size, IWL_HCMD_MIN_COPY_SIZE);
809
810 phys_addr = dma_map_single(trans->dev, &out_cmd->hdr, dma_size,
811 DMA_BIDIRECTIONAL);
812 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
813 idx = -ENOMEM;
814 goto out;
815 }
816
817 dma_unmap_addr_set(out_meta, mapping, phys_addr);
818 dma_unmap_len_set(out_meta, len, dma_size);
819
820 iwlagn_txq_attach_buf_to_tfd(trans, txq,
821 phys_addr, copy_size, 1);
822 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
823 trace_bufs[0] = &out_cmd->hdr;
824 trace_lens[0] = copy_size;
825 trace_idx = 1;
826 #endif
827
828 /* map the remaining (adjusted) nocopy/dup fragments */
829 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
830 if (!cmdlen[i])
831 continue;
832 if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
833 continue;
834 phys_addr = dma_map_single(trans->dev,
835 (void *)cmddata[i],
836 cmdlen[i], DMA_BIDIRECTIONAL);
837 if (dma_mapping_error(trans->dev, phys_addr)) {
838 iwlagn_unmap_tfd(trans, out_meta,
839 &txq->tfds[q->write_ptr],
840 DMA_BIDIRECTIONAL);
841 idx = -ENOMEM;
842 goto out;
843 }
844
845 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
846 cmdlen[i], 0);
847 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
848 trace_bufs[trace_idx] = cmddata[i];
849 trace_lens[trace_idx] = cmdlen[i];
850 trace_idx++;
851 #endif
852 }
853
854 out_meta->flags = cmd->flags;
855
856 txq->need_update = 1;
857
858 /* check that tracing gets all possible blocks */
859 BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3);
860 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
861 trace_iwlwifi_dev_hcmd(trans->dev, cmd->flags,
862 trace_bufs[0], trace_lens[0],
863 trace_bufs[1], trace_lens[1],
864 trace_bufs[2], trace_lens[2]);
865 #endif
866
867 /* Increment and update queue's write index */
868 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
869 iwl_txq_update_write_ptr(trans, txq);
870
871 out:
872 spin_unlock_bh(&txq->lock);
873 return idx;
874 }
875
876 /**
877 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
878 *
879 * When FW advances 'R' index, all entries between old and new 'R' index
880 * need to be reclaimed. As result, some free space forms. If there is
881 * enough free space (> low mark), wake the stack that feeds us.
882 */
iwl_hcmd_queue_reclaim(struct iwl_trans * trans,int txq_id,int idx)883 static void iwl_hcmd_queue_reclaim(struct iwl_trans *trans, int txq_id,
884 int idx)
885 {
886 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
887 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
888 struct iwl_queue *q = &txq->q;
889 int nfreed = 0;
890
891 lockdep_assert_held(&txq->lock);
892
893 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
894 IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), "
895 "index %d is out of range [0-%d] %d %d.\n", __func__,
896 txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr);
897 return;
898 }
899
900 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
901 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
902
903 if (nfreed++ > 0) {
904 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", idx,
905 q->write_ptr, q->read_ptr);
906 iwl_op_mode_nic_error(trans->op_mode);
907 }
908
909 }
910 }
911
912 /**
913 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
914 * @rxb: Rx buffer to reclaim
915 * @handler_status: return value of the handler of the command
916 * (put in setup_rx_handlers)
917 *
918 * If an Rx buffer has an async callback associated with it the callback
919 * will be executed. The attached skb (if present) will only be freed
920 * if the callback returns 1
921 */
iwl_tx_cmd_complete(struct iwl_trans * trans,struct iwl_rx_cmd_buffer * rxb,int handler_status)922 void iwl_tx_cmd_complete(struct iwl_trans *trans, struct iwl_rx_cmd_buffer *rxb,
923 int handler_status)
924 {
925 struct iwl_rx_packet *pkt = rxb_addr(rxb);
926 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
927 int txq_id = SEQ_TO_QUEUE(sequence);
928 int index = SEQ_TO_INDEX(sequence);
929 int cmd_index;
930 struct iwl_device_cmd *cmd;
931 struct iwl_cmd_meta *meta;
932 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
933 struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
934
935 /* If a Tx command is being handled and it isn't in the actual
936 * command queue then there a command routing bug has been introduced
937 * in the queue management code. */
938 if (WARN(txq_id != trans_pcie->cmd_queue,
939 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
940 txq_id, trans_pcie->cmd_queue, sequence,
941 trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
942 trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
943 iwl_print_hex_error(trans, pkt, 32);
944 return;
945 }
946
947 spin_lock(&txq->lock);
948
949 cmd_index = get_cmd_index(&txq->q, index);
950 cmd = txq->cmd[cmd_index];
951 meta = &txq->meta[cmd_index];
952
953 txq->time_stamp = jiffies;
954
955 iwlagn_unmap_tfd(trans, meta, &txq->tfds[index],
956 DMA_BIDIRECTIONAL);
957
958 /* Input error checking is done when commands are added to queue. */
959 if (meta->flags & CMD_WANT_SKB) {
960 struct page *p = rxb_steal_page(rxb);
961
962 meta->source->resp_pkt = pkt;
963 meta->source->_rx_page_addr = (unsigned long)page_address(p);
964 meta->source->_rx_page_order = hw_params(trans).rx_page_order;
965 meta->source->handler_status = handler_status;
966 }
967
968 iwl_hcmd_queue_reclaim(trans, txq_id, index);
969
970 if (!(meta->flags & CMD_ASYNC)) {
971 if (!test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) {
972 IWL_WARN(trans,
973 "HCMD_ACTIVE already clear for command %s\n",
974 get_cmd_string(cmd->hdr.cmd));
975 }
976 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
977 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
978 get_cmd_string(cmd->hdr.cmd));
979 wake_up(&trans->wait_command_queue);
980 }
981
982 meta->flags = 0;
983
984 spin_unlock(&txq->lock);
985 }
986
987 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
988
iwl_send_cmd_async(struct iwl_trans * trans,struct iwl_host_cmd * cmd)989 static int iwl_send_cmd_async(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
990 {
991 int ret;
992
993 /* An asynchronous command can not expect an SKB to be set. */
994 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
995 return -EINVAL;
996
997
998 ret = iwl_enqueue_hcmd(trans, cmd);
999 if (ret < 0) {
1000 IWL_ERR(trans,
1001 "Error sending %s: enqueue_hcmd failed: %d\n",
1002 get_cmd_string(cmd->id), ret);
1003 return ret;
1004 }
1005 return 0;
1006 }
1007
iwl_send_cmd_sync(struct iwl_trans * trans,struct iwl_host_cmd * cmd)1008 static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1009 {
1010 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1011 int cmd_idx;
1012 int ret;
1013
1014 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1015 get_cmd_string(cmd->id));
1016
1017 if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) {
1018 IWL_ERR(trans, "Command %s failed: FW Error\n",
1019 get_cmd_string(cmd->id));
1020 return -EIO;
1021 }
1022
1023 if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE,
1024 &trans->shrd->status))) {
1025 IWL_ERR(trans, "Command %s: a command is already active!\n",
1026 get_cmd_string(cmd->id));
1027 return -EIO;
1028 }
1029
1030 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1031 get_cmd_string(cmd->id));
1032
1033 cmd_idx = iwl_enqueue_hcmd(trans, cmd);
1034 if (cmd_idx < 0) {
1035 ret = cmd_idx;
1036 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
1037 IWL_ERR(trans,
1038 "Error sending %s: enqueue_hcmd failed: %d\n",
1039 get_cmd_string(cmd->id), ret);
1040 return ret;
1041 }
1042
1043 ret = wait_event_timeout(trans->wait_command_queue,
1044 !test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status),
1045 HOST_COMPLETE_TIMEOUT);
1046 if (!ret) {
1047 if (test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) {
1048 struct iwl_tx_queue *txq =
1049 &trans_pcie->txq[trans_pcie->cmd_queue];
1050 struct iwl_queue *q = &txq->q;
1051
1052 IWL_ERR(trans,
1053 "Error sending %s: time out after %dms.\n",
1054 get_cmd_string(cmd->id),
1055 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1056
1057 IWL_ERR(trans,
1058 "Current CMD queue read_ptr %d write_ptr %d\n",
1059 q->read_ptr, q->write_ptr);
1060
1061 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
1062 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command"
1063 "%s\n", get_cmd_string(cmd->id));
1064 ret = -ETIMEDOUT;
1065 goto cancel;
1066 }
1067 }
1068
1069 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1070 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1071 get_cmd_string(cmd->id));
1072 ret = -EIO;
1073 goto cancel;
1074 }
1075
1076 return 0;
1077
1078 cancel:
1079 if (cmd->flags & CMD_WANT_SKB) {
1080 /*
1081 * Cancel the CMD_WANT_SKB flag for the cmd in the
1082 * TX cmd queue. Otherwise in case the cmd comes
1083 * in later, it will possibly set an invalid
1084 * address (cmd->meta.source).
1085 */
1086 trans_pcie->txq[trans_pcie->cmd_queue].meta[cmd_idx].flags &=
1087 ~CMD_WANT_SKB;
1088 }
1089
1090 if (cmd->resp_pkt) {
1091 iwl_free_resp(cmd);
1092 cmd->resp_pkt = NULL;
1093 }
1094
1095 return ret;
1096 }
1097
iwl_trans_pcie_send_cmd(struct iwl_trans * trans,struct iwl_host_cmd * cmd)1098 int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1099 {
1100 if (cmd->flags & CMD_ASYNC)
1101 return iwl_send_cmd_async(trans, cmd);
1102
1103 return iwl_send_cmd_sync(trans, cmd);
1104 }
1105
1106 /* Frees buffers until index _not_ inclusive */
iwl_tx_queue_reclaim(struct iwl_trans * trans,int txq_id,int index,struct sk_buff_head * skbs)1107 int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
1108 struct sk_buff_head *skbs)
1109 {
1110 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1111 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1112 struct iwl_queue *q = &txq->q;
1113 int last_to_free;
1114 int freed = 0;
1115
1116 /* This function is not meant to release cmd queue*/
1117 if (WARN_ON(txq_id == trans_pcie->cmd_queue))
1118 return 0;
1119
1120 lockdep_assert_held(&txq->lock);
1121
1122 /*Since we free until index _not_ inclusive, the one before index is
1123 * the last we will free. This one must be used */
1124 last_to_free = iwl_queue_dec_wrap(index, q->n_bd);
1125
1126 if ((index >= q->n_bd) ||
1127 (iwl_queue_used(q, last_to_free) == 0)) {
1128 IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), "
1129 "last_to_free %d is out of range [0-%d] %d %d.\n",
1130 __func__, txq_id, last_to_free, q->n_bd,
1131 q->write_ptr, q->read_ptr);
1132 return 0;
1133 }
1134
1135 if (WARN_ON(!skb_queue_empty(skbs)))
1136 return 0;
1137
1138 for (;
1139 q->read_ptr != index;
1140 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1141
1142 if (WARN_ON_ONCE(txq->skbs[txq->q.read_ptr] == NULL))
1143 continue;
1144
1145 __skb_queue_tail(skbs, txq->skbs[txq->q.read_ptr]);
1146
1147 txq->skbs[txq->q.read_ptr] = NULL;
1148
1149 iwlagn_txq_inval_byte_cnt_tbl(trans, txq);
1150
1151 iwlagn_txq_free_tfd(trans, txq, DMA_TO_DEVICE);
1152 freed++;
1153 }
1154 return freed;
1155 }
1156