1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2017 Intel Deutschland GmbH
4 * Copyright (C) 2018-2021 Intel Corporation
5 */
6 #include "iwl-trans.h"
7 #include "iwl-prph.h"
8 #include "iwl-context-info.h"
9 #include "iwl-context-info-gen3.h"
10 #include "internal.h"
11 #include "fw/dbg.h"
12
13 #define FW_RESET_TIMEOUT (HZ / 5)
14
15 /*
16 * Start up NIC's basic functionality after it has been reset
17 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
18 * NOTE: This does not load uCode nor start the embedded processor
19 */
iwl_pcie_gen2_apm_init(struct iwl_trans * trans)20 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)
21 {
22 int ret = 0;
23
24 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
25
26 /*
27 * Use "set_bit" below rather than "write", to preserve any hardware
28 * bits already set by default after reset.
29 */
30
31 /*
32 * Disable L0s without affecting L1;
33 * don't wait for ICH L0s (ICH bug W/A)
34 */
35 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
36 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
37
38 /* Set FH wait threshold to maximum (HW error during stress W/A) */
39 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
40
41 /*
42 * Enable HAP INTA (interrupt from management bus) to
43 * wake device's PCI Express link L1a -> L0s
44 */
45 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
46 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
47
48 iwl_pcie_apm_config(trans);
49
50 ret = iwl_finish_nic_init(trans);
51 if (ret)
52 return ret;
53
54 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
55
56 return 0;
57 }
58
iwl_pcie_gen2_apm_stop(struct iwl_trans * trans,bool op_mode_leave)59 static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
60 {
61 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
62
63 if (op_mode_leave) {
64 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
65 iwl_pcie_gen2_apm_init(trans);
66
67 /* inform ME that we are leaving */
68 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
69 CSR_RESET_LINK_PWR_MGMT_DISABLED);
70 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
71 CSR_HW_IF_CONFIG_REG_PREPARE |
72 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
73 mdelay(1);
74 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
75 CSR_RESET_LINK_PWR_MGMT_DISABLED);
76 mdelay(5);
77 }
78
79 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
80
81 /* Stop device's DMA activity */
82 iwl_pcie_apm_stop_master(trans);
83
84 iwl_trans_sw_reset(trans, false);
85
86 /*
87 * Clear "initialization complete" bit to move adapter from
88 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
89 */
90 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
91 iwl_clear_bit(trans, CSR_GP_CNTRL,
92 CSR_GP_CNTRL_REG_FLAG_MAC_INIT);
93 else
94 iwl_clear_bit(trans, CSR_GP_CNTRL,
95 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
96 }
97
iwl_trans_pcie_fw_reset_handshake(struct iwl_trans * trans)98 static void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans)
99 {
100 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
101 int ret;
102
103 trans_pcie->fw_reset_state = FW_RESET_REQUESTED;
104
105 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
106 iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,
107 UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE);
108 else if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210)
109 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
110 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
111 else
112 iwl_write32(trans, CSR_DOORBELL_VECTOR,
113 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
114
115 /* wait 200ms */
116 ret = wait_event_timeout(trans_pcie->fw_reset_waitq,
117 trans_pcie->fw_reset_state != FW_RESET_REQUESTED,
118 FW_RESET_TIMEOUT);
119 if (!ret || trans_pcie->fw_reset_state == FW_RESET_ERROR) {
120 IWL_INFO(trans,
121 "firmware didn't ACK the reset - continue anyway\n");
122 iwl_trans_fw_error(trans, true);
123 }
124
125 trans_pcie->fw_reset_state = FW_RESET_IDLE;
126 }
127
_iwl_trans_pcie_gen2_stop_device(struct iwl_trans * trans)128 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
129 {
130 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
131
132 lockdep_assert_held(&trans_pcie->mutex);
133
134 if (trans_pcie->is_down)
135 return;
136
137 if (trans->state >= IWL_TRANS_FW_STARTED)
138 if (trans_pcie->fw_reset_handshake)
139 iwl_trans_pcie_fw_reset_handshake(trans);
140
141 trans_pcie->is_down = true;
142
143 /* tell the device to stop sending interrupts */
144 iwl_disable_interrupts(trans);
145
146 /* device going down, Stop using ICT table */
147 iwl_pcie_disable_ict(trans);
148
149 /*
150 * If a HW restart happens during firmware loading,
151 * then the firmware loading might call this function
152 * and later it might be called again due to the
153 * restart. So don't process again if the device is
154 * already dead.
155 */
156 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
157 IWL_DEBUG_INFO(trans,
158 "DEVICE_ENABLED bit was set and is now cleared\n");
159 iwl_txq_gen2_tx_free(trans);
160 iwl_pcie_rx_stop(trans);
161 }
162
163 iwl_pcie_ctxt_info_free_paging(trans);
164 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
165 iwl_pcie_ctxt_info_gen3_free(trans, false);
166 else
167 iwl_pcie_ctxt_info_free(trans);
168
169 /* Stop the device, and put it in low power state */
170 iwl_pcie_gen2_apm_stop(trans, false);
171
172 /* re-take ownership to prevent other users from stealing the device */
173 iwl_trans_sw_reset(trans, true);
174
175 /*
176 * Upon stop, the IVAR table gets erased, so msi-x won't
177 * work. This causes a bug in RF-KILL flows, since the interrupt
178 * that enables radio won't fire on the correct irq, and the
179 * driver won't be able to handle the interrupt.
180 * Configure the IVAR table again after reset.
181 */
182 iwl_pcie_conf_msix_hw(trans_pcie);
183
184 /*
185 * Upon stop, the APM issues an interrupt if HW RF kill is set.
186 * This is a bug in certain verions of the hardware.
187 * Certain devices also keep sending HW RF kill interrupt all
188 * the time, unless the interrupt is ACKed even if the interrupt
189 * should be masked. Re-ACK all the interrupts here.
190 */
191 iwl_disable_interrupts(trans);
192
193 /* clear all status bits */
194 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
195 clear_bit(STATUS_INT_ENABLED, &trans->status);
196 clear_bit(STATUS_TPOWER_PMI, &trans->status);
197
198 /*
199 * Even if we stop the HW, we still want the RF kill
200 * interrupt
201 */
202 iwl_enable_rfkill_int(trans);
203 }
204
iwl_trans_pcie_gen2_stop_device(struct iwl_trans * trans)205 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
206 {
207 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
208 bool was_in_rfkill;
209
210 iwl_op_mode_time_point(trans->op_mode,
211 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,
212 NULL);
213
214 mutex_lock(&trans_pcie->mutex);
215 trans_pcie->opmode_down = true;
216 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
217 _iwl_trans_pcie_gen2_stop_device(trans);
218 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
219 mutex_unlock(&trans_pcie->mutex);
220 }
221
iwl_pcie_gen2_nic_init(struct iwl_trans * trans)222 static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)
223 {
224 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
225 int queue_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
226 trans->cfg->min_txq_size);
227
228 /* TODO: most of the logic can be removed in A0 - but not in Z0 */
229 spin_lock_bh(&trans_pcie->irq_lock);
230 iwl_pcie_gen2_apm_init(trans);
231 spin_unlock_bh(&trans_pcie->irq_lock);
232
233 iwl_op_mode_nic_config(trans->op_mode);
234
235 /* Allocate the RX queue, or reset if it is already allocated */
236 if (iwl_pcie_gen2_rx_init(trans))
237 return -ENOMEM;
238
239 /* Allocate or reset and init all Tx and Command queues */
240 if (iwl_txq_gen2_init(trans, trans->txqs.cmd.q_id, queue_size))
241 return -ENOMEM;
242
243 /* enable shadow regs in HW */
244 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
245 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
246
247 return 0;
248 }
249
iwl_pcie_get_rf_name(struct iwl_trans * trans)250 static void iwl_pcie_get_rf_name(struct iwl_trans *trans)
251 {
252 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
253 char *buf = trans_pcie->rf_name;
254 size_t buflen = sizeof(trans_pcie->rf_name);
255 size_t pos;
256 u32 version;
257
258 if (buf[0])
259 return;
260
261 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
262 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_JF):
263 pos = scnprintf(buf, buflen, "JF");
264 break;
265 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF):
266 pos = scnprintf(buf, buflen, "GF");
267 break;
268 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF4):
269 pos = scnprintf(buf, buflen, "GF4");
270 break;
271 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
272 pos = scnprintf(buf, buflen, "HR");
273 break;
274 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
275 pos = scnprintf(buf, buflen, "HR1");
276 break;
277 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
278 pos = scnprintf(buf, buflen, "HRCDB");
279 break;
280 default:
281 return;
282 }
283
284 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
285 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
286 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
287 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
288 version = iwl_read_prph(trans, CNVI_MBOX_C);
289 switch (version) {
290 case 0x20000:
291 pos += scnprintf(buf + pos, buflen - pos, " B3");
292 break;
293 case 0x120000:
294 pos += scnprintf(buf + pos, buflen - pos, " B5");
295 break;
296 default:
297 pos += scnprintf(buf + pos, buflen - pos,
298 " (0x%x)", version);
299 break;
300 }
301 break;
302 default:
303 break;
304 }
305
306 pos += scnprintf(buf + pos, buflen - pos, ", rfid=0x%x",
307 trans->hw_rf_id);
308
309 IWL_INFO(trans, "Detected RF %s\n", buf);
310
311 /*
312 * also add a \n for debugfs - need to do it after printing
313 * since our IWL_INFO machinery wants to see a static \n at
314 * the end of the string
315 */
316 pos += scnprintf(buf + pos, buflen - pos, "\n");
317 }
318
iwl_trans_pcie_gen2_fw_alive(struct iwl_trans * trans,u32 scd_addr)319 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr)
320 {
321 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
322
323 iwl_pcie_reset_ict(trans);
324
325 /* make sure all queue are not stopped/used */
326 memset(trans->txqs.queue_stopped, 0,
327 sizeof(trans->txqs.queue_stopped));
328 memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used));
329
330 /* now that we got alive we can free the fw image & the context info.
331 * paging memory cannot be freed included since FW will still use it
332 */
333 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
334 iwl_pcie_ctxt_info_gen3_free(trans, true);
335 else
336 iwl_pcie_ctxt_info_free(trans);
337
338 /*
339 * Re-enable all the interrupts, including the RF-Kill one, now that
340 * the firmware is alive.
341 */
342 iwl_enable_interrupts(trans);
343 mutex_lock(&trans_pcie->mutex);
344 iwl_pcie_check_hw_rf_kill(trans);
345
346 iwl_pcie_get_rf_name(trans);
347 mutex_unlock(&trans_pcie->mutex);
348 }
349
iwl_pcie_set_ltr(struct iwl_trans * trans)350 static void iwl_pcie_set_ltr(struct iwl_trans *trans)
351 {
352 u32 ltr_val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ |
353 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
354 CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) |
355 u32_encode_bits(250,
356 CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) |
357 CSR_LTR_LONG_VAL_AD_SNOOP_REQ |
358 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
359 CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) |
360 u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL);
361
362 /*
363 * To workaround hardware latency issues during the boot process,
364 * initialize the LTR to ~250 usec (see ltr_val above).
365 * The firmware initializes this again later (to a smaller value).
366 */
367 if ((trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210 ||
368 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) &&
369 !trans->trans_cfg->integrated) {
370 iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val);
371 } else if (trans->trans_cfg->integrated &&
372 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) {
373 iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL);
374 iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val);
375 }
376 }
377
iwl_trans_pcie_gen2_start_fw(struct iwl_trans * trans,const struct fw_img * fw,bool run_in_rfkill)378 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
379 const struct fw_img *fw, bool run_in_rfkill)
380 {
381 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
382 bool hw_rfkill;
383 int ret;
384
385 /* This may fail if AMT took ownership of the device */
386 if (iwl_pcie_prepare_card_hw(trans)) {
387 IWL_WARN(trans, "Exit HW not ready\n");
388 return -EIO;
389 }
390
391 iwl_enable_rfkill_int(trans);
392
393 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
394
395 /*
396 * We enabled the RF-Kill interrupt and the handler may very
397 * well be running. Disable the interrupts to make sure no other
398 * interrupt can be fired.
399 */
400 iwl_disable_interrupts(trans);
401
402 /* Make sure it finished running */
403 iwl_pcie_synchronize_irqs(trans);
404
405 mutex_lock(&trans_pcie->mutex);
406
407 /* If platform's RF_KILL switch is NOT set to KILL */
408 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
409 if (hw_rfkill && !run_in_rfkill) {
410 ret = -ERFKILL;
411 goto out;
412 }
413
414 /* Someone called stop_device, don't try to start_fw */
415 if (trans_pcie->is_down) {
416 IWL_WARN(trans,
417 "Can't start_fw since the HW hasn't been started\n");
418 ret = -EIO;
419 goto out;
420 }
421
422 /* make sure rfkill handshake bits are cleared */
423 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
424 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
425 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
426
427 /* clear (again), then enable host interrupts */
428 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
429
430 ret = iwl_pcie_gen2_nic_init(trans);
431 if (ret) {
432 IWL_ERR(trans, "Unable to init nic\n");
433 goto out;
434 }
435
436 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
437 ret = iwl_pcie_ctxt_info_gen3_init(trans, fw);
438 else
439 ret = iwl_pcie_ctxt_info_init(trans, fw);
440 if (ret)
441 goto out;
442
443 iwl_pcie_set_ltr(trans);
444
445 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
446 iwl_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE);
447 iwl_set_bit(trans, CSR_GP_CNTRL,
448 CSR_GP_CNTRL_REG_FLAG_ROM_START);
449 } else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
450 iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);
451 } else {
452 iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1);
453 }
454
455 /* re-check RF-Kill state since we may have missed the interrupt */
456 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
457 if (hw_rfkill && !run_in_rfkill)
458 ret = -ERFKILL;
459
460 out:
461 mutex_unlock(&trans_pcie->mutex);
462 return ret;
463 }
464