1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/slab.h>
33 #include <linux/init.h>
34
35 #include <net/mac80211.h>
36
37 #include "iwl-eeprom.h"
38 #include "iwl-dev.h"
39 #include "iwl-core.h"
40 #include "iwl-io.h"
41 #include "iwl-commands.h"
42 #include "iwl-debug.h"
43 #include "iwl-power.h"
44
45 /*
46 * Setting power level allows the card to go to sleep when not busy.
47 *
48 * We calculate a sleep command based on the required latency, which
49 * we get from mac80211. In order to handle thermal throttling, we can
50 * also use pre-defined power levels.
51 */
52
53 /*
54 * For now, keep using power level 1 instead of automatically
55 * adjusting ...
56 */
57 bool no_sleep_autoadjust = true;
58 module_param(no_sleep_autoadjust, bool, S_IRUGO);
59 MODULE_PARM_DESC(no_sleep_autoadjust,
60 "don't automatically adjust sleep level "
61 "according to maximum network latency");
62
63 /*
64 * This defines the old power levels. They are still used by default
65 * (level 1) and for thermal throttle (levels 3 through 5)
66 */
67
68 struct iwl_power_vec_entry {
69 struct iwl_powertable_cmd cmd;
70 u8 no_dtim; /* number of skip dtim */
71 };
72
73 #define IWL_DTIM_RANGE_0_MAX 2
74 #define IWL_DTIM_RANGE_1_MAX 10
75
76 #define NOSLP cpu_to_le16(0), 0, 0
77 #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
78 #define ASLP (IWL_POWER_POWER_SAVE_ENA_MSK | \
79 IWL_POWER_POWER_MANAGEMENT_ENA_MSK | \
80 IWL_POWER_ADVANCE_PM_ENA_MSK)
81 #define ASLP_TOUT(T) cpu_to_le32(T)
82 #define TU_TO_USEC 1024
83 #define SLP_TOUT(T) cpu_to_le32((T) * TU_TO_USEC)
84 #define SLP_VEC(X0, X1, X2, X3, X4) {cpu_to_le32(X0), \
85 cpu_to_le32(X1), \
86 cpu_to_le32(X2), \
87 cpu_to_le32(X3), \
88 cpu_to_le32(X4)}
89 /* default power management (not Tx power) table values */
90 /* for DTIM period 0 through IWL_DTIM_RANGE_0_MAX */
91 /* DTIM 0 - 2 */
92 static const struct iwl_power_vec_entry range_0[IWL_POWER_NUM] = {
93 {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 1, 2, 2, 0xFF)}, 0},
94 {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0},
95 {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 2, 2, 2, 0xFF)}, 0},
96 {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 2, 4, 4, 0xFF)}, 1},
97 {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 2, 4, 6, 0xFF)}, 2}
98 };
99
100
101 /* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
102 /* DTIM 3 - 10 */
103 static const struct iwl_power_vec_entry range_1[IWL_POWER_NUM] = {
104 {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
105 {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 3, 4, 7)}, 0},
106 {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 4, 6, 7, 9)}, 0},
107 {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 4, 6, 9, 10)}, 1},
108 {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 4, 6, 10, 10)}, 2}
109 };
110
111 /* for DTIM period > IWL_DTIM_RANGE_1_MAX */
112 /* DTIM 11 - */
113 static const struct iwl_power_vec_entry range_2[IWL_POWER_NUM] = {
114 {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
115 {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
116 {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
117 {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
118 {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
119 };
120
121 /* advance power management */
122 /* DTIM 0 - 2 */
123 static const struct iwl_power_vec_entry apm_range_0[IWL_POWER_NUM] = {
124 {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
125 SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
126 {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
127 SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
128 {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
129 SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
130 {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
131 SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
132 {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
133 SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2}
134 };
135
136
137 /* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
138 /* DTIM 3 - 10 */
139 static const struct iwl_power_vec_entry apm_range_1[IWL_POWER_NUM] = {
140 {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
141 SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
142 {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
143 SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
144 {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
145 SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
146 {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
147 SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
148 {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
149 SLP_VEC(1, 2, 6, 8, 0xFF), 0}, 2}
150 };
151
152 /* for DTIM period > IWL_DTIM_RANGE_1_MAX */
153 /* DTIM 11 - */
154 static const struct iwl_power_vec_entry apm_range_2[IWL_POWER_NUM] = {
155 {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
156 SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
157 {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
158 SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
159 {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
160 SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
161 {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
162 SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
163 {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
164 SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2}
165 };
166
iwl_static_sleep_cmd(struct iwl_priv * priv,struct iwl_powertable_cmd * cmd,enum iwl_power_level lvl,int period)167 static void iwl_static_sleep_cmd(struct iwl_priv *priv,
168 struct iwl_powertable_cmd *cmd,
169 enum iwl_power_level lvl, int period)
170 {
171 const struct iwl_power_vec_entry *table;
172 int max_sleep[IWL_POWER_VEC_SIZE] = { 0 };
173 int i;
174 u8 skip;
175 u32 slp_itrvl;
176
177 if (priv->cfg->adv_pm) {
178 table = apm_range_2;
179 if (period <= IWL_DTIM_RANGE_1_MAX)
180 table = apm_range_1;
181 if (period <= IWL_DTIM_RANGE_0_MAX)
182 table = apm_range_0;
183 } else {
184 table = range_2;
185 if (period <= IWL_DTIM_RANGE_1_MAX)
186 table = range_1;
187 if (period <= IWL_DTIM_RANGE_0_MAX)
188 table = range_0;
189 }
190
191 BUG_ON(lvl < 0 || lvl >= IWL_POWER_NUM);
192
193 *cmd = table[lvl].cmd;
194
195 if (period == 0) {
196 skip = 0;
197 period = 1;
198 for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
199 max_sleep[i] = 1;
200
201 } else {
202 skip = table[lvl].no_dtim;
203 for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
204 max_sleep[i] = le32_to_cpu(cmd->sleep_interval[i]);
205 max_sleep[IWL_POWER_VEC_SIZE - 1] = skip + 1;
206 }
207
208 slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
209 /* figure out the listen interval based on dtim period and skip */
210 if (slp_itrvl == 0xFF)
211 cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
212 cpu_to_le32(period * (skip + 1));
213
214 slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
215 if (slp_itrvl > period)
216 cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
217 cpu_to_le32((slp_itrvl / period) * period);
218
219 if (skip)
220 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
221 else
222 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
223
224 if (priv->cfg->base_params->shadow_reg_enable)
225 cmd->flags |= IWL_POWER_SHADOW_REG_ENA;
226 else
227 cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;
228
229 if (iwl_advanced_bt_coexist(priv)) {
230 if (!priv->cfg->bt_params->bt_sco_disable)
231 cmd->flags |= IWL_POWER_BT_SCO_ENA;
232 else
233 cmd->flags &= ~IWL_POWER_BT_SCO_ENA;
234 }
235
236
237 slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
238 if (slp_itrvl > IWL_CONN_MAX_LISTEN_INTERVAL)
239 cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
240 cpu_to_le32(IWL_CONN_MAX_LISTEN_INTERVAL);
241
242 /* enforce max sleep interval */
243 for (i = IWL_POWER_VEC_SIZE - 1; i >= 0 ; i--) {
244 if (le32_to_cpu(cmd->sleep_interval[i]) >
245 (max_sleep[i] * period))
246 cmd->sleep_interval[i] =
247 cpu_to_le32(max_sleep[i] * period);
248 if (i != (IWL_POWER_VEC_SIZE - 1)) {
249 if (le32_to_cpu(cmd->sleep_interval[i]) >
250 le32_to_cpu(cmd->sleep_interval[i+1]))
251 cmd->sleep_interval[i] =
252 cmd->sleep_interval[i+1];
253 }
254 }
255
256 if (priv->power_data.pci_pm)
257 cmd->flags |= IWL_POWER_PCI_PM_MSK;
258 else
259 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
260
261 IWL_DEBUG_POWER(priv, "numSkipDtim = %u, dtimPeriod = %d\n",
262 skip, period);
263 IWL_DEBUG_POWER(priv, "Sleep command for index %d\n", lvl + 1);
264 }
265
iwl_power_sleep_cam_cmd(struct iwl_priv * priv,struct iwl_powertable_cmd * cmd)266 static void iwl_power_sleep_cam_cmd(struct iwl_priv *priv,
267 struct iwl_powertable_cmd *cmd)
268 {
269 memset(cmd, 0, sizeof(*cmd));
270
271 if (priv->power_data.pci_pm)
272 cmd->flags |= IWL_POWER_PCI_PM_MSK;
273
274 IWL_DEBUG_POWER(priv, "Sleep command for CAM\n");
275 }
276
iwl_power_fill_sleep_cmd(struct iwl_priv * priv,struct iwl_powertable_cmd * cmd,int dynps_ms,int wakeup_period)277 static void iwl_power_fill_sleep_cmd(struct iwl_priv *priv,
278 struct iwl_powertable_cmd *cmd,
279 int dynps_ms, int wakeup_period)
280 {
281 /*
282 * These are the original power level 3 sleep successions. The
283 * device may behave better with such succession and was also
284 * only tested with that. Just like the original sleep commands,
285 * also adjust the succession here to the wakeup_period below.
286 * The ranges are the same as for the sleep commands, 0-2, 3-9
287 * and >10, which is selected based on the DTIM interval for
288 * the sleep index but here we use the wakeup period since that
289 * is what we need to do for the latency requirements.
290 */
291 static const u8 slp_succ_r0[IWL_POWER_VEC_SIZE] = { 2, 2, 2, 2, 2 };
292 static const u8 slp_succ_r1[IWL_POWER_VEC_SIZE] = { 2, 4, 6, 7, 9 };
293 static const u8 slp_succ_r2[IWL_POWER_VEC_SIZE] = { 2, 7, 9, 9, 0xFF };
294 const u8 *slp_succ = slp_succ_r0;
295 int i;
296
297 if (wakeup_period > IWL_DTIM_RANGE_0_MAX)
298 slp_succ = slp_succ_r1;
299 if (wakeup_period > IWL_DTIM_RANGE_1_MAX)
300 slp_succ = slp_succ_r2;
301
302 memset(cmd, 0, sizeof(*cmd));
303
304 cmd->flags = IWL_POWER_DRIVER_ALLOW_SLEEP_MSK |
305 IWL_POWER_FAST_PD; /* no use seeing frames for others */
306
307 if (priv->power_data.pci_pm)
308 cmd->flags |= IWL_POWER_PCI_PM_MSK;
309
310 if (priv->cfg->base_params->shadow_reg_enable)
311 cmd->flags |= IWL_POWER_SHADOW_REG_ENA;
312 else
313 cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;
314
315 if (iwl_advanced_bt_coexist(priv)) {
316 if (!priv->cfg->bt_params->bt_sco_disable)
317 cmd->flags |= IWL_POWER_BT_SCO_ENA;
318 else
319 cmd->flags &= ~IWL_POWER_BT_SCO_ENA;
320 }
321
322 cmd->rx_data_timeout = cpu_to_le32(1000 * dynps_ms);
323 cmd->tx_data_timeout = cpu_to_le32(1000 * dynps_ms);
324
325 for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
326 cmd->sleep_interval[i] =
327 cpu_to_le32(min_t(int, slp_succ[i], wakeup_period));
328
329 IWL_DEBUG_POWER(priv, "Automatic sleep command\n");
330 }
331
iwl_set_power(struct iwl_priv * priv,struct iwl_powertable_cmd * cmd)332 static int iwl_set_power(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd)
333 {
334 IWL_DEBUG_POWER(priv, "Sending power/sleep command\n");
335 IWL_DEBUG_POWER(priv, "Flags value = 0x%08X\n", cmd->flags);
336 IWL_DEBUG_POWER(priv, "Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
337 IWL_DEBUG_POWER(priv, "Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
338 IWL_DEBUG_POWER(priv, "Sleep interval vector = { %d , %d , %d , %d , %d }\n",
339 le32_to_cpu(cmd->sleep_interval[0]),
340 le32_to_cpu(cmd->sleep_interval[1]),
341 le32_to_cpu(cmd->sleep_interval[2]),
342 le32_to_cpu(cmd->sleep_interval[3]),
343 le32_to_cpu(cmd->sleep_interval[4]));
344
345 return iwl_send_cmd_pdu(priv, POWER_TABLE_CMD,
346 sizeof(struct iwl_powertable_cmd), cmd);
347 }
348
iwl_power_build_cmd(struct iwl_priv * priv,struct iwl_powertable_cmd * cmd)349 static void iwl_power_build_cmd(struct iwl_priv *priv,
350 struct iwl_powertable_cmd *cmd)
351 {
352 bool enabled = priv->hw->conf.flags & IEEE80211_CONF_PS;
353 int dtimper;
354
355 dtimper = priv->hw->conf.ps_dtim_period ?: 1;
356
357 if (priv->cfg->base_params->broken_powersave)
358 iwl_power_sleep_cam_cmd(priv, cmd);
359 else if (priv->hw->conf.flags & IEEE80211_CONF_IDLE)
360 iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, 20);
361 else if (priv->cfg->ops->lib->tt_ops.lower_power_detection &&
362 priv->cfg->ops->lib->tt_ops.tt_power_mode &&
363 priv->cfg->ops->lib->tt_ops.lower_power_detection(priv)) {
364 /* in thermal throttling low power state */
365 iwl_static_sleep_cmd(priv, cmd,
366 priv->cfg->ops->lib->tt_ops.tt_power_mode(priv), dtimper);
367 } else if (!enabled)
368 iwl_power_sleep_cam_cmd(priv, cmd);
369 else if (priv->power_data.debug_sleep_level_override >= 0)
370 iwl_static_sleep_cmd(priv, cmd,
371 priv->power_data.debug_sleep_level_override,
372 dtimper);
373 else if (no_sleep_autoadjust)
374 iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_1, dtimper);
375 else
376 iwl_power_fill_sleep_cmd(priv, cmd,
377 priv->hw->conf.dynamic_ps_timeout,
378 priv->hw->conf.max_sleep_period);
379 }
380
iwl_power_set_mode(struct iwl_priv * priv,struct iwl_powertable_cmd * cmd,bool force)381 int iwl_power_set_mode(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd,
382 bool force)
383 {
384 int ret;
385 bool update_chains;
386
387 lockdep_assert_held(&priv->mutex);
388
389 /* Don't update the RX chain when chain noise calibration is running */
390 update_chains = priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE ||
391 priv->chain_noise_data.state == IWL_CHAIN_NOISE_ALIVE;
392
393 if (!memcmp(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
394 return 0;
395
396 if (!iwl_is_ready_rf(priv))
397 return -EIO;
398
399 /* scan complete use sleep_power_next, need to be updated */
400 memcpy(&priv->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
401 if (test_bit(STATUS_SCANNING, &priv->status) && !force) {
402 IWL_DEBUG_INFO(priv, "Defer power set mode while scanning\n");
403 return 0;
404 }
405
406 if (cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK)
407 set_bit(STATUS_POWER_PMI, &priv->status);
408
409 ret = iwl_set_power(priv, cmd);
410 if (!ret) {
411 if (!(cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK))
412 clear_bit(STATUS_POWER_PMI, &priv->status);
413
414 if (priv->cfg->ops->lib->update_chain_flags && update_chains)
415 priv->cfg->ops->lib->update_chain_flags(priv);
416 else if (priv->cfg->ops->lib->update_chain_flags)
417 IWL_DEBUG_POWER(priv,
418 "Cannot update the power, chain noise "
419 "calibration running: %d\n",
420 priv->chain_noise_data.state);
421
422 memcpy(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd));
423 } else
424 IWL_ERR(priv, "set power fail, ret = %d", ret);
425
426 return ret;
427 }
428
iwl_power_update_mode(struct iwl_priv * priv,bool force)429 int iwl_power_update_mode(struct iwl_priv *priv, bool force)
430 {
431 struct iwl_powertable_cmd cmd;
432
433 iwl_power_build_cmd(priv, &cmd);
434 return iwl_power_set_mode(priv, &cmd, force);
435 }
436
437 /* initialize to default */
iwl_power_initialize(struct iwl_priv * priv)438 void iwl_power_initialize(struct iwl_priv *priv)
439 {
440 u16 lctl = iwl_pcie_link_ctl(priv);
441
442 priv->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
443
444 priv->power_data.debug_sleep_level_override = -1;
445
446 memset(&priv->power_data.sleep_cmd, 0,
447 sizeof(priv->power_data.sleep_cmd));
448 }
449