1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2015-2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2022 Intel Corporation 5 */ 6 #include <linux/module.h> 7 #include <linux/stringify.h> 8 #include "iwl-config.h" 9 #include "iwl-prph.h" 10 #include "fw/api/txq.h" 11 12 /* Highest firmware API version supported */ 13 #define IWL_22000_UCODE_API_MAX 72 14 15 /* Lowest firmware API version supported */ 16 #define IWL_22000_UCODE_API_MIN 39 17 18 /* NVM versions */ 19 #define IWL_22000_NVM_VERSION 0x0a1d 20 21 /* Memory offsets and lengths */ 22 #define IWL_22000_DCCM_OFFSET 0x800000 /* LMAC1 */ 23 #define IWL_22000_DCCM_LEN 0x10000 /* LMAC1 */ 24 #define IWL_22000_DCCM2_OFFSET 0x880000 25 #define IWL_22000_DCCM2_LEN 0x8000 26 #define IWL_22000_SMEM_OFFSET 0x400000 27 #define IWL_22000_SMEM_LEN 0xD0000 28 29 #define IWL_QU_B_HR_B_FW_PRE "iwlwifi-Qu-b0-hr-b0-" 30 #define IWL_QNJ_B_HR_B_FW_PRE "iwlwifi-QuQnj-b0-hr-b0-" 31 #define IWL_QU_C_HR_B_FW_PRE "iwlwifi-Qu-c0-hr-b0-" 32 #define IWL_QU_B_JF_B_FW_PRE "iwlwifi-Qu-b0-jf-b0-" 33 #define IWL_QU_C_JF_B_FW_PRE "iwlwifi-Qu-c0-jf-b0-" 34 #define IWL_QUZ_A_HR_B_FW_PRE "iwlwifi-QuZ-a0-hr-b0-" 35 #define IWL_QUZ_A_JF_B_FW_PRE "iwlwifi-QuZ-a0-jf-b0-" 36 #define IWL_QNJ_B_JF_B_FW_PRE "iwlwifi-QuQnj-b0-jf-b0-" 37 #define IWL_CC_A_FW_PRE "iwlwifi-cc-a0-" 38 #define IWL_SO_A_JF_B_FW_PRE "iwlwifi-so-a0-jf-b0-" 39 #define IWL_SO_A_HR_B_FW_PRE "iwlwifi-so-a0-hr-b0-" 40 #define IWL_SO_A_GF_A_FW_PRE "iwlwifi-so-a0-gf-a0-" 41 #define IWL_TY_A_GF_A_FW_PRE "iwlwifi-ty-a0-gf-a0-" 42 #define IWL_SO_A_GF4_A_FW_PRE "iwlwifi-so-a0-gf4-a0-" 43 #define IWL_SO_A_MR_A_FW_PRE "iwlwifi-so-a0-mr-a0-" 44 #define IWL_SNJ_A_GF4_A_FW_PRE "iwlwifi-SoSnj-a0-gf4-a0-" 45 #define IWL_SNJ_A_GF_A_FW_PRE "iwlwifi-SoSnj-a0-gf-a0-" 46 #define IWL_SNJ_A_HR_B_FW_PRE "iwlwifi-SoSnj-a0-hr-b0-" 47 #define IWL_SNJ_A_JF_B_FW_PRE "iwlwifi-SoSnj-a0-jf-b0-" 48 #define IWL_MA_A_HR_B_FW_PRE "iwlwifi-ma-a0-hr-b0-" 49 #define IWL_MA_A_GF_A_FW_PRE "iwlwifi-ma-a0-gf-a0-" 50 #define IWL_MA_A_GF4_A_FW_PRE "iwlwifi-ma-a0-gf4-a0-" 51 #define IWL_MA_A_MR_A_FW_PRE "iwlwifi-ma-a0-mr-a0-" 52 #define IWL_MA_A_FM_A_FW_PRE "iwlwifi-ma-a0-fm-a0-" 53 #define IWL_SNJ_A_MR_A_FW_PRE "iwlwifi-SoSnj-a0-mr-a0-" 54 #define IWL_BZ_A_HR_B_FW_PRE "iwlwifi-bz-a0-hr-b0-" 55 #define IWL_BZ_A_GF_A_FW_PRE "iwlwifi-bz-a0-gf-a0-" 56 #define IWL_BZ_A_GF4_A_FW_PRE "iwlwifi-bz-a0-gf4-a0-" 57 #define IWL_BZ_A_MR_A_FW_PRE "iwlwifi-bz-a0-mr-a0-" 58 #define IWL_BZ_A_FM_A_FW_PRE "iwlwifi-bz-a0-fm-a0-" 59 #define IWL_BZ_A_FM4_A_FW_PRE "iwlwifi-bz-a0-fm4-a0-" 60 #define IWL_GL_A_FM_A_FW_PRE "iwlwifi-gl-a0-fm-a0-" 61 #define IWL_GL_B_FM_B_FW_PRE "iwlwifi-gl-b0-fm-b0-" 62 #define IWL_BZ_Z_GF_A_FW_PRE "iwlwifi-bz-z0-gf-a0-" 63 #define IWL_BNJ_A_FM_A_FW_PRE "iwlwifi-BzBnj-a0-fm-a0-" 64 #define IWL_BNJ_A_FM4_A_FW_PRE "iwlwifi-BzBnj-a0-fm4-a0-" 65 #define IWL_BNJ_A_GF_A_FW_PRE "iwlwifi-BzBnj-a0-gf-a0-" 66 #define IWL_BNJ_A_GF4_A_FW_PRE "iwlwifi-BzBnj-a0-gf4-a0-" 67 #define IWL_BNJ_A_HR_B_FW_PRE "iwlwifi-BzBnj-a0-hr-b0-" 68 #define IWL_BNJ_B_FM_B_FW_PRE "iwlwifi-BzBnj-b0-fm-b0-" 69 70 71 #define IWL_QU_B_HR_B_MODULE_FIRMWARE(api) \ 72 IWL_QU_B_HR_B_FW_PRE __stringify(api) ".ucode" 73 #define IWL_QNJ_B_HR_B_MODULE_FIRMWARE(api) \ 74 IWL_QNJ_B_HR_B_FW_PRE __stringify(api) ".ucode" 75 #define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \ 76 IWL_QUZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 77 #define IWL_QUZ_A_JF_B_MODULE_FIRMWARE(api) \ 78 IWL_QUZ_A_JF_B_FW_PRE __stringify(api) ".ucode" 79 #define IWL_QU_C_HR_B_MODULE_FIRMWARE(api) \ 80 IWL_QU_C_HR_B_FW_PRE __stringify(api) ".ucode" 81 #define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \ 82 IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode" 83 #define IWL_QNJ_B_JF_B_MODULE_FIRMWARE(api) \ 84 IWL_QNJ_B_JF_B_FW_PRE __stringify(api) ".ucode" 85 #define IWL_CC_A_MODULE_FIRMWARE(api) \ 86 IWL_CC_A_FW_PRE __stringify(api) ".ucode" 87 #define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \ 88 IWL_SO_A_JF_B_FW_PRE __stringify(api) ".ucode" 89 #define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \ 90 IWL_SO_A_HR_B_FW_PRE __stringify(api) ".ucode" 91 #define IWL_SO_A_GF_A_MODULE_FIRMWARE(api) \ 92 IWL_SO_A_GF_A_FW_PRE __stringify(api) ".ucode" 93 #define IWL_TY_A_GF_A_MODULE_FIRMWARE(api) \ 94 IWL_TY_A_GF_A_FW_PRE __stringify(api) ".ucode" 95 #define IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(api) \ 96 IWL_SNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 97 #define IWL_SNJ_A_GF_A_MODULE_FIRMWARE(api) \ 98 IWL_SNJ_A_GF_A_FW_PRE __stringify(api) ".ucode" 99 #define IWL_SNJ_A_HR_B_MODULE_FIRMWARE(api) \ 100 IWL_SNJ_A_HR_B_FW_PRE __stringify(api) ".ucode" 101 #define IWL_SNJ_A_JF_B_MODULE_FIRMWARE(api) \ 102 IWL_SNJ_A_JF_B_FW_PRE __stringify(api) ".ucode" 103 #define IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(api) \ 104 IWL_MA_A_HR_B_FW_PRE __stringify(api) ".ucode" 105 #define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api) \ 106 IWL_MA_A_GF_A_FW_PRE __stringify(api) ".ucode" 107 #define IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(api) \ 108 IWL_MA_A_GF4_A_FW_PRE __stringify(api) ".ucode" 109 #define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \ 110 IWL_MA_A_MR_A_FW_PRE __stringify(api) ".ucode" 111 #define IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(api) \ 112 IWL_MA_A_FM_A_FW_PRE __stringify(api) ".ucode" 113 #define IWL_SNJ_A_MR_A_MODULE_FIRMWARE(api) \ 114 IWL_SNJ_A_MR_A_FW_PRE __stringify(api) ".ucode" 115 #define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \ 116 IWL_BZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 117 #define IWL_BZ_A_GF_A_MODULE_FIRMWARE(api) \ 118 IWL_BZ_A_GF_A_FW_PRE __stringify(api) ".ucode" 119 #define IWL_BZ_A_GF4_A_MODULE_FIRMWARE(api) \ 120 IWL_BZ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 121 #define IWL_BZ_A_MR_A_MODULE_FIRMWARE(api) \ 122 IWL_BZ_A_MR_A_FW_PRE __stringify(api) ".ucode" 123 #define IWL_BZ_A_FM_A_MODULE_FIRMWARE(api) \ 124 IWL_BZ_A_FM_A_FW_PRE __stringify(api) ".ucode" 125 #define IWL_BZ_A_FM4_A_MODULE_FIRMWARE(api) \ 126 IWL_BZ_A_FM4_A_FW_PRE __stringify(api) ".ucode" 127 #define IWL_GL_A_FM_A_MODULE_FIRMWARE(api) \ 128 IWL_GL_A_FM_A_FW_PRE __stringify(api) ".ucode" 129 #define IWL_GL_B_FM_B_MODULE_FIRMWARE(api) \ 130 IWL_GL_B_FM_B_FW_PRE __stringify(api) ".ucode" 131 #define IWL_BNJ_A_FM_A_MODULE_FIRMWARE(api) \ 132 IWL_BNJ_A_FM_A_FW_PRE __stringify(api) ".ucode" 133 #define IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(api) \ 134 IWL_BNJ_A_FM4_A_FW_PRE __stringify(api) ".ucode" 135 #define IWL_BNJ_A_GF_A_MODULE_FIRMWARE(api) \ 136 IWL_BNJ_A_GF_A_FW_PRE __stringify(api) ".ucode" 137 #define IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(api) \ 138 IWL_BNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 139 #define IWL_BNJ_A_HR_B_MODULE_FIRMWARE(api) \ 140 IWL_BNJ_A_HR_B_FW_PRE __stringify(api) ".ucode" 141 #define IWL_BNJ_B_FM_B_MODULE_FIRMWARE(api) \ 142 IWL_BNJ_B_FM_B_FW_PRE __stringify(api) ".ucode" 143 144 static const struct iwl_base_params iwl_22000_base_params = { 145 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 146 .num_of_queues = 512, 147 .max_tfd_queue_size = 256, 148 .shadow_ram_support = true, 149 .led_compensation = 57, 150 .wd_timeout = IWL_LONG_WD_TIMEOUT, 151 .max_event_log_size = 512, 152 .shadow_reg_enable = true, 153 .pcie_l1_allowed = true, 154 }; 155 156 static const struct iwl_base_params iwl_ax210_base_params = { 157 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 158 .num_of_queues = 512, 159 .max_tfd_queue_size = 65536, 160 .shadow_ram_support = true, 161 .led_compensation = 57, 162 .wd_timeout = IWL_LONG_WD_TIMEOUT, 163 .max_event_log_size = 512, 164 .shadow_reg_enable = true, 165 .pcie_l1_allowed = true, 166 }; 167 168 static const struct iwl_ht_params iwl_22000_ht_params = { 169 .stbc = true, 170 .ldpc = true, 171 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) | 172 BIT(NL80211_BAND_6GHZ), 173 }; 174 175 #define IWL_DEVICE_22000_COMMON \ 176 .ucode_api_max = IWL_22000_UCODE_API_MAX, \ 177 .ucode_api_min = IWL_22000_UCODE_API_MIN, \ 178 .led_mode = IWL_LED_RF_STATE, \ 179 .nvm_hw_section_num = 10, \ 180 .non_shared_ant = ANT_B, \ 181 .dccm_offset = IWL_22000_DCCM_OFFSET, \ 182 .dccm_len = IWL_22000_DCCM_LEN, \ 183 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \ 184 .dccm2_len = IWL_22000_DCCM2_LEN, \ 185 .smem_offset = IWL_22000_SMEM_OFFSET, \ 186 .smem_len = IWL_22000_SMEM_LEN, \ 187 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \ 188 .apmg_not_supported = true, \ 189 .trans.mq_rx_supported = true, \ 190 .vht_mu_mimo_supported = true, \ 191 .mac_addr_from_csr = 0x380, \ 192 .ht_params = &iwl_22000_ht_params, \ 193 .nvm_ver = IWL_22000_NVM_VERSION, \ 194 .trans.use_tfh = true, \ 195 .trans.rf_id = true, \ 196 .trans.gen2 = true, \ 197 .nvm_type = IWL_NVM_EXT, \ 198 .dbgc_supported = true, \ 199 .min_umac_error_event_table = 0x400000, \ 200 .d3_debug_data_base_addr = 0x401000, \ 201 .d3_debug_data_length = 60 * 1024, \ 202 .mon_smem_regs = { \ 203 .write_ptr = { \ 204 .addr = LDBG_M2S_BUF_WPTR, \ 205 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 206 }, \ 207 .cycle_cnt = { \ 208 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 209 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 210 }, \ 211 } 212 213 #define IWL_DEVICE_22500 \ 214 IWL_DEVICE_22000_COMMON, \ 215 .trans.device_family = IWL_DEVICE_FAMILY_22000, \ 216 .trans.base_params = &iwl_22000_base_params, \ 217 .gp2_reg_addr = 0xa02c68, \ 218 .mon_dram_regs = { \ 219 .write_ptr = { \ 220 .addr = MON_BUFF_WRPTR_VER2, \ 221 .mask = 0xffffffff, \ 222 }, \ 223 .cycle_cnt = { \ 224 .addr = MON_BUFF_CYCLE_CNT_VER2, \ 225 .mask = 0xffffffff, \ 226 }, \ 227 } 228 229 #define IWL_DEVICE_AX210 \ 230 IWL_DEVICE_22000_COMMON, \ 231 .trans.umac_prph_offset = 0x300000, \ 232 .trans.device_family = IWL_DEVICE_FAMILY_AX210, \ 233 .trans.base_params = &iwl_ax210_base_params, \ 234 .min_txq_size = 128, \ 235 .gp2_reg_addr = 0xd02c68, \ 236 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_HE, \ 237 .mon_dram_regs = { \ 238 .write_ptr = { \ 239 .addr = DBGC_CUR_DBGBUF_STATUS, \ 240 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 241 }, \ 242 .cycle_cnt = { \ 243 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 244 .mask = 0xffffffff, \ 245 }, \ 246 .cur_frag = { \ 247 .addr = DBGC_CUR_DBGBUF_STATUS, \ 248 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 249 }, \ 250 } 251 252 #define IWL_DEVICE_BZ \ 253 .ucode_api_max = IWL_22000_UCODE_API_MAX, \ 254 .ucode_api_min = IWL_22000_UCODE_API_MIN, \ 255 .led_mode = IWL_LED_RF_STATE, \ 256 .nvm_hw_section_num = 10, \ 257 .non_shared_ant = ANT_B, \ 258 .dccm_offset = IWL_22000_DCCM_OFFSET, \ 259 .dccm_len = IWL_22000_DCCM_LEN, \ 260 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \ 261 .dccm2_len = IWL_22000_DCCM2_LEN, \ 262 .smem_offset = IWL_22000_SMEM_OFFSET, \ 263 .smem_len = IWL_22000_SMEM_LEN, \ 264 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, \ 265 .apmg_not_supported = true, \ 266 .trans.mq_rx_supported = true, \ 267 .vht_mu_mimo_supported = true, \ 268 .mac_addr_from_csr = 0x30, \ 269 .ht_params = &iwl_22000_ht_params, \ 270 .nvm_ver = IWL_22000_NVM_VERSION, \ 271 .trans.use_tfh = true, \ 272 .trans.rf_id = true, \ 273 .trans.gen2 = true, \ 274 .nvm_type = IWL_NVM_EXT, \ 275 .dbgc_supported = true, \ 276 .min_umac_error_event_table = 0x400000, \ 277 .d3_debug_data_base_addr = 0x401000, \ 278 .d3_debug_data_length = 60 * 1024, \ 279 .mon_smem_regs = { \ 280 .write_ptr = { \ 281 .addr = LDBG_M2S_BUF_WPTR, \ 282 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 283 }, \ 284 .cycle_cnt = { \ 285 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 286 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 287 }, \ 288 }, \ 289 .trans.umac_prph_offset = 0x300000, \ 290 .trans.device_family = IWL_DEVICE_FAMILY_BZ, \ 291 .trans.base_params = &iwl_ax210_base_params, \ 292 .min_txq_size = 128, \ 293 .gp2_reg_addr = 0xd02c68, \ 294 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, \ 295 .mon_dram_regs = { \ 296 .write_ptr = { \ 297 .addr = DBGC_CUR_DBGBUF_STATUS, \ 298 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 299 }, \ 300 .cycle_cnt = { \ 301 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 302 .mask = 0xffffffff, \ 303 }, \ 304 .cur_frag = { \ 305 .addr = DBGC_CUR_DBGBUF_STATUS, \ 306 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 307 }, \ 308 }, \ 309 .mon_dbgi_regs = { \ 310 .write_ptr = { \ 311 .addr = DBGI_SRAM_FIFO_POINTERS, \ 312 .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, \ 313 }, \ 314 } 315 316 const struct iwl_cfg_trans_params iwl_qnj_trans_cfg = { 317 .mq_rx_supported = true, 318 .use_tfh = true, 319 .rf_id = true, 320 .gen2 = true, 321 .device_family = IWL_DEVICE_FAMILY_22000, 322 .base_params = &iwl_22000_base_params, 323 }; 324 325 const struct iwl_cfg_trans_params iwl_qu_trans_cfg = { 326 .mq_rx_supported = true, 327 .use_tfh = true, 328 .rf_id = true, 329 .gen2 = true, 330 .device_family = IWL_DEVICE_FAMILY_22000, 331 .base_params = &iwl_22000_base_params, 332 .integrated = true, 333 .xtal_latency = 500, 334 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 335 }; 336 337 const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg = { 338 .mq_rx_supported = true, 339 .use_tfh = true, 340 .rf_id = true, 341 .gen2 = true, 342 .device_family = IWL_DEVICE_FAMILY_22000, 343 .base_params = &iwl_22000_base_params, 344 .integrated = true, 345 .xtal_latency = 1820, 346 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_1820US, 347 }; 348 349 const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg = { 350 .mq_rx_supported = true, 351 .use_tfh = true, 352 .rf_id = true, 353 .gen2 = true, 354 .device_family = IWL_DEVICE_FAMILY_22000, 355 .base_params = &iwl_22000_base_params, 356 .integrated = true, 357 .xtal_latency = 12000, 358 .low_latency_xtal = true, 359 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 360 }; 361 362 const struct iwl_cfg_trans_params iwl_snj_trans_cfg = { 363 .mq_rx_supported = true, 364 .use_tfh = true, 365 .rf_id = true, 366 .gen2 = true, 367 .device_family = IWL_DEVICE_FAMILY_AX210, 368 .base_params = &iwl_ax210_base_params, 369 .umac_prph_offset = 0x300000, 370 }; 371 372 const struct iwl_cfg_trans_params iwl_so_trans_cfg = { 373 .mq_rx_supported = true, 374 .use_tfh = true, 375 .rf_id = true, 376 .gen2 = true, 377 .device_family = IWL_DEVICE_FAMILY_AX210, 378 .base_params = &iwl_ax210_base_params, 379 .umac_prph_offset = 0x300000, 380 .integrated = true, 381 /* TODO: the following values need to be checked */ 382 .xtal_latency = 500, 383 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 384 }; 385 386 const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg = { 387 .mq_rx_supported = true, 388 .use_tfh = true, 389 .rf_id = true, 390 .gen2 = true, 391 .device_family = IWL_DEVICE_FAMILY_AX210, 392 .base_params = &iwl_ax210_base_params, 393 .umac_prph_offset = 0x300000, 394 .integrated = true, 395 .low_latency_xtal = true, 396 .xtal_latency = 12000, 397 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 398 }; 399 400 const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg = { 401 .mq_rx_supported = true, 402 .use_tfh = true, 403 .rf_id = true, 404 .gen2 = true, 405 .device_family = IWL_DEVICE_FAMILY_AX210, 406 .base_params = &iwl_ax210_base_params, 407 .umac_prph_offset = 0x300000, 408 .integrated = true, 409 .low_latency_xtal = true, 410 .xtal_latency = 12000, 411 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 412 .imr_enabled = true, 413 }; 414 415 /* 416 * If the device doesn't support HE, no need to have that many buffers. 417 * 22000 devices can split multiple frames into a single RB, so fewer are 418 * needed; AX210 cannot (but use smaller RBs by default) - these sizes 419 * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with 420 * additional overhead to account for processing time. 421 */ 422 #define IWL_NUM_RBDS_NON_HE 512 423 #define IWL_NUM_RBDS_22000_HE 2048 424 #define IWL_NUM_RBDS_AX210_HE 4096 425 426 /* 427 * All JF radio modules are part of the 9000 series, but the MAC part 428 * looks more like 22000. That's why this device is here, but called 429 * 9560 nevertheless. 430 */ 431 const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg = { 432 .fw_name_pre = IWL_QU_B_JF_B_FW_PRE, 433 IWL_DEVICE_22500, 434 .num_rbds = IWL_NUM_RBDS_NON_HE, 435 }; 436 437 const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg = { 438 .fw_name_pre = IWL_QU_C_JF_B_FW_PRE, 439 IWL_DEVICE_22500, 440 .num_rbds = IWL_NUM_RBDS_NON_HE, 441 }; 442 443 const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg = { 444 .fw_name_pre = IWL_QUZ_A_JF_B_FW_PRE, 445 IWL_DEVICE_22500, 446 /* 447 * This device doesn't support receiving BlockAck with a large bitmap 448 * so we need to restrict the size of transmitted aggregation to the 449 * HT size; mac80211 would otherwise pick the HE max (256) by default. 450 */ 451 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 452 .num_rbds = IWL_NUM_RBDS_NON_HE, 453 }; 454 455 const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg = { 456 .fw_name_pre = IWL_QNJ_B_JF_B_FW_PRE, 457 IWL_DEVICE_22500, 458 /* 459 * This device doesn't support receiving BlockAck with a large bitmap 460 * so we need to restrict the size of transmitted aggregation to the 461 * HT size; mac80211 would otherwise pick the HE max (256) by default. 462 */ 463 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 464 .num_rbds = IWL_NUM_RBDS_NON_HE, 465 }; 466 467 const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = { 468 .device_family = IWL_DEVICE_FAMILY_22000, 469 .base_params = &iwl_22000_base_params, 470 .mq_rx_supported = true, 471 .use_tfh = true, 472 .rf_id = true, 473 .gen2 = true, 474 .bisr_workaround = 1, 475 }; 476 477 const struct iwl_cfg_trans_params iwl_ma_trans_cfg = { 478 .device_family = IWL_DEVICE_FAMILY_AX210, 479 .base_params = &iwl_ax210_base_params, 480 .mq_rx_supported = true, 481 .use_tfh = true, 482 .rf_id = true, 483 .gen2 = true, 484 .integrated = true, 485 .umac_prph_offset = 0x300000 486 }; 487 488 const struct iwl_cfg_trans_params iwl_bz_trans_cfg = { 489 .device_family = IWL_DEVICE_FAMILY_BZ, 490 .base_params = &iwl_ax210_base_params, 491 .mq_rx_supported = true, 492 .use_tfh = true, 493 .rf_id = true, 494 .gen2 = true, 495 .integrated = true, 496 .umac_prph_offset = 0x300000, 497 .xtal_latency = 12000, 498 .low_latency_xtal = true, 499 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 500 }; 501 502 const char iwl_ax101_name[] = "Intel(R) Wi-Fi 6 AX101"; 503 const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz"; 504 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz"; 505 const char iwl_ax203_name[] = "Intel(R) Wi-Fi 6 AX203"; 506 const char iwl_ax204_name[] = "Intel(R) Wi-Fi 6 AX204 160MHz"; 507 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz"; 508 const char iwl_ax221_name[] = "Intel(R) Wi-Fi 6E AX221 160MHz"; 509 const char iwl_ax231_name[] = "Intel(R) Wi-Fi 6E AX231 160MHz"; 510 const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6E AX411 160MHz"; 511 const char iwl_bz_name[] = "Intel(R) TBD Bz device"; 512 513 const char iwl_ax200_killer_1650w_name[] = 514 "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)"; 515 const char iwl_ax200_killer_1650x_name[] = 516 "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)"; 517 const char iwl_ax201_killer_1650s_name[] = 518 "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)"; 519 const char iwl_ax201_killer_1650i_name[] = 520 "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)"; 521 const char iwl_ax210_killer_1675w_name[] = 522 "Killer(R) Wi-Fi 6E AX1675w 160MHz Wireless Network Adapter (210D2W)"; 523 const char iwl_ax210_killer_1675x_name[] = 524 "Killer(R) Wi-Fi 6E AX1675x 160MHz Wireless Network Adapter (210NGW)"; 525 const char iwl_ax211_killer_1675s_name[] = 526 "Killer(R) Wi-Fi 6E AX1675s 160MHz Wireless Network Adapter (211NGW)"; 527 const char iwl_ax211_killer_1675i_name[] = 528 "Killer(R) Wi-Fi 6E AX1675i 160MHz Wireless Network Adapter (211NGW)"; 529 const char iwl_ax411_killer_1690s_name[] = 530 "Killer(R) Wi-Fi 6E AX1690s 160MHz Wireless Network Adapter (411D2W)"; 531 const char iwl_ax411_killer_1690i_name[] = 532 "Killer(R) Wi-Fi 6E AX1690i 160MHz Wireless Network Adapter (411NGW)"; 533 534 const struct iwl_cfg iwl_qu_b0_hr1_b0 = { 535 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 536 IWL_DEVICE_22500, 537 /* 538 * This device doesn't support receiving BlockAck with a large bitmap 539 * so we need to restrict the size of transmitted aggregation to the 540 * HT size; mac80211 would otherwise pick the HE max (256) by default. 541 */ 542 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 543 .tx_with_siso_diversity = true, 544 .num_rbds = IWL_NUM_RBDS_22000_HE, 545 }; 546 547 const struct iwl_cfg iwl_qu_b0_hr_b0 = { 548 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 549 IWL_DEVICE_22500, 550 /* 551 * This device doesn't support receiving BlockAck with a large bitmap 552 * so we need to restrict the size of transmitted aggregation to the 553 * HT size; mac80211 would otherwise pick the HE max (256) by default. 554 */ 555 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 556 .num_rbds = IWL_NUM_RBDS_22000_HE, 557 }; 558 559 const struct iwl_cfg iwl_ax201_cfg_qu_hr = { 560 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 561 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 562 IWL_DEVICE_22500, 563 /* 564 * This device doesn't support receiving BlockAck with a large bitmap 565 * so we need to restrict the size of transmitted aggregation to the 566 * HT size; mac80211 would otherwise pick the HE max (256) by default. 567 */ 568 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 569 .num_rbds = IWL_NUM_RBDS_22000_HE, 570 }; 571 572 const struct iwl_cfg iwl_qu_c0_hr1_b0 = { 573 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 574 IWL_DEVICE_22500, 575 /* 576 * This device doesn't support receiving BlockAck with a large bitmap 577 * so we need to restrict the size of transmitted aggregation to the 578 * HT size; mac80211 would otherwise pick the HE max (256) by default. 579 */ 580 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 581 .tx_with_siso_diversity = true, 582 .num_rbds = IWL_NUM_RBDS_22000_HE, 583 }; 584 585 const struct iwl_cfg iwl_qu_c0_hr_b0 = { 586 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 587 IWL_DEVICE_22500, 588 /* 589 * This device doesn't support receiving BlockAck with a large bitmap 590 * so we need to restrict the size of transmitted aggregation to the 591 * HT size; mac80211 would otherwise pick the HE max (256) by default. 592 */ 593 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 594 .num_rbds = IWL_NUM_RBDS_22000_HE, 595 }; 596 597 const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = { 598 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 599 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 600 IWL_DEVICE_22500, 601 /* 602 * This device doesn't support receiving BlockAck with a large bitmap 603 * so we need to restrict the size of transmitted aggregation to the 604 * HT size; mac80211 would otherwise pick the HE max (256) by default. 605 */ 606 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 607 .num_rbds = IWL_NUM_RBDS_22000_HE, 608 }; 609 610 const struct iwl_cfg iwl_quz_a0_hr1_b0 = { 611 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 612 IWL_DEVICE_22500, 613 /* 614 * This device doesn't support receiving BlockAck with a large bitmap 615 * so we need to restrict the size of transmitted aggregation to the 616 * HT size; mac80211 would otherwise pick the HE max (256) by default. 617 */ 618 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 619 .tx_with_siso_diversity = true, 620 .num_rbds = IWL_NUM_RBDS_22000_HE, 621 }; 622 623 const struct iwl_cfg iwl_ax201_cfg_quz_hr = { 624 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 625 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 626 IWL_DEVICE_22500, 627 /* 628 * This device doesn't support receiving BlockAck with a large bitmap 629 * so we need to restrict the size of transmitted aggregation to the 630 * HT size; mac80211 would otherwise pick the HE max (256) by default. 631 */ 632 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 633 .num_rbds = IWL_NUM_RBDS_22000_HE, 634 }; 635 636 const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = { 637 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)", 638 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 639 IWL_DEVICE_22500, 640 /* 641 * This device doesn't support receiving BlockAck with a large bitmap 642 * so we need to restrict the size of transmitted aggregation to the 643 * HT size; mac80211 would otherwise pick the HE max (256) by default. 644 */ 645 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 646 .num_rbds = IWL_NUM_RBDS_22000_HE, 647 }; 648 649 const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = { 650 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)", 651 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 652 IWL_DEVICE_22500, 653 /* 654 * This device doesn't support receiving BlockAck with a large bitmap 655 * so we need to restrict the size of transmitted aggregation to the 656 * HT size; mac80211 would otherwise pick the HE max (256) by default. 657 */ 658 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 659 .num_rbds = IWL_NUM_RBDS_22000_HE, 660 }; 661 662 const struct iwl_cfg iwl_ax200_cfg_cc = { 663 .fw_name_pre = IWL_CC_A_FW_PRE, 664 IWL_DEVICE_22500, 665 /* 666 * This device doesn't support receiving BlockAck with a large bitmap 667 * so we need to restrict the size of transmitted aggregation to the 668 * HT size; mac80211 would otherwise pick the HE max (256) by default. 669 */ 670 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 671 .num_rbds = IWL_NUM_RBDS_22000_HE, 672 }; 673 674 const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = { 675 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)", 676 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 677 IWL_DEVICE_22500, 678 /* 679 * This device doesn't support receiving BlockAck with a large bitmap 680 * so we need to restrict the size of transmitted aggregation to the 681 * HT size; mac80211 would otherwise pick the HE max (256) by default. 682 */ 683 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 684 .num_rbds = IWL_NUM_RBDS_22000_HE, 685 }; 686 687 const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = { 688 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)", 689 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 690 IWL_DEVICE_22500, 691 /* 692 * This device doesn't support receiving BlockAck with a large bitmap 693 * so we need to restrict the size of transmitted aggregation to the 694 * HT size; mac80211 would otherwise pick the HE max (256) by default. 695 */ 696 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 697 .num_rbds = IWL_NUM_RBDS_22000_HE, 698 }; 699 700 const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = { 701 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)", 702 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 703 IWL_DEVICE_22500, 704 /* 705 * This device doesn't support receiving BlockAck with a large bitmap 706 * so we need to restrict the size of transmitted aggregation to the 707 * HT size; mac80211 would otherwise pick the HE max (256) by default. 708 */ 709 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 710 .num_rbds = IWL_NUM_RBDS_22000_HE, 711 }; 712 713 const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = { 714 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)", 715 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 716 IWL_DEVICE_22500, 717 /* 718 * This device doesn't support receiving BlockAck with a large bitmap 719 * so we need to restrict the size of transmitted aggregation to the 720 * HT size; mac80211 would otherwise pick the HE max (256) by default. 721 */ 722 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 723 .num_rbds = IWL_NUM_RBDS_22000_HE, 724 }; 725 726 const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg = { 727 .fw_name_pre = IWL_QNJ_B_HR_B_FW_PRE, 728 IWL_DEVICE_22500, 729 /* 730 * This device doesn't support receiving BlockAck with a large bitmap 731 * so we need to restrict the size of transmitted aggregation to the 732 * HT size; mac80211 would otherwise pick the HE max (256) by default. 733 */ 734 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 735 .num_rbds = IWL_NUM_RBDS_22000_HE, 736 }; 737 738 const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0 = { 739 .name = "Intel(R) Wireless-AC 9560 160MHz", 740 .fw_name_pre = IWL_SO_A_JF_B_FW_PRE, 741 IWL_DEVICE_AX210, 742 .num_rbds = IWL_NUM_RBDS_NON_HE, 743 }; 744 745 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = { 746 .name = iwl_ax211_name, 747 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 748 .uhb_supported = true, 749 IWL_DEVICE_AX210, 750 .num_rbds = IWL_NUM_RBDS_AX210_HE, 751 }; 752 753 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = { 754 .name = iwl_ax211_name, 755 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 756 .uhb_supported = true, 757 IWL_DEVICE_AX210, 758 .num_rbds = IWL_NUM_RBDS_AX210_HE, 759 .trans.xtal_latency = 12000, 760 .trans.low_latency_xtal = true, 761 }; 762 763 const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = { 764 .name = "Intel(R) Wi-Fi 6 AX210 160MHz", 765 .fw_name_pre = IWL_TY_A_GF_A_FW_PRE, 766 .uhb_supported = true, 767 IWL_DEVICE_AX210, 768 .num_rbds = IWL_NUM_RBDS_AX210_HE, 769 }; 770 771 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = { 772 .name = iwl_ax411_name, 773 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 774 .uhb_supported = true, 775 IWL_DEVICE_AX210, 776 .num_rbds = IWL_NUM_RBDS_AX210_HE, 777 }; 778 779 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = { 780 .name = iwl_ax411_name, 781 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 782 .uhb_supported = true, 783 IWL_DEVICE_AX210, 784 .num_rbds = IWL_NUM_RBDS_AX210_HE, 785 .trans.xtal_latency = 12000, 786 .trans.low_latency_xtal = true, 787 }; 788 789 const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0 = { 790 .name = iwl_ax411_name, 791 .fw_name_pre = IWL_SNJ_A_GF4_A_FW_PRE, 792 .uhb_supported = true, 793 IWL_DEVICE_AX210, 794 .num_rbds = IWL_NUM_RBDS_AX210_HE, 795 }; 796 797 const struct iwl_cfg iwlax211_cfg_snj_gf_a0 = { 798 .name = iwl_ax211_name, 799 .fw_name_pre = IWL_SNJ_A_GF_A_FW_PRE, 800 .uhb_supported = true, 801 IWL_DEVICE_AX210, 802 .num_rbds = IWL_NUM_RBDS_AX210_HE, 803 }; 804 805 const struct iwl_cfg iwl_cfg_snj_hr_b0 = { 806 .fw_name_pre = IWL_SNJ_A_HR_B_FW_PRE, 807 .uhb_supported = true, 808 IWL_DEVICE_AX210, 809 .num_rbds = IWL_NUM_RBDS_AX210_HE, 810 }; 811 812 const struct iwl_cfg iwl_cfg_snj_a0_jf_b0 = { 813 .fw_name_pre = IWL_SNJ_A_JF_B_FW_PRE, 814 .uhb_supported = true, 815 IWL_DEVICE_AX210, 816 .num_rbds = IWL_NUM_RBDS_AX210_HE, 817 }; 818 819 const struct iwl_cfg iwl_cfg_ma_a0_hr_b0 = { 820 .fw_name_pre = IWL_MA_A_HR_B_FW_PRE, 821 .uhb_supported = true, 822 IWL_DEVICE_AX210, 823 .num_rbds = IWL_NUM_RBDS_AX210_HE, 824 }; 825 826 const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = { 827 .fw_name_pre = IWL_MA_A_GF_A_FW_PRE, 828 .uhb_supported = true, 829 IWL_DEVICE_AX210, 830 .num_rbds = IWL_NUM_RBDS_AX210_HE, 831 }; 832 833 const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0 = { 834 .fw_name_pre = IWL_MA_A_GF4_A_FW_PRE, 835 .uhb_supported = true, 836 IWL_DEVICE_AX210, 837 .num_rbds = IWL_NUM_RBDS_AX210_HE, 838 }; 839 840 const struct iwl_cfg iwl_cfg_ma_a0_mr_a0 = { 841 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE, 842 .uhb_supported = true, 843 IWL_DEVICE_AX210, 844 .num_rbds = IWL_NUM_RBDS_AX210_HE, 845 }; 846 847 const struct iwl_cfg iwl_cfg_ma_a0_ms_a0 = { 848 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE, 849 .uhb_supported = false, 850 IWL_DEVICE_AX210, 851 .num_rbds = IWL_NUM_RBDS_AX210_HE, 852 }; 853 854 const struct iwl_cfg iwl_cfg_so_a0_ms_a0 = { 855 .fw_name_pre = IWL_SO_A_MR_A_FW_PRE, 856 .uhb_supported = false, 857 IWL_DEVICE_AX210, 858 .num_rbds = IWL_NUM_RBDS_AX210_HE, 859 }; 860 861 const struct iwl_cfg iwl_cfg_ma_a0_fm_a0 = { 862 .fw_name_pre = IWL_MA_A_FM_A_FW_PRE, 863 .uhb_supported = true, 864 IWL_DEVICE_AX210, 865 .num_rbds = IWL_NUM_RBDS_AX210_HE, 866 }; 867 868 const struct iwl_cfg iwl_cfg_snj_a0_mr_a0 = { 869 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE, 870 .uhb_supported = true, 871 IWL_DEVICE_AX210, 872 .num_rbds = IWL_NUM_RBDS_AX210_HE, 873 }; 874 875 const struct iwl_cfg iwl_cfg_snj_a0_ms_a0 = { 876 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE, 877 .uhb_supported = false, 878 IWL_DEVICE_AX210, 879 .num_rbds = IWL_NUM_RBDS_AX210_HE, 880 }; 881 882 const struct iwl_cfg iwl_cfg_so_a0_hr_a0 = { 883 .fw_name_pre = IWL_SO_A_HR_B_FW_PRE, 884 IWL_DEVICE_AX210, 885 .num_rbds = IWL_NUM_RBDS_AX210_HE, 886 }; 887 888 const struct iwl_cfg iwl_cfg_quz_a0_hr_b0 = { 889 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 890 IWL_DEVICE_22500, 891 /* 892 * This device doesn't support receiving BlockAck with a large bitmap 893 * so we need to restrict the size of transmitted aggregation to the 894 * HT size; mac80211 would otherwise pick the HE max (256) by default. 895 */ 896 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 897 .num_rbds = IWL_NUM_RBDS_22000_HE, 898 }; 899 900 const struct iwl_cfg iwl_cfg_bz_a0_hr_b0 = { 901 .fw_name_pre = IWL_BZ_A_HR_B_FW_PRE, 902 .uhb_supported = true, 903 IWL_DEVICE_BZ, 904 .num_rbds = IWL_NUM_RBDS_AX210_HE, 905 }; 906 907 const struct iwl_cfg iwl_cfg_bz_a0_gf_a0 = { 908 .fw_name_pre = IWL_BZ_A_GF_A_FW_PRE, 909 .uhb_supported = true, 910 IWL_DEVICE_BZ, 911 .num_rbds = IWL_NUM_RBDS_AX210_HE, 912 }; 913 914 const struct iwl_cfg iwl_cfg_bz_a0_gf4_a0 = { 915 .fw_name_pre = IWL_BZ_A_GF4_A_FW_PRE, 916 .uhb_supported = true, 917 IWL_DEVICE_BZ, 918 .num_rbds = IWL_NUM_RBDS_AX210_HE, 919 }; 920 921 const struct iwl_cfg iwl_cfg_bz_a0_mr_a0 = { 922 .fw_name_pre = IWL_BZ_A_MR_A_FW_PRE, 923 .uhb_supported = true, 924 IWL_DEVICE_BZ, 925 .num_rbds = IWL_NUM_RBDS_AX210_HE, 926 }; 927 928 const struct iwl_cfg iwl_cfg_bz_a0_fm_a0 = { 929 .fw_name_pre = IWL_BZ_A_FM_A_FW_PRE, 930 .uhb_supported = true, 931 IWL_DEVICE_BZ, 932 .num_rbds = IWL_NUM_RBDS_AX210_HE, 933 }; 934 935 const struct iwl_cfg iwl_cfg_bz_a0_fm4_a0 = { 936 .fw_name_pre = IWL_BZ_A_FM4_A_FW_PRE, 937 .uhb_supported = true, 938 IWL_DEVICE_BZ, 939 .num_rbds = IWL_NUM_RBDS_AX210_HE, 940 }; 941 942 const struct iwl_cfg iwl_cfg_gl_a0_fm_a0 = { 943 .fw_name_pre = IWL_GL_A_FM_A_FW_PRE, 944 .uhb_supported = true, 945 IWL_DEVICE_BZ, 946 .num_rbds = IWL_NUM_RBDS_AX210_HE, 947 }; 948 949 const struct iwl_cfg iwl_cfg_gl_b0_fm_b0 = { 950 .fw_name_pre = IWL_GL_B_FM_B_FW_PRE, 951 .uhb_supported = true, 952 IWL_DEVICE_BZ, 953 .num_rbds = IWL_NUM_RBDS_AX210_HE, 954 }; 955 956 const struct iwl_cfg iwl_cfg_bz_z0_gf_a0 = { 957 .fw_name_pre = IWL_BZ_Z_GF_A_FW_PRE, 958 .uhb_supported = true, 959 IWL_DEVICE_BZ, 960 .num_rbds = IWL_NUM_RBDS_AX210_HE, 961 }; 962 963 const struct iwl_cfg iwl_cfg_bnj_a0_fm_a0 = { 964 .fw_name_pre = IWL_BNJ_A_FM_A_FW_PRE, 965 .uhb_supported = true, 966 IWL_DEVICE_BZ, 967 .num_rbds = IWL_NUM_RBDS_AX210_HE, 968 }; 969 970 const struct iwl_cfg iwl_cfg_bnj_a0_fm4_a0 = { 971 .fw_name_pre = IWL_BNJ_A_FM4_A_FW_PRE, 972 .uhb_supported = true, 973 IWL_DEVICE_BZ, 974 .num_rbds = IWL_NUM_RBDS_AX210_HE, 975 }; 976 977 const struct iwl_cfg iwl_cfg_bnj_a0_gf_a0 = { 978 .fw_name_pre = IWL_BNJ_A_GF_A_FW_PRE, 979 .uhb_supported = true, 980 IWL_DEVICE_BZ, 981 .num_rbds = IWL_NUM_RBDS_AX210_HE, 982 }; 983 984 const struct iwl_cfg iwl_cfg_bnj_a0_gf4_a0 = { 985 .fw_name_pre = IWL_BNJ_A_GF4_A_FW_PRE, 986 .uhb_supported = true, 987 IWL_DEVICE_BZ, 988 .num_rbds = IWL_NUM_RBDS_AX210_HE, 989 }; 990 991 const struct iwl_cfg iwl_cfg_bnj_a0_hr_b0 = { 992 .fw_name_pre = IWL_BNJ_A_HR_B_FW_PRE, 993 .uhb_supported = true, 994 IWL_DEVICE_BZ, 995 .num_rbds = IWL_NUM_RBDS_AX210_HE, 996 }; 997 998 const struct iwl_cfg iwl_cfg_bnj_b0_fm_b0 = { 999 .fw_name_pre = IWL_BNJ_B_FM_B_FW_PRE, 1000 .uhb_supported = true, 1001 IWL_DEVICE_BZ, 1002 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1003 }; 1004 MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1005 MODULE_FIRMWARE(IWL_QNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1006 MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1007 MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1008 MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1009 MODULE_FIRMWARE(IWL_QUZ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1010 MODULE_FIRMWARE(IWL_QNJ_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1011 MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1012 MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1013 MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1014 MODULE_FIRMWARE(IWL_SO_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1015 MODULE_FIRMWARE(IWL_TY_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1016 MODULE_FIRMWARE(IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1017 MODULE_FIRMWARE(IWL_SNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1018 MODULE_FIRMWARE(IWL_SNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1019 MODULE_FIRMWARE(IWL_SNJ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1020 MODULE_FIRMWARE(IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1021 MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1022 MODULE_FIRMWARE(IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1023 MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1024 MODULE_FIRMWARE(IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1025 MODULE_FIRMWARE(IWL_SNJ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1026 MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1027 MODULE_FIRMWARE(IWL_BZ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1028 MODULE_FIRMWARE(IWL_BZ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1029 MODULE_FIRMWARE(IWL_BZ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1030 MODULE_FIRMWARE(IWL_BZ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1031 MODULE_FIRMWARE(IWL_GL_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1032 MODULE_FIRMWARE(IWL_BNJ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1033 MODULE_FIRMWARE(IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1034 MODULE_FIRMWARE(IWL_BNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1035 MODULE_FIRMWARE(IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1036 MODULE_FIRMWARE(IWL_BNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1037 MODULE_FIRMWARE(IWL_BZ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1038 MODULE_FIRMWARE(IWL_GL_B_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1039 MODULE_FIRMWARE(IWL_BNJ_B_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1040