1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * UFS Host Controller driver for Exynos specific extensions
4 *
5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
6 * Author: Seungwon Jeon <essuuj@gmail.com>
7 * Author: Alim Akhtar <alim.akhtar@samsung.com>
8 *
9 */
10
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/phy/phy.h>
18 #include <linux/platform_device.h>
19 #include <linux/regmap.h>
20
21 #include <ufs/ufshcd.h>
22 #include "ufshcd-pltfrm.h"
23 #include <ufs/ufshci.h>
24 #include <ufs/unipro.h>
25
26 #include "ufs-exynos.h"
27
28 /*
29 * Exynos's Vendor specific registers for UFSHCI
30 */
31 #define HCI_TXPRDT_ENTRY_SIZE 0x00
32 #define PRDT_PREFECT_EN BIT(31)
33 #define PRDT_SET_SIZE(x) ((x) & 0x1F)
34 #define HCI_RXPRDT_ENTRY_SIZE 0x04
35 #define HCI_1US_TO_CNT_VAL 0x0C
36 #define CNT_VAL_1US_MASK 0x3FF
37 #define HCI_UTRL_NEXUS_TYPE 0x40
38 #define HCI_UTMRL_NEXUS_TYPE 0x44
39 #define HCI_SW_RST 0x50
40 #define UFS_LINK_SW_RST BIT(0)
41 #define UFS_UNIPRO_SW_RST BIT(1)
42 #define UFS_SW_RST_MASK (UFS_UNIPRO_SW_RST | UFS_LINK_SW_RST)
43 #define HCI_DATA_REORDER 0x60
44 #define HCI_UNIPRO_APB_CLK_CTRL 0x68
45 #define UNIPRO_APB_CLK(v, x) (((v) & ~0xF) | ((x) & 0xF))
46 #define HCI_AXIDMA_RWDATA_BURST_LEN 0x6C
47 #define HCI_GPIO_OUT 0x70
48 #define HCI_ERR_EN_PA_LAYER 0x78
49 #define HCI_ERR_EN_DL_LAYER 0x7C
50 #define HCI_ERR_EN_N_LAYER 0x80
51 #define HCI_ERR_EN_T_LAYER 0x84
52 #define HCI_ERR_EN_DME_LAYER 0x88
53 #define HCI_CLKSTOP_CTRL 0xB0
54 #define REFCLKOUT_STOP BIT(4)
55 #define MPHY_APBCLK_STOP BIT(3)
56 #define REFCLK_STOP BIT(2)
57 #define UNIPRO_MCLK_STOP BIT(1)
58 #define UNIPRO_PCLK_STOP BIT(0)
59 #define CLK_STOP_MASK (REFCLKOUT_STOP | REFCLK_STOP |\
60 UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\
61 UNIPRO_PCLK_STOP)
62 #define HCI_MISC 0xB4
63 #define REFCLK_CTRL_EN BIT(7)
64 #define UNIPRO_PCLK_CTRL_EN BIT(6)
65 #define UNIPRO_MCLK_CTRL_EN BIT(5)
66 #define HCI_CORECLK_CTRL_EN BIT(4)
67 #define CLK_CTRL_EN_MASK (REFCLK_CTRL_EN |\
68 UNIPRO_PCLK_CTRL_EN |\
69 UNIPRO_MCLK_CTRL_EN)
70 /* Device fatal error */
71 #define DFES_ERR_EN BIT(31)
72 #define DFES_DEF_L2_ERRS (UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF |\
73 UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
74 #define DFES_DEF_L3_ERRS (UIC_NETWORK_UNSUPPORTED_HEADER_TYPE |\
75 UIC_NETWORK_BAD_DEVICEID_ENC |\
76 UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING)
77 #define DFES_DEF_L4_ERRS (UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE |\
78 UIC_TRANSPORT_UNKNOWN_CPORTID |\
79 UIC_TRANSPORT_NO_CONNECTION_RX |\
80 UIC_TRANSPORT_BAD_TC)
81
82 /* FSYS UFS Shareability */
83 #define UFS_WR_SHARABLE BIT(2)
84 #define UFS_RD_SHARABLE BIT(1)
85 #define UFS_SHARABLE (UFS_WR_SHARABLE | UFS_RD_SHARABLE)
86 #define UFS_SHAREABILITY_OFFSET 0x710
87
88 /* Multi-host registers */
89 #define MHCTRL 0xC4
90 #define MHCTRL_EN_VH_MASK (0xE)
91 #define MHCTRL_EN_VH(vh) (vh << 1)
92 #define PH2VH_MBOX 0xD8
93
94 #define MH_MSG_MASK (0xFF)
95
96 #define MH_MSG(id, msg) ((id << 8) | (msg & 0xFF))
97 #define MH_MSG_PH_READY 0x1
98 #define MH_MSG_VH_READY 0x2
99
100 #define ALLOW_INQUIRY BIT(25)
101 #define ALLOW_MODE_SELECT BIT(24)
102 #define ALLOW_MODE_SENSE BIT(23)
103 #define ALLOW_PRE_FETCH GENMASK(22, 21)
104 #define ALLOW_READ_CMD_ALL GENMASK(20, 18) /* read_6/10/16 */
105 #define ALLOW_READ_BUFFER BIT(17)
106 #define ALLOW_READ_CAPACITY GENMASK(16, 15)
107 #define ALLOW_REPORT_LUNS BIT(14)
108 #define ALLOW_REQUEST_SENSE BIT(13)
109 #define ALLOW_SYNCHRONIZE_CACHE GENMASK(8, 7)
110 #define ALLOW_TEST_UNIT_READY BIT(6)
111 #define ALLOW_UNMAP BIT(5)
112 #define ALLOW_VERIFY BIT(4)
113 #define ALLOW_WRITE_CMD_ALL GENMASK(3, 1) /* write_6/10/16 */
114
115 #define ALLOW_TRANS_VH_DEFAULT (ALLOW_INQUIRY | ALLOW_MODE_SELECT | \
116 ALLOW_MODE_SENSE | ALLOW_PRE_FETCH | \
117 ALLOW_READ_CMD_ALL | ALLOW_READ_BUFFER | \
118 ALLOW_READ_CAPACITY | ALLOW_REPORT_LUNS | \
119 ALLOW_REQUEST_SENSE | ALLOW_SYNCHRONIZE_CACHE | \
120 ALLOW_TEST_UNIT_READY | ALLOW_UNMAP | \
121 ALLOW_VERIFY | ALLOW_WRITE_CMD_ALL)
122
123 #define HCI_MH_ALLOWABLE_TRAN_OF_VH 0x30C
124 #define HCI_MH_IID_IN_TASK_TAG 0X308
125
126 #define PH_READY_TIMEOUT_MS (5 * MSEC_PER_SEC)
127
128 enum {
129 UNIPRO_L1_5 = 0,/* PHY Adapter */
130 UNIPRO_L2, /* Data Link */
131 UNIPRO_L3, /* Network */
132 UNIPRO_L4, /* Transport */
133 UNIPRO_DME, /* DME */
134 };
135
136 /*
137 * UNIPRO registers
138 */
139 #define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0 0x78B8
140 #define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1 0x78BC
141 #define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2 0x78C0
142
143 /*
144 * UFS Protector registers
145 */
146 #define UFSPRSECURITY 0x010
147 #define NSSMU BIT(14)
148 #define UFSPSBEGIN0 0x200
149 #define UFSPSEND0 0x204
150 #define UFSPSLUN0 0x208
151 #define UFSPSCTRL0 0x20C
152
153 #define CNTR_DIV_VAL 40
154
155 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en);
156 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en);
157
exynos_ufs_enable_auto_ctrl_hcc(struct exynos_ufs * ufs)158 static inline void exynos_ufs_enable_auto_ctrl_hcc(struct exynos_ufs *ufs)
159 {
160 exynos_ufs_auto_ctrl_hcc(ufs, true);
161 }
162
exynos_ufs_disable_auto_ctrl_hcc(struct exynos_ufs * ufs)163 static inline void exynos_ufs_disable_auto_ctrl_hcc(struct exynos_ufs *ufs)
164 {
165 exynos_ufs_auto_ctrl_hcc(ufs, false);
166 }
167
exynos_ufs_disable_auto_ctrl_hcc_save(struct exynos_ufs * ufs,u32 * val)168 static inline void exynos_ufs_disable_auto_ctrl_hcc_save(
169 struct exynos_ufs *ufs, u32 *val)
170 {
171 *val = hci_readl(ufs, HCI_MISC);
172 exynos_ufs_auto_ctrl_hcc(ufs, false);
173 }
174
exynos_ufs_auto_ctrl_hcc_restore(struct exynos_ufs * ufs,u32 * val)175 static inline void exynos_ufs_auto_ctrl_hcc_restore(
176 struct exynos_ufs *ufs, u32 *val)
177 {
178 hci_writel(ufs, *val, HCI_MISC);
179 }
180
exynos_ufs_gate_clks(struct exynos_ufs * ufs)181 static inline void exynos_ufs_gate_clks(struct exynos_ufs *ufs)
182 {
183 exynos_ufs_ctrl_clkstop(ufs, true);
184 }
185
exynos_ufs_ungate_clks(struct exynos_ufs * ufs)186 static inline void exynos_ufs_ungate_clks(struct exynos_ufs *ufs)
187 {
188 exynos_ufs_ctrl_clkstop(ufs, false);
189 }
190
exynos7_ufs_drv_init(struct device * dev,struct exynos_ufs * ufs)191 static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
192 {
193 return 0;
194 }
195
exynosauto_ufs_drv_init(struct device * dev,struct exynos_ufs * ufs)196 static int exynosauto_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
197 {
198 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
199
200 /* IO Coherency setting */
201 if (ufs->sysreg) {
202 return regmap_update_bits(ufs->sysreg,
203 ufs->shareability_reg_offset,
204 UFS_SHARABLE, UFS_SHARABLE);
205 }
206
207 attr->tx_dif_p_nsec = 3200000;
208
209 return 0;
210 }
211
exynosauto_ufs_post_hce_enable(struct exynos_ufs * ufs)212 static int exynosauto_ufs_post_hce_enable(struct exynos_ufs *ufs)
213 {
214 struct ufs_hba *hba = ufs->hba;
215
216 /* Enable Virtual Host #1 */
217 ufshcd_rmwl(hba, MHCTRL_EN_VH_MASK, MHCTRL_EN_VH(1), MHCTRL);
218 /* Default VH Transfer permissions */
219 hci_writel(ufs, ALLOW_TRANS_VH_DEFAULT, HCI_MH_ALLOWABLE_TRAN_OF_VH);
220 /* IID information is replaced in TASKTAG[7:5] instead of IID in UCD */
221 hci_writel(ufs, 0x1, HCI_MH_IID_IN_TASK_TAG);
222
223 return 0;
224 }
225
exynosauto_ufs_pre_link(struct exynos_ufs * ufs)226 static int exynosauto_ufs_pre_link(struct exynos_ufs *ufs)
227 {
228 struct ufs_hba *hba = ufs->hba;
229 int i;
230 u32 tx_line_reset_period, rx_line_reset_period;
231
232 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC;
233 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC;
234
235 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
236 for_each_ufs_rx_lane(ufs, i) {
237 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i),
238 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
239 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0);
240
241 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i),
242 (rx_line_reset_period >> 16) & 0xFF);
243 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i),
244 (rx_line_reset_period >> 8) & 0xFF);
245 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i),
246 (rx_line_reset_period) & 0xFF);
247
248 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x79);
249 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1);
250 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6);
251 }
252
253 for_each_ufs_tx_lane(ufs, i) {
254 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i),
255 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
256 /* Not to affect VND_TX_LINERESET_PVALUE to VND_TX_CLK_PRD */
257 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i),
258 0x02);
259
260 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i),
261 (tx_line_reset_period >> 16) & 0xFF);
262 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i),
263 (tx_line_reset_period >> 8) & 0xFF);
264 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i),
265 (tx_line_reset_period) & 0xFF);
266
267 /* TX PWM Gear Capability / PWM_G1_ONLY */
268 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 0x1);
269 }
270
271 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
272
273 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0);
274
275 ufshcd_dme_set(hba, UIC_ARG_MIB(0xa011), 0x8000);
276
277 return 0;
278 }
279
exynosauto_ufs_pre_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)280 static int exynosauto_ufs_pre_pwr_change(struct exynos_ufs *ufs,
281 struct ufs_pa_layer_attr *pwr)
282 {
283 struct ufs_hba *hba = ufs->hba;
284
285 /* PACP_PWR_req and delivered to the remote DME */
286 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000);
287 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000);
288 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000);
289
290 return 0;
291 }
292
exynosauto_ufs_post_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)293 static int exynosauto_ufs_post_pwr_change(struct exynos_ufs *ufs,
294 struct ufs_pa_layer_attr *pwr)
295 {
296 struct ufs_hba *hba = ufs->hba;
297 u32 enabled_vh;
298
299 enabled_vh = ufshcd_readl(hba, MHCTRL) & MHCTRL_EN_VH_MASK;
300
301 /* Send physical host ready message to virtual hosts */
302 ufshcd_writel(hba, MH_MSG(enabled_vh, MH_MSG_PH_READY), PH2VH_MBOX);
303
304 return 0;
305 }
306
exynos7_ufs_pre_link(struct exynos_ufs * ufs)307 static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
308 {
309 struct ufs_hba *hba = ufs->hba;
310 u32 val = ufs->drv_data->uic_attr->pa_dbg_option_suite;
311 int i;
312
313 exynos_ufs_enable_ov_tm(hba);
314 for_each_ufs_tx_lane(ufs, i)
315 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17);
316 for_each_ufs_rx_lane(ufs, i) {
317 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff);
318 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00);
319 }
320 exynos_ufs_disable_ov_tm(hba);
321
322 for_each_ufs_tx_lane(ufs, i)
323 ufshcd_dme_set(hba,
324 UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0);
325 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1);
326 udelay(1);
327 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val | (1 << 12));
328 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1);
329 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1);
330 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1);
331 udelay(1600);
332 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val);
333
334 return 0;
335 }
336
exynos7_ufs_post_link(struct exynos_ufs * ufs)337 static int exynos7_ufs_post_link(struct exynos_ufs *ufs)
338 {
339 struct ufs_hba *hba = ufs->hba;
340 int i;
341
342 exynos_ufs_enable_ov_tm(hba);
343 for_each_ufs_tx_lane(ufs, i) {
344 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x28b, i), 0x83);
345 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x29a, i), 0x07);
346 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x277, i),
347 TX_LINERESET_N(exynos_ufs_calc_time_cntr(ufs, 200000)));
348 }
349 exynos_ufs_disable_ov_tm(hba);
350
351 exynos_ufs_enable_dbg_mode(hba);
352 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xbb8);
353 exynos_ufs_disable_dbg_mode(hba);
354
355 return 0;
356 }
357
exynos7_ufs_pre_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)358 static int exynos7_ufs_pre_pwr_change(struct exynos_ufs *ufs,
359 struct ufs_pa_layer_attr *pwr)
360 {
361 unipro_writel(ufs, 0x22, UNIPRO_DBG_FORCE_DME_CTRL_STATE);
362
363 return 0;
364 }
365
exynos7_ufs_post_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)366 static int exynos7_ufs_post_pwr_change(struct exynos_ufs *ufs,
367 struct ufs_pa_layer_attr *pwr)
368 {
369 struct ufs_hba *hba = ufs->hba;
370 int lanes = max_t(u32, pwr->lane_rx, pwr->lane_tx);
371
372 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_RXPHY_CFGUPDT), 0x1);
373
374 if (lanes == 1) {
375 exynos_ufs_enable_dbg_mode(hba);
376 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 0x1);
377 exynos_ufs_disable_dbg_mode(hba);
378 }
379
380 return 0;
381 }
382
383 /*
384 * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
385 * Control should be disabled in the below cases
386 * - Before host controller S/W reset
387 * - Access to UFS protector's register
388 */
exynos_ufs_auto_ctrl_hcc(struct exynos_ufs * ufs,bool en)389 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en)
390 {
391 u32 misc = hci_readl(ufs, HCI_MISC);
392
393 if (en)
394 hci_writel(ufs, misc | HCI_CORECLK_CTRL_EN, HCI_MISC);
395 else
396 hci_writel(ufs, misc & ~HCI_CORECLK_CTRL_EN, HCI_MISC);
397 }
398
exynos_ufs_ctrl_clkstop(struct exynos_ufs * ufs,bool en)399 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en)
400 {
401 u32 ctrl = hci_readl(ufs, HCI_CLKSTOP_CTRL);
402 u32 misc = hci_readl(ufs, HCI_MISC);
403
404 if (en) {
405 hci_writel(ufs, misc | CLK_CTRL_EN_MASK, HCI_MISC);
406 hci_writel(ufs, ctrl | CLK_STOP_MASK, HCI_CLKSTOP_CTRL);
407 } else {
408 hci_writel(ufs, ctrl & ~CLK_STOP_MASK, HCI_CLKSTOP_CTRL);
409 hci_writel(ufs, misc & ~CLK_CTRL_EN_MASK, HCI_MISC);
410 }
411 }
412
exynos_ufs_get_clk_info(struct exynos_ufs * ufs)413 static int exynos_ufs_get_clk_info(struct exynos_ufs *ufs)
414 {
415 struct ufs_hba *hba = ufs->hba;
416 struct list_head *head = &hba->clk_list_head;
417 struct ufs_clk_info *clki;
418 unsigned long pclk_rate;
419 u32 f_min, f_max;
420 u8 div = 0;
421 int ret = 0;
422
423 if (list_empty(head))
424 goto out;
425
426 list_for_each_entry(clki, head, list) {
427 if (!IS_ERR(clki->clk)) {
428 if (!strcmp(clki->name, "core_clk"))
429 ufs->clk_hci_core = clki->clk;
430 else if (!strcmp(clki->name, "sclk_unipro_main"))
431 ufs->clk_unipro_main = clki->clk;
432 }
433 }
434
435 if (!ufs->clk_hci_core || !ufs->clk_unipro_main) {
436 dev_err(hba->dev, "failed to get clk info\n");
437 ret = -EINVAL;
438 goto out;
439 }
440
441 ufs->mclk_rate = clk_get_rate(ufs->clk_unipro_main);
442 pclk_rate = clk_get_rate(ufs->clk_hci_core);
443 f_min = ufs->pclk_avail_min;
444 f_max = ufs->pclk_avail_max;
445
446 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) {
447 do {
448 pclk_rate /= (div + 1);
449
450 if (pclk_rate <= f_max)
451 break;
452 div++;
453 } while (pclk_rate >= f_min);
454 }
455
456 if (unlikely(pclk_rate < f_min || pclk_rate > f_max)) {
457 dev_err(hba->dev, "not available pclk range %lu\n", pclk_rate);
458 ret = -EINVAL;
459 goto out;
460 }
461
462 ufs->pclk_rate = pclk_rate;
463 ufs->pclk_div = div;
464
465 out:
466 return ret;
467 }
468
exynos_ufs_set_unipro_pclk_div(struct exynos_ufs * ufs)469 static void exynos_ufs_set_unipro_pclk_div(struct exynos_ufs *ufs)
470 {
471 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) {
472 u32 val;
473
474 val = hci_readl(ufs, HCI_UNIPRO_APB_CLK_CTRL);
475 hci_writel(ufs, UNIPRO_APB_CLK(val, ufs->pclk_div),
476 HCI_UNIPRO_APB_CLK_CTRL);
477 }
478 }
479
exynos_ufs_set_pwm_clk_div(struct exynos_ufs * ufs)480 static void exynos_ufs_set_pwm_clk_div(struct exynos_ufs *ufs)
481 {
482 struct ufs_hba *hba = ufs->hba;
483 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
484
485 ufshcd_dme_set(hba,
486 UIC_ARG_MIB(CMN_PWM_CLK_CTRL), attr->cmn_pwm_clk_ctrl);
487 }
488
exynos_ufs_calc_pwm_clk_div(struct exynos_ufs * ufs)489 static void exynos_ufs_calc_pwm_clk_div(struct exynos_ufs *ufs)
490 {
491 struct ufs_hba *hba = ufs->hba;
492 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
493 const unsigned int div = 30, mult = 20;
494 const unsigned long pwm_min = 3 * 1000 * 1000;
495 const unsigned long pwm_max = 9 * 1000 * 1000;
496 const int divs[] = {32, 16, 8, 4};
497 unsigned long clk = 0, _clk, clk_period;
498 int i = 0, clk_idx = -1;
499
500 clk_period = UNIPRO_PCLK_PERIOD(ufs);
501 for (i = 0; i < ARRAY_SIZE(divs); i++) {
502 _clk = NSEC_PER_SEC * mult / (clk_period * divs[i] * div);
503 if (_clk >= pwm_min && _clk <= pwm_max) {
504 if (_clk > clk) {
505 clk_idx = i;
506 clk = _clk;
507 }
508 }
509 }
510
511 if (clk_idx == -1) {
512 ufshcd_dme_get(hba, UIC_ARG_MIB(CMN_PWM_CLK_CTRL), &clk_idx);
513 dev_err(hba->dev,
514 "failed to decide pwm clock divider, will not change\n");
515 }
516
517 attr->cmn_pwm_clk_ctrl = clk_idx & PWM_CLK_CTRL_MASK;
518 }
519
exynos_ufs_calc_time_cntr(struct exynos_ufs * ufs,long period)520 long exynos_ufs_calc_time_cntr(struct exynos_ufs *ufs, long period)
521 {
522 const int precise = 10;
523 long pclk_rate = ufs->pclk_rate;
524 long clk_period, fraction;
525
526 clk_period = UNIPRO_PCLK_PERIOD(ufs);
527 fraction = ((NSEC_PER_SEC % pclk_rate) * precise) / pclk_rate;
528
529 return (period * precise) / ((clk_period * precise) + fraction);
530 }
531
exynos_ufs_specify_phy_time_attr(struct exynos_ufs * ufs)532 static void exynos_ufs_specify_phy_time_attr(struct exynos_ufs *ufs)
533 {
534 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
535 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg;
536
537 t_cfg->tx_linereset_p =
538 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_p_nsec);
539 t_cfg->tx_linereset_n =
540 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_n_nsec);
541 t_cfg->tx_high_z_cnt =
542 exynos_ufs_calc_time_cntr(ufs, attr->tx_high_z_cnt_nsec);
543 t_cfg->tx_base_n_val =
544 exynos_ufs_calc_time_cntr(ufs, attr->tx_base_unit_nsec);
545 t_cfg->tx_gran_n_val =
546 exynos_ufs_calc_time_cntr(ufs, attr->tx_gran_unit_nsec);
547 t_cfg->tx_sleep_cnt =
548 exynos_ufs_calc_time_cntr(ufs, attr->tx_sleep_cnt);
549
550 t_cfg->rx_linereset =
551 exynos_ufs_calc_time_cntr(ufs, attr->rx_dif_p_nsec);
552 t_cfg->rx_hibern8_wait =
553 exynos_ufs_calc_time_cntr(ufs, attr->rx_hibern8_wait_nsec);
554 t_cfg->rx_base_n_val =
555 exynos_ufs_calc_time_cntr(ufs, attr->rx_base_unit_nsec);
556 t_cfg->rx_gran_n_val =
557 exynos_ufs_calc_time_cntr(ufs, attr->rx_gran_unit_nsec);
558 t_cfg->rx_sleep_cnt =
559 exynos_ufs_calc_time_cntr(ufs, attr->rx_sleep_cnt);
560 t_cfg->rx_stall_cnt =
561 exynos_ufs_calc_time_cntr(ufs, attr->rx_stall_cnt);
562 }
563
exynos_ufs_config_phy_time_attr(struct exynos_ufs * ufs)564 static void exynos_ufs_config_phy_time_attr(struct exynos_ufs *ufs)
565 {
566 struct ufs_hba *hba = ufs->hba;
567 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg;
568 int i;
569
570 exynos_ufs_set_pwm_clk_div(ufs);
571
572 exynos_ufs_enable_ov_tm(hba);
573
574 for_each_ufs_rx_lane(ufs, i) {
575 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_FILLER_ENABLE, i),
576 ufs->drv_data->uic_attr->rx_filler_enable);
577 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_LINERESET_VAL, i),
578 RX_LINERESET(t_cfg->rx_linereset));
579 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_07_00, i),
580 RX_BASE_NVAL_L(t_cfg->rx_base_n_val));
581 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_15_08, i),
582 RX_BASE_NVAL_H(t_cfg->rx_base_n_val));
583 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_07_00, i),
584 RX_GRAN_NVAL_L(t_cfg->rx_gran_n_val));
585 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_10_08, i),
586 RX_GRAN_NVAL_H(t_cfg->rx_gran_n_val));
587 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_SLEEP_CNT_TIMER, i),
588 RX_OV_SLEEP_CNT(t_cfg->rx_sleep_cnt));
589 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_STALL_CNT_TIMER, i),
590 RX_OV_STALL_CNT(t_cfg->rx_stall_cnt));
591 }
592
593 for_each_ufs_tx_lane(ufs, i) {
594 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_LINERESET_P_VAL, i),
595 TX_LINERESET_P(t_cfg->tx_linereset_p));
596 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_07_00, i),
597 TX_HIGH_Z_CNT_L(t_cfg->tx_high_z_cnt));
598 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_11_08, i),
599 TX_HIGH_Z_CNT_H(t_cfg->tx_high_z_cnt));
600 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_07_00, i),
601 TX_BASE_NVAL_L(t_cfg->tx_base_n_val));
602 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_15_08, i),
603 TX_BASE_NVAL_H(t_cfg->tx_base_n_val));
604 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_07_00, i),
605 TX_GRAN_NVAL_L(t_cfg->tx_gran_n_val));
606 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_10_08, i),
607 TX_GRAN_NVAL_H(t_cfg->tx_gran_n_val));
608 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_OV_SLEEP_CNT_TIMER, i),
609 TX_OV_H8_ENTER_EN |
610 TX_OV_SLEEP_CNT(t_cfg->tx_sleep_cnt));
611 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_MIN_ACTIVATETIME, i),
612 ufs->drv_data->uic_attr->tx_min_activatetime);
613 }
614
615 exynos_ufs_disable_ov_tm(hba);
616 }
617
exynos_ufs_config_phy_cap_attr(struct exynos_ufs * ufs)618 static void exynos_ufs_config_phy_cap_attr(struct exynos_ufs *ufs)
619 {
620 struct ufs_hba *hba = ufs->hba;
621 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
622 int i;
623
624 exynos_ufs_enable_ov_tm(hba);
625
626 for_each_ufs_rx_lane(ufs, i) {
627 ufshcd_dme_set(hba,
628 UIC_ARG_MIB_SEL(RX_HS_G1_SYNC_LENGTH_CAP, i),
629 attr->rx_hs_g1_sync_len_cap);
630 ufshcd_dme_set(hba,
631 UIC_ARG_MIB_SEL(RX_HS_G2_SYNC_LENGTH_CAP, i),
632 attr->rx_hs_g2_sync_len_cap);
633 ufshcd_dme_set(hba,
634 UIC_ARG_MIB_SEL(RX_HS_G3_SYNC_LENGTH_CAP, i),
635 attr->rx_hs_g3_sync_len_cap);
636 ufshcd_dme_set(hba,
637 UIC_ARG_MIB_SEL(RX_HS_G1_PREP_LENGTH_CAP, i),
638 attr->rx_hs_g1_prep_sync_len_cap);
639 ufshcd_dme_set(hba,
640 UIC_ARG_MIB_SEL(RX_HS_G2_PREP_LENGTH_CAP, i),
641 attr->rx_hs_g2_prep_sync_len_cap);
642 ufshcd_dme_set(hba,
643 UIC_ARG_MIB_SEL(RX_HS_G3_PREP_LENGTH_CAP, i),
644 attr->rx_hs_g3_prep_sync_len_cap);
645 }
646
647 if (attr->rx_adv_fine_gran_sup_en == 0) {
648 for_each_ufs_rx_lane(ufs, i) {
649 ufshcd_dme_set(hba,
650 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP, i), 0);
651
652 if (attr->rx_min_actv_time_cap)
653 ufshcd_dme_set(hba,
654 UIC_ARG_MIB_SEL(
655 RX_MIN_ACTIVATETIME_CAPABILITY, i),
656 attr->rx_min_actv_time_cap);
657
658 if (attr->rx_hibern8_time_cap)
659 ufshcd_dme_set(hba,
660 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAP, i),
661 attr->rx_hibern8_time_cap);
662 }
663 } else if (attr->rx_adv_fine_gran_sup_en == 1) {
664 for_each_ufs_rx_lane(ufs, i) {
665 if (attr->rx_adv_fine_gran_step)
666 ufshcd_dme_set(hba,
667 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP,
668 i), RX_ADV_FINE_GRAN_STEP(
669 attr->rx_adv_fine_gran_step));
670
671 if (attr->rx_adv_min_actv_time_cap)
672 ufshcd_dme_set(hba,
673 UIC_ARG_MIB_SEL(
674 RX_ADV_MIN_ACTIVATETIME_CAP, i),
675 attr->rx_adv_min_actv_time_cap);
676
677 if (attr->rx_adv_hibern8_time_cap)
678 ufshcd_dme_set(hba,
679 UIC_ARG_MIB_SEL(RX_ADV_HIBERN8TIME_CAP,
680 i),
681 attr->rx_adv_hibern8_time_cap);
682 }
683 }
684
685 exynos_ufs_disable_ov_tm(hba);
686 }
687
exynos_ufs_establish_connt(struct exynos_ufs * ufs)688 static void exynos_ufs_establish_connt(struct exynos_ufs *ufs)
689 {
690 struct ufs_hba *hba = ufs->hba;
691 enum {
692 DEV_ID = 0x00,
693 PEER_DEV_ID = 0x01,
694 PEER_CPORT_ID = 0x00,
695 TRAFFIC_CLASS = 0x00,
696 };
697
698 /* allow cport attributes to be set */
699 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_IDLE);
700
701 /* local unipro attributes */
702 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), DEV_ID);
703 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), true);
704 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), PEER_DEV_ID);
705 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERCPORTID), PEER_CPORT_ID);
706 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CPORTFLAGS), CPORT_DEF_FLAGS);
707 ufshcd_dme_set(hba, UIC_ARG_MIB(T_TRAFFICCLASS), TRAFFIC_CLASS);
708 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED);
709 }
710
exynos_ufs_config_smu(struct exynos_ufs * ufs)711 static void exynos_ufs_config_smu(struct exynos_ufs *ufs)
712 {
713 u32 reg, val;
714
715 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val);
716
717 /* make encryption disabled by default */
718 reg = ufsp_readl(ufs, UFSPRSECURITY);
719 ufsp_writel(ufs, reg | NSSMU, UFSPRSECURITY);
720 ufsp_writel(ufs, 0x0, UFSPSBEGIN0);
721 ufsp_writel(ufs, 0xffffffff, UFSPSEND0);
722 ufsp_writel(ufs, 0xff, UFSPSLUN0);
723 ufsp_writel(ufs, 0xf1, UFSPSCTRL0);
724
725 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val);
726 }
727
exynos_ufs_config_sync_pattern_mask(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)728 static void exynos_ufs_config_sync_pattern_mask(struct exynos_ufs *ufs,
729 struct ufs_pa_layer_attr *pwr)
730 {
731 struct ufs_hba *hba = ufs->hba;
732 u8 g = max_t(u32, pwr->gear_rx, pwr->gear_tx);
733 u32 mask, sync_len;
734 enum {
735 SYNC_LEN_G1 = 80 * 1000, /* 80us */
736 SYNC_LEN_G2 = 40 * 1000, /* 44us */
737 SYNC_LEN_G3 = 20 * 1000, /* 20us */
738 };
739 int i;
740
741 if (g == 1)
742 sync_len = SYNC_LEN_G1;
743 else if (g == 2)
744 sync_len = SYNC_LEN_G2;
745 else if (g == 3)
746 sync_len = SYNC_LEN_G3;
747 else
748 return;
749
750 mask = exynos_ufs_calc_time_cntr(ufs, sync_len);
751 mask = (mask >> 8) & 0xff;
752
753 exynos_ufs_enable_ov_tm(hba);
754
755 for_each_ufs_rx_lane(ufs, i)
756 ufshcd_dme_set(hba,
757 UIC_ARG_MIB_SEL(RX_SYNC_MASK_LENGTH, i), mask);
758
759 exynos_ufs_disable_ov_tm(hba);
760 }
761
exynos_ufs_pre_pwr_mode(struct ufs_hba * hba,struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)762 static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba,
763 struct ufs_pa_layer_attr *dev_max_params,
764 struct ufs_pa_layer_attr *dev_req_params)
765 {
766 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
767 struct phy *generic_phy = ufs->phy;
768 struct ufs_dev_params ufs_exynos_cap;
769 int ret;
770
771 if (!dev_req_params) {
772 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
773 ret = -EINVAL;
774 goto out;
775 }
776
777 ufshcd_init_pwr_dev_param(&ufs_exynos_cap);
778
779 ret = ufshcd_get_pwr_dev_param(&ufs_exynos_cap,
780 dev_max_params, dev_req_params);
781 if (ret) {
782 pr_err("%s: failed to determine capabilities\n", __func__);
783 goto out;
784 }
785
786 if (ufs->drv_data->pre_pwr_change)
787 ufs->drv_data->pre_pwr_change(ufs, dev_req_params);
788
789 if (ufshcd_is_hs_mode(dev_req_params)) {
790 exynos_ufs_config_sync_pattern_mask(ufs, dev_req_params);
791
792 switch (dev_req_params->hs_rate) {
793 case PA_HS_MODE_A:
794 case PA_HS_MODE_B:
795 phy_calibrate(generic_phy);
796 break;
797 }
798 }
799
800 /* setting for three timeout values for traffic class #0 */
801 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064);
802 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL), 28224);
803 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160);
804
805 return 0;
806 out:
807 return ret;
808 }
809
810 #define PWR_MODE_STR_LEN 64
exynos_ufs_post_pwr_mode(struct ufs_hba * hba,struct ufs_pa_layer_attr * pwr_req)811 static int exynos_ufs_post_pwr_mode(struct ufs_hba *hba,
812 struct ufs_pa_layer_attr *pwr_req)
813 {
814 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
815 struct phy *generic_phy = ufs->phy;
816 int gear = max_t(u32, pwr_req->gear_rx, pwr_req->gear_tx);
817 int lanes = max_t(u32, pwr_req->lane_rx, pwr_req->lane_tx);
818 char pwr_str[PWR_MODE_STR_LEN] = "";
819
820 /* let default be PWM Gear 1, Lane 1 */
821 if (!gear)
822 gear = 1;
823
824 if (!lanes)
825 lanes = 1;
826
827 if (ufs->drv_data->post_pwr_change)
828 ufs->drv_data->post_pwr_change(ufs, pwr_req);
829
830 if ((ufshcd_is_hs_mode(pwr_req))) {
831 switch (pwr_req->hs_rate) {
832 case PA_HS_MODE_A:
833 case PA_HS_MODE_B:
834 phy_calibrate(generic_phy);
835 break;
836 }
837
838 snprintf(pwr_str, PWR_MODE_STR_LEN, "%s series_%s G_%d L_%d",
839 "FAST", pwr_req->hs_rate == PA_HS_MODE_A ? "A" : "B",
840 gear, lanes);
841 } else {
842 snprintf(pwr_str, PWR_MODE_STR_LEN, "%s G_%d L_%d",
843 "SLOW", gear, lanes);
844 }
845
846 dev_info(hba->dev, "Power mode changed to : %s\n", pwr_str);
847
848 return 0;
849 }
850
exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba * hba,int tag,bool is_scsi_cmd)851 static void exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba *hba,
852 int tag, bool is_scsi_cmd)
853 {
854 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
855 u32 type;
856
857 type = hci_readl(ufs, HCI_UTRL_NEXUS_TYPE);
858
859 if (is_scsi_cmd)
860 hci_writel(ufs, type | (1 << tag), HCI_UTRL_NEXUS_TYPE);
861 else
862 hci_writel(ufs, type & ~(1 << tag), HCI_UTRL_NEXUS_TYPE);
863 }
864
exynos_ufs_specify_nexus_t_tm_req(struct ufs_hba * hba,int tag,u8 func)865 static void exynos_ufs_specify_nexus_t_tm_req(struct ufs_hba *hba,
866 int tag, u8 func)
867 {
868 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
869 u32 type;
870
871 type = hci_readl(ufs, HCI_UTMRL_NEXUS_TYPE);
872
873 switch (func) {
874 case UFS_ABORT_TASK:
875 case UFS_QUERY_TASK:
876 hci_writel(ufs, type | (1 << tag), HCI_UTMRL_NEXUS_TYPE);
877 break;
878 case UFS_ABORT_TASK_SET:
879 case UFS_CLEAR_TASK_SET:
880 case UFS_LOGICAL_RESET:
881 case UFS_QUERY_TASK_SET:
882 hci_writel(ufs, type & ~(1 << tag), HCI_UTMRL_NEXUS_TYPE);
883 break;
884 }
885 }
886
exynos_ufs_phy_init(struct exynos_ufs * ufs)887 static int exynos_ufs_phy_init(struct exynos_ufs *ufs)
888 {
889 struct ufs_hba *hba = ufs->hba;
890 struct phy *generic_phy = ufs->phy;
891 int ret = 0;
892
893 if (ufs->avail_ln_rx == 0 || ufs->avail_ln_tx == 0) {
894 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES),
895 &ufs->avail_ln_rx);
896 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES),
897 &ufs->avail_ln_tx);
898 WARN(ufs->avail_ln_rx != ufs->avail_ln_tx,
899 "available data lane is not equal(rx:%d, tx:%d)\n",
900 ufs->avail_ln_rx, ufs->avail_ln_tx);
901 }
902
903 phy_set_bus_width(generic_phy, ufs->avail_ln_rx);
904 ret = phy_init(generic_phy);
905 if (ret) {
906 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
907 __func__, ret);
908 return ret;
909 }
910
911 ret = phy_power_on(generic_phy);
912 if (ret)
913 goto out_exit_phy;
914
915 return 0;
916
917 out_exit_phy:
918 phy_exit(generic_phy);
919
920 return ret;
921 }
922
exynos_ufs_config_unipro(struct exynos_ufs * ufs)923 static void exynos_ufs_config_unipro(struct exynos_ufs *ufs)
924 {
925 struct ufs_hba *hba = ufs->hba;
926
927 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD),
928 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
929 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTRAILINGCLOCKS),
930 ufs->drv_data->uic_attr->tx_trailingclks);
931 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE),
932 ufs->drv_data->uic_attr->pa_dbg_option_suite);
933 }
934
exynos_ufs_config_intr(struct exynos_ufs * ufs,u32 errs,u8 index)935 static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index)
936 {
937 switch (index) {
938 case UNIPRO_L1_5:
939 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_PA_LAYER);
940 break;
941 case UNIPRO_L2:
942 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DL_LAYER);
943 break;
944 case UNIPRO_L3:
945 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_N_LAYER);
946 break;
947 case UNIPRO_L4:
948 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_T_LAYER);
949 break;
950 case UNIPRO_DME:
951 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DME_LAYER);
952 break;
953 }
954 }
955
exynos_ufs_setup_clocks(struct ufs_hba * hba,bool on,enum ufs_notify_change_status status)956 static int exynos_ufs_setup_clocks(struct ufs_hba *hba, bool on,
957 enum ufs_notify_change_status status)
958 {
959 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
960
961 if (!ufs)
962 return 0;
963
964 if (on && status == PRE_CHANGE) {
965 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
966 exynos_ufs_disable_auto_ctrl_hcc(ufs);
967 exynos_ufs_ungate_clks(ufs);
968 } else if (!on && status == POST_CHANGE) {
969 exynos_ufs_gate_clks(ufs);
970 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
971 exynos_ufs_enable_auto_ctrl_hcc(ufs);
972 }
973
974 return 0;
975 }
976
exynos_ufs_pre_link(struct ufs_hba * hba)977 static int exynos_ufs_pre_link(struct ufs_hba *hba)
978 {
979 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
980
981 /* hci */
982 exynos_ufs_config_intr(ufs, DFES_DEF_L2_ERRS, UNIPRO_L2);
983 exynos_ufs_config_intr(ufs, DFES_DEF_L3_ERRS, UNIPRO_L3);
984 exynos_ufs_config_intr(ufs, DFES_DEF_L4_ERRS, UNIPRO_L4);
985 exynos_ufs_set_unipro_pclk_div(ufs);
986
987 /* unipro */
988 exynos_ufs_config_unipro(ufs);
989
990 /* m-phy */
991 exynos_ufs_phy_init(ufs);
992 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)) {
993 exynos_ufs_config_phy_time_attr(ufs);
994 exynos_ufs_config_phy_cap_attr(ufs);
995 }
996
997 exynos_ufs_setup_clocks(hba, true, PRE_CHANGE);
998
999 if (ufs->drv_data->pre_link)
1000 ufs->drv_data->pre_link(ufs);
1001
1002 return 0;
1003 }
1004
exynos_ufs_fit_aggr_timeout(struct exynos_ufs * ufs)1005 static void exynos_ufs_fit_aggr_timeout(struct exynos_ufs *ufs)
1006 {
1007 u32 val;
1008
1009 val = exynos_ufs_calc_time_cntr(ufs, IATOVAL_NSEC / CNTR_DIV_VAL);
1010 hci_writel(ufs, val & CNT_VAL_1US_MASK, HCI_1US_TO_CNT_VAL);
1011 }
1012
exynos_ufs_post_link(struct ufs_hba * hba)1013 static int exynos_ufs_post_link(struct ufs_hba *hba)
1014 {
1015 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1016 struct phy *generic_phy = ufs->phy;
1017 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
1018
1019 exynos_ufs_establish_connt(ufs);
1020 exynos_ufs_fit_aggr_timeout(ufs);
1021
1022 hci_writel(ufs, 0xa, HCI_DATA_REORDER);
1023 hci_writel(ufs, PRDT_SET_SIZE(12), HCI_TXPRDT_ENTRY_SIZE);
1024 hci_writel(ufs, PRDT_SET_SIZE(12), HCI_RXPRDT_ENTRY_SIZE);
1025 hci_writel(ufs, (1 << hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE);
1026 hci_writel(ufs, (1 << hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE);
1027 hci_writel(ufs, 0xf, HCI_AXIDMA_RWDATA_BURST_LEN);
1028
1029 if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB)
1030 ufshcd_dme_set(hba,
1031 UIC_ARG_MIB(T_DBG_SKIP_INIT_HIBERN8_EXIT), true);
1032
1033 if (attr->pa_granularity) {
1034 exynos_ufs_enable_dbg_mode(hba);
1035 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_GRANULARITY),
1036 attr->pa_granularity);
1037 exynos_ufs_disable_dbg_mode(hba);
1038
1039 if (attr->pa_tactivate)
1040 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
1041 attr->pa_tactivate);
1042 if (attr->pa_hibern8time &&
1043 !(ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER))
1044 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
1045 attr->pa_hibern8time);
1046 }
1047
1048 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) {
1049 if (!attr->pa_granularity)
1050 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
1051 &attr->pa_granularity);
1052 if (!attr->pa_hibern8time)
1053 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
1054 &attr->pa_hibern8time);
1055 /*
1056 * not wait for HIBERN8 time to exit hibernation
1057 */
1058 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 0);
1059
1060 if (attr->pa_granularity < 1 || attr->pa_granularity > 6) {
1061 /* Valid range for granularity: 1 ~ 6 */
1062 dev_warn(hba->dev,
1063 "%s: pa_granularity %d is invalid, assuming backwards compatibility\n",
1064 __func__,
1065 attr->pa_granularity);
1066 attr->pa_granularity = 6;
1067 }
1068 }
1069
1070 phy_calibrate(generic_phy);
1071
1072 if (ufs->drv_data->post_link)
1073 ufs->drv_data->post_link(ufs);
1074
1075 return 0;
1076 }
1077
exynos_ufs_parse_dt(struct device * dev,struct exynos_ufs * ufs)1078 static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs)
1079 {
1080 struct device_node *np = dev->of_node;
1081 struct exynos_ufs_uic_attr *attr;
1082 int ret = 0;
1083
1084 ufs->drv_data = device_get_match_data(dev);
1085
1086 if (ufs->drv_data && ufs->drv_data->uic_attr) {
1087 attr = ufs->drv_data->uic_attr;
1088 } else {
1089 dev_err(dev, "failed to get uic attributes\n");
1090 ret = -EINVAL;
1091 goto out;
1092 }
1093
1094 ufs->sysreg = syscon_regmap_lookup_by_phandle(np, "samsung,sysreg");
1095 if (IS_ERR(ufs->sysreg))
1096 ufs->sysreg = NULL;
1097 else {
1098 if (of_property_read_u32_index(np, "samsung,sysreg", 1,
1099 &ufs->shareability_reg_offset)) {
1100 dev_warn(dev, "can't get an offset from sysreg. Set to default value\n");
1101 ufs->shareability_reg_offset = UFS_SHAREABILITY_OFFSET;
1102 }
1103 }
1104
1105 ufs->pclk_avail_min = PCLK_AVAIL_MIN;
1106 ufs->pclk_avail_max = PCLK_AVAIL_MAX;
1107
1108 attr->rx_adv_fine_gran_sup_en = RX_ADV_FINE_GRAN_SUP_EN;
1109 attr->rx_adv_fine_gran_step = RX_ADV_FINE_GRAN_STEP_VAL;
1110 attr->rx_adv_min_actv_time_cap = RX_ADV_MIN_ACTV_TIME_CAP;
1111 attr->pa_granularity = PA_GRANULARITY_VAL;
1112 attr->pa_tactivate = PA_TACTIVATE_VAL;
1113 attr->pa_hibern8time = PA_HIBERN8TIME_VAL;
1114
1115 out:
1116 return ret;
1117 }
1118
exynos_ufs_priv_init(struct ufs_hba * hba,struct exynos_ufs * ufs)1119 static inline void exynos_ufs_priv_init(struct ufs_hba *hba,
1120 struct exynos_ufs *ufs)
1121 {
1122 ufs->hba = hba;
1123 ufs->opts = ufs->drv_data->opts;
1124 ufs->rx_sel_idx = PA_MAXDATALANES;
1125 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX)
1126 ufs->rx_sel_idx = 0;
1127 hba->priv = (void *)ufs;
1128 hba->quirks = ufs->drv_data->quirks;
1129 }
1130
exynos_ufs_init(struct ufs_hba * hba)1131 static int exynos_ufs_init(struct ufs_hba *hba)
1132 {
1133 struct device *dev = hba->dev;
1134 struct platform_device *pdev = to_platform_device(dev);
1135 struct exynos_ufs *ufs;
1136 int ret;
1137
1138 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL);
1139 if (!ufs)
1140 return -ENOMEM;
1141
1142 /* exynos-specific hci */
1143 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci");
1144 if (IS_ERR(ufs->reg_hci)) {
1145 dev_err(dev, "cannot ioremap for hci vendor register\n");
1146 return PTR_ERR(ufs->reg_hci);
1147 }
1148
1149 /* unipro */
1150 ufs->reg_unipro = devm_platform_ioremap_resource_byname(pdev, "unipro");
1151 if (IS_ERR(ufs->reg_unipro)) {
1152 dev_err(dev, "cannot ioremap for unipro register\n");
1153 return PTR_ERR(ufs->reg_unipro);
1154 }
1155
1156 /* ufs protector */
1157 ufs->reg_ufsp = devm_platform_ioremap_resource_byname(pdev, "ufsp");
1158 if (IS_ERR(ufs->reg_ufsp)) {
1159 dev_err(dev, "cannot ioremap for ufs protector register\n");
1160 return PTR_ERR(ufs->reg_ufsp);
1161 }
1162
1163 ret = exynos_ufs_parse_dt(dev, ufs);
1164 if (ret) {
1165 dev_err(dev, "failed to get dt info.\n");
1166 goto out;
1167 }
1168
1169 ufs->phy = devm_phy_get(dev, "ufs-phy");
1170 if (IS_ERR(ufs->phy)) {
1171 ret = PTR_ERR(ufs->phy);
1172 dev_err(dev, "failed to get ufs-phy\n");
1173 goto out;
1174 }
1175
1176 exynos_ufs_priv_init(hba, ufs);
1177
1178 if (ufs->drv_data->drv_init) {
1179 ret = ufs->drv_data->drv_init(dev, ufs);
1180 if (ret) {
1181 dev_err(dev, "failed to init drv-data\n");
1182 goto out;
1183 }
1184 }
1185
1186 ret = exynos_ufs_get_clk_info(ufs);
1187 if (ret)
1188 goto out;
1189 exynos_ufs_specify_phy_time_attr(ufs);
1190 exynos_ufs_config_smu(ufs);
1191 return 0;
1192
1193 out:
1194 hba->priv = NULL;
1195 return ret;
1196 }
1197
exynos_ufs_host_reset(struct ufs_hba * hba)1198 static int exynos_ufs_host_reset(struct ufs_hba *hba)
1199 {
1200 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1201 unsigned long timeout = jiffies + msecs_to_jiffies(1);
1202 u32 val;
1203 int ret = 0;
1204
1205 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val);
1206
1207 hci_writel(ufs, UFS_SW_RST_MASK, HCI_SW_RST);
1208
1209 do {
1210 if (!(hci_readl(ufs, HCI_SW_RST) & UFS_SW_RST_MASK))
1211 goto out;
1212 } while (time_before(jiffies, timeout));
1213
1214 dev_err(hba->dev, "timeout host sw-reset\n");
1215 ret = -ETIMEDOUT;
1216
1217 out:
1218 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val);
1219 return ret;
1220 }
1221
exynos_ufs_dev_hw_reset(struct ufs_hba * hba)1222 static void exynos_ufs_dev_hw_reset(struct ufs_hba *hba)
1223 {
1224 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1225
1226 hci_writel(ufs, 0 << 0, HCI_GPIO_OUT);
1227 udelay(5);
1228 hci_writel(ufs, 1 << 0, HCI_GPIO_OUT);
1229 }
1230
exynos_ufs_pre_hibern8(struct ufs_hba * hba,u8 enter)1231 static void exynos_ufs_pre_hibern8(struct ufs_hba *hba, u8 enter)
1232 {
1233 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1234 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
1235
1236 if (!enter) {
1237 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
1238 exynos_ufs_disable_auto_ctrl_hcc(ufs);
1239 exynos_ufs_ungate_clks(ufs);
1240
1241 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) {
1242 static const unsigned int granularity_tbl[] = {
1243 1, 4, 8, 16, 32, 100
1244 };
1245 int h8_time = attr->pa_hibern8time *
1246 granularity_tbl[attr->pa_granularity - 1];
1247 unsigned long us;
1248 s64 delta;
1249
1250 do {
1251 delta = h8_time - ktime_us_delta(ktime_get(),
1252 ufs->entry_hibern8_t);
1253 if (delta <= 0)
1254 break;
1255
1256 us = min_t(s64, delta, USEC_PER_MSEC);
1257 if (us >= 10)
1258 usleep_range(us, us + 10);
1259 } while (1);
1260 }
1261 }
1262 }
1263
exynos_ufs_post_hibern8(struct ufs_hba * hba,u8 enter)1264 static void exynos_ufs_post_hibern8(struct ufs_hba *hba, u8 enter)
1265 {
1266 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1267
1268 if (!enter) {
1269 u32 cur_mode = 0;
1270 u32 pwrmode;
1271
1272 if (ufshcd_is_hs_mode(&ufs->dev_req_params))
1273 pwrmode = FAST_MODE;
1274 else
1275 pwrmode = SLOW_MODE;
1276
1277 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &cur_mode);
1278 if (cur_mode != (pwrmode << 4 | pwrmode)) {
1279 dev_warn(hba->dev, "%s: power mode change\n", __func__);
1280 hba->pwr_info.pwr_rx = (cur_mode >> 4) & 0xf;
1281 hba->pwr_info.pwr_tx = cur_mode & 0xf;
1282 ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
1283 }
1284
1285 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB))
1286 exynos_ufs_establish_connt(ufs);
1287 } else {
1288 ufs->entry_hibern8_t = ktime_get();
1289 exynos_ufs_gate_clks(ufs);
1290 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
1291 exynos_ufs_enable_auto_ctrl_hcc(ufs);
1292 }
1293 }
1294
exynos_ufs_hce_enable_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)1295 static int exynos_ufs_hce_enable_notify(struct ufs_hba *hba,
1296 enum ufs_notify_change_status status)
1297 {
1298 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1299 int ret = 0;
1300
1301 switch (status) {
1302 case PRE_CHANGE:
1303 if (ufs->drv_data->pre_hce_enable) {
1304 ret = ufs->drv_data->pre_hce_enable(ufs);
1305 if (ret)
1306 return ret;
1307 }
1308
1309 ret = exynos_ufs_host_reset(hba);
1310 if (ret)
1311 return ret;
1312 exynos_ufs_dev_hw_reset(hba);
1313 break;
1314 case POST_CHANGE:
1315 exynos_ufs_calc_pwm_clk_div(ufs);
1316 if (!(ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL))
1317 exynos_ufs_enable_auto_ctrl_hcc(ufs);
1318
1319 if (ufs->drv_data->post_hce_enable)
1320 ret = ufs->drv_data->post_hce_enable(ufs);
1321
1322 break;
1323 }
1324
1325 return ret;
1326 }
1327
exynos_ufs_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)1328 static int exynos_ufs_link_startup_notify(struct ufs_hba *hba,
1329 enum ufs_notify_change_status status)
1330 {
1331 int ret = 0;
1332
1333 switch (status) {
1334 case PRE_CHANGE:
1335 ret = exynos_ufs_pre_link(hba);
1336 break;
1337 case POST_CHANGE:
1338 ret = exynos_ufs_post_link(hba);
1339 break;
1340 }
1341
1342 return ret;
1343 }
1344
exynos_ufs_pwr_change_notify(struct ufs_hba * hba,enum ufs_notify_change_status status,struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)1345 static int exynos_ufs_pwr_change_notify(struct ufs_hba *hba,
1346 enum ufs_notify_change_status status,
1347 struct ufs_pa_layer_attr *dev_max_params,
1348 struct ufs_pa_layer_attr *dev_req_params)
1349 {
1350 int ret = 0;
1351
1352 switch (status) {
1353 case PRE_CHANGE:
1354 ret = exynos_ufs_pre_pwr_mode(hba, dev_max_params,
1355 dev_req_params);
1356 break;
1357 case POST_CHANGE:
1358 ret = exynos_ufs_post_pwr_mode(hba, dev_req_params);
1359 break;
1360 }
1361
1362 return ret;
1363 }
1364
exynos_ufs_hibern8_notify(struct ufs_hba * hba,enum uic_cmd_dme enter,enum ufs_notify_change_status notify)1365 static void exynos_ufs_hibern8_notify(struct ufs_hba *hba,
1366 enum uic_cmd_dme enter,
1367 enum ufs_notify_change_status notify)
1368 {
1369 switch ((u8)notify) {
1370 case PRE_CHANGE:
1371 exynos_ufs_pre_hibern8(hba, enter);
1372 break;
1373 case POST_CHANGE:
1374 exynos_ufs_post_hibern8(hba, enter);
1375 break;
1376 }
1377 }
1378
exynos_ufs_suspend(struct ufs_hba * hba,enum ufs_pm_op pm_op,enum ufs_notify_change_status status)1379 static int exynos_ufs_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
1380 enum ufs_notify_change_status status)
1381 {
1382 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1383
1384 if (status == PRE_CHANGE)
1385 return 0;
1386
1387 if (!ufshcd_is_link_active(hba))
1388 phy_power_off(ufs->phy);
1389
1390 return 0;
1391 }
1392
exynos_ufs_resume(struct ufs_hba * hba,enum ufs_pm_op pm_op)1393 static int exynos_ufs_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
1394 {
1395 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1396
1397 if (!ufshcd_is_link_active(hba))
1398 phy_power_on(ufs->phy);
1399
1400 exynos_ufs_config_smu(ufs);
1401
1402 return 0;
1403 }
1404
exynosauto_ufs_vh_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)1405 static int exynosauto_ufs_vh_link_startup_notify(struct ufs_hba *hba,
1406 enum ufs_notify_change_status status)
1407 {
1408 if (status == POST_CHANGE) {
1409 ufshcd_set_link_active(hba);
1410 ufshcd_set_ufs_dev_active(hba);
1411 }
1412
1413 return 0;
1414 }
1415
exynosauto_ufs_vh_wait_ph_ready(struct ufs_hba * hba)1416 static int exynosauto_ufs_vh_wait_ph_ready(struct ufs_hba *hba)
1417 {
1418 u32 mbox;
1419 ktime_t start, stop;
1420
1421 start = ktime_get();
1422 stop = ktime_add(start, ms_to_ktime(PH_READY_TIMEOUT_MS));
1423
1424 do {
1425 mbox = ufshcd_readl(hba, PH2VH_MBOX);
1426 /* TODO: Mailbox message protocols between the PH and VHs are
1427 * not implemented yet. This will be supported later
1428 */
1429 if ((mbox & MH_MSG_MASK) == MH_MSG_PH_READY)
1430 return 0;
1431
1432 usleep_range(40, 50);
1433 } while (ktime_before(ktime_get(), stop));
1434
1435 return -ETIME;
1436 }
1437
exynosauto_ufs_vh_init(struct ufs_hba * hba)1438 static int exynosauto_ufs_vh_init(struct ufs_hba *hba)
1439 {
1440 struct device *dev = hba->dev;
1441 struct platform_device *pdev = to_platform_device(dev);
1442 struct exynos_ufs *ufs;
1443 int ret;
1444
1445 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL);
1446 if (!ufs)
1447 return -ENOMEM;
1448
1449 /* exynos-specific hci */
1450 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci");
1451 if (IS_ERR(ufs->reg_hci)) {
1452 dev_err(dev, "cannot ioremap for hci vendor register\n");
1453 return PTR_ERR(ufs->reg_hci);
1454 }
1455
1456 ret = exynosauto_ufs_vh_wait_ph_ready(hba);
1457 if (ret)
1458 return ret;
1459
1460 ufs->drv_data = device_get_match_data(dev);
1461 if (!ufs->drv_data)
1462 return -ENODEV;
1463
1464 exynos_ufs_priv_init(hba, ufs);
1465
1466 return 0;
1467 }
1468
fsd_ufs_pre_link(struct exynos_ufs * ufs)1469 static int fsd_ufs_pre_link(struct exynos_ufs *ufs)
1470 {
1471 int i;
1472 struct ufs_hba *hba = ufs->hba;
1473
1474 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD),
1475 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
1476 ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12);
1477 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
1478
1479 for_each_ufs_tx_lane(ufs, i) {
1480 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i),
1481 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
1482 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F);
1483 }
1484
1485 for_each_ufs_rx_lane(ufs, i) {
1486 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i),
1487 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
1488 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38);
1489 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0);
1490 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1);
1491 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1);
1492 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0);
1493 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0);
1494 }
1495
1496 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
1497 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_AUTOMODE_THLD), 0x4E20);
1498 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), 0x2e820183);
1499 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0);
1500
1501 exynos_ufs_establish_connt(ufs);
1502
1503 return 0;
1504 }
1505
fsd_ufs_post_link(struct exynos_ufs * ufs)1506 static int fsd_ufs_post_link(struct exynos_ufs *ufs)
1507 {
1508 int i;
1509 struct ufs_hba *hba = ufs->hba;
1510 u32 hw_cap_min_tactivate;
1511 u32 peer_rx_min_actv_time_cap;
1512 u32 max_rx_hibern8_time_cap;
1513
1514 ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4),
1515 &hw_cap_min_tactivate); /* HW Capability of MIN_TACTIVATE */
1516 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
1517 &peer_rx_min_actv_time_cap); /* PA_TActivate */
1518 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
1519 &max_rx_hibern8_time_cap); /* PA_Hibern8Time */
1520
1521 if (peer_rx_min_actv_time_cap >= hw_cap_min_tactivate)
1522 ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
1523 peer_rx_min_actv_time_cap + 1);
1524 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), max_rx_hibern8_time_cap + 1);
1525
1526 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), 0x01);
1527 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xFA);
1528 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), 0x00);
1529
1530 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
1531
1532 for_each_ufs_rx_lane(ufs, i) {
1533 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05);
1534 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01);
1535 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02);
1536 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC);
1537 }
1538
1539 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
1540
1541 return 0;
1542 }
1543
fsd_ufs_pre_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)1544 static int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs,
1545 struct ufs_pa_layer_attr *pwr)
1546 {
1547 struct ufs_hba *hba = ufs->hba;
1548
1549 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), 0x1);
1550 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), 0x1);
1551 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000);
1552 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000);
1553 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000);
1554
1555 unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0);
1556 unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1);
1557 unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2);
1558
1559 return 0;
1560 }
1561
1562 static const struct ufs_hba_variant_ops ufs_hba_exynos_ops = {
1563 .name = "exynos_ufs",
1564 .init = exynos_ufs_init,
1565 .hce_enable_notify = exynos_ufs_hce_enable_notify,
1566 .link_startup_notify = exynos_ufs_link_startup_notify,
1567 .pwr_change_notify = exynos_ufs_pwr_change_notify,
1568 .setup_clocks = exynos_ufs_setup_clocks,
1569 .setup_xfer_req = exynos_ufs_specify_nexus_t_xfer_req,
1570 .setup_task_mgmt = exynos_ufs_specify_nexus_t_tm_req,
1571 .hibern8_notify = exynos_ufs_hibern8_notify,
1572 .suspend = exynos_ufs_suspend,
1573 .resume = exynos_ufs_resume,
1574 };
1575
1576 static struct ufs_hba_variant_ops ufs_hba_exynosauto_vh_ops = {
1577 .name = "exynosauto_ufs_vh",
1578 .init = exynosauto_ufs_vh_init,
1579 .link_startup_notify = exynosauto_ufs_vh_link_startup_notify,
1580 };
1581
exynos_ufs_probe(struct platform_device * pdev)1582 static int exynos_ufs_probe(struct platform_device *pdev)
1583 {
1584 int err;
1585 struct device *dev = &pdev->dev;
1586 const struct ufs_hba_variant_ops *vops = &ufs_hba_exynos_ops;
1587 const struct exynos_ufs_drv_data *drv_data =
1588 device_get_match_data(dev);
1589
1590 if (drv_data && drv_data->vops)
1591 vops = drv_data->vops;
1592
1593 err = ufshcd_pltfrm_init(pdev, vops);
1594 if (err)
1595 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1596
1597 return err;
1598 }
1599
exynos_ufs_remove(struct platform_device * pdev)1600 static int exynos_ufs_remove(struct platform_device *pdev)
1601 {
1602 struct ufs_hba *hba = platform_get_drvdata(pdev);
1603 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1604
1605 pm_runtime_get_sync(&(pdev)->dev);
1606 ufshcd_remove(hba);
1607
1608 phy_power_off(ufs->phy);
1609 phy_exit(ufs->phy);
1610
1611 return 0;
1612 }
1613
1614 static struct exynos_ufs_uic_attr exynos7_uic_attr = {
1615 .tx_trailingclks = 0x10,
1616 .tx_dif_p_nsec = 3000000, /* unit: ns */
1617 .tx_dif_n_nsec = 1000000, /* unit: ns */
1618 .tx_high_z_cnt_nsec = 20000, /* unit: ns */
1619 .tx_base_unit_nsec = 100000, /* unit: ns */
1620 .tx_gran_unit_nsec = 4000, /* unit: ns */
1621 .tx_sleep_cnt = 1000, /* unit: ns */
1622 .tx_min_activatetime = 0xa,
1623 .rx_filler_enable = 0x2,
1624 .rx_dif_p_nsec = 1000000, /* unit: ns */
1625 .rx_hibern8_wait_nsec = 4000000, /* unit: ns */
1626 .rx_base_unit_nsec = 100000, /* unit: ns */
1627 .rx_gran_unit_nsec = 4000, /* unit: ns */
1628 .rx_sleep_cnt = 1280, /* unit: ns */
1629 .rx_stall_cnt = 320, /* unit: ns */
1630 .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf),
1631 .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf),
1632 .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf),
1633 .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf),
1634 .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf),
1635 .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf),
1636 .pa_dbg_option_suite = 0x30103,
1637 };
1638
1639 static const struct exynos_ufs_drv_data exynosauto_ufs_drvs = {
1640 .uic_attr = &exynos7_uic_attr,
1641 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
1642 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
1643 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
1644 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
1645 .opts = EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
1646 EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
1647 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
1648 .drv_init = exynosauto_ufs_drv_init,
1649 .post_hce_enable = exynosauto_ufs_post_hce_enable,
1650 .pre_link = exynosauto_ufs_pre_link,
1651 .pre_pwr_change = exynosauto_ufs_pre_pwr_change,
1652 .post_pwr_change = exynosauto_ufs_post_pwr_change,
1653 };
1654
1655 static const struct exynos_ufs_drv_data exynosauto_ufs_vh_drvs = {
1656 .vops = &ufs_hba_exynosauto_vh_ops,
1657 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
1658 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
1659 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
1660 UFSHCI_QUIRK_BROKEN_HCE |
1661 UFSHCD_QUIRK_BROKEN_UIC_CMD |
1662 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION |
1663 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
1664 .opts = EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
1665 };
1666
1667 static const struct exynos_ufs_drv_data exynos_ufs_drvs = {
1668 .uic_attr = &exynos7_uic_attr,
1669 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
1670 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
1671 UFSHCI_QUIRK_BROKEN_HCE |
1672 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
1673 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
1674 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL |
1675 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING |
1676 UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE,
1677 .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
1678 EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
1679 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX |
1680 EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB |
1681 EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER,
1682 .drv_init = exynos7_ufs_drv_init,
1683 .pre_link = exynos7_ufs_pre_link,
1684 .post_link = exynos7_ufs_post_link,
1685 .pre_pwr_change = exynos7_ufs_pre_pwr_change,
1686 .post_pwr_change = exynos7_ufs_post_pwr_change,
1687 };
1688
1689 static struct exynos_ufs_uic_attr fsd_uic_attr = {
1690 .tx_trailingclks = 0x10,
1691 .tx_dif_p_nsec = 3000000, /* unit: ns */
1692 .tx_dif_n_nsec = 1000000, /* unit: ns */
1693 .tx_high_z_cnt_nsec = 20000, /* unit: ns */
1694 .tx_base_unit_nsec = 100000, /* unit: ns */
1695 .tx_gran_unit_nsec = 4000, /* unit: ns */
1696 .tx_sleep_cnt = 1000, /* unit: ns */
1697 .tx_min_activatetime = 0xa,
1698 .rx_filler_enable = 0x2,
1699 .rx_dif_p_nsec = 1000000, /* unit: ns */
1700 .rx_hibern8_wait_nsec = 4000000, /* unit: ns */
1701 .rx_base_unit_nsec = 100000, /* unit: ns */
1702 .rx_gran_unit_nsec = 4000, /* unit: ns */
1703 .rx_sleep_cnt = 1280, /* unit: ns */
1704 .rx_stall_cnt = 320, /* unit: ns */
1705 .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf),
1706 .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf),
1707 .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf),
1708 .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf),
1709 .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf),
1710 .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf),
1711 .pa_dbg_option_suite = 0x2E820183,
1712 };
1713
1714 static const struct exynos_ufs_drv_data fsd_ufs_drvs = {
1715 .uic_attr = &fsd_uic_attr,
1716 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
1717 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
1718 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
1719 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING |
1720 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR,
1721 .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
1722 EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
1723 EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
1724 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
1725 .pre_link = fsd_ufs_pre_link,
1726 .post_link = fsd_ufs_post_link,
1727 .pre_pwr_change = fsd_ufs_pre_pwr_change,
1728 };
1729
1730 static const struct of_device_id exynos_ufs_of_match[] = {
1731 { .compatible = "samsung,exynos7-ufs",
1732 .data = &exynos_ufs_drvs },
1733 { .compatible = "samsung,exynosautov9-ufs",
1734 .data = &exynosauto_ufs_drvs },
1735 { .compatible = "samsung,exynosautov9-ufs-vh",
1736 .data = &exynosauto_ufs_vh_drvs },
1737 { .compatible = "tesla,fsd-ufs",
1738 .data = &fsd_ufs_drvs },
1739 {},
1740 };
1741
1742 static const struct dev_pm_ops exynos_ufs_pm_ops = {
1743 SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume)
1744 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
1745 .prepare = ufshcd_suspend_prepare,
1746 .complete = ufshcd_resume_complete,
1747 };
1748
1749 static struct platform_driver exynos_ufs_pltform = {
1750 .probe = exynos_ufs_probe,
1751 .remove = exynos_ufs_remove,
1752 .shutdown = ufshcd_pltfrm_shutdown,
1753 .driver = {
1754 .name = "exynos-ufshc",
1755 .pm = &exynos_ufs_pm_ops,
1756 .of_match_table = of_match_ptr(exynos_ufs_of_match),
1757 },
1758 };
1759 module_platform_driver(exynos_ufs_pltform);
1760
1761 MODULE_AUTHOR("Alim Akhtar <alim.akhtar@samsung.com>");
1762 MODULE_AUTHOR("Seungwon Jeon <essuuj@gmail.com>");
1763 MODULE_DESCRIPTION("Exynos UFS HCI Driver");
1764 MODULE_LICENSE("GPL v2");
1765