1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2009-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 */
6
7 #ifndef AMD_IOMMU_H
8 #define AMD_IOMMU_H
9
10 #include <linux/iommu.h>
11
12 #include "amd_iommu_types.h"
13
14 extern irqreturn_t amd_iommu_int_thread(int irq, void *data);
15 extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
16 extern void amd_iommu_apply_erratum_63(u16 devid);
17 extern void amd_iommu_restart_event_logging(struct amd_iommu *iommu);
18 extern int amd_iommu_init_devices(void);
19 extern void amd_iommu_uninit_devices(void);
20 extern void amd_iommu_init_notifier(void);
21 extern int amd_iommu_init_api(void);
22
23 #ifdef CONFIG_AMD_IOMMU_DEBUGFS
24 void amd_iommu_debugfs_setup(struct amd_iommu *iommu);
25 #else
amd_iommu_debugfs_setup(struct amd_iommu * iommu)26 static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {}
27 #endif
28
29 /* Needed for interrupt remapping */
30 extern int amd_iommu_prepare(void);
31 extern int amd_iommu_enable(void);
32 extern void amd_iommu_disable(void);
33 extern int amd_iommu_reenable(int);
34 extern int amd_iommu_enable_faulting(void);
35 extern int amd_iommu_guest_ir;
36 extern enum io_pgtable_fmt amd_iommu_pgtable;
37
38 /* IOMMUv2 specific functions */
39 struct iommu_domain;
40
41 extern bool amd_iommu_v2_supported(void);
42 extern struct amd_iommu *get_amd_iommu(unsigned int idx);
43 extern u8 amd_iommu_pc_get_max_banks(unsigned int idx);
44 extern bool amd_iommu_pc_supported(void);
45 extern u8 amd_iommu_pc_get_max_counters(unsigned int idx);
46 extern int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
47 u8 fxn, u64 *value);
48 extern int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
49 u8 fxn, u64 *value);
50
51 extern int amd_iommu_register_ppr_notifier(struct notifier_block *nb);
52 extern int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb);
53 extern void amd_iommu_domain_direct_map(struct iommu_domain *dom);
54 extern int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids);
55 extern int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,
56 u64 address);
57 extern void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);
58 extern void amd_iommu_domain_update(struct protection_domain *domain);
59 extern void amd_iommu_domain_flush_complete(struct protection_domain *domain);
60 extern void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain);
61 extern int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid);
62 extern int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
63 unsigned long cr3);
64 extern int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid);
65
66 #ifdef CONFIG_IRQ_REMAP
67 extern int amd_iommu_create_irq_domain(struct amd_iommu *iommu);
68 #else
amd_iommu_create_irq_domain(struct amd_iommu * iommu)69 static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
70 {
71 return 0;
72 }
73 #endif
74
75 #define PPR_SUCCESS 0x0
76 #define PPR_INVALID 0x1
77 #define PPR_FAILURE 0xf
78
79 extern int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
80 int status, int tag);
81
is_rd890_iommu(struct pci_dev * pdev)82 static inline bool is_rd890_iommu(struct pci_dev *pdev)
83 {
84 return (pdev->vendor == PCI_VENDOR_ID_ATI) &&
85 (pdev->device == PCI_DEVICE_ID_RD890_IOMMU);
86 }
87
iommu_feature(struct amd_iommu * iommu,u64 mask)88 static inline bool iommu_feature(struct amd_iommu *iommu, u64 mask)
89 {
90 return !!(iommu->features & mask);
91 }
92
iommu_virt_to_phys(void * vaddr)93 static inline u64 iommu_virt_to_phys(void *vaddr)
94 {
95 return (u64)__sme_set(virt_to_phys(vaddr));
96 }
97
iommu_phys_to_virt(unsigned long paddr)98 static inline void *iommu_phys_to_virt(unsigned long paddr)
99 {
100 return phys_to_virt(__sme_clr(paddr));
101 }
102
103 static inline
amd_iommu_domain_set_pt_root(struct protection_domain * domain,u64 root)104 void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root)
105 {
106 atomic64_set(&domain->iop.pt_root, root);
107 domain->iop.root = (u64 *)(root & PAGE_MASK);
108 domain->iop.mode = root & 7; /* lowest 3 bits encode pgtable mode */
109 }
110
111 static inline
amd_iommu_domain_clr_pt_root(struct protection_domain * domain)112 void amd_iommu_domain_clr_pt_root(struct protection_domain *domain)
113 {
114 amd_iommu_domain_set_pt_root(domain, 0);
115 }
116
117
118 extern bool translation_pre_enabled(struct amd_iommu *iommu);
119 extern bool amd_iommu_is_attach_deferred(struct device *dev);
120 extern int __init add_special_device(u8 type, u8 id, u16 *devid,
121 bool cmd_line);
122
123 #ifdef CONFIG_DMI
124 void amd_iommu_apply_ivrs_quirks(void);
125 #else
amd_iommu_apply_ivrs_quirks(void)126 static inline void amd_iommu_apply_ivrs_quirks(void) { }
127 #endif
128
129 extern void amd_iommu_domain_set_pgtable(struct protection_domain *domain,
130 u64 *root, int mode);
131 #endif
132