1 /*
2  * This is the Fusion MPT base driver providing common API layer interface
3  * for access to MPT (Message Passing Technology) firmware.
4  *
5  * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.h
6  * Copyright (C) 2012-2014  LSI Corporation
7  * Copyright (C) 2013-2014 Avago Technologies
8  *  (mailto: MPT-FusionLinux.pdl@avagotech.com)
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License
12  * as published by the Free Software Foundation; either version 2
13  * of the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * NO WARRANTY
21  * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22  * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23  * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25  * solely responsible for determining the appropriateness of using and
26  * distributing the Program and assumes all risks associated with its
27  * exercise of rights under this Agreement, including but not limited to
28  * the risks and costs of program errors, damage to or loss of data,
29  * programs or equipment, and unavailability or interruption of operations.
30 
31  * DISCLAIMER OF LIABILITY
32  * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34  * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36  * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37  * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38  * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
39 
40  * You should have received a copy of the GNU General Public License
41  * along with this program; if not, write to the Free Software
42  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301,
43  * USA.
44  */
45 
46 #ifndef MPT3SAS_BASE_H_INCLUDED
47 #define MPT3SAS_BASE_H_INCLUDED
48 
49 #include "mpi/mpi2_type.h"
50 #include "mpi/mpi2.h"
51 #include "mpi/mpi2_ioc.h"
52 #include "mpi/mpi2_cnfg.h"
53 #include "mpi/mpi2_init.h"
54 #include "mpi/mpi2_raid.h"
55 #include "mpi/mpi2_tool.h"
56 #include "mpi/mpi2_sas.h"
57 #include "mpi/mpi2_pci.h"
58 #include "mpi/mpi2_image.h"
59 
60 #include <scsi/scsi.h>
61 #include <scsi/scsi_cmnd.h>
62 #include <scsi/scsi_device.h>
63 #include <scsi/scsi_host.h>
64 #include <scsi/scsi_tcq.h>
65 #include <scsi/scsi_transport_sas.h>
66 #include <scsi/scsi_dbg.h>
67 #include <scsi/scsi_eh.h>
68 #include <linux/pci.h>
69 #include <linux/poll.h>
70 #include <linux/irq_poll.h>
71 
72 #include "mpt3sas_debug.h"
73 #include "mpt3sas_trigger_diag.h"
74 #include "mpt3sas_trigger_pages.h"
75 
76 /* driver versioning info */
77 #define MPT3SAS_DRIVER_NAME		"mpt3sas"
78 #define MPT3SAS_AUTHOR "Avago Technologies <MPT-FusionLinux.pdl@avagotech.com>"
79 #define MPT3SAS_DESCRIPTION	"LSI MPT Fusion SAS 3.0 Device Driver"
80 #define MPT3SAS_DRIVER_VERSION		"43.100.00.00"
81 #define MPT3SAS_MAJOR_VERSION		43
82 #define MPT3SAS_MINOR_VERSION		100
83 #define MPT3SAS_BUILD_VERSION		0
84 #define MPT3SAS_RELEASE_VERSION	00
85 
86 #define MPT2SAS_DRIVER_NAME		"mpt2sas"
87 #define MPT2SAS_DESCRIPTION	"LSI MPT Fusion SAS 2.0 Device Driver"
88 #define MPT2SAS_DRIVER_VERSION		"20.102.00.00"
89 #define MPT2SAS_MAJOR_VERSION		20
90 #define MPT2SAS_MINOR_VERSION		102
91 #define MPT2SAS_BUILD_VERSION		0
92 #define MPT2SAS_RELEASE_VERSION	00
93 
94 /* CoreDump: Default timeout */
95 #define MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS	(15) /*15 seconds*/
96 #define MPT3SAS_COREDUMP_LOOP_DONE                     (0xFF)
97 #define MPT3SAS_TIMESYNC_TIMEOUT_SECONDS		(10) /* 10 seconds */
98 #define MPT3SAS_TIMESYNC_UPDATE_INTERVAL		(900) /* 15 minutes */
99 #define MPT3SAS_TIMESYNC_UNIT_MASK			(0x80) /* bit 7 */
100 #define MPT3SAS_TIMESYNC_MASK				(0x7F) /* 0 - 6 bits */
101 #define SECONDS_PER_MIN					(60)
102 #define SECONDS_PER_HOUR				(3600)
103 #define MPT3SAS_COREDUMP_LOOP_DONE			(0xFF)
104 #define MPI26_SET_IOC_PARAMETER_SYNC_TIMESTAMP		(0x81)
105 
106 /*
107  * Set MPT3SAS_SG_DEPTH value based on user input.
108  */
109 #define MPT_MAX_PHYS_SEGMENTS	SG_CHUNK_SIZE
110 #define MPT_MIN_PHYS_SEGMENTS	16
111 #define MPT_KDUMP_MIN_PHYS_SEGMENTS	32
112 
113 #define MCPU_MAX_CHAINS_PER_IO	3
114 
115 #ifdef CONFIG_SCSI_MPT3SAS_MAX_SGE
116 #define MPT3SAS_SG_DEPTH		CONFIG_SCSI_MPT3SAS_MAX_SGE
117 #else
118 #define MPT3SAS_SG_DEPTH		MPT_MAX_PHYS_SEGMENTS
119 #endif
120 
121 #ifdef CONFIG_SCSI_MPT2SAS_MAX_SGE
122 #define MPT2SAS_SG_DEPTH		CONFIG_SCSI_MPT2SAS_MAX_SGE
123 #else
124 #define MPT2SAS_SG_DEPTH		MPT_MAX_PHYS_SEGMENTS
125 #endif
126 
127 /*
128  * Generic Defines
129  */
130 #define MPT3SAS_SATA_QUEUE_DEPTH	32
131 #define MPT3SAS_SAS_QUEUE_DEPTH		254
132 #define MPT3SAS_RAID_QUEUE_DEPTH	128
133 #define MPT3SAS_KDUMP_SCSI_IO_DEPTH	200
134 
135 #define MPT3SAS_RAID_MAX_SECTORS	8192
136 #define MPT3SAS_HOST_PAGE_SIZE_4K	12
137 #define MPT3SAS_NVME_QUEUE_DEPTH	128
138 #define MPT_NAME_LENGTH			32	/* generic length of strings */
139 #define MPT_STRING_LENGTH		64
140 #define MPI_FRAME_START_OFFSET		256
141 #define REPLY_FREE_POOL_SIZE		512 /*(32 maxcredix *4)*(4 times)*/
142 
143 #define MPT_MAX_CALLBACKS		32
144 
145 #define MPT_MAX_HBA_NUM_PHYS		32
146 
147 #define INTERNAL_CMDS_COUNT		10	/* reserved cmds */
148 /* reserved for issuing internally framed scsi io cmds */
149 #define INTERNAL_SCSIIO_CMDS_COUNT	3
150 
151 #define MPI3_HIM_MASK			0xFFFFFFFF /* mask every bit*/
152 
153 #define MPT3SAS_INVALID_DEVICE_HANDLE	0xFFFF
154 
155 #define MAX_CHAIN_ELEMT_SZ		16
156 #define DEFAULT_NUM_FWCHAIN_ELEMTS	8
157 
158 #define IO_UNIT_CONTROL_SHUTDOWN_TIMEOUT 6
159 #define FW_IMG_HDR_READ_TIMEOUT	15
160 
161 #define IOC_OPERATIONAL_WAIT_COUNT	10
162 
163 /*
164  * NVMe defines
165  */
166 #define	NVME_PRP_SIZE			8	/* PRP size */
167 #define	NVME_ERROR_RESPONSE_SIZE	16	/* Max NVME Error Response */
168 #define NVME_TASK_ABORT_MIN_TIMEOUT	6
169 #define NVME_TASK_ABORT_MAX_TIMEOUT	60
170 #define NVME_TASK_MNGT_CUSTOM_MASK	(0x0010)
171 #define	NVME_PRP_PAGE_SIZE		4096	/* Page size */
172 
173 struct mpt3sas_nvme_cmd {
174 	u8	rsvd[24];
175 	__le64	prp1;
176 	__le64	prp2;
177 };
178 
179 /*
180  * logging format
181  */
182 #define ioc_err(ioc, fmt, ...)						\
183 	pr_err("%s: " fmt, (ioc)->name, ##__VA_ARGS__)
184 #define ioc_notice(ioc, fmt, ...)					\
185 	pr_notice("%s: " fmt, (ioc)->name, ##__VA_ARGS__)
186 #define ioc_warn(ioc, fmt, ...)						\
187 	pr_warn("%s: " fmt, (ioc)->name, ##__VA_ARGS__)
188 #define ioc_info(ioc, fmt, ...)						\
189 	pr_info("%s: " fmt, (ioc)->name, ##__VA_ARGS__)
190 
191 /*
192  *  WarpDrive Specific Log codes
193  */
194 
195 #define MPT2_WARPDRIVE_LOGENTRY		(0x8002)
196 #define MPT2_WARPDRIVE_LC_SSDT			(0x41)
197 #define MPT2_WARPDRIVE_LC_SSDLW		(0x43)
198 #define MPT2_WARPDRIVE_LC_SSDLF		(0x44)
199 #define MPT2_WARPDRIVE_LC_BRMF			(0x4D)
200 
201 /*
202  * per target private data
203  */
204 #define MPT_TARGET_FLAGS_RAID_COMPONENT	0x01
205 #define MPT_TARGET_FLAGS_VOLUME		0x02
206 #define MPT_TARGET_FLAGS_DELETED	0x04
207 #define MPT_TARGET_FASTPATH_IO		0x08
208 #define MPT_TARGET_FLAGS_PCIE_DEVICE	0x10
209 
210 #define SAS2_PCI_DEVICE_B0_REVISION	(0x01)
211 #define SAS3_PCI_DEVICE_C0_REVISION	(0x02)
212 
213 /* Atlas PCIe Switch Management Port */
214 #define MPI26_ATLAS_PCIe_SWITCH_DEVID	(0x00B2)
215 
216 /*
217  * Intel HBA branding
218  */
219 #define MPT2SAS_INTEL_RMS25JB080_BRANDING    \
220 	"Intel(R) Integrated RAID Module RMS25JB080"
221 #define MPT2SAS_INTEL_RMS25JB040_BRANDING    \
222 	"Intel(R) Integrated RAID Module RMS25JB040"
223 #define MPT2SAS_INTEL_RMS25KB080_BRANDING    \
224 	"Intel(R) Integrated RAID Module RMS25KB080"
225 #define MPT2SAS_INTEL_RMS25KB040_BRANDING    \
226 	"Intel(R) Integrated RAID Module RMS25KB040"
227 #define MPT2SAS_INTEL_RMS25LB040_BRANDING	\
228 	"Intel(R) Integrated RAID Module RMS25LB040"
229 #define MPT2SAS_INTEL_RMS25LB080_BRANDING	\
230 	"Intel(R) Integrated RAID Module RMS25LB080"
231 #define MPT2SAS_INTEL_RMS2LL080_BRANDING	\
232 	"Intel Integrated RAID Module RMS2LL080"
233 #define MPT2SAS_INTEL_RMS2LL040_BRANDING	\
234 	"Intel Integrated RAID Module RMS2LL040"
235 #define MPT2SAS_INTEL_RS25GB008_BRANDING       \
236 	"Intel(R) RAID Controller RS25GB008"
237 #define MPT2SAS_INTEL_SSD910_BRANDING          \
238 	"Intel(R) SSD 910 Series"
239 
240 #define MPT3SAS_INTEL_RMS3JC080_BRANDING       \
241 	"Intel(R) Integrated RAID Module RMS3JC080"
242 #define MPT3SAS_INTEL_RS3GC008_BRANDING       \
243 	"Intel(R) RAID Controller RS3GC008"
244 #define MPT3SAS_INTEL_RS3FC044_BRANDING       \
245 	"Intel(R) RAID Controller RS3FC044"
246 #define MPT3SAS_INTEL_RS3UC080_BRANDING       \
247 	"Intel(R) RAID Controller RS3UC080"
248 
249 /*
250  * Intel HBA SSDIDs
251  */
252 #define MPT2SAS_INTEL_RMS25JB080_SSDID		0x3516
253 #define MPT2SAS_INTEL_RMS25JB040_SSDID		0x3517
254 #define MPT2SAS_INTEL_RMS25KB080_SSDID		0x3518
255 #define MPT2SAS_INTEL_RMS25KB040_SSDID		0x3519
256 #define MPT2SAS_INTEL_RMS25LB040_SSDID		0x351A
257 #define MPT2SAS_INTEL_RMS25LB080_SSDID		0x351B
258 #define MPT2SAS_INTEL_RMS2LL080_SSDID		0x350E
259 #define MPT2SAS_INTEL_RMS2LL040_SSDID		0x350F
260 #define MPT2SAS_INTEL_RS25GB008_SSDID		0x3000
261 #define MPT2SAS_INTEL_SSD910_SSDID		0x3700
262 
263 #define MPT3SAS_INTEL_RMS3JC080_SSDID		0x3521
264 #define MPT3SAS_INTEL_RS3GC008_SSDID		0x3522
265 #define MPT3SAS_INTEL_RS3FC044_SSDID		0x3523
266 #define MPT3SAS_INTEL_RS3UC080_SSDID		0x3524
267 
268 /*
269  * Dell HBA branding
270  */
271 #define MPT2SAS_DELL_BRANDING_SIZE                 32
272 
273 #define MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING        "Dell 6Gbps SAS HBA"
274 #define MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING    "Dell PERC H200 Adapter"
275 #define MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING "Dell PERC H200 Integrated"
276 #define MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING    "Dell PERC H200 Modular"
277 #define MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING   "Dell PERC H200 Embedded"
278 #define MPT2SAS_DELL_PERC_H200_BRANDING            "Dell PERC H200"
279 #define MPT2SAS_DELL_6GBPS_SAS_BRANDING            "Dell 6Gbps SAS"
280 
281 #define MPT3SAS_DELL_12G_HBA_BRANDING       \
282 	"Dell 12Gbps HBA"
283 
284 /*
285  * Dell HBA SSDIDs
286  */
287 #define MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID	0x1F1C
288 #define MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID	0x1F1D
289 #define MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID	0x1F1E
290 #define MPT2SAS_DELL_PERC_H200_MODULAR_SSDID	0x1F1F
291 #define MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID	0x1F20
292 #define MPT2SAS_DELL_PERC_H200_SSDID		0x1F21
293 #define MPT2SAS_DELL_6GBPS_SAS_SSDID		0x1F22
294 
295 #define MPT3SAS_DELL_12G_HBA_SSDID		0x1F46
296 
297 /*
298  * Cisco HBA branding
299  */
300 #define MPT3SAS_CISCO_12G_8E_HBA_BRANDING		\
301 	"Cisco 9300-8E 12G SAS HBA"
302 #define MPT3SAS_CISCO_12G_8I_HBA_BRANDING		\
303 	"Cisco 9300-8i 12G SAS HBA"
304 #define MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING	\
305 	"Cisco 12G Modular SAS Pass through Controller"
306 #define MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING		\
307 	"UCS C3X60 12G SAS Pass through Controller"
308 /*
309  * Cisco HBA SSSDIDs
310  */
311 #define MPT3SAS_CISCO_12G_8E_HBA_SSDID  0x14C
312 #define MPT3SAS_CISCO_12G_8I_HBA_SSDID  0x154
313 #define MPT3SAS_CISCO_12G_AVILA_HBA_SSDID  0x155
314 #define MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID  0x156
315 
316 /*
317  * status bits for ioc->diag_buffer_status
318  */
319 #define MPT3_DIAG_BUFFER_IS_REGISTERED	(0x01)
320 #define MPT3_DIAG_BUFFER_IS_RELEASED	(0x02)
321 #define MPT3_DIAG_BUFFER_IS_DIAG_RESET	(0x04)
322 #define MPT3_DIAG_BUFFER_IS_DRIVER_ALLOCATED (0x08)
323 #define MPT3_DIAG_BUFFER_IS_APP_OWNED (0x10)
324 
325 /*
326  * HP HBA branding
327  */
328 #define MPT2SAS_HP_3PAR_SSVID                0x1590
329 
330 #define MPT2SAS_HP_2_4_INTERNAL_BRANDING	\
331 	"HP H220 Host Bus Adapter"
332 #define MPT2SAS_HP_2_4_EXTERNAL_BRANDING	\
333 	"HP H221 Host Bus Adapter"
334 #define MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING	\
335 	"HP H222 Host Bus Adapter"
336 #define MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING	\
337 	"HP H220i Host Bus Adapter"
338 #define MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING	\
339 	"HP H210i Host Bus Adapter"
340 
341 /*
342  * HO HBA SSDIDs
343  */
344 #define MPT2SAS_HP_2_4_INTERNAL_SSDID			0x0041
345 #define MPT2SAS_HP_2_4_EXTERNAL_SSDID			0x0042
346 #define MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID	0x0043
347 #define MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID		0x0044
348 #define MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID		0x0046
349 
350 /*
351  * Combined Reply Queue constants,
352  * There are twelve Supplemental Reply Post Host Index Registers
353  * and each register is at offset 0x10 bytes from the previous one.
354  */
355 #define MAX_COMBINED_MSIX_VECTORS(gen35) ((gen35 == 1) ? 16 : 8)
356 #define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT_G3	12
357 #define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT_G35	16
358 #define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET	(0x10)
359 #define MPT3_MIN_IRQS					1
360 
361 /* OEM Identifiers */
362 #define MFG10_OEM_ID_INVALID                   (0x00000000)
363 #define MFG10_OEM_ID_DELL                      (0x00000001)
364 #define MFG10_OEM_ID_FSC                       (0x00000002)
365 #define MFG10_OEM_ID_SUN                       (0x00000003)
366 #define MFG10_OEM_ID_IBM                       (0x00000004)
367 
368 /* GENERIC Flags 0*/
369 #define MFG10_GF0_OCE_DISABLED                 (0x00000001)
370 #define MFG10_GF0_R1E_DRIVE_COUNT              (0x00000002)
371 #define MFG10_GF0_R10_DISPLAY                  (0x00000004)
372 #define MFG10_GF0_SSD_DATA_SCRUB_DISABLE       (0x00000008)
373 #define MFG10_GF0_SINGLE_DRIVE_R0              (0x00000010)
374 
375 #define VIRTUAL_IO_FAILED_RETRY			(0x32010081)
376 
377 /* High IOPs definitions */
378 #define MPT3SAS_DEVICE_HIGH_IOPS_DEPTH		8
379 #define MPT3SAS_HIGH_IOPS_REPLY_QUEUES		8
380 #define MPT3SAS_HIGH_IOPS_BATCH_COUNT		16
381 #define MPT3SAS_GEN35_MAX_MSIX_QUEUES		128
382 #define RDPQ_MAX_INDEX_IN_ONE_CHUNK		16
383 
384 /* OEM Specific Flags will come from OEM specific header files */
385 struct Mpi2ManufacturingPage10_t {
386 	MPI2_CONFIG_PAGE_HEADER	Header;		/* 00h */
387 	U8	OEMIdentifier;			/* 04h */
388 	U8	Reserved1;			/* 05h */
389 	U16	Reserved2;			/* 08h */
390 	U32	Reserved3;			/* 0Ch */
391 	U32	GenericFlags0;			/* 10h */
392 	U32	GenericFlags1;			/* 14h */
393 	U32	Reserved4;			/* 18h */
394 	U32	OEMSpecificFlags0;		/* 1Ch */
395 	U32	OEMSpecificFlags1;		/* 20h */
396 	U32	Reserved5[18];			/* 24h - 60h*/
397 };
398 
399 
400 /* Miscellaneous options */
401 struct Mpi2ManufacturingPage11_t {
402 	MPI2_CONFIG_PAGE_HEADER Header;		/* 00h */
403 	__le32	Reserved1;			/* 04h */
404 	u8	Reserved2;			/* 08h */
405 	u8	EEDPTagMode;			/* 09h */
406 	u8	Reserved3;			/* 0Ah */
407 	u8	Reserved4;			/* 0Bh */
408 	__le32	Reserved5[8];			/* 0Ch-2Ch */
409 	u16	AddlFlags2;			/* 2Ch */
410 	u8	AddlFlags3;			/* 2Eh */
411 	u8	Reserved6;			/* 2Fh */
412 	__le32	Reserved7[7];			/* 30h - 4Bh */
413 	u8	NVMeAbortTO;			/* 4Ch */
414 	u8	NumPerDevEvents;		/* 4Dh */
415 	u8	HostTraceBufferDecrementSizeKB;	/* 4Eh */
416 	u8	HostTraceBufferFlags;		/* 4Fh */
417 	u16	HostTraceBufferMaxSizeKB;	/* 50h */
418 	u16	HostTraceBufferMinSizeKB;	/* 52h */
419 	u8	CoreDumpTOSec;			/* 54h */
420 	u8	TimeSyncInterval;		/* 55h */
421 	u16	Reserved9;			/* 56h */
422 	__le32	Reserved10;			/* 58h */
423 };
424 
425 /**
426  * struct MPT3SAS_TARGET - starget private hostdata
427  * @starget: starget object
428  * @sas_address: target sas address
429  * @raid_device: raid_device pointer to access volume data
430  * @handle: device handle
431  * @num_luns: number luns
432  * @flags: MPT_TARGET_FLAGS_XXX flags
433  * @deleted: target flaged for deletion
434  * @tm_busy: target is busy with TM request.
435  * @port: hba port entry containing target's port number info
436  * @sas_dev: The sas_device associated with this target
437  * @pcie_dev: The pcie device associated with this target
438  */
439 struct MPT3SAS_TARGET {
440 	struct scsi_target *starget;
441 	u64	sas_address;
442 	struct _raid_device *raid_device;
443 	u16	handle;
444 	int	num_luns;
445 	u32	flags;
446 	u8	deleted;
447 	u8	tm_busy;
448 	struct hba_port *port;
449 	struct _sas_device *sas_dev;
450 	struct _pcie_device *pcie_dev;
451 };
452 
453 
454 /*
455  * per device private data
456  */
457 #define MPT_DEVICE_FLAGS_INIT		0x01
458 
459 #define MFG_PAGE10_HIDE_SSDS_MASK	(0x00000003)
460 #define MFG_PAGE10_HIDE_ALL_DISKS	(0x00)
461 #define MFG_PAGE10_EXPOSE_ALL_DISKS	(0x01)
462 #define MFG_PAGE10_HIDE_IF_VOL_PRESENT	(0x02)
463 
464 /**
465  * struct MPT3SAS_DEVICE - sdev private hostdata
466  * @sas_target: starget private hostdata
467  * @lun: lun number
468  * @flags: MPT_DEVICE_XXX flags
469  * @configured_lun: lun is configured
470  * @block: device is in SDEV_BLOCK state
471  * @tlr_snoop_check: flag used in determining whether to disable TLR
472  * @eedp_enable: eedp support enable bit
473  * @eedp_type: 0(type_1), 1(type_2), 2(type_3)
474  * @eedp_block_length: block size
475  * @ata_command_pending: SATL passthrough outstanding for device
476  */
477 struct MPT3SAS_DEVICE {
478 	struct MPT3SAS_TARGET *sas_target;
479 	unsigned int	lun;
480 	u32	flags;
481 	u8	configured_lun;
482 	u8	block;
483 	u8	tlr_snoop_check;
484 	u8	ignore_delay_remove;
485 	/* Iopriority Command Handling */
486 	u8	ncq_prio_enable;
487 	/*
488 	 * Bug workaround for SATL handling: the mpt2/3sas firmware
489 	 * doesn't return BUSY or TASK_SET_FULL for subsequent
490 	 * commands while a SATL pass through is in operation as the
491 	 * spec requires, it simply does nothing with them until the
492 	 * pass through completes, causing them possibly to timeout if
493 	 * the passthrough is a long executing command (like format or
494 	 * secure erase).  This variable allows us to do the right
495 	 * thing while a SATL command is pending.
496 	 */
497 	unsigned long ata_command_pending;
498 
499 };
500 
501 #define MPT3_CMD_NOT_USED	0x8000	/* free */
502 #define MPT3_CMD_COMPLETE	0x0001	/* completed */
503 #define MPT3_CMD_PENDING	0x0002	/* pending */
504 #define MPT3_CMD_REPLY_VALID	0x0004	/* reply is valid */
505 #define MPT3_CMD_RESET		0x0008	/* host reset dropped the command */
506 #define MPT3_CMD_COMPLETE_ASYNC 0x0010  /* tells whether cmd completes in same thread or not */
507 
508 /**
509  * struct _internal_cmd - internal commands struct
510  * @mutex: mutex
511  * @done: completion
512  * @reply: reply message pointer
513  * @sense: sense data
514  * @status: MPT3_CMD_XXX status
515  * @smid: system message id
516  */
517 struct _internal_cmd {
518 	struct mutex mutex;
519 	struct completion done;
520 	void	*reply;
521 	void	*sense;
522 	u16	status;
523 	u16	smid;
524 };
525 
526 
527 
528 /**
529  * struct _sas_device - attached device information
530  * @list: sas device list
531  * @starget: starget object
532  * @sas_address: device sas address
533  * @device_name: retrieved from the SAS IDENTIFY frame.
534  * @handle: device handle
535  * @sas_address_parent: sas address of parent expander or sas host
536  * @enclosure_handle: enclosure handle
537  * @enclosure_logical_id: enclosure logical identifier
538  * @volume_handle: volume handle (valid when hidden raid member)
539  * @volume_wwid: volume unique identifier
540  * @device_info: bitfield provides detailed info about the device
541  * @id: target id
542  * @channel: target channel
543  * @slot: number number
544  * @phy: phy identifier provided in sas device page 0
545  * @responding: used in _scsih_sas_device_mark_responding
546  * @fast_path: fast path feature enable bit
547  * @pfa_led_on: flag for PFA LED status
548  * @pend_sas_rphy_add: flag to check if device is in sas_rphy_add()
549  *	addition routine.
550  * @chassis_slot: chassis slot
551  * @is_chassis_slot_valid: chassis slot valid or not
552  * @port: hba port entry containing device's port number info
553  * @rphy: device's sas_rphy address used to identify this device structure in
554  *	target_alloc callback function
555  */
556 struct _sas_device {
557 	struct list_head list;
558 	struct scsi_target *starget;
559 	u64	sas_address;
560 	u64	device_name;
561 	u16	handle;
562 	u64	sas_address_parent;
563 	u16	enclosure_handle;
564 	u64	enclosure_logical_id;
565 	u16	volume_handle;
566 	u64	volume_wwid;
567 	u32	device_info;
568 	int	id;
569 	int	channel;
570 	u16	slot;
571 	u8	phy;
572 	u8	responding;
573 	u8	fast_path;
574 	u8	pfa_led_on;
575 	u8	pend_sas_rphy_add;
576 	u8	enclosure_level;
577 	u8	chassis_slot;
578 	u8	is_chassis_slot_valid;
579 	u8	connector_name[5];
580 	struct kref refcount;
581 	u8	port_type;
582 	struct hba_port *port;
583 	struct sas_rphy *rphy;
584 };
585 
sas_device_get(struct _sas_device * s)586 static inline void sas_device_get(struct _sas_device *s)
587 {
588 	kref_get(&s->refcount);
589 }
590 
sas_device_free(struct kref * r)591 static inline void sas_device_free(struct kref *r)
592 {
593 	kfree(container_of(r, struct _sas_device, refcount));
594 }
595 
sas_device_put(struct _sas_device * s)596 static inline void sas_device_put(struct _sas_device *s)
597 {
598 	kref_put(&s->refcount, sas_device_free);
599 }
600 
601 /*
602  * struct _pcie_device - attached PCIe device information
603  * @list: pcie device list
604  * @starget: starget object
605  * @wwid: device WWID
606  * @handle: device handle
607  * @device_info: bitfield provides detailed info about the device
608  * @id: target id
609  * @channel: target channel
610  * @slot: slot number
611  * @port_num: port number
612  * @responding: used in _scsih_pcie_device_mark_responding
613  * @fast_path: fast path feature enable bit
614  * @nvme_mdts: MaximumDataTransferSize from PCIe Device Page 2 for
615  *		NVMe device only
616  * @enclosure_handle: enclosure handle
617  * @enclosure_logical_id: enclosure logical identifier
618  * @enclosure_level: The level of device's enclosure from the controller
619  * @connector_name: ASCII value of the Connector's name
620  * @serial_number: pointer of serial number string allocated runtime
621  * @access_status: Device's Access Status
622  * @shutdown_latency: NVMe device's RTD3 Entry Latency
623  * @refcount: reference count for deletion
624  */
625 struct _pcie_device {
626 	struct list_head list;
627 	struct scsi_target *starget;
628 	u64	wwid;
629 	u16	handle;
630 	u32	device_info;
631 	int	id;
632 	int	channel;
633 	u16	slot;
634 	u8	port_num;
635 	u8	responding;
636 	u8	fast_path;
637 	u32	nvme_mdts;
638 	u16	enclosure_handle;
639 	u64	enclosure_logical_id;
640 	u8	enclosure_level;
641 	u8	connector_name[4];
642 	u8	*serial_number;
643 	u8	reset_timeout;
644 	u8	access_status;
645 	u16	shutdown_latency;
646 	struct kref refcount;
647 };
648 /**
649  * pcie_device_get - Increment the pcie device reference count
650  *
651  * @p: pcie_device object
652  *
653  * When ever this function called it will increment the
654  * reference count of the pcie device for which this function called.
655  *
656  */
pcie_device_get(struct _pcie_device * p)657 static inline void pcie_device_get(struct _pcie_device *p)
658 {
659 	kref_get(&p->refcount);
660 }
661 
662 /**
663  * pcie_device_free - Release the pcie device object
664  * @r - kref object
665  *
666  * Free's the pcie device object. It will be called when reference count
667  * reaches to zero.
668  */
pcie_device_free(struct kref * r)669 static inline void pcie_device_free(struct kref *r)
670 {
671 	kfree(container_of(r, struct _pcie_device, refcount));
672 }
673 
674 /**
675  * pcie_device_put - Decrement the pcie device reference count
676  *
677  * @p: pcie_device object
678  *
679  * When ever this function called it will decrement the
680  * reference count of the pcie device for which this function called.
681  *
682  * When refernce count reaches to Zero, this will call pcie_device_free to the
683  * pcie_device object.
684  */
pcie_device_put(struct _pcie_device * p)685 static inline void pcie_device_put(struct _pcie_device *p)
686 {
687 	kref_put(&p->refcount, pcie_device_free);
688 }
689 /**
690  * struct _raid_device - raid volume link list
691  * @list: sas device list
692  * @starget: starget object
693  * @sdev: scsi device struct (volumes are single lun)
694  * @wwid: unique identifier for the volume
695  * @handle: device handle
696  * @block_size: Block size of the volume
697  * @id: target id
698  * @channel: target channel
699  * @volume_type: the raid level
700  * @device_info: bitfield provides detailed info about the hidden components
701  * @num_pds: number of hidden raid components
702  * @responding: used in _scsih_raid_device_mark_responding
703  * @percent_complete: resync percent complete
704  * @direct_io_enabled: Whether direct io to PDs are allowed or not
705  * @stripe_exponent: X where 2powX is the stripe sz in blocks
706  * @block_exponent: X where 2powX is the block sz in bytes
707  * @max_lba: Maximum number of LBA in the volume
708  * @stripe_sz: Stripe Size of the volume
709  * @device_info: Device info of the volume member disk
710  * @pd_handle: Array of handles of the physical drives for direct I/O in le16
711  */
712 #define MPT_MAX_WARPDRIVE_PDS		8
713 struct _raid_device {
714 	struct list_head list;
715 	struct scsi_target *starget;
716 	struct scsi_device *sdev;
717 	u64	wwid;
718 	u16	handle;
719 	u16	block_sz;
720 	int	id;
721 	int	channel;
722 	u8	volume_type;
723 	u8	num_pds;
724 	u8	responding;
725 	u8	percent_complete;
726 	u8	direct_io_enabled;
727 	u8	stripe_exponent;
728 	u8	block_exponent;
729 	u64	max_lba;
730 	u32	stripe_sz;
731 	u32	device_info;
732 	u16	pd_handle[MPT_MAX_WARPDRIVE_PDS];
733 };
734 
735 /**
736  * struct _boot_device - boot device info
737  *
738  * @channel: sas, raid, or pcie channel
739  * @device: holds pointer for struct _sas_device, struct _raid_device or
740  *     struct _pcie_device
741  */
742 struct _boot_device {
743 	int channel;
744 	void *device;
745 };
746 
747 /**
748  * struct _sas_port - wide/narrow sas port information
749  * @port_list: list of ports belonging to expander
750  * @num_phys: number of phys belonging to this port
751  * @remote_identify: attached device identification
752  * @rphy: sas transport rphy object
753  * @port: sas transport wide/narrow port object
754  * @hba_port: hba port entry containing port's port number info
755  * @phy_list: _sas_phy list objects belonging to this port
756  */
757 struct _sas_port {
758 	struct list_head port_list;
759 	u8	num_phys;
760 	struct sas_identify remote_identify;
761 	struct sas_rphy *rphy;
762 	struct sas_port *port;
763 	struct hba_port *hba_port;
764 	struct list_head phy_list;
765 };
766 
767 /**
768  * struct _sas_phy - phy information
769  * @port_siblings: list of phys belonging to a port
770  * @identify: phy identification
771  * @remote_identify: attached device identification
772  * @phy: sas transport phy object
773  * @phy_id: unique phy id
774  * @handle: device handle for this phy
775  * @attached_handle: device handle for attached device
776  * @phy_belongs_to_port: port has been created for this phy
777  * @port: hba port entry containing port number info
778  */
779 struct _sas_phy {
780 	struct list_head port_siblings;
781 	struct sas_identify identify;
782 	struct sas_identify remote_identify;
783 	struct sas_phy *phy;
784 	u8	phy_id;
785 	u16	handle;
786 	u16	attached_handle;
787 	u8	phy_belongs_to_port;
788 	u8	hba_vphy;
789 	struct hba_port *port;
790 };
791 
792 /**
793  * struct _sas_node - sas_host/expander information
794  * @list: list of expanders
795  * @parent_dev: parent device class
796  * @num_phys: number phys belonging to this sas_host/expander
797  * @sas_address: sas address of this sas_host/expander
798  * @handle: handle for this sas_host/expander
799  * @sas_address_parent: sas address of parent expander or sas host
800  * @enclosure_handle: handle for this a member of an enclosure
801  * @device_info: bitwise defining capabilities of this sas_host/expander
802  * @responding: used in _scsih_expander_device_mark_responding
803  * @nr_phys_allocated: Allocated memory for this many count phys
804  * @phy: a list of phys that make up this sas_host/expander
805  * @sas_port_list: list of ports attached to this sas_host/expander
806  * @port: hba port entry containing node's port number info
807  * @rphy: sas_rphy object of this expander
808  */
809 struct _sas_node {
810 	struct list_head list;
811 	struct device *parent_dev;
812 	u8	num_phys;
813 	u64	sas_address;
814 	u16	handle;
815 	u64	sas_address_parent;
816 	u16	enclosure_handle;
817 	u64	enclosure_logical_id;
818 	u8	responding;
819 	u8	nr_phys_allocated;
820 	struct hba_port *port;
821 	struct	_sas_phy *phy;
822 	struct list_head sas_port_list;
823 	struct sas_rphy *rphy;
824 };
825 
826 /**
827  * struct _enclosure_node - enclosure information
828  * @list: list of enclosures
829  * @pg0: enclosure pg0;
830  */
831 struct _enclosure_node {
832 	struct list_head list;
833 	Mpi2SasEnclosurePage0_t pg0;
834 };
835 
836 /**
837  * enum reset_type - reset state
838  * @FORCE_BIG_HAMMER: issue diagnostic reset
839  * @SOFT_RESET: issue message_unit_reset, if fails to to big hammer
840  */
841 enum reset_type {
842 	FORCE_BIG_HAMMER,
843 	SOFT_RESET,
844 };
845 
846 /**
847  * struct pcie_sg_list - PCIe SGL buffer (contiguous per I/O)
848  * @pcie_sgl: PCIe native SGL for NVMe devices
849  * @pcie_sgl_dma: physical address
850  */
851 struct pcie_sg_list {
852 	void            *pcie_sgl;
853 	dma_addr_t      pcie_sgl_dma;
854 };
855 
856 /**
857  * struct chain_tracker - firmware chain tracker
858  * @chain_buffer: chain buffer
859  * @chain_buffer_dma: physical address
860  * @tracker_list: list of free request (ioc->free_chain_list)
861  */
862 struct chain_tracker {
863 	void *chain_buffer;
864 	dma_addr_t chain_buffer_dma;
865 };
866 
867 struct chain_lookup {
868 	struct chain_tracker *chains_per_smid;
869 	atomic_t	chain_offset;
870 };
871 
872 /**
873  * struct scsiio_tracker - scsi mf request tracker
874  * @smid: system message id
875  * @cb_idx: callback index
876  * @direct_io: To indicate whether I/O is direct (WARPDRIVE)
877  * @chain_list: list of associated firmware chain tracker
878  * @msix_io: IO's msix
879  */
880 struct scsiio_tracker {
881 	u16	smid;
882 	struct scsi_cmnd *scmd;
883 	u8	cb_idx;
884 	u8	direct_io;
885 	struct pcie_sg_list pcie_sg_list;
886 	struct list_head chain_list;
887 	u16     msix_io;
888 };
889 
890 /**
891  * struct request_tracker - firmware request tracker
892  * @smid: system message id
893  * @cb_idx: callback index
894  * @tracker_list: list of free request (ioc->free_list)
895  */
896 struct request_tracker {
897 	u16	smid;
898 	u8	cb_idx;
899 	struct list_head tracker_list;
900 };
901 
902 /**
903  * struct _tr_list - target reset list
904  * @handle: device handle
905  * @state: state machine
906  */
907 struct _tr_list {
908 	struct list_head list;
909 	u16	handle;
910 	u16	state;
911 };
912 
913 /**
914  * struct _sc_list - delayed SAS_IO_UNIT_CONTROL message list
915  * @handle: device handle
916  */
917 struct _sc_list {
918 	struct list_head list;
919 	u16     handle;
920 };
921 
922 /**
923  * struct _event_ack_list - delayed event acknowledgment list
924  * @Event: Event ID
925  * @EventContext: used to track the event uniquely
926  */
927 struct _event_ack_list {
928 	struct list_head list;
929 	U16     Event;
930 	U32     EventContext;
931 };
932 
933 /**
934  * struct adapter_reply_queue - the reply queue struct
935  * @ioc: per adapter object
936  * @msix_index: msix index into vector table
937  * @vector: irq vector
938  * @reply_post_host_index: head index in the pool where FW completes IO
939  * @reply_post_free: reply post base virt address
940  * @name: the name registered to request_irq()
941  * @busy: isr is actively processing replies on another cpu
942  * @os_irq: irq number
943  * @irqpoll: irq_poll object
944  * @irq_poll_scheduled: Tells whether irq poll is scheduled or not
945  * @is_iouring_poll_q: Tells whether reply queues is assigned
946  *			to io uring poll queues or not
947  * @list: this list
948 */
949 struct adapter_reply_queue {
950 	struct MPT3SAS_ADAPTER	*ioc;
951 	u8			msix_index;
952 	u32			reply_post_host_index;
953 	Mpi2ReplyDescriptorsUnion_t *reply_post_free;
954 	char			name[MPT_NAME_LENGTH];
955 	atomic_t		busy;
956 	u32			os_irq;
957 	struct irq_poll         irqpoll;
958 	bool			irq_poll_scheduled;
959 	bool			irq_line_enable;
960 	bool			is_iouring_poll_q;
961 	struct list_head	list;
962 };
963 
964 /**
965  * struct io_uring_poll_queue - the io uring poll queue structure
966  * @busy: Tells whether io uring poll queue is busy or not
967  * @pause: Tells whether IOs are paused on io uring poll queue or not
968  * @reply_q: reply queue mapped for io uring poll queue
969  */
970 struct io_uring_poll_queue {
971 	atomic_t	busy;
972 	atomic_t	pause;
973 	struct adapter_reply_queue *reply_q;
974 };
975 
976 typedef void (*MPT_ADD_SGE)(void *paddr, u32 flags_length, dma_addr_t dma_addr);
977 
978 /* SAS3.0 support */
979 typedef int (*MPT_BUILD_SG_SCMD)(struct MPT3SAS_ADAPTER *ioc,
980 	struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *pcie_device);
981 typedef void (*MPT_BUILD_SG)(struct MPT3SAS_ADAPTER *ioc, void *psge,
982 		dma_addr_t data_out_dma, size_t data_out_sz,
983 		dma_addr_t data_in_dma, size_t data_in_sz);
984 typedef void (*MPT_BUILD_ZERO_LEN_SGE)(struct MPT3SAS_ADAPTER *ioc,
985 		void *paddr);
986 
987 /* SAS3.5 support */
988 typedef void (*NVME_BUILD_PRP)(struct MPT3SAS_ADAPTER *ioc, u16 smid,
989 	Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request,
990 	dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
991 	size_t data_in_sz);
992 
993 /* To support atomic and non atomic descriptors*/
994 typedef void (*PUT_SMID_IO_FP_HIP) (struct MPT3SAS_ADAPTER *ioc, u16 smid,
995 	u16 funcdep);
996 typedef void (*PUT_SMID_DEFAULT) (struct MPT3SAS_ADAPTER *ioc, u16 smid);
997 typedef u32 (*BASE_READ_REG) (const volatile void __iomem *addr);
998 /*
999  * To get high iops reply queue's msix index when high iops mode is enabled
1000  * else get the msix index of general reply queues.
1001  */
1002 typedef u8 (*GET_MSIX_INDEX) (struct MPT3SAS_ADAPTER *ioc,
1003 	struct scsi_cmnd *scmd);
1004 
1005 /* IOC Facts and Port Facts converted from little endian to cpu */
1006 union mpi3_version_union {
1007 	MPI2_VERSION_STRUCT		Struct;
1008 	u32				Word;
1009 };
1010 
1011 struct mpt3sas_facts {
1012 	u16			MsgVersion;
1013 	u16			HeaderVersion;
1014 	u8			IOCNumber;
1015 	u8			VP_ID;
1016 	u8			VF_ID;
1017 	u16			IOCExceptions;
1018 	u16			IOCStatus;
1019 	u32			IOCLogInfo;
1020 	u8			MaxChainDepth;
1021 	u8			WhoInit;
1022 	u8			NumberOfPorts;
1023 	u8			MaxMSIxVectors;
1024 	u16			RequestCredit;
1025 	u16			ProductID;
1026 	u32			IOCCapabilities;
1027 	union mpi3_version_union	FWVersion;
1028 	u16			IOCRequestFrameSize;
1029 	u16			IOCMaxChainSegmentSize;
1030 	u16			MaxInitiators;
1031 	u16			MaxTargets;
1032 	u16			MaxSasExpanders;
1033 	u16			MaxEnclosures;
1034 	u16			ProtocolFlags;
1035 	u16			HighPriorityCredit;
1036 	u16			MaxReplyDescriptorPostQueueDepth;
1037 	u8			ReplyFrameSize;
1038 	u8			MaxVolumes;
1039 	u16			MaxDevHandle;
1040 	u16			MaxPersistentEntries;
1041 	u16			MinDevHandle;
1042 	u8			CurrentHostPageSize;
1043 };
1044 
1045 struct mpt3sas_port_facts {
1046 	u8			PortNumber;
1047 	u8			VP_ID;
1048 	u8			VF_ID;
1049 	u8			PortType;
1050 	u16			MaxPostedCmdBuffers;
1051 };
1052 
1053 struct reply_post_struct {
1054 	Mpi2ReplyDescriptorsUnion_t	*reply_post_free;
1055 	dma_addr_t			reply_post_free_dma;
1056 };
1057 
1058 /**
1059  * struct virtual_phy - vSES phy structure
1060  * sas_address: SAS Address of vSES device
1061  * phy_mask: vSES device's phy number
1062  * flags: flags used to manage this structure
1063  */
1064 struct virtual_phy {
1065 	struct	list_head list;
1066 	u64	sas_address;
1067 	u32	phy_mask;
1068 	u8	flags;
1069 };
1070 
1071 #define MPT_VPHY_FLAG_DIRTY_PHY	0x01
1072 
1073 /**
1074  * struct hba_port - Saves each HBA's Wide/Narrow port info
1075  * @sas_address: sas address of this wide/narrow port's attached device
1076  * @phy_mask: HBA PHY's belonging to this port
1077  * @port_id: port number
1078  * @flags: hba port flags
1079  * @vphys_mask : mask of vSES devices Phy number
1080  * @vphys_list : list containing vSES device structures
1081  */
1082 struct hba_port {
1083 	struct list_head list;
1084 	u64	sas_address;
1085 	u32	phy_mask;
1086 	u8      port_id;
1087 	u8	flags;
1088 	u32	vphys_mask;
1089 	struct list_head vphys_list;
1090 };
1091 
1092 /* hba port flags */
1093 #define HBA_PORT_FLAG_DIRTY_PORT       0x01
1094 #define HBA_PORT_FLAG_NEW_PORT         0x02
1095 
1096 #define MULTIPATH_DISABLED_PORT_ID     0xFF
1097 
1098 /**
1099  * struct htb_rel_query - diagnostic buffer release reason
1100  * @unique_id - unique id associated with this buffer.
1101  * @buffer_rel_condition - Release condition ioctl/sysfs/reset
1102  * @reserved
1103  * @trigger_type - Master/Event/scsi/MPI
1104  * @trigger_info_dwords - Data Correspondig to trigger type
1105  */
1106 struct htb_rel_query {
1107 	u16	buffer_rel_condition;
1108 	u16	reserved;
1109 	u32	trigger_type;
1110 	u32	trigger_info_dwords[2];
1111 };
1112 
1113 /* Buffer_rel_condition bit fields */
1114 
1115 /* Bit 0 - Diag Buffer not Released */
1116 #define MPT3_DIAG_BUFFER_NOT_RELEASED	(0x00)
1117 /* Bit 0 - Diag Buffer Released */
1118 #define MPT3_DIAG_BUFFER_RELEASED	(0x01)
1119 
1120 /*
1121  * Bit 1 - Diag Buffer Released by IOCTL,
1122  * This bit is valid only if Bit 0 is one
1123  */
1124 #define MPT3_DIAG_BUFFER_REL_IOCTL	(0x02 | MPT3_DIAG_BUFFER_RELEASED)
1125 
1126 /*
1127  * Bit 2 - Diag Buffer Released by Trigger,
1128  * This bit is valid only if Bit 0 is one
1129  */
1130 #define MPT3_DIAG_BUFFER_REL_TRIGGER	(0x04 | MPT3_DIAG_BUFFER_RELEASED)
1131 
1132 /*
1133  * Bit 3 - Diag Buffer Released by SysFs,
1134  * This bit is valid only if Bit 0 is one
1135  */
1136 #define MPT3_DIAG_BUFFER_REL_SYSFS	(0x08 | MPT3_DIAG_BUFFER_RELEASED)
1137 
1138 /* DIAG RESET Master trigger flags */
1139 #define MPT_DIAG_RESET_ISSUED_BY_DRIVER 0x00000000
1140 #define MPT_DIAG_RESET_ISSUED_BY_USER	0x00000001
1141 
1142 typedef void (*MPT3SAS_FLUSH_RUNNING_CMDS)(struct MPT3SAS_ADAPTER *ioc);
1143 /**
1144  * struct MPT3SAS_ADAPTER - per adapter struct
1145  * @list: ioc_list
1146  * @shost: shost object
1147  * @id: unique adapter id
1148  * @cpu_count: number online cpus
1149  * @name: generic ioc string
1150  * @tmp_string: tmp string used for logging
1151  * @pdev: pci pdev object
1152  * @pio_chip: physical io register space
1153  * @chip: memory mapped register space
1154  * @chip_phys: physical addrss prior to mapping
1155  * @logging_level: see mpt3sas_debug.h
1156  * @fwfault_debug: debuging FW timeouts
1157  * @ir_firmware: IR firmware present
1158  * @bars: bitmask of BAR's that must be configured
1159  * @mask_interrupts: ignore interrupt
1160  * @pci_access_mutex: Mutex to synchronize ioctl, sysfs show path and
1161  *			pci resource handling
1162  * @fault_reset_work_q_name: fw fault work queue
1163  * @fault_reset_work_q: ""
1164  * @fault_reset_work: ""
1165  * @firmware_event_name: fw event work queue
1166  * @firmware_event_thread: ""
1167  * @fw_event_lock:
1168  * @fw_event_list: list of fw events
1169  * @current_evet: current processing firmware event
1170  * @fw_event_cleanup: set to one while cleaning up the fw events
1171  * @aen_event_read_flag: event log was read
1172  * @broadcast_aen_busy: broadcast aen waiting to be serviced
1173  * @shost_recovery: host reset in progress
1174  * @ioc_reset_in_progress_lock:
1175  * @ioc_link_reset_in_progress: phy/hard reset in progress
1176  * @ignore_loginfos: ignore loginfos during task management
1177  * @remove_host: flag for when driver unloads, to avoid sending dev resets
1178  * @pci_error_recovery: flag to prevent ioc access until slot reset completes
1179  * @wait_for_discovery_to_complete: flag set at driver load time when
1180  *                                               waiting on reporting devices
1181  * @is_driver_loading: flag set at driver load time
1182  * @port_enable_failed: flag set when port enable has failed
1183  * @start_scan: flag set from scan_start callback, cleared from _mpt3sas_fw_work
1184  * @start_scan_failed: means port enable failed, return's the ioc_status
1185  * @msix_enable: flag indicating msix is enabled
1186  * @msix_vector_count: number msix vectors
1187  * @cpu_msix_table: table for mapping cpus to msix index
1188  * @cpu_msix_table_sz: table size
1189  * @total_io_cnt: Gives total IO count, used to load balance the interrupts
1190  * @ioc_coredump_loop: will have non-zero value when FW is in CoreDump state
1191  * @timestamp_update_count: Counter to fire timeSync command
1192  * time_sync_interval: Time sync interval read from man page 11
1193  * @high_iops_outstanding: used to load balance the interrupts
1194  *				within high iops reply queues
1195  * @msix_load_balance: Enables load balancing of interrupts across
1196  * the multiple MSIXs
1197  * @schedule_dead_ioc_flush_running_cmds: callback to flush pending commands
1198  * @thresh_hold: Max number of reply descriptors processed
1199  *				before updating Host Index
1200  * @iopoll_q_start_index: starting index of io uring poll queues
1201  *				in reply queue list
1202  * @drv_internal_flags: Bit map internal to driver
1203  * @drv_support_bitmap: driver's supported feature bit map
1204  * @use_32bit_dma: Flag to use 32 bit consistent dma mask
1205  * @scsi_io_cb_idx: shost generated commands
1206  * @tm_cb_idx: task management commands
1207  * @scsih_cb_idx: scsih internal commands
1208  * @transport_cb_idx: transport internal commands
1209  * @ctl_cb_idx: clt internal commands
1210  * @base_cb_idx: base internal commands
1211  * @config_cb_idx: base internal commands
1212  * @tm_tr_cb_idx : device removal target reset handshake
1213  * @tm_tr_volume_cb_idx : volume removal target reset
1214  * @base_cmds:
1215  * @transport_cmds:
1216  * @scsih_cmds:
1217  * @tm_cmds:
1218  * @ctl_cmds:
1219  * @config_cmds:
1220  * @base_add_sg_single: handler for either 32/64 bit sgl's
1221  * @event_type: bits indicating which events to log
1222  * @event_context: unique id for each logged event
1223  * @event_log: event log pointer
1224  * @event_masks: events that are masked
1225  * @max_shutdown_latency: timeout value for NVMe shutdown operation,
1226  *			which is equal that NVMe drive's RTD3 Entry Latency
1227  *			which has reported maximum RTD3 Entry Latency value
1228  *			among attached NVMe drives.
1229  * @facts: static facts data
1230  * @prev_fw_facts: previous fw facts data
1231  * @pfacts: static port facts data
1232  * @manu_pg0: static manufacturing page 0
1233  * @manu_pg10: static manufacturing page 10
1234  * @manu_pg11: static manufacturing page 11
1235  * @bios_pg2: static bios page 2
1236  * @bios_pg3: static bios page 3
1237  * @ioc_pg8: static ioc page 8
1238  * @iounit_pg0: static iounit page 0
1239  * @iounit_pg1: static iounit page 1
1240  * @iounit_pg8: static iounit page 8
1241  * @sas_hba: sas host object
1242  * @sas_expander_list: expander object list
1243  * @enclosure_list: enclosure object list
1244  * @sas_node_lock:
1245  * @sas_device_list: sas device object list
1246  * @sas_device_init_list: sas device object list (used only at init time)
1247  * @sas_device_lock:
1248  * @pcie_device_list: pcie device object list
1249  * @pcie_device_init_list: pcie device object list (used only at init time)
1250  * @pcie_device_lock:
1251  * @io_missing_delay: time for IO completed by fw when PDR enabled
1252  * @device_missing_delay: time for device missing by fw when PDR enabled
1253  * @sas_id : used for setting volume target IDs
1254  * @pcie_target_id: used for setting pcie target IDs
1255  * @blocking_handles: bitmask used to identify which devices need blocking
1256  * @pd_handles : bitmask for PD handles
1257  * @pd_handles_sz : size of pd_handle bitmask
1258  * @config_page_sz: config page size
1259  * @config_page: reserve memory for config page payload
1260  * @config_page_dma:
1261  * @hba_queue_depth: hba request queue depth
1262  * @sge_size: sg element size for either 32/64 bit
1263  * @scsiio_depth: SCSI_IO queue depth
1264  * @request_sz: per request frame size
1265  * @request: pool of request frames
1266  * @request_dma:
1267  * @request_dma_sz:
1268  * @scsi_lookup: firmware request tracker list
1269  * @scsi_lookup_lock:
1270  * @free_list: free list of request
1271  * @pending_io_count:
1272  * @reset_wq:
1273  * @chain: pool of chains
1274  * @chain_dma:
1275  * @max_sges_in_main_message: number sg elements in main message
1276  * @max_sges_in_chain_message: number sg elements per chain
1277  * @chains_needed_per_io: max chains per io
1278  * @chain_depth: total chains allocated
1279  * @chain_segment_sz: gives the max number of
1280  *			SGEs accommodate on single chain buffer
1281  * @hi_priority_smid:
1282  * @hi_priority:
1283  * @hi_priority_dma:
1284  * @hi_priority_depth:
1285  * @hpr_lookup:
1286  * @hpr_free_list:
1287  * @internal_smid:
1288  * @internal:
1289  * @internal_dma:
1290  * @internal_depth:
1291  * @internal_lookup:
1292  * @internal_free_list:
1293  * @sense: pool of sense
1294  * @sense_dma:
1295  * @sense_dma_pool:
1296  * @reply_depth: hba reply queue depth:
1297  * @reply_sz: per reply frame size:
1298  * @reply: pool of replys:
1299  * @reply_dma:
1300  * @reply_dma_pool:
1301  * @reply_free_queue_depth: reply free depth
1302  * @reply_free: pool for reply free queue (32 bit addr)
1303  * @reply_free_dma:
1304  * @reply_free_dma_pool:
1305  * @reply_free_host_index: tail index in pool to insert free replys
1306  * @reply_post_queue_depth: reply post queue depth
1307  * @reply_post_struct: struct for reply_post_free physical & virt address
1308  * @rdpq_array_capable: FW supports multiple reply queue addresses in ioc_init
1309  * @rdpq_array_enable: rdpq_array support is enabled in the driver
1310  * @rdpq_array_enable_assigned: this ensures that rdpq_array_enable flag
1311  *				is assigned only ones
1312  * @reply_queue_count: number of reply queue's
1313  * @reply_queue_list: link list contaning the reply queue info
1314  * @msix96_vector: 96 MSI-X vector support
1315  * @replyPostRegisterIndex: index of next position in Reply Desc Post Queue
1316  * @delayed_tr_list: target reset link list
1317  * @delayed_tr_volume_list: volume target reset link list
1318  * @delayed_sc_list:
1319  * @delayed_event_ack_list:
1320  * @temp_sensors_count: flag to carry the number of temperature sensors
1321  * @pci_access_mutex: Mutex to synchronize ioctl,sysfs show path and
1322  *	pci resource handling. PCI resource freeing will lead to free
1323  *	vital hardware/memory resource, which might be in use by cli/sysfs
1324  *	path functions resulting in Null pointer reference followed by kernel
1325  *	crash. To avoid the above race condition we use mutex syncrhonization
1326  *	which ensures the syncrhonization between cli/sysfs_show path.
1327  * @atomic_desc_capable: Atomic Request Descriptor support.
1328  * @GET_MSIX_INDEX: Get the msix index of high iops queues.
1329  * @multipath_on_hba: flag to determine multipath on hba is enabled or not
1330  * @port_table_list: list containing HBA's wide/narrow port's info
1331  */
1332 struct MPT3SAS_ADAPTER {
1333 	struct list_head list;
1334 	struct Scsi_Host *shost;
1335 	u8		id;
1336 	int		cpu_count;
1337 	char		name[MPT_NAME_LENGTH];
1338 	char		driver_name[MPT_NAME_LENGTH - 8];
1339 	char		tmp_string[MPT_STRING_LENGTH];
1340 	struct pci_dev	*pdev;
1341 	Mpi2SystemInterfaceRegs_t __iomem *chip;
1342 	phys_addr_t	chip_phys;
1343 	int		logging_level;
1344 	int		fwfault_debug;
1345 	u8		ir_firmware;
1346 	int		bars;
1347 	u8		mask_interrupts;
1348 
1349 	/* fw fault handler */
1350 	char		fault_reset_work_q_name[20];
1351 	struct workqueue_struct *fault_reset_work_q;
1352 	struct delayed_work fault_reset_work;
1353 
1354 	/* fw event handler */
1355 	char		firmware_event_name[20];
1356 	struct workqueue_struct	*firmware_event_thread;
1357 	spinlock_t	fw_event_lock;
1358 	struct list_head fw_event_list;
1359 	struct fw_event_work	*current_event;
1360 	u8		fw_events_cleanup;
1361 
1362 	 /* misc flags */
1363 	int		aen_event_read_flag;
1364 	u8		broadcast_aen_busy;
1365 	u16		broadcast_aen_pending;
1366 	u8		shost_recovery;
1367 	u8		got_task_abort_from_ioctl;
1368 
1369 	struct mutex	reset_in_progress_mutex;
1370 	spinlock_t	ioc_reset_in_progress_lock;
1371 	u8		ioc_link_reset_in_progress;
1372 
1373 	u8		ignore_loginfos;
1374 	u8		remove_host;
1375 	u8		pci_error_recovery;
1376 	u8		wait_for_discovery_to_complete;
1377 	u8		is_driver_loading;
1378 	u8		port_enable_failed;
1379 	u8		start_scan;
1380 	u16		start_scan_failed;
1381 
1382 	u8		msix_enable;
1383 	u16		msix_vector_count;
1384 	u8		*cpu_msix_table;
1385 	u16		cpu_msix_table_sz;
1386 	resource_size_t __iomem **reply_post_host_index;
1387 	u32		ioc_reset_count;
1388 	MPT3SAS_FLUSH_RUNNING_CMDS schedule_dead_ioc_flush_running_cmds;
1389 	u32             non_operational_loop;
1390 	u8              ioc_coredump_loop;
1391 	u32		timestamp_update_count;
1392 	u32		time_sync_interval;
1393 	atomic64_t      total_io_cnt;
1394 	atomic64_t	high_iops_outstanding;
1395 	bool            msix_load_balance;
1396 	u16		thresh_hold;
1397 	u8		high_iops_queues;
1398 	u8		iopoll_q_start_index;
1399 	u32             drv_internal_flags;
1400 	u32		drv_support_bitmap;
1401 	u32             dma_mask;
1402 	bool		enable_sdev_max_qd;
1403 	bool		use_32bit_dma;
1404 	struct io_uring_poll_queue *io_uring_poll_queues;
1405 
1406 	/* internal commands, callback index */
1407 	u8		scsi_io_cb_idx;
1408 	u8		tm_cb_idx;
1409 	u8		transport_cb_idx;
1410 	u8		scsih_cb_idx;
1411 	u8		ctl_cb_idx;
1412 	u8		base_cb_idx;
1413 	u8		port_enable_cb_idx;
1414 	u8		config_cb_idx;
1415 	u8		tm_tr_cb_idx;
1416 	u8		tm_tr_volume_cb_idx;
1417 	u8		tm_sas_control_cb_idx;
1418 	struct _internal_cmd base_cmds;
1419 	struct _internal_cmd port_enable_cmds;
1420 	struct _internal_cmd transport_cmds;
1421 	struct _internal_cmd scsih_cmds;
1422 	struct _internal_cmd tm_cmds;
1423 	struct _internal_cmd ctl_cmds;
1424 	struct _internal_cmd config_cmds;
1425 
1426 	MPT_ADD_SGE	base_add_sg_single;
1427 
1428 	/* function ptr for either IEEE or MPI sg elements */
1429 	MPT_BUILD_SG_SCMD build_sg_scmd;
1430 	MPT_BUILD_SG    build_sg;
1431 	MPT_BUILD_ZERO_LEN_SGE build_zero_len_sge;
1432 	u16             sge_size_ieee;
1433 	u16		hba_mpi_version_belonged;
1434 
1435 	/* function ptr for MPI sg elements only */
1436 	MPT_BUILD_SG    build_sg_mpi;
1437 	MPT_BUILD_ZERO_LEN_SGE build_zero_len_sge_mpi;
1438 
1439 	/* function ptr for NVMe PRP elements only */
1440 	NVME_BUILD_PRP  build_nvme_prp;
1441 
1442 	/* event log */
1443 	u32		event_type[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];
1444 	u32		event_context;
1445 	void		*event_log;
1446 	u32		event_masks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];
1447 
1448 	u8		tm_custom_handling;
1449 	u8		nvme_abort_timeout;
1450 	u16		max_shutdown_latency;
1451 	u16		max_wideport_qd;
1452 	u16		max_narrowport_qd;
1453 	u16		max_nvme_qd;
1454 	u8		max_sata_qd;
1455 
1456 	/* static config pages */
1457 	struct mpt3sas_facts facts;
1458 	struct mpt3sas_facts prev_fw_facts;
1459 	struct mpt3sas_port_facts *pfacts;
1460 	Mpi2ManufacturingPage0_t manu_pg0;
1461 	struct Mpi2ManufacturingPage10_t manu_pg10;
1462 	struct Mpi2ManufacturingPage11_t manu_pg11;
1463 	Mpi2BiosPage2_t	bios_pg2;
1464 	Mpi2BiosPage3_t	bios_pg3;
1465 	Mpi2IOCPage8_t ioc_pg8;
1466 	Mpi2IOUnitPage0_t iounit_pg0;
1467 	Mpi2IOUnitPage1_t iounit_pg1;
1468 	Mpi2IOUnitPage8_t iounit_pg8;
1469 	Mpi2IOCPage1_t	ioc_pg1_copy;
1470 
1471 	struct _boot_device req_boot_device;
1472 	struct _boot_device req_alt_boot_device;
1473 	struct _boot_device current_boot_device;
1474 
1475 	/* sas hba, expander, and device list */
1476 	struct _sas_node sas_hba;
1477 	struct list_head sas_expander_list;
1478 	struct list_head enclosure_list;
1479 	spinlock_t	sas_node_lock;
1480 	struct list_head sas_device_list;
1481 	struct list_head sas_device_init_list;
1482 	spinlock_t	sas_device_lock;
1483 	struct list_head pcie_device_list;
1484 	struct list_head pcie_device_init_list;
1485 	spinlock_t      pcie_device_lock;
1486 
1487 	struct list_head raid_device_list;
1488 	spinlock_t	raid_device_lock;
1489 	u8		io_missing_delay;
1490 	u16		device_missing_delay;
1491 	int		sas_id;
1492 	int		pcie_target_id;
1493 
1494 	void		*blocking_handles;
1495 	void		*pd_handles;
1496 	u16		pd_handles_sz;
1497 
1498 	void		*pend_os_device_add;
1499 	u16		pend_os_device_add_sz;
1500 
1501 	/* config page */
1502 	u16		config_page_sz;
1503 	void		*config_page;
1504 	dma_addr_t	config_page_dma;
1505 	void		*config_vaddr;
1506 
1507 	/* scsiio request */
1508 	u16		hba_queue_depth;
1509 	u16		sge_size;
1510 	u16		scsiio_depth;
1511 	u16		request_sz;
1512 	u8		*request;
1513 	dma_addr_t	request_dma;
1514 	u32		request_dma_sz;
1515 	struct pcie_sg_list *pcie_sg_lookup;
1516 	spinlock_t	scsi_lookup_lock;
1517 	int		pending_io_count;
1518 	wait_queue_head_t reset_wq;
1519 	u16		*io_queue_num;
1520 
1521 	/* PCIe SGL */
1522 	struct dma_pool *pcie_sgl_dma_pool;
1523 	/* Host Page Size */
1524 	u32		page_size;
1525 
1526 	/* chain */
1527 	struct chain_lookup *chain_lookup;
1528 	struct list_head free_chain_list;
1529 	struct dma_pool *chain_dma_pool;
1530 	ulong		chain_pages;
1531 	u16		max_sges_in_main_message;
1532 	u16		max_sges_in_chain_message;
1533 	u16		chains_needed_per_io;
1534 	u32		chain_depth;
1535 	u16		chain_segment_sz;
1536 	u16		chains_per_prp_buffer;
1537 
1538 	/* hi-priority queue */
1539 	u16		hi_priority_smid;
1540 	u8		*hi_priority;
1541 	dma_addr_t	hi_priority_dma;
1542 	u16		hi_priority_depth;
1543 	struct request_tracker *hpr_lookup;
1544 	struct list_head hpr_free_list;
1545 
1546 	/* internal queue */
1547 	u16		internal_smid;
1548 	u8		*internal;
1549 	dma_addr_t	internal_dma;
1550 	u16		internal_depth;
1551 	struct request_tracker *internal_lookup;
1552 	struct list_head internal_free_list;
1553 
1554 	/* sense */
1555 	u8		*sense;
1556 	dma_addr_t	sense_dma;
1557 	struct dma_pool *sense_dma_pool;
1558 
1559 	/* reply */
1560 	u16		reply_sz;
1561 	u8		*reply;
1562 	dma_addr_t	reply_dma;
1563 	u32		reply_dma_max_address;
1564 	u32		reply_dma_min_address;
1565 	struct dma_pool *reply_dma_pool;
1566 
1567 	/* reply free queue */
1568 	u16		reply_free_queue_depth;
1569 	__le32		*reply_free;
1570 	dma_addr_t	reply_free_dma;
1571 	struct dma_pool *reply_free_dma_pool;
1572 	u32		reply_free_host_index;
1573 
1574 	/* reply post queue */
1575 	u16		reply_post_queue_depth;
1576 	struct reply_post_struct *reply_post;
1577 	u8		rdpq_array_capable;
1578 	u8		rdpq_array_enable;
1579 	u8		rdpq_array_enable_assigned;
1580 	struct dma_pool *reply_post_free_dma_pool;
1581 	struct dma_pool *reply_post_free_array_dma_pool;
1582 	Mpi2IOCInitRDPQArrayEntry *reply_post_free_array;
1583 	dma_addr_t reply_post_free_array_dma;
1584 	u8		reply_queue_count;
1585 	struct list_head reply_queue_list;
1586 
1587 	u8		combined_reply_queue;
1588 	u8		combined_reply_index_count;
1589 	u8		smp_affinity_enable;
1590 	/* reply post register index */
1591 	resource_size_t	__iomem **replyPostRegisterIndex;
1592 
1593 	struct list_head delayed_tr_list;
1594 	struct list_head delayed_tr_volume_list;
1595 	struct list_head delayed_sc_list;
1596 	struct list_head delayed_event_ack_list;
1597 	u8		temp_sensors_count;
1598 	struct mutex pci_access_mutex;
1599 
1600 	/* diag buffer support */
1601 	u8		*diag_buffer[MPI2_DIAG_BUF_TYPE_COUNT];
1602 	u32		diag_buffer_sz[MPI2_DIAG_BUF_TYPE_COUNT];
1603 	dma_addr_t	diag_buffer_dma[MPI2_DIAG_BUF_TYPE_COUNT];
1604 	u8		diag_buffer_status[MPI2_DIAG_BUF_TYPE_COUNT];
1605 	u32		unique_id[MPI2_DIAG_BUF_TYPE_COUNT];
1606 	u32		product_specific[MPI2_DIAG_BUF_TYPE_COUNT][23];
1607 	u32		diagnostic_flags[MPI2_DIAG_BUF_TYPE_COUNT];
1608 	u32		ring_buffer_offset;
1609 	u32		ring_buffer_sz;
1610 	struct htb_rel_query htb_rel;
1611 	u8 reset_from_user;
1612 	u8		is_warpdrive;
1613 	u8		is_mcpu_endpoint;
1614 	u8		hide_ir_msg;
1615 	u8		mfg_pg10_hide_flag;
1616 	u8		hide_drives;
1617 	spinlock_t	diag_trigger_lock;
1618 	u8		diag_trigger_active;
1619 	u8		atomic_desc_capable;
1620 	BASE_READ_REG	base_readl;
1621 	struct SL_WH_MASTER_TRIGGER_T diag_trigger_master;
1622 	struct SL_WH_EVENT_TRIGGERS_T diag_trigger_event;
1623 	struct SL_WH_SCSI_TRIGGERS_T diag_trigger_scsi;
1624 	struct SL_WH_MPI_TRIGGERS_T diag_trigger_mpi;
1625 	u8		supports_trigger_pages;
1626 	void		*device_remove_in_progress;
1627 	u16		device_remove_in_progress_sz;
1628 	u8		is_gen35_ioc;
1629 	u8		is_aero_ioc;
1630 	struct dentry	*debugfs_root;
1631 	struct dentry	*ioc_dump;
1632 	PUT_SMID_IO_FP_HIP put_smid_scsi_io;
1633 	PUT_SMID_IO_FP_HIP put_smid_fast_path;
1634 	PUT_SMID_IO_FP_HIP put_smid_hi_priority;
1635 	PUT_SMID_DEFAULT put_smid_default;
1636 	GET_MSIX_INDEX get_msix_index_for_smlio;
1637 
1638 	u8		multipath_on_hba;
1639 	struct list_head port_table_list;
1640 };
1641 
1642 struct mpt3sas_debugfs_buffer {
1643 	void	*buf;
1644 	u32	len;
1645 };
1646 
1647 #define MPT_DRV_SUPPORT_BITMAP_MEMMOVE 0x00000001
1648 #define MPT_DRV_SUPPORT_BITMAP_ADDNLQUERY	0x00000002
1649 
1650 #define MPT_DRV_INTERNAL_FIRST_PE_ISSUED		0x00000001
1651 
1652 typedef u8 (*MPT_CALLBACK)(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
1653 	u32 reply);
1654 
1655 /*
1656  * struct ATTO_SAS_NVRAM - ATTO NVRAM settings stored
1657  *				in Manufacturing page 1 used to get
1658  *				ATTO SasAddr.
1659  */
1660 struct ATTO_SAS_NVRAM {
1661 	u8		Signature[4];
1662 	u8		Version;
1663 #define ATTO_SASNVR_VERSION		0
1664 
1665 	u8		Checksum;
1666 #define ATTO_SASNVR_CKSUM_SEED	0x5A
1667 	u8		Pad[10];
1668 	u8		SasAddr[8];
1669 #define ATTO_SAS_ADDR_ALIGN		64
1670 	u8		Reserved[232];
1671 };
1672 
1673 #define ATTO_SAS_ADDR_DEVNAME_BIAS		63
1674 
1675 union ATTO_SAS_ADDRESS {
1676 	U8		b[8];
1677 	U16		w[4];
1678 	U32		d[2];
1679 	U64		q;
1680 };
1681 
1682 /* base shared API */
1683 extern struct list_head mpt3sas_ioc_list;
1684 extern char    driver_name[MPT_NAME_LENGTH];
1685 /* spinlock on list operations over IOCs
1686  * Case: when multiple warpdrive cards(IOCs) are in use
1687  * Each IOC will added to the ioc list structure on initialization.
1688  * Watchdog threads run at regular intervals to check IOC for any
1689  * fault conditions which will trigger the dead_ioc thread to
1690  * deallocate pci resource, resulting deleting the IOC netry from list,
1691  * this deletion need to protected by spinlock to enusre that
1692  * ioc removal is syncrhonized, if not synchronized it might lead to
1693  * list_del corruption as the ioc list is traversed in cli path.
1694  */
1695 extern spinlock_t gioc_lock;
1696 
1697 void mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc);
1698 void mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc);
1699 
1700 int mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc);
1701 void mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc);
1702 int mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc);
1703 void mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc);
1704 void mpt3sas_free_enclosure_list(struct MPT3SAS_ADAPTER *ioc);
1705 int mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc,
1706 	enum reset_type type);
1707 
1708 void *mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid);
1709 void *mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid);
1710 __le32 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc,
1711 	u16 smid);
1712 void *mpt3sas_base_get_pcie_sgl(struct MPT3SAS_ADAPTER *ioc, u16 smid);
1713 dma_addr_t mpt3sas_base_get_pcie_sgl_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid);
1714 void mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc, u8 poll);
1715 void mpt3sas_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc);
1716 void mpt3sas_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc);
1717 
1718 void mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
1719 	u16 handle);
1720 void mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid,
1721 	u16 msix_task);
1722 void mpt3sas_base_put_smid_nvme_encap(struct MPT3SAS_ADAPTER *ioc, u16 smid);
1723 void mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid);
1724 /* hi-priority queue */
1725 u16 mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx);
1726 u16 mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
1727 		struct scsi_cmnd *scmd);
1728 void mpt3sas_base_clear_st(struct MPT3SAS_ADAPTER *ioc,
1729 		struct scsiio_tracker *st);
1730 
1731 u16 mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx);
1732 void mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid);
1733 void mpt3sas_base_initialize_callback_handler(void);
1734 u8 mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func);
1735 void mpt3sas_base_release_callback_handler(u8 cb_idx);
1736 
1737 u8 mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
1738 	u32 reply);
1739 u8 mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid,
1740 	u8 msix_index, u32 reply);
1741 void *mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc,
1742 	u32 phys_addr);
1743 
1744 u32 mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked);
1745 
1746 void mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code);
1747 #define mpt3sas_print_fault_code(ioc, fault_code) \
1748 do { pr_err("%s fault info from func: %s\n", ioc->name, __func__); \
1749 	mpt3sas_base_fault_info(ioc, fault_code); } while (0)
1750 
1751 void mpt3sas_base_coredump_info(struct MPT3SAS_ADAPTER *ioc, u16 fault_code);
1752 #define mpt3sas_print_coredump_info(ioc, fault_code) \
1753 do { pr_err("%s fault info from func: %s\n", ioc->name, __func__); \
1754 	mpt3sas_base_coredump_info(ioc, fault_code); } while (0)
1755 
1756 int mpt3sas_base_wait_for_coredump_completion(struct MPT3SAS_ADAPTER *ioc,
1757 		const char *caller);
1758 int mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
1759 	Mpi2SasIoUnitControlReply_t *mpi_reply,
1760 	Mpi2SasIoUnitControlRequest_t *mpi_request);
1761 int mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
1762 	Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request);
1763 
1764 void mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc,
1765 	u32 *event_type);
1766 
1767 void mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc);
1768 
1769 void mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
1770 	u16 device_missing_delay, u8 io_missing_delay);
1771 
1772 int mpt3sas_base_check_for_fault_and_issue_reset(
1773 	struct MPT3SAS_ADAPTER *ioc);
1774 
1775 int mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc);
1776 
1777 void
1778 mpt3sas_wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc);
1779 
1780 u8 mpt3sas_base_check_cmd_timeout(struct MPT3SAS_ADAPTER *ioc,
1781 	u8 status, void *mpi_request, int sz);
1782 #define mpt3sas_check_cmd_timeout(ioc, status, mpi_request, sz, issue_reset) \
1783 do {	ioc_err(ioc, "In func: %s\n", __func__); \
1784 	issue_reset = mpt3sas_base_check_cmd_timeout(ioc, \
1785 	status, mpi_request, sz); } while (0)
1786 
1787 int mpt3sas_wait_for_ioc(struct MPT3SAS_ADAPTER *ioc, int wait_count);
1788 int mpt3sas_base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type);
1789 void mpt3sas_base_free_irq(struct MPT3SAS_ADAPTER *ioc);
1790 void mpt3sas_base_disable_msix(struct MPT3SAS_ADAPTER *ioc);
1791 int mpt3sas_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num);
1792 void mpt3sas_base_pause_mq_polling(struct MPT3SAS_ADAPTER *ioc);
1793 void mpt3sas_base_resume_mq_polling(struct MPT3SAS_ADAPTER *ioc);
1794 
1795 /* scsih shared API */
1796 struct scsi_cmnd *mpt3sas_scsih_scsi_lookup_get(struct MPT3SAS_ADAPTER *ioc,
1797 	u16 smid);
1798 u8 mpt3sas_scsih_event_callback(struct MPT3SAS_ADAPTER *ioc, u8 msix_index,
1799 	u32 reply);
1800 void mpt3sas_scsih_pre_reset_handler(struct MPT3SAS_ADAPTER *ioc);
1801 void mpt3sas_scsih_clear_outstanding_scsi_tm_commands(
1802 	struct MPT3SAS_ADAPTER *ioc);
1803 void mpt3sas_scsih_reset_done_handler(struct MPT3SAS_ADAPTER *ioc);
1804 
1805 int mpt3sas_scsih_issue_tm(struct MPT3SAS_ADAPTER *ioc, u16 handle,
1806 	uint channel, uint id, u64 lun, u8 type, u16 smid_task,
1807 	u16 msix_task, u8 timeout, u8 tr_method);
1808 int mpt3sas_scsih_issue_locked_tm(struct MPT3SAS_ADAPTER *ioc, u16 handle,
1809 	uint channel, uint id, u64 lun, u8 type, u16 smid_task,
1810 	u16 msix_task, u8 timeout, u8 tr_method);
1811 
1812 void mpt3sas_scsih_set_tm_flag(struct MPT3SAS_ADAPTER *ioc, u16 handle);
1813 void mpt3sas_scsih_clear_tm_flag(struct MPT3SAS_ADAPTER *ioc, u16 handle);
1814 void mpt3sas_expander_remove(struct MPT3SAS_ADAPTER *ioc, u64 sas_address,
1815 	struct hba_port *port);
1816 void mpt3sas_device_remove_by_sas_address(struct MPT3SAS_ADAPTER *ioc,
1817 	u64 sas_address, struct hba_port *port);
1818 u8 mpt3sas_check_for_pending_internal_cmds(struct MPT3SAS_ADAPTER *ioc,
1819 	u16 smid);
1820 struct hba_port *
1821 mpt3sas_get_port_by_id(struct MPT3SAS_ADAPTER *ioc, u8 port,
1822 	u8 bypass_dirty_port_flag);
1823 
1824 struct _sas_node *mpt3sas_scsih_expander_find_by_handle(
1825 	struct MPT3SAS_ADAPTER *ioc, u16 handle);
1826 struct _sas_node *mpt3sas_scsih_expander_find_by_sas_address(
1827 	struct MPT3SAS_ADAPTER *ioc, u64 sas_address,
1828 	struct hba_port *port);
1829 struct _sas_device *mpt3sas_get_sdev_by_addr(
1830 	 struct MPT3SAS_ADAPTER *ioc, u64 sas_address,
1831 	 struct hba_port *port);
1832 struct _sas_device *__mpt3sas_get_sdev_by_addr(
1833 	 struct MPT3SAS_ADAPTER *ioc, u64 sas_address,
1834 	 struct hba_port *port);
1835 struct _sas_device *mpt3sas_get_sdev_by_handle(struct MPT3SAS_ADAPTER *ioc,
1836 	u16 handle);
1837 struct _pcie_device *mpt3sas_get_pdev_by_handle(struct MPT3SAS_ADAPTER *ioc,
1838 	u16 handle);
1839 
1840 void mpt3sas_port_enable_complete(struct MPT3SAS_ADAPTER *ioc);
1841 struct _raid_device *
1842 mpt3sas_raid_device_find_by_handle(struct MPT3SAS_ADAPTER *ioc, u16 handle);
1843 void mpt3sas_scsih_change_queue_depth(struct scsi_device *sdev, int qdepth);
1844 struct _sas_device *
1845 __mpt3sas_get_sdev_by_rphy(struct MPT3SAS_ADAPTER *ioc, struct sas_rphy *rphy);
1846 struct virtual_phy *
1847 mpt3sas_get_vphy_by_phy(struct MPT3SAS_ADAPTER *ioc,
1848 	struct hba_port *port, u32 phy);
1849 
1850 /* config shared API */
1851 u8 mpt3sas_config_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
1852 	u32 reply);
1853 int mpt3sas_config_get_number_hba_phys(struct MPT3SAS_ADAPTER *ioc,
1854 	u8 *num_phys);
1855 int mpt3sas_config_get_manufacturing_pg0(struct MPT3SAS_ADAPTER *ioc,
1856 	Mpi2ConfigReply_t *mpi_reply, Mpi2ManufacturingPage0_t *config_page);
1857 int mpt3sas_config_get_manufacturing_pg1(struct MPT3SAS_ADAPTER *ioc,
1858 	Mpi2ConfigReply_t *mpi_reply, Mpi2ManufacturingPage1_t *config_page);
1859 
1860 int mpt3sas_config_get_manufacturing_pg7(struct MPT3SAS_ADAPTER *ioc,
1861 	Mpi2ConfigReply_t *mpi_reply, Mpi2ManufacturingPage7_t *config_page,
1862 	u16 sz);
1863 int mpt3sas_config_get_manufacturing_pg10(struct MPT3SAS_ADAPTER *ioc,
1864 	Mpi2ConfigReply_t *mpi_reply,
1865 	struct Mpi2ManufacturingPage10_t *config_page);
1866 
1867 int mpt3sas_config_get_manufacturing_pg11(struct MPT3SAS_ADAPTER *ioc,
1868 	Mpi2ConfigReply_t *mpi_reply,
1869 	struct Mpi2ManufacturingPage11_t  *config_page);
1870 int mpt3sas_config_set_manufacturing_pg11(struct MPT3SAS_ADAPTER *ioc,
1871 	Mpi2ConfigReply_t *mpi_reply,
1872 	struct Mpi2ManufacturingPage11_t *config_page);
1873 
1874 int mpt3sas_config_get_bios_pg2(struct MPT3SAS_ADAPTER *ioc, Mpi2ConfigReply_t
1875 	*mpi_reply, Mpi2BiosPage2_t *config_page);
1876 int mpt3sas_config_get_bios_pg3(struct MPT3SAS_ADAPTER *ioc, Mpi2ConfigReply_t
1877 	*mpi_reply, Mpi2BiosPage3_t *config_page);
1878 int mpt3sas_config_set_bios_pg4(struct MPT3SAS_ADAPTER *ioc,
1879 	Mpi2ConfigReply_t *mpi_reply, Mpi2BiosPage4_t *config_page,
1880 	int sz_config_page);
1881 int mpt3sas_config_get_bios_pg4(struct MPT3SAS_ADAPTER *ioc,
1882 	Mpi2ConfigReply_t *mpi_reply, Mpi2BiosPage4_t *config_page,
1883 	int sz_config_page);
1884 int mpt3sas_config_get_iounit_pg0(struct MPT3SAS_ADAPTER *ioc, Mpi2ConfigReply_t
1885 	*mpi_reply, Mpi2IOUnitPage0_t *config_page);
1886 int mpt3sas_config_get_sas_device_pg0(struct MPT3SAS_ADAPTER *ioc,
1887 	Mpi2ConfigReply_t *mpi_reply, Mpi2SasDevicePage0_t *config_page,
1888 	u32 form, u32 handle);
1889 int mpt3sas_config_get_sas_device_pg1(struct MPT3SAS_ADAPTER *ioc,
1890 	Mpi2ConfigReply_t *mpi_reply, Mpi2SasDevicePage1_t *config_page,
1891 	u32 form, u32 handle);
1892 int mpt3sas_config_get_pcie_device_pg0(struct MPT3SAS_ADAPTER *ioc,
1893 	Mpi2ConfigReply_t *mpi_reply, Mpi26PCIeDevicePage0_t *config_page,
1894 	u32 form, u32 handle);
1895 int mpt3sas_config_get_pcie_device_pg2(struct MPT3SAS_ADAPTER *ioc,
1896 	Mpi2ConfigReply_t *mpi_reply, Mpi26PCIeDevicePage2_t *config_page,
1897 	u32 form, u32 handle);
1898 int mpt3sas_config_get_pcie_iounit_pg1(struct MPT3SAS_ADAPTER *ioc,
1899 	Mpi2ConfigReply_t *mpi_reply, Mpi26PCIeIOUnitPage1_t *config_page,
1900 	u16 sz);
1901 int mpt3sas_config_get_sas_iounit_pg0(struct MPT3SAS_ADAPTER *ioc,
1902 	Mpi2ConfigReply_t *mpi_reply, Mpi2SasIOUnitPage0_t *config_page,
1903 	u16 sz);
1904 int mpt3sas_config_get_iounit_pg1(struct MPT3SAS_ADAPTER *ioc, Mpi2ConfigReply_t
1905 	*mpi_reply, Mpi2IOUnitPage1_t *config_page);
1906 int mpt3sas_config_get_iounit_pg3(struct MPT3SAS_ADAPTER *ioc,
1907 	Mpi2ConfigReply_t *mpi_reply, Mpi2IOUnitPage3_t *config_page, u16 sz);
1908 int mpt3sas_config_set_iounit_pg1(struct MPT3SAS_ADAPTER *ioc, Mpi2ConfigReply_t
1909 	*mpi_reply, Mpi2IOUnitPage1_t *config_page);
1910 int mpt3sas_config_get_iounit_pg8(struct MPT3SAS_ADAPTER *ioc, Mpi2ConfigReply_t
1911 	*mpi_reply, Mpi2IOUnitPage8_t *config_page);
1912 int mpt3sas_config_get_sas_iounit_pg1(struct MPT3SAS_ADAPTER *ioc,
1913 	Mpi2ConfigReply_t *mpi_reply, Mpi2SasIOUnitPage1_t *config_page,
1914 	u16 sz);
1915 int mpt3sas_config_set_sas_iounit_pg1(struct MPT3SAS_ADAPTER *ioc,
1916 	Mpi2ConfigReply_t *mpi_reply, Mpi2SasIOUnitPage1_t *config_page,
1917 	u16 sz);
1918 int mpt3sas_config_get_ioc_pg1(struct MPT3SAS_ADAPTER *ioc, Mpi2ConfigReply_t
1919 	*mpi_reply, Mpi2IOCPage1_t *config_page);
1920 int mpt3sas_config_set_ioc_pg1(struct MPT3SAS_ADAPTER *ioc, Mpi2ConfigReply_t
1921 	*mpi_reply, Mpi2IOCPage1_t *config_page);
1922 int mpt3sas_config_get_ioc_pg8(struct MPT3SAS_ADAPTER *ioc, Mpi2ConfigReply_t
1923 	*mpi_reply, Mpi2IOCPage8_t *config_page);
1924 int mpt3sas_config_get_expander_pg0(struct MPT3SAS_ADAPTER *ioc,
1925 	Mpi2ConfigReply_t *mpi_reply, Mpi2ExpanderPage0_t *config_page,
1926 	u32 form, u32 handle);
1927 int mpt3sas_config_get_expander_pg1(struct MPT3SAS_ADAPTER *ioc,
1928 	Mpi2ConfigReply_t *mpi_reply, Mpi2ExpanderPage1_t *config_page,
1929 	u32 phy_number, u16 handle);
1930 int mpt3sas_config_get_enclosure_pg0(struct MPT3SAS_ADAPTER *ioc,
1931 	Mpi2ConfigReply_t *mpi_reply, Mpi2SasEnclosurePage0_t *config_page,
1932 	u32 form, u32 handle);
1933 int mpt3sas_config_get_phy_pg0(struct MPT3SAS_ADAPTER *ioc, Mpi2ConfigReply_t
1934 	*mpi_reply, Mpi2SasPhyPage0_t *config_page, u32 phy_number);
1935 int mpt3sas_config_get_phy_pg1(struct MPT3SAS_ADAPTER *ioc, Mpi2ConfigReply_t
1936 	*mpi_reply, Mpi2SasPhyPage1_t *config_page, u32 phy_number);
1937 int mpt3sas_config_get_raid_volume_pg1(struct MPT3SAS_ADAPTER *ioc,
1938 	Mpi2ConfigReply_t *mpi_reply, Mpi2RaidVolPage1_t *config_page, u32 form,
1939 	u32 handle);
1940 int mpt3sas_config_get_number_pds(struct MPT3SAS_ADAPTER *ioc, u16 handle,
1941 	u8 *num_pds);
1942 int mpt3sas_config_get_raid_volume_pg0(struct MPT3SAS_ADAPTER *ioc,
1943 	Mpi2ConfigReply_t *mpi_reply, Mpi2RaidVolPage0_t *config_page, u32 form,
1944 	u32 handle, u16 sz);
1945 int mpt3sas_config_get_phys_disk_pg0(struct MPT3SAS_ADAPTER *ioc,
1946 	Mpi2ConfigReply_t *mpi_reply, Mpi2RaidPhysDiskPage0_t *config_page,
1947 	u32 form, u32 form_specific);
1948 int mpt3sas_config_get_volume_handle(struct MPT3SAS_ADAPTER *ioc, u16 pd_handle,
1949 	u16 *volume_handle);
1950 int mpt3sas_config_get_volume_wwid(struct MPT3SAS_ADAPTER *ioc,
1951 	u16 volume_handle, u64 *wwid);
1952 int
1953 mpt3sas_config_get_driver_trigger_pg0(struct MPT3SAS_ADAPTER *ioc,
1954 	Mpi2ConfigReply_t *mpi_reply, Mpi26DriverTriggerPage0_t *config_page);
1955 int
1956 mpt3sas_config_get_driver_trigger_pg1(struct MPT3SAS_ADAPTER *ioc,
1957 	Mpi2ConfigReply_t *mpi_reply, Mpi26DriverTriggerPage1_t *config_page);
1958 int
1959 mpt3sas_config_get_driver_trigger_pg2(struct MPT3SAS_ADAPTER *ioc,
1960 	Mpi2ConfigReply_t *mpi_reply, Mpi26DriverTriggerPage2_t *config_page);
1961 int
1962 mpt3sas_config_get_driver_trigger_pg3(struct MPT3SAS_ADAPTER *ioc,
1963 	Mpi2ConfigReply_t *mpi_reply, Mpi26DriverTriggerPage3_t *config_page);
1964 int
1965 mpt3sas_config_get_driver_trigger_pg4(struct MPT3SAS_ADAPTER *ioc,
1966 	Mpi2ConfigReply_t *mpi_reply, Mpi26DriverTriggerPage4_t *config_page);
1967 int
1968 mpt3sas_config_update_driver_trigger_pg1(struct MPT3SAS_ADAPTER *ioc,
1969 	struct SL_WH_MASTER_TRIGGER_T *master_tg, bool set);
1970 int
1971 mpt3sas_config_update_driver_trigger_pg2(struct MPT3SAS_ADAPTER *ioc,
1972 	struct SL_WH_EVENT_TRIGGERS_T *event_tg, bool set);
1973 int
1974 mpt3sas_config_update_driver_trigger_pg3(struct MPT3SAS_ADAPTER *ioc,
1975 	struct SL_WH_SCSI_TRIGGERS_T *scsi_tg, bool set);
1976 int
1977 mpt3sas_config_update_driver_trigger_pg4(struct MPT3SAS_ADAPTER *ioc,
1978 	struct SL_WH_MPI_TRIGGERS_T *mpi_tg, bool set);
1979 
1980 /* ctl shared API */
1981 extern const struct attribute_group *mpt3sas_host_groups[];
1982 extern const struct attribute_group *mpt3sas_dev_groups[];
1983 void mpt3sas_ctl_init(ushort hbas_to_enumerate);
1984 void mpt3sas_ctl_exit(ushort hbas_to_enumerate);
1985 u8 mpt3sas_ctl_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
1986 	u32 reply);
1987 void mpt3sas_ctl_pre_reset_handler(struct MPT3SAS_ADAPTER *ioc);
1988 void mpt3sas_ctl_clear_outstanding_ioctls(struct MPT3SAS_ADAPTER *ioc);
1989 void mpt3sas_ctl_reset_done_handler(struct MPT3SAS_ADAPTER *ioc);
1990 u8 mpt3sas_ctl_event_callback(struct MPT3SAS_ADAPTER *ioc,
1991 	u8 msix_index, u32 reply);
1992 void mpt3sas_ctl_add_to_event_log(struct MPT3SAS_ADAPTER *ioc,
1993 	Mpi2EventNotificationReply_t *mpi_reply);
1994 
1995 void mpt3sas_enable_diag_buffer(struct MPT3SAS_ADAPTER *ioc,
1996 	u8 bits_to_register);
1997 int mpt3sas_send_diag_release(struct MPT3SAS_ADAPTER *ioc, u8 buffer_type,
1998 	u8 *issue_reset);
1999 
2000 /* transport shared API */
2001 extern struct scsi_transport_template *mpt3sas_transport_template;
2002 u8 mpt3sas_transport_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
2003 	u32 reply);
2004 struct _sas_port *mpt3sas_transport_port_add(struct MPT3SAS_ADAPTER *ioc,
2005 	u16 handle, u64 sas_address, struct hba_port *port);
2006 void mpt3sas_transport_port_remove(struct MPT3SAS_ADAPTER *ioc, u64 sas_address,
2007 	u64 sas_address_parent, struct hba_port *port);
2008 int mpt3sas_transport_add_host_phy(struct MPT3SAS_ADAPTER *ioc, struct _sas_phy
2009 	*mpt3sas_phy, Mpi2SasPhyPage0_t phy_pg0, struct device *parent_dev);
2010 int mpt3sas_transport_add_expander_phy(struct MPT3SAS_ADAPTER *ioc,
2011 	struct _sas_phy *mpt3sas_phy, Mpi2ExpanderPage1_t expander_pg1,
2012 	struct device *parent_dev);
2013 void mpt3sas_transport_update_links(struct MPT3SAS_ADAPTER *ioc,
2014 	u64 sas_address, u16 handle, u8 phy_number, u8 link_rate,
2015 	struct hba_port *port);
2016 extern struct sas_function_template mpt3sas_transport_functions;
2017 extern struct scsi_transport_template *mpt3sas_transport_template;
2018 void
2019 mpt3sas_transport_del_phy_from_an_existing_port(struct MPT3SAS_ADAPTER *ioc,
2020 	struct _sas_node *sas_node, struct _sas_phy *mpt3sas_phy);
2021 void
2022 mpt3sas_transport_add_phy_to_an_existing_port(struct MPT3SAS_ADAPTER *ioc,
2023 	struct _sas_node *sas_node, struct _sas_phy *mpt3sas_phy,
2024 	u64 sas_address, struct hba_port *port);
2025 /* trigger data externs */
2026 void mpt3sas_send_trigger_data_event(struct MPT3SAS_ADAPTER *ioc,
2027 	struct SL_WH_TRIGGERS_EVENT_DATA_T *event_data);
2028 void mpt3sas_process_trigger_data(struct MPT3SAS_ADAPTER *ioc,
2029 	struct SL_WH_TRIGGERS_EVENT_DATA_T *event_data);
2030 void mpt3sas_trigger_master(struct MPT3SAS_ADAPTER *ioc,
2031 	u32 trigger_bitmask);
2032 void mpt3sas_trigger_event(struct MPT3SAS_ADAPTER *ioc, u16 event,
2033 	u16 log_entry_qualifier);
2034 void mpt3sas_trigger_scsi(struct MPT3SAS_ADAPTER *ioc, u8 sense_key,
2035 	u8 asc, u8 ascq);
2036 void mpt3sas_trigger_mpi(struct MPT3SAS_ADAPTER *ioc, u16 ioc_status,
2037 	u32 loginfo);
2038 
2039 /* warpdrive APIs */
2040 u8 mpt3sas_get_num_volumes(struct MPT3SAS_ADAPTER *ioc);
2041 void mpt3sas_init_warpdrive_properties(struct MPT3SAS_ADAPTER *ioc,
2042 	struct _raid_device *raid_device);
2043 void
2044 mpt3sas_setup_direct_io(struct MPT3SAS_ADAPTER *ioc, struct scsi_cmnd *scmd,
2045 	struct _raid_device *raid_device, Mpi25SCSIIORequest_t *mpi_request);
2046 
2047 /* NCQ Prio Handling Check */
2048 bool scsih_ncq_prio_supp(struct scsi_device *sdev);
2049 
2050 void mpt3sas_setup_debugfs(struct MPT3SAS_ADAPTER *ioc);
2051 void mpt3sas_destroy_debugfs(struct MPT3SAS_ADAPTER *ioc);
2052 void mpt3sas_init_debugfs(void);
2053 void mpt3sas_exit_debugfs(void);
2054 
2055 /**
2056  * _scsih_is_pcie_scsi_device - determines if device is an pcie scsi device
2057  * @device_info: bitfield providing information about the device.
2058  * Context: none
2059  *
2060  * Returns 1 if scsi device.
2061  */
2062 static inline int
mpt3sas_scsih_is_pcie_scsi_device(u32 device_info)2063 mpt3sas_scsih_is_pcie_scsi_device(u32 device_info)
2064 {
2065 	if ((device_info &
2066 	    MPI26_PCIE_DEVINFO_MASK_DEVICE_TYPE) == MPI26_PCIE_DEVINFO_SCSI)
2067 		return 1;
2068 	else
2069 		return 0;
2070 }
2071 #endif /* MPT3SAS_BASE_H_INCLUDED */
2072