1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Admin Function driver
3  *
4  * Copyright (C) 2018 Marvell.
5  *
6  */
7 
8 #include <linux/module.h>
9 #include <linux/interrupt.h>
10 #include <linux/delay.h>
11 #include <linux/irq.h>
12 #include <linux/pci.h>
13 #include <linux/sysfs.h>
14 
15 #include "cgx.h"
16 #include "rvu.h"
17 #include "rvu_reg.h"
18 #include "ptp.h"
19 #include "mcs.h"
20 
21 #include "rvu_trace.h"
22 #include "rvu_npc_hash.h"
23 
24 #define DRV_NAME	"rvu_af"
25 #define DRV_STRING      "Marvell OcteonTX2 RVU Admin Function Driver"
26 
27 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
28 				struct rvu_block *block, int lf);
29 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
30 				  struct rvu_block *block, int lf);
31 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc);
32 
33 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw,
34 			 int type, int num,
35 			 void (mbox_handler)(struct work_struct *),
36 			 void (mbox_up_handler)(struct work_struct *));
37 enum {
38 	TYPE_AFVF,
39 	TYPE_AFPF,
40 };
41 
42 /* Supported devices */
43 static const struct pci_device_id rvu_id_table[] = {
44 	{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AF) },
45 	{ 0, }  /* end of table */
46 };
47 
48 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>");
49 MODULE_DESCRIPTION(DRV_STRING);
50 MODULE_LICENSE("GPL v2");
51 MODULE_DEVICE_TABLE(pci, rvu_id_table);
52 
53 static char *mkex_profile; /* MKEX profile name */
54 module_param(mkex_profile, charp, 0000);
55 MODULE_PARM_DESC(mkex_profile, "MKEX profile name string");
56 
57 static char *kpu_profile; /* KPU profile name */
58 module_param(kpu_profile, charp, 0000);
59 MODULE_PARM_DESC(kpu_profile, "KPU profile name string");
60 
rvu_setup_hw_capabilities(struct rvu * rvu)61 static void rvu_setup_hw_capabilities(struct rvu *rvu)
62 {
63 	struct rvu_hwinfo *hw = rvu->hw;
64 
65 	hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1;
66 	hw->cap.nix_fixed_txschq_mapping = false;
67 	hw->cap.nix_shaping = true;
68 	hw->cap.nix_tx_link_bp = true;
69 	hw->cap.nix_rx_multicast = true;
70 	hw->cap.nix_shaper_toggle_wait = false;
71 	hw->cap.npc_hash_extract = false;
72 	hw->cap.npc_exact_match_enabled = false;
73 	hw->rvu = rvu;
74 
75 	if (is_rvu_pre_96xx_C0(rvu)) {
76 		hw->cap.nix_fixed_txschq_mapping = true;
77 		hw->cap.nix_txsch_per_cgx_lmac = 4;
78 		hw->cap.nix_txsch_per_lbk_lmac = 132;
79 		hw->cap.nix_txsch_per_sdp_lmac = 76;
80 		hw->cap.nix_shaping = false;
81 		hw->cap.nix_tx_link_bp = false;
82 		if (is_rvu_96xx_A0(rvu) || is_rvu_95xx_A0(rvu))
83 			hw->cap.nix_rx_multicast = false;
84 	}
85 	if (!is_rvu_pre_96xx_C0(rvu))
86 		hw->cap.nix_shaper_toggle_wait = true;
87 
88 	if (!is_rvu_otx2(rvu))
89 		hw->cap.per_pf_mbox_regs = true;
90 
91 	if (is_rvu_npc_hash_extract_en(rvu))
92 		hw->cap.npc_hash_extract = true;
93 }
94 
95 /* Poll a RVU block's register 'offset', for a 'zero'
96  * or 'nonzero' at bits specified by 'mask'
97  */
rvu_poll_reg(struct rvu * rvu,u64 block,u64 offset,u64 mask,bool zero)98 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero)
99 {
100 	unsigned long timeout = jiffies + usecs_to_jiffies(20000);
101 	bool twice = false;
102 	void __iomem *reg;
103 	u64 reg_val;
104 
105 	reg = rvu->afreg_base + ((block << 28) | offset);
106 again:
107 	reg_val = readq(reg);
108 	if (zero && !(reg_val & mask))
109 		return 0;
110 	if (!zero && (reg_val & mask))
111 		return 0;
112 	if (time_before(jiffies, timeout)) {
113 		usleep_range(1, 5);
114 		goto again;
115 	}
116 	/* In scenarios where CPU is scheduled out before checking
117 	 * 'time_before' (above) and gets scheduled in such that
118 	 * jiffies are beyond timeout value, then check again if HW is
119 	 * done with the operation in the meantime.
120 	 */
121 	if (!twice) {
122 		twice = true;
123 		goto again;
124 	}
125 	return -EBUSY;
126 }
127 
rvu_alloc_rsrc(struct rsrc_bmap * rsrc)128 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc)
129 {
130 	int id;
131 
132 	if (!rsrc->bmap)
133 		return -EINVAL;
134 
135 	id = find_first_zero_bit(rsrc->bmap, rsrc->max);
136 	if (id >= rsrc->max)
137 		return -ENOSPC;
138 
139 	__set_bit(id, rsrc->bmap);
140 
141 	return id;
142 }
143 
rvu_alloc_rsrc_contig(struct rsrc_bmap * rsrc,int nrsrc)144 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc)
145 {
146 	int start;
147 
148 	if (!rsrc->bmap)
149 		return -EINVAL;
150 
151 	start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0);
152 	if (start >= rsrc->max)
153 		return -ENOSPC;
154 
155 	bitmap_set(rsrc->bmap, start, nrsrc);
156 	return start;
157 }
158 
rvu_free_rsrc_contig(struct rsrc_bmap * rsrc,int nrsrc,int start)159 static void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start)
160 {
161 	if (!rsrc->bmap)
162 		return;
163 	if (start >= rsrc->max)
164 		return;
165 
166 	bitmap_clear(rsrc->bmap, start, nrsrc);
167 }
168 
rvu_rsrc_check_contig(struct rsrc_bmap * rsrc,int nrsrc)169 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc)
170 {
171 	int start;
172 
173 	if (!rsrc->bmap)
174 		return false;
175 
176 	start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0);
177 	if (start >= rsrc->max)
178 		return false;
179 
180 	return true;
181 }
182 
rvu_free_rsrc(struct rsrc_bmap * rsrc,int id)183 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id)
184 {
185 	if (!rsrc->bmap)
186 		return;
187 
188 	__clear_bit(id, rsrc->bmap);
189 }
190 
rvu_rsrc_free_count(struct rsrc_bmap * rsrc)191 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc)
192 {
193 	int used;
194 
195 	if (!rsrc->bmap)
196 		return 0;
197 
198 	used = bitmap_weight(rsrc->bmap, rsrc->max);
199 	return (rsrc->max - used);
200 }
201 
is_rsrc_free(struct rsrc_bmap * rsrc,int id)202 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id)
203 {
204 	if (!rsrc->bmap)
205 		return false;
206 
207 	return !test_bit(id, rsrc->bmap);
208 }
209 
rvu_alloc_bitmap(struct rsrc_bmap * rsrc)210 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc)
211 {
212 	rsrc->bmap = kcalloc(BITS_TO_LONGS(rsrc->max),
213 			     sizeof(long), GFP_KERNEL);
214 	if (!rsrc->bmap)
215 		return -ENOMEM;
216 	return 0;
217 }
218 
rvu_free_bitmap(struct rsrc_bmap * rsrc)219 void rvu_free_bitmap(struct rsrc_bmap *rsrc)
220 {
221 	kfree(rsrc->bmap);
222 }
223 
224 /* Get block LF's HW index from a PF_FUNC's block slot number */
rvu_get_lf(struct rvu * rvu,struct rvu_block * block,u16 pcifunc,u16 slot)225 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot)
226 {
227 	u16 match = 0;
228 	int lf;
229 
230 	mutex_lock(&rvu->rsrc_lock);
231 	for (lf = 0; lf < block->lf.max; lf++) {
232 		if (block->fn_map[lf] == pcifunc) {
233 			if (slot == match) {
234 				mutex_unlock(&rvu->rsrc_lock);
235 				return lf;
236 			}
237 			match++;
238 		}
239 	}
240 	mutex_unlock(&rvu->rsrc_lock);
241 	return -ENODEV;
242 }
243 
244 /* Convert BLOCK_TYPE_E to a BLOCK_ADDR_E.
245  * Some silicon variants of OcteonTX2 supports
246  * multiple blocks of same type.
247  *
248  * @pcifunc has to be zero when no LF is yet attached.
249  *
250  * For a pcifunc if LFs are attached from multiple blocks of same type, then
251  * return blkaddr of first encountered block.
252  */
rvu_get_blkaddr(struct rvu * rvu,int blktype,u16 pcifunc)253 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc)
254 {
255 	int devnum, blkaddr = -ENODEV;
256 	u64 cfg, reg;
257 	bool is_pf;
258 
259 	switch (blktype) {
260 	case BLKTYPE_NPC:
261 		blkaddr = BLKADDR_NPC;
262 		goto exit;
263 	case BLKTYPE_NPA:
264 		blkaddr = BLKADDR_NPA;
265 		goto exit;
266 	case BLKTYPE_NIX:
267 		/* For now assume NIX0 */
268 		if (!pcifunc) {
269 			blkaddr = BLKADDR_NIX0;
270 			goto exit;
271 		}
272 		break;
273 	case BLKTYPE_SSO:
274 		blkaddr = BLKADDR_SSO;
275 		goto exit;
276 	case BLKTYPE_SSOW:
277 		blkaddr = BLKADDR_SSOW;
278 		goto exit;
279 	case BLKTYPE_TIM:
280 		blkaddr = BLKADDR_TIM;
281 		goto exit;
282 	case BLKTYPE_CPT:
283 		/* For now assume CPT0 */
284 		if (!pcifunc) {
285 			blkaddr = BLKADDR_CPT0;
286 			goto exit;
287 		}
288 		break;
289 	}
290 
291 	/* Check if this is a RVU PF or VF */
292 	if (pcifunc & RVU_PFVF_FUNC_MASK) {
293 		is_pf = false;
294 		devnum = rvu_get_hwvf(rvu, pcifunc);
295 	} else {
296 		is_pf = true;
297 		devnum = rvu_get_pf(pcifunc);
298 	}
299 
300 	/* Check if the 'pcifunc' has a NIX LF from 'BLKADDR_NIX0' or
301 	 * 'BLKADDR_NIX1'.
302 	 */
303 	if (blktype == BLKTYPE_NIX) {
304 		reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(0) :
305 			RVU_PRIV_HWVFX_NIXX_CFG(0);
306 		cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
307 		if (cfg) {
308 			blkaddr = BLKADDR_NIX0;
309 			goto exit;
310 		}
311 
312 		reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(1) :
313 			RVU_PRIV_HWVFX_NIXX_CFG(1);
314 		cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
315 		if (cfg)
316 			blkaddr = BLKADDR_NIX1;
317 	}
318 
319 	if (blktype == BLKTYPE_CPT) {
320 		reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(0) :
321 			RVU_PRIV_HWVFX_CPTX_CFG(0);
322 		cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
323 		if (cfg) {
324 			blkaddr = BLKADDR_CPT0;
325 			goto exit;
326 		}
327 
328 		reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(1) :
329 			RVU_PRIV_HWVFX_CPTX_CFG(1);
330 		cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
331 		if (cfg)
332 			blkaddr = BLKADDR_CPT1;
333 	}
334 
335 exit:
336 	if (is_block_implemented(rvu->hw, blkaddr))
337 		return blkaddr;
338 	return -ENODEV;
339 }
340 
rvu_update_rsrc_map(struct rvu * rvu,struct rvu_pfvf * pfvf,struct rvu_block * block,u16 pcifunc,u16 lf,bool attach)341 static void rvu_update_rsrc_map(struct rvu *rvu, struct rvu_pfvf *pfvf,
342 				struct rvu_block *block, u16 pcifunc,
343 				u16 lf, bool attach)
344 {
345 	int devnum, num_lfs = 0;
346 	bool is_pf;
347 	u64 reg;
348 
349 	if (lf >= block->lf.max) {
350 		dev_err(&rvu->pdev->dev,
351 			"%s: FATAL: LF %d is >= %s's max lfs i.e %d\n",
352 			__func__, lf, block->name, block->lf.max);
353 		return;
354 	}
355 
356 	/* Check if this is for a RVU PF or VF */
357 	if (pcifunc & RVU_PFVF_FUNC_MASK) {
358 		is_pf = false;
359 		devnum = rvu_get_hwvf(rvu, pcifunc);
360 	} else {
361 		is_pf = true;
362 		devnum = rvu_get_pf(pcifunc);
363 	}
364 
365 	block->fn_map[lf] = attach ? pcifunc : 0;
366 
367 	switch (block->addr) {
368 	case BLKADDR_NPA:
369 		pfvf->npalf = attach ? true : false;
370 		num_lfs = pfvf->npalf;
371 		break;
372 	case BLKADDR_NIX0:
373 	case BLKADDR_NIX1:
374 		pfvf->nixlf = attach ? true : false;
375 		num_lfs = pfvf->nixlf;
376 		break;
377 	case BLKADDR_SSO:
378 		attach ? pfvf->sso++ : pfvf->sso--;
379 		num_lfs = pfvf->sso;
380 		break;
381 	case BLKADDR_SSOW:
382 		attach ? pfvf->ssow++ : pfvf->ssow--;
383 		num_lfs = pfvf->ssow;
384 		break;
385 	case BLKADDR_TIM:
386 		attach ? pfvf->timlfs++ : pfvf->timlfs--;
387 		num_lfs = pfvf->timlfs;
388 		break;
389 	case BLKADDR_CPT0:
390 		attach ? pfvf->cptlfs++ : pfvf->cptlfs--;
391 		num_lfs = pfvf->cptlfs;
392 		break;
393 	case BLKADDR_CPT1:
394 		attach ? pfvf->cpt1_lfs++ : pfvf->cpt1_lfs--;
395 		num_lfs = pfvf->cpt1_lfs;
396 		break;
397 	}
398 
399 	reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg;
400 	rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs);
401 }
402 
rvu_get_pf(u16 pcifunc)403 inline int rvu_get_pf(u16 pcifunc)
404 {
405 	return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK;
406 }
407 
rvu_get_pf_numvfs(struct rvu * rvu,int pf,int * numvfs,int * hwvf)408 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf)
409 {
410 	u64 cfg;
411 
412 	/* Get numVFs attached to this PF and first HWVF */
413 	cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
414 	if (numvfs)
415 		*numvfs = (cfg >> 12) & 0xFF;
416 	if (hwvf)
417 		*hwvf = cfg & 0xFFF;
418 }
419 
rvu_get_hwvf(struct rvu * rvu,int pcifunc)420 int rvu_get_hwvf(struct rvu *rvu, int pcifunc)
421 {
422 	int pf, func;
423 	u64 cfg;
424 
425 	pf = rvu_get_pf(pcifunc);
426 	func = pcifunc & RVU_PFVF_FUNC_MASK;
427 
428 	/* Get first HWVF attached to this PF */
429 	cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
430 
431 	return ((cfg & 0xFFF) + func - 1);
432 }
433 
rvu_get_pfvf(struct rvu * rvu,int pcifunc)434 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc)
435 {
436 	/* Check if it is a PF or VF */
437 	if (pcifunc & RVU_PFVF_FUNC_MASK)
438 		return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)];
439 	else
440 		return &rvu->pf[rvu_get_pf(pcifunc)];
441 }
442 
is_pf_func_valid(struct rvu * rvu,u16 pcifunc)443 static bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc)
444 {
445 	int pf, vf, nvfs;
446 	u64 cfg;
447 
448 	pf = rvu_get_pf(pcifunc);
449 	if (pf >= rvu->hw->total_pfs)
450 		return false;
451 
452 	if (!(pcifunc & RVU_PFVF_FUNC_MASK))
453 		return true;
454 
455 	/* Check if VF is within number of VFs attached to this PF */
456 	vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1;
457 	cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
458 	nvfs = (cfg >> 12) & 0xFF;
459 	if (vf >= nvfs)
460 		return false;
461 
462 	return true;
463 }
464 
is_block_implemented(struct rvu_hwinfo * hw,int blkaddr)465 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr)
466 {
467 	struct rvu_block *block;
468 
469 	if (blkaddr < BLKADDR_RVUM || blkaddr >= BLK_COUNT)
470 		return false;
471 
472 	block = &hw->block[blkaddr];
473 	return block->implemented;
474 }
475 
rvu_check_block_implemented(struct rvu * rvu)476 static void rvu_check_block_implemented(struct rvu *rvu)
477 {
478 	struct rvu_hwinfo *hw = rvu->hw;
479 	struct rvu_block *block;
480 	int blkid;
481 	u64 cfg;
482 
483 	/* For each block check if 'implemented' bit is set */
484 	for (blkid = 0; blkid < BLK_COUNT; blkid++) {
485 		block = &hw->block[blkid];
486 		cfg = rvupf_read64(rvu, RVU_PF_BLOCK_ADDRX_DISC(blkid));
487 		if (cfg & BIT_ULL(11))
488 			block->implemented = true;
489 	}
490 }
491 
rvu_setup_rvum_blk_revid(struct rvu * rvu)492 static void rvu_setup_rvum_blk_revid(struct rvu *rvu)
493 {
494 	rvu_write64(rvu, BLKADDR_RVUM,
495 		    RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM),
496 		    RVU_BLK_RVUM_REVID);
497 }
498 
rvu_clear_rvum_blk_revid(struct rvu * rvu)499 static void rvu_clear_rvum_blk_revid(struct rvu *rvu)
500 {
501 	rvu_write64(rvu, BLKADDR_RVUM,
502 		    RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 0x00);
503 }
504 
rvu_lf_reset(struct rvu * rvu,struct rvu_block * block,int lf)505 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf)
506 {
507 	int err;
508 
509 	if (!block->implemented)
510 		return 0;
511 
512 	rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12));
513 	err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12),
514 			   true);
515 	return err;
516 }
517 
rvu_block_reset(struct rvu * rvu,int blkaddr,u64 rst_reg)518 static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg)
519 {
520 	struct rvu_block *block = &rvu->hw->block[blkaddr];
521 	int err;
522 
523 	if (!block->implemented)
524 		return;
525 
526 	rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0));
527 	err = rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true);
528 	if (err) {
529 		dev_err(rvu->dev, "HW block:%d reset timeout retrying again\n", blkaddr);
530 		while (rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true) == -EBUSY)
531 			;
532 	}
533 }
534 
rvu_reset_all_blocks(struct rvu * rvu)535 static void rvu_reset_all_blocks(struct rvu *rvu)
536 {
537 	/* Do a HW reset of all RVU blocks */
538 	rvu_block_reset(rvu, BLKADDR_NPA, NPA_AF_BLK_RST);
539 	rvu_block_reset(rvu, BLKADDR_NIX0, NIX_AF_BLK_RST);
540 	rvu_block_reset(rvu, BLKADDR_NIX1, NIX_AF_BLK_RST);
541 	rvu_block_reset(rvu, BLKADDR_NPC, NPC_AF_BLK_RST);
542 	rvu_block_reset(rvu, BLKADDR_SSO, SSO_AF_BLK_RST);
543 	rvu_block_reset(rvu, BLKADDR_TIM, TIM_AF_BLK_RST);
544 	rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST);
545 	rvu_block_reset(rvu, BLKADDR_CPT1, CPT_AF_BLK_RST);
546 	rvu_block_reset(rvu, BLKADDR_NDC_NIX0_RX, NDC_AF_BLK_RST);
547 	rvu_block_reset(rvu, BLKADDR_NDC_NIX0_TX, NDC_AF_BLK_RST);
548 	rvu_block_reset(rvu, BLKADDR_NDC_NIX1_RX, NDC_AF_BLK_RST);
549 	rvu_block_reset(rvu, BLKADDR_NDC_NIX1_TX, NDC_AF_BLK_RST);
550 	rvu_block_reset(rvu, BLKADDR_NDC_NPA0, NDC_AF_BLK_RST);
551 }
552 
rvu_scan_block(struct rvu * rvu,struct rvu_block * block)553 static void rvu_scan_block(struct rvu *rvu, struct rvu_block *block)
554 {
555 	struct rvu_pfvf *pfvf;
556 	u64 cfg;
557 	int lf;
558 
559 	for (lf = 0; lf < block->lf.max; lf++) {
560 		cfg = rvu_read64(rvu, block->addr,
561 				 block->lfcfg_reg | (lf << block->lfshift));
562 		if (!(cfg & BIT_ULL(63)))
563 			continue;
564 
565 		/* Set this resource as being used */
566 		__set_bit(lf, block->lf.bmap);
567 
568 		/* Get, to whom this LF is attached */
569 		pfvf = rvu_get_pfvf(rvu, (cfg >> 8) & 0xFFFF);
570 		rvu_update_rsrc_map(rvu, pfvf, block,
571 				    (cfg >> 8) & 0xFFFF, lf, true);
572 
573 		/* Set start MSIX vector for this LF within this PF/VF */
574 		rvu_set_msix_offset(rvu, pfvf, block, lf);
575 	}
576 }
577 
rvu_check_min_msix_vec(struct rvu * rvu,int nvecs,int pf,int vf)578 static void rvu_check_min_msix_vec(struct rvu *rvu, int nvecs, int pf, int vf)
579 {
580 	int min_vecs;
581 
582 	if (!vf)
583 		goto check_pf;
584 
585 	if (!nvecs) {
586 		dev_warn(rvu->dev,
587 			 "PF%d:VF%d is configured with zero msix vectors, %d\n",
588 			 pf, vf - 1, nvecs);
589 	}
590 	return;
591 
592 check_pf:
593 	if (pf == 0)
594 		min_vecs = RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT;
595 	else
596 		min_vecs = RVU_PF_INT_VEC_CNT;
597 
598 	if (!(nvecs < min_vecs))
599 		return;
600 	dev_warn(rvu->dev,
601 		 "PF%d is configured with too few vectors, %d, min is %d\n",
602 		 pf, nvecs, min_vecs);
603 }
604 
rvu_setup_msix_resources(struct rvu * rvu)605 static int rvu_setup_msix_resources(struct rvu *rvu)
606 {
607 	struct rvu_hwinfo *hw = rvu->hw;
608 	int pf, vf, numvfs, hwvf, err;
609 	int nvecs, offset, max_msix;
610 	struct rvu_pfvf *pfvf;
611 	u64 cfg, phy_addr;
612 	dma_addr_t iova;
613 
614 	for (pf = 0; pf < hw->total_pfs; pf++) {
615 		cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
616 		/* If PF is not enabled, nothing to do */
617 		if (!((cfg >> 20) & 0x01))
618 			continue;
619 
620 		rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf);
621 
622 		pfvf = &rvu->pf[pf];
623 		/* Get num of MSIX vectors attached to this PF */
624 		cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf));
625 		pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1;
626 		rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0);
627 
628 		/* Alloc msix bitmap for this PF */
629 		err = rvu_alloc_bitmap(&pfvf->msix);
630 		if (err)
631 			return err;
632 
633 		/* Allocate memory for MSIX vector to RVU block LF mapping */
634 		pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max,
635 						sizeof(u16), GFP_KERNEL);
636 		if (!pfvf->msix_lfmap)
637 			return -ENOMEM;
638 
639 		/* For PF0 (AF) firmware will set msix vector offsets for
640 		 * AF, block AF and PF0_INT vectors, so jump to VFs.
641 		 */
642 		if (!pf)
643 			goto setup_vfmsix;
644 
645 		/* Set MSIX offset for PF's 'RVU_PF_INT_VEC' vectors.
646 		 * These are allocated on driver init and never freed,
647 		 * so no need to set 'msix_lfmap' for these.
648 		 */
649 		cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf));
650 		nvecs = (cfg >> 12) & 0xFF;
651 		cfg &= ~0x7FFULL;
652 		offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
653 		rvu_write64(rvu, BLKADDR_RVUM,
654 			    RVU_PRIV_PFX_INT_CFG(pf), cfg | offset);
655 setup_vfmsix:
656 		/* Alloc msix bitmap for VFs */
657 		for (vf = 0; vf < numvfs; vf++) {
658 			pfvf =  &rvu->hwvf[hwvf + vf];
659 			/* Get num of MSIX vectors attached to this VF */
660 			cfg = rvu_read64(rvu, BLKADDR_RVUM,
661 					 RVU_PRIV_PFX_MSIX_CFG(pf));
662 			pfvf->msix.max = (cfg & 0xFFF) + 1;
663 			rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1);
664 
665 			/* Alloc msix bitmap for this VF */
666 			err = rvu_alloc_bitmap(&pfvf->msix);
667 			if (err)
668 				return err;
669 
670 			pfvf->msix_lfmap =
671 				devm_kcalloc(rvu->dev, pfvf->msix.max,
672 					     sizeof(u16), GFP_KERNEL);
673 			if (!pfvf->msix_lfmap)
674 				return -ENOMEM;
675 
676 			/* Set MSIX offset for HWVF's 'RVU_VF_INT_VEC' vectors.
677 			 * These are allocated on driver init and never freed,
678 			 * so no need to set 'msix_lfmap' for these.
679 			 */
680 			cfg = rvu_read64(rvu, BLKADDR_RVUM,
681 					 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf));
682 			nvecs = (cfg >> 12) & 0xFF;
683 			cfg &= ~0x7FFULL;
684 			offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
685 			rvu_write64(rvu, BLKADDR_RVUM,
686 				    RVU_PRIV_HWVFX_INT_CFG(hwvf + vf),
687 				    cfg | offset);
688 		}
689 	}
690 
691 	/* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence
692 	 * create an IOMMU mapping for the physical address configured by
693 	 * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA.
694 	 */
695 	cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
696 	max_msix = cfg & 0xFFFFF;
697 	if (rvu->fwdata && rvu->fwdata->msixtr_base)
698 		phy_addr = rvu->fwdata->msixtr_base;
699 	else
700 		phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE);
701 
702 	iova = dma_map_resource(rvu->dev, phy_addr,
703 				max_msix * PCI_MSIX_ENTRY_SIZE,
704 				DMA_BIDIRECTIONAL, 0);
705 
706 	if (dma_mapping_error(rvu->dev, iova))
707 		return -ENOMEM;
708 
709 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova);
710 	rvu->msix_base_iova = iova;
711 	rvu->msixtr_base_phy = phy_addr;
712 
713 	return 0;
714 }
715 
rvu_reset_msix(struct rvu * rvu)716 static void rvu_reset_msix(struct rvu *rvu)
717 {
718 	/* Restore msixtr base register */
719 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE,
720 		    rvu->msixtr_base_phy);
721 }
722 
rvu_free_hw_resources(struct rvu * rvu)723 static void rvu_free_hw_resources(struct rvu *rvu)
724 {
725 	struct rvu_hwinfo *hw = rvu->hw;
726 	struct rvu_block *block;
727 	struct rvu_pfvf  *pfvf;
728 	int id, max_msix;
729 	u64 cfg;
730 
731 	rvu_npa_freemem(rvu);
732 	rvu_npc_freemem(rvu);
733 	rvu_nix_freemem(rvu);
734 
735 	/* Free block LF bitmaps */
736 	for (id = 0; id < BLK_COUNT; id++) {
737 		block = &hw->block[id];
738 		kfree(block->lf.bmap);
739 	}
740 
741 	/* Free MSIX bitmaps */
742 	for (id = 0; id < hw->total_pfs; id++) {
743 		pfvf = &rvu->pf[id];
744 		kfree(pfvf->msix.bmap);
745 	}
746 
747 	for (id = 0; id < hw->total_vfs; id++) {
748 		pfvf = &rvu->hwvf[id];
749 		kfree(pfvf->msix.bmap);
750 	}
751 
752 	/* Unmap MSIX vector base IOVA mapping */
753 	if (!rvu->msix_base_iova)
754 		return;
755 	cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
756 	max_msix = cfg & 0xFFFFF;
757 	dma_unmap_resource(rvu->dev, rvu->msix_base_iova,
758 			   max_msix * PCI_MSIX_ENTRY_SIZE,
759 			   DMA_BIDIRECTIONAL, 0);
760 
761 	rvu_reset_msix(rvu);
762 	mutex_destroy(&rvu->rsrc_lock);
763 }
764 
rvu_setup_pfvf_macaddress(struct rvu * rvu)765 static void rvu_setup_pfvf_macaddress(struct rvu *rvu)
766 {
767 	struct rvu_hwinfo *hw = rvu->hw;
768 	int pf, vf, numvfs, hwvf;
769 	struct rvu_pfvf *pfvf;
770 	u64 *mac;
771 
772 	for (pf = 0; pf < hw->total_pfs; pf++) {
773 		/* For PF0(AF), Assign MAC address to only VFs (LBKVFs) */
774 		if (!pf)
775 			goto lbkvf;
776 
777 		if (!is_pf_cgxmapped(rvu, pf))
778 			continue;
779 		/* Assign MAC address to PF */
780 		pfvf = &rvu->pf[pf];
781 		if (rvu->fwdata && pf < PF_MACNUM_MAX) {
782 			mac = &rvu->fwdata->pf_macs[pf];
783 			if (*mac)
784 				u64_to_ether_addr(*mac, pfvf->mac_addr);
785 			else
786 				eth_random_addr(pfvf->mac_addr);
787 		} else {
788 			eth_random_addr(pfvf->mac_addr);
789 		}
790 		ether_addr_copy(pfvf->default_mac, pfvf->mac_addr);
791 
792 lbkvf:
793 		/* Assign MAC address to VFs*/
794 		rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf);
795 		for (vf = 0; vf < numvfs; vf++, hwvf++) {
796 			pfvf = &rvu->hwvf[hwvf];
797 			if (rvu->fwdata && hwvf < VF_MACNUM_MAX) {
798 				mac = &rvu->fwdata->vf_macs[hwvf];
799 				if (*mac)
800 					u64_to_ether_addr(*mac, pfvf->mac_addr);
801 				else
802 					eth_random_addr(pfvf->mac_addr);
803 			} else {
804 				eth_random_addr(pfvf->mac_addr);
805 			}
806 			ether_addr_copy(pfvf->default_mac, pfvf->mac_addr);
807 		}
808 	}
809 }
810 
rvu_fwdata_init(struct rvu * rvu)811 static int rvu_fwdata_init(struct rvu *rvu)
812 {
813 	u64 fwdbase;
814 	int err;
815 
816 	/* Get firmware data base address */
817 	err = cgx_get_fwdata_base(&fwdbase);
818 	if (err)
819 		goto fail;
820 	rvu->fwdata = ioremap_wc(fwdbase, sizeof(struct rvu_fwdata));
821 	if (!rvu->fwdata)
822 		goto fail;
823 	if (!is_rvu_fwdata_valid(rvu)) {
824 		dev_err(rvu->dev,
825 			"Mismatch in 'fwdata' struct btw kernel and firmware\n");
826 		iounmap(rvu->fwdata);
827 		rvu->fwdata = NULL;
828 		return -EINVAL;
829 	}
830 	return 0;
831 fail:
832 	dev_info(rvu->dev, "Unable to fetch 'fwdata' from firmware\n");
833 	return -EIO;
834 }
835 
rvu_fwdata_exit(struct rvu * rvu)836 static void rvu_fwdata_exit(struct rvu *rvu)
837 {
838 	if (rvu->fwdata)
839 		iounmap(rvu->fwdata);
840 }
841 
rvu_setup_nix_hw_resource(struct rvu * rvu,int blkaddr)842 static int rvu_setup_nix_hw_resource(struct rvu *rvu, int blkaddr)
843 {
844 	struct rvu_hwinfo *hw = rvu->hw;
845 	struct rvu_block *block;
846 	int blkid;
847 	u64 cfg;
848 
849 	/* Init NIX LF's bitmap */
850 	block = &hw->block[blkaddr];
851 	if (!block->implemented)
852 		return 0;
853 	blkid = (blkaddr == BLKADDR_NIX0) ? 0 : 1;
854 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2);
855 	block->lf.max = cfg & 0xFFF;
856 	block->addr = blkaddr;
857 	block->type = BLKTYPE_NIX;
858 	block->lfshift = 8;
859 	block->lookup_reg = NIX_AF_RVU_LF_CFG_DEBUG;
860 	block->pf_lfcnt_reg = RVU_PRIV_PFX_NIXX_CFG(blkid);
861 	block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NIXX_CFG(blkid);
862 	block->lfcfg_reg = NIX_PRIV_LFX_CFG;
863 	block->msixcfg_reg = NIX_PRIV_LFX_INT_CFG;
864 	block->lfreset_reg = NIX_AF_LF_RST;
865 	block->rvu = rvu;
866 	sprintf(block->name, "NIX%d", blkid);
867 	rvu->nix_blkaddr[blkid] = blkaddr;
868 	return rvu_alloc_bitmap(&block->lf);
869 }
870 
rvu_setup_cpt_hw_resource(struct rvu * rvu,int blkaddr)871 static int rvu_setup_cpt_hw_resource(struct rvu *rvu, int blkaddr)
872 {
873 	struct rvu_hwinfo *hw = rvu->hw;
874 	struct rvu_block *block;
875 	int blkid;
876 	u64 cfg;
877 
878 	/* Init CPT LF's bitmap */
879 	block = &hw->block[blkaddr];
880 	if (!block->implemented)
881 		return 0;
882 	blkid = (blkaddr == BLKADDR_CPT0) ? 0 : 1;
883 	cfg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS0);
884 	block->lf.max = cfg & 0xFF;
885 	block->addr = blkaddr;
886 	block->type = BLKTYPE_CPT;
887 	block->multislot = true;
888 	block->lfshift = 3;
889 	block->lookup_reg = CPT_AF_RVU_LF_CFG_DEBUG;
890 	block->pf_lfcnt_reg = RVU_PRIV_PFX_CPTX_CFG(blkid);
891 	block->vf_lfcnt_reg = RVU_PRIV_HWVFX_CPTX_CFG(blkid);
892 	block->lfcfg_reg = CPT_PRIV_LFX_CFG;
893 	block->msixcfg_reg = CPT_PRIV_LFX_INT_CFG;
894 	block->lfreset_reg = CPT_AF_LF_RST;
895 	block->rvu = rvu;
896 	sprintf(block->name, "CPT%d", blkid);
897 	return rvu_alloc_bitmap(&block->lf);
898 }
899 
rvu_get_lbk_bufsize(struct rvu * rvu)900 static void rvu_get_lbk_bufsize(struct rvu *rvu)
901 {
902 	struct pci_dev *pdev = NULL;
903 	void __iomem *base;
904 	u64 lbk_const;
905 
906 	pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
907 			      PCI_DEVID_OCTEONTX2_LBK, pdev);
908 	if (!pdev)
909 		return;
910 
911 	base = pci_ioremap_bar(pdev, 0);
912 	if (!base)
913 		goto err_put;
914 
915 	lbk_const = readq(base + LBK_CONST);
916 
917 	/* cache fifo size */
918 	rvu->hw->lbk_bufsize = FIELD_GET(LBK_CONST_BUF_SIZE, lbk_const);
919 
920 	iounmap(base);
921 err_put:
922 	pci_dev_put(pdev);
923 }
924 
rvu_setup_hw_resources(struct rvu * rvu)925 static int rvu_setup_hw_resources(struct rvu *rvu)
926 {
927 	struct rvu_hwinfo *hw = rvu->hw;
928 	struct rvu_block *block;
929 	int blkid, err;
930 	u64 cfg;
931 
932 	/* Get HW supported max RVU PF & VF count */
933 	cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
934 	hw->total_pfs = (cfg >> 32) & 0xFF;
935 	hw->total_vfs = (cfg >> 20) & 0xFFF;
936 	hw->max_vfs_per_pf = (cfg >> 40) & 0xFF;
937 
938 	/* Init NPA LF's bitmap */
939 	block = &hw->block[BLKADDR_NPA];
940 	if (!block->implemented)
941 		goto nix;
942 	cfg = rvu_read64(rvu, BLKADDR_NPA, NPA_AF_CONST);
943 	block->lf.max = (cfg >> 16) & 0xFFF;
944 	block->addr = BLKADDR_NPA;
945 	block->type = BLKTYPE_NPA;
946 	block->lfshift = 8;
947 	block->lookup_reg = NPA_AF_RVU_LF_CFG_DEBUG;
948 	block->pf_lfcnt_reg = RVU_PRIV_PFX_NPA_CFG;
949 	block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NPA_CFG;
950 	block->lfcfg_reg = NPA_PRIV_LFX_CFG;
951 	block->msixcfg_reg = NPA_PRIV_LFX_INT_CFG;
952 	block->lfreset_reg = NPA_AF_LF_RST;
953 	block->rvu = rvu;
954 	sprintf(block->name, "NPA");
955 	err = rvu_alloc_bitmap(&block->lf);
956 	if (err) {
957 		dev_err(rvu->dev,
958 			"%s: Failed to allocate NPA LF bitmap\n", __func__);
959 		return err;
960 	}
961 
962 nix:
963 	err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX0);
964 	if (err) {
965 		dev_err(rvu->dev,
966 			"%s: Failed to allocate NIX0 LFs bitmap\n", __func__);
967 		return err;
968 	}
969 
970 	err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX1);
971 	if (err) {
972 		dev_err(rvu->dev,
973 			"%s: Failed to allocate NIX1 LFs bitmap\n", __func__);
974 		return err;
975 	}
976 
977 	/* Init SSO group's bitmap */
978 	block = &hw->block[BLKADDR_SSO];
979 	if (!block->implemented)
980 		goto ssow;
981 	cfg = rvu_read64(rvu, BLKADDR_SSO, SSO_AF_CONST);
982 	block->lf.max = cfg & 0xFFFF;
983 	block->addr = BLKADDR_SSO;
984 	block->type = BLKTYPE_SSO;
985 	block->multislot = true;
986 	block->lfshift = 3;
987 	block->lookup_reg = SSO_AF_RVU_LF_CFG_DEBUG;
988 	block->pf_lfcnt_reg = RVU_PRIV_PFX_SSO_CFG;
989 	block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSO_CFG;
990 	block->lfcfg_reg = SSO_PRIV_LFX_HWGRP_CFG;
991 	block->msixcfg_reg = SSO_PRIV_LFX_HWGRP_INT_CFG;
992 	block->lfreset_reg = SSO_AF_LF_HWGRP_RST;
993 	block->rvu = rvu;
994 	sprintf(block->name, "SSO GROUP");
995 	err = rvu_alloc_bitmap(&block->lf);
996 	if (err) {
997 		dev_err(rvu->dev,
998 			"%s: Failed to allocate SSO LF bitmap\n", __func__);
999 		return err;
1000 	}
1001 
1002 ssow:
1003 	/* Init SSO workslot's bitmap */
1004 	block = &hw->block[BLKADDR_SSOW];
1005 	if (!block->implemented)
1006 		goto tim;
1007 	block->lf.max = (cfg >> 56) & 0xFF;
1008 	block->addr = BLKADDR_SSOW;
1009 	block->type = BLKTYPE_SSOW;
1010 	block->multislot = true;
1011 	block->lfshift = 3;
1012 	block->lookup_reg = SSOW_AF_RVU_LF_HWS_CFG_DEBUG;
1013 	block->pf_lfcnt_reg = RVU_PRIV_PFX_SSOW_CFG;
1014 	block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSOW_CFG;
1015 	block->lfcfg_reg = SSOW_PRIV_LFX_HWS_CFG;
1016 	block->msixcfg_reg = SSOW_PRIV_LFX_HWS_INT_CFG;
1017 	block->lfreset_reg = SSOW_AF_LF_HWS_RST;
1018 	block->rvu = rvu;
1019 	sprintf(block->name, "SSOWS");
1020 	err = rvu_alloc_bitmap(&block->lf);
1021 	if (err) {
1022 		dev_err(rvu->dev,
1023 			"%s: Failed to allocate SSOW LF bitmap\n", __func__);
1024 		return err;
1025 	}
1026 
1027 tim:
1028 	/* Init TIM LF's bitmap */
1029 	block = &hw->block[BLKADDR_TIM];
1030 	if (!block->implemented)
1031 		goto cpt;
1032 	cfg = rvu_read64(rvu, BLKADDR_TIM, TIM_AF_CONST);
1033 	block->lf.max = cfg & 0xFFFF;
1034 	block->addr = BLKADDR_TIM;
1035 	block->type = BLKTYPE_TIM;
1036 	block->multislot = true;
1037 	block->lfshift = 3;
1038 	block->lookup_reg = TIM_AF_RVU_LF_CFG_DEBUG;
1039 	block->pf_lfcnt_reg = RVU_PRIV_PFX_TIM_CFG;
1040 	block->vf_lfcnt_reg = RVU_PRIV_HWVFX_TIM_CFG;
1041 	block->lfcfg_reg = TIM_PRIV_LFX_CFG;
1042 	block->msixcfg_reg = TIM_PRIV_LFX_INT_CFG;
1043 	block->lfreset_reg = TIM_AF_LF_RST;
1044 	block->rvu = rvu;
1045 	sprintf(block->name, "TIM");
1046 	err = rvu_alloc_bitmap(&block->lf);
1047 	if (err) {
1048 		dev_err(rvu->dev,
1049 			"%s: Failed to allocate TIM LF bitmap\n", __func__);
1050 		return err;
1051 	}
1052 
1053 cpt:
1054 	err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT0);
1055 	if (err) {
1056 		dev_err(rvu->dev,
1057 			"%s: Failed to allocate CPT0 LF bitmap\n", __func__);
1058 		return err;
1059 	}
1060 	err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT1);
1061 	if (err) {
1062 		dev_err(rvu->dev,
1063 			"%s: Failed to allocate CPT1 LF bitmap\n", __func__);
1064 		return err;
1065 	}
1066 
1067 	/* Allocate memory for PFVF data */
1068 	rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs,
1069 			       sizeof(struct rvu_pfvf), GFP_KERNEL);
1070 	if (!rvu->pf) {
1071 		dev_err(rvu->dev,
1072 			"%s: Failed to allocate memory for PF's rvu_pfvf struct\n", __func__);
1073 		return -ENOMEM;
1074 	}
1075 
1076 	rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs,
1077 				 sizeof(struct rvu_pfvf), GFP_KERNEL);
1078 	if (!rvu->hwvf) {
1079 		dev_err(rvu->dev,
1080 			"%s: Failed to allocate memory for VF's rvu_pfvf struct\n", __func__);
1081 		return -ENOMEM;
1082 	}
1083 
1084 	mutex_init(&rvu->rsrc_lock);
1085 
1086 	rvu_fwdata_init(rvu);
1087 
1088 	err = rvu_setup_msix_resources(rvu);
1089 	if (err) {
1090 		dev_err(rvu->dev,
1091 			"%s: Failed to setup MSIX resources\n", __func__);
1092 		return err;
1093 	}
1094 
1095 	for (blkid = 0; blkid < BLK_COUNT; blkid++) {
1096 		block = &hw->block[blkid];
1097 		if (!block->lf.bmap)
1098 			continue;
1099 
1100 		/* Allocate memory for block LF/slot to pcifunc mapping info */
1101 		block->fn_map = devm_kcalloc(rvu->dev, block->lf.max,
1102 					     sizeof(u16), GFP_KERNEL);
1103 		if (!block->fn_map) {
1104 			err = -ENOMEM;
1105 			goto msix_err;
1106 		}
1107 
1108 		/* Scan all blocks to check if low level firmware has
1109 		 * already provisioned any of the resources to a PF/VF.
1110 		 */
1111 		rvu_scan_block(rvu, block);
1112 	}
1113 
1114 	err = rvu_set_channels_base(rvu);
1115 	if (err)
1116 		goto msix_err;
1117 
1118 	err = rvu_npc_init(rvu);
1119 	if (err) {
1120 		dev_err(rvu->dev, "%s: Failed to initialize npc\n", __func__);
1121 		goto npc_err;
1122 	}
1123 
1124 	err = rvu_cgx_init(rvu);
1125 	if (err) {
1126 		dev_err(rvu->dev, "%s: Failed to initialize cgx\n", __func__);
1127 		goto cgx_err;
1128 	}
1129 
1130 	err = rvu_npc_exact_init(rvu);
1131 	if (err) {
1132 		dev_err(rvu->dev, "failed to initialize exact match table\n");
1133 		return err;
1134 	}
1135 
1136 	/* Assign MACs for CGX mapped functions */
1137 	rvu_setup_pfvf_macaddress(rvu);
1138 
1139 	err = rvu_npa_init(rvu);
1140 	if (err) {
1141 		dev_err(rvu->dev, "%s: Failed to initialize npa\n", __func__);
1142 		goto npa_err;
1143 	}
1144 
1145 	rvu_get_lbk_bufsize(rvu);
1146 
1147 	err = rvu_nix_init(rvu);
1148 	if (err) {
1149 		dev_err(rvu->dev, "%s: Failed to initialize nix\n", __func__);
1150 		goto nix_err;
1151 	}
1152 
1153 	err = rvu_sdp_init(rvu);
1154 	if (err) {
1155 		dev_err(rvu->dev, "%s: Failed to initialize sdp\n", __func__);
1156 		goto nix_err;
1157 	}
1158 
1159 	rvu_program_channels(rvu);
1160 
1161 	err = rvu_mcs_init(rvu);
1162 	if (err) {
1163 		dev_err(rvu->dev, "%s: Failed to initialize mcs\n", __func__);
1164 		goto nix_err;
1165 	}
1166 
1167 	return 0;
1168 
1169 nix_err:
1170 	rvu_nix_freemem(rvu);
1171 npa_err:
1172 	rvu_npa_freemem(rvu);
1173 cgx_err:
1174 	rvu_cgx_exit(rvu);
1175 npc_err:
1176 	rvu_npc_freemem(rvu);
1177 	rvu_fwdata_exit(rvu);
1178 msix_err:
1179 	rvu_reset_msix(rvu);
1180 	return err;
1181 }
1182 
1183 /* NPA and NIX admin queue APIs */
rvu_aq_free(struct rvu * rvu,struct admin_queue * aq)1184 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq)
1185 {
1186 	if (!aq)
1187 		return;
1188 
1189 	qmem_free(rvu->dev, aq->inst);
1190 	qmem_free(rvu->dev, aq->res);
1191 	devm_kfree(rvu->dev, aq);
1192 }
1193 
rvu_aq_alloc(struct rvu * rvu,struct admin_queue ** ad_queue,int qsize,int inst_size,int res_size)1194 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
1195 		 int qsize, int inst_size, int res_size)
1196 {
1197 	struct admin_queue *aq;
1198 	int err;
1199 
1200 	*ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL);
1201 	if (!*ad_queue)
1202 		return -ENOMEM;
1203 	aq = *ad_queue;
1204 
1205 	/* Alloc memory for instructions i.e AQ */
1206 	err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size);
1207 	if (err) {
1208 		devm_kfree(rvu->dev, aq);
1209 		return err;
1210 	}
1211 
1212 	/* Alloc memory for results */
1213 	err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size);
1214 	if (err) {
1215 		rvu_aq_free(rvu, aq);
1216 		return err;
1217 	}
1218 
1219 	spin_lock_init(&aq->lock);
1220 	return 0;
1221 }
1222 
rvu_mbox_handler_ready(struct rvu * rvu,struct msg_req * req,struct ready_msg_rsp * rsp)1223 int rvu_mbox_handler_ready(struct rvu *rvu, struct msg_req *req,
1224 			   struct ready_msg_rsp *rsp)
1225 {
1226 	if (rvu->fwdata) {
1227 		rsp->rclk_freq = rvu->fwdata->rclk;
1228 		rsp->sclk_freq = rvu->fwdata->sclk;
1229 	}
1230 	return 0;
1231 }
1232 
1233 /* Get current count of a RVU block's LF/slots
1234  * provisioned to a given RVU func.
1235  */
rvu_get_rsrc_mapcount(struct rvu_pfvf * pfvf,int blkaddr)1236 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr)
1237 {
1238 	switch (blkaddr) {
1239 	case BLKADDR_NPA:
1240 		return pfvf->npalf ? 1 : 0;
1241 	case BLKADDR_NIX0:
1242 	case BLKADDR_NIX1:
1243 		return pfvf->nixlf ? 1 : 0;
1244 	case BLKADDR_SSO:
1245 		return pfvf->sso;
1246 	case BLKADDR_SSOW:
1247 		return pfvf->ssow;
1248 	case BLKADDR_TIM:
1249 		return pfvf->timlfs;
1250 	case BLKADDR_CPT0:
1251 		return pfvf->cptlfs;
1252 	case BLKADDR_CPT1:
1253 		return pfvf->cpt1_lfs;
1254 	}
1255 	return 0;
1256 }
1257 
1258 /* Return true if LFs of block type are attached to pcifunc */
is_blktype_attached(struct rvu_pfvf * pfvf,int blktype)1259 static bool is_blktype_attached(struct rvu_pfvf *pfvf, int blktype)
1260 {
1261 	switch (blktype) {
1262 	case BLKTYPE_NPA:
1263 		return pfvf->npalf ? 1 : 0;
1264 	case BLKTYPE_NIX:
1265 		return pfvf->nixlf ? 1 : 0;
1266 	case BLKTYPE_SSO:
1267 		return !!pfvf->sso;
1268 	case BLKTYPE_SSOW:
1269 		return !!pfvf->ssow;
1270 	case BLKTYPE_TIM:
1271 		return !!pfvf->timlfs;
1272 	case BLKTYPE_CPT:
1273 		return pfvf->cptlfs || pfvf->cpt1_lfs;
1274 	}
1275 
1276 	return false;
1277 }
1278 
is_pffunc_map_valid(struct rvu * rvu,u16 pcifunc,int blktype)1279 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype)
1280 {
1281 	struct rvu_pfvf *pfvf;
1282 
1283 	if (!is_pf_func_valid(rvu, pcifunc))
1284 		return false;
1285 
1286 	pfvf = rvu_get_pfvf(rvu, pcifunc);
1287 
1288 	/* Check if this PFFUNC has a LF of type blktype attached */
1289 	if (!is_blktype_attached(pfvf, blktype))
1290 		return false;
1291 
1292 	return true;
1293 }
1294 
rvu_lookup_rsrc(struct rvu * rvu,struct rvu_block * block,int pcifunc,int slot)1295 static int rvu_lookup_rsrc(struct rvu *rvu, struct rvu_block *block,
1296 			   int pcifunc, int slot)
1297 {
1298 	u64 val;
1299 
1300 	val = ((u64)pcifunc << 24) | (slot << 16) | (1ULL << 13);
1301 	rvu_write64(rvu, block->addr, block->lookup_reg, val);
1302 	/* Wait for the lookup to finish */
1303 	/* TODO: put some timeout here */
1304 	while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13))
1305 		;
1306 
1307 	val = rvu_read64(rvu, block->addr, block->lookup_reg);
1308 
1309 	/* Check LF valid bit */
1310 	if (!(val & (1ULL << 12)))
1311 		return -1;
1312 
1313 	return (val & 0xFFF);
1314 }
1315 
rvu_get_blkaddr_from_slot(struct rvu * rvu,int blktype,u16 pcifunc,u16 global_slot,u16 * slot_in_block)1316 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc,
1317 			      u16 global_slot, u16 *slot_in_block)
1318 {
1319 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1320 	int numlfs, total_lfs = 0, nr_blocks = 0;
1321 	int i, num_blkaddr[BLK_COUNT] = { 0 };
1322 	struct rvu_block *block;
1323 	int blkaddr;
1324 	u16 start_slot;
1325 
1326 	if (!is_blktype_attached(pfvf, blktype))
1327 		return -ENODEV;
1328 
1329 	/* Get all the block addresses from which LFs are attached to
1330 	 * the given pcifunc in num_blkaddr[].
1331 	 */
1332 	for (blkaddr = BLKADDR_RVUM; blkaddr < BLK_COUNT; blkaddr++) {
1333 		block = &rvu->hw->block[blkaddr];
1334 		if (block->type != blktype)
1335 			continue;
1336 		if (!is_block_implemented(rvu->hw, blkaddr))
1337 			continue;
1338 
1339 		numlfs = rvu_get_rsrc_mapcount(pfvf, blkaddr);
1340 		if (numlfs) {
1341 			total_lfs += numlfs;
1342 			num_blkaddr[nr_blocks] = blkaddr;
1343 			nr_blocks++;
1344 		}
1345 	}
1346 
1347 	if (global_slot >= total_lfs)
1348 		return -ENODEV;
1349 
1350 	/* Based on the given global slot number retrieve the
1351 	 * correct block address out of all attached block
1352 	 * addresses and slot number in that block.
1353 	 */
1354 	total_lfs = 0;
1355 	blkaddr = -ENODEV;
1356 	for (i = 0; i < nr_blocks; i++) {
1357 		numlfs = rvu_get_rsrc_mapcount(pfvf, num_blkaddr[i]);
1358 		total_lfs += numlfs;
1359 		if (global_slot < total_lfs) {
1360 			blkaddr = num_blkaddr[i];
1361 			start_slot = total_lfs - numlfs;
1362 			*slot_in_block = global_slot - start_slot;
1363 			break;
1364 		}
1365 	}
1366 
1367 	return blkaddr;
1368 }
1369 
rvu_detach_block(struct rvu * rvu,int pcifunc,int blktype)1370 static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype)
1371 {
1372 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1373 	struct rvu_hwinfo *hw = rvu->hw;
1374 	struct rvu_block *block;
1375 	int slot, lf, num_lfs;
1376 	int blkaddr;
1377 
1378 	blkaddr = rvu_get_blkaddr(rvu, blktype, pcifunc);
1379 	if (blkaddr < 0)
1380 		return;
1381 
1382 	if (blktype == BLKTYPE_NIX)
1383 		rvu_nix_reset_mac(pfvf, pcifunc);
1384 
1385 	block = &hw->block[blkaddr];
1386 
1387 	num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1388 	if (!num_lfs)
1389 		return;
1390 
1391 	for (slot = 0; slot < num_lfs; slot++) {
1392 		lf = rvu_lookup_rsrc(rvu, block, pcifunc, slot);
1393 		if (lf < 0) /* This should never happen */
1394 			continue;
1395 
1396 		/* Disable the LF */
1397 		rvu_write64(rvu, blkaddr, block->lfcfg_reg |
1398 			    (lf << block->lfshift), 0x00ULL);
1399 
1400 		/* Update SW maintained mapping info as well */
1401 		rvu_update_rsrc_map(rvu, pfvf, block,
1402 				    pcifunc, lf, false);
1403 
1404 		/* Free the resource */
1405 		rvu_free_rsrc(&block->lf, lf);
1406 
1407 		/* Clear MSIX vector offset for this LF */
1408 		rvu_clear_msix_offset(rvu, pfvf, block, lf);
1409 	}
1410 }
1411 
rvu_detach_rsrcs(struct rvu * rvu,struct rsrc_detach * detach,u16 pcifunc)1412 static int rvu_detach_rsrcs(struct rvu *rvu, struct rsrc_detach *detach,
1413 			    u16 pcifunc)
1414 {
1415 	struct rvu_hwinfo *hw = rvu->hw;
1416 	bool detach_all = true;
1417 	struct rvu_block *block;
1418 	int blkid;
1419 
1420 	mutex_lock(&rvu->rsrc_lock);
1421 
1422 	/* Check for partial resource detach */
1423 	if (detach && detach->partial)
1424 		detach_all = false;
1425 
1426 	/* Check for RVU block's LFs attached to this func,
1427 	 * if so, detach them.
1428 	 */
1429 	for (blkid = 0; blkid < BLK_COUNT; blkid++) {
1430 		block = &hw->block[blkid];
1431 		if (!block->lf.bmap)
1432 			continue;
1433 		if (!detach_all && detach) {
1434 			if (blkid == BLKADDR_NPA && !detach->npalf)
1435 				continue;
1436 			else if ((blkid == BLKADDR_NIX0) && !detach->nixlf)
1437 				continue;
1438 			else if ((blkid == BLKADDR_NIX1) && !detach->nixlf)
1439 				continue;
1440 			else if ((blkid == BLKADDR_SSO) && !detach->sso)
1441 				continue;
1442 			else if ((blkid == BLKADDR_SSOW) && !detach->ssow)
1443 				continue;
1444 			else if ((blkid == BLKADDR_TIM) && !detach->timlfs)
1445 				continue;
1446 			else if ((blkid == BLKADDR_CPT0) && !detach->cptlfs)
1447 				continue;
1448 			else if ((blkid == BLKADDR_CPT1) && !detach->cptlfs)
1449 				continue;
1450 		}
1451 		rvu_detach_block(rvu, pcifunc, block->type);
1452 	}
1453 
1454 	mutex_unlock(&rvu->rsrc_lock);
1455 	return 0;
1456 }
1457 
rvu_mbox_handler_detach_resources(struct rvu * rvu,struct rsrc_detach * detach,struct msg_rsp * rsp)1458 int rvu_mbox_handler_detach_resources(struct rvu *rvu,
1459 				      struct rsrc_detach *detach,
1460 				      struct msg_rsp *rsp)
1461 {
1462 	return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc);
1463 }
1464 
rvu_get_nix_blkaddr(struct rvu * rvu,u16 pcifunc)1465 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc)
1466 {
1467 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1468 	int blkaddr = BLKADDR_NIX0, vf;
1469 	struct rvu_pfvf *pf;
1470 
1471 	pf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK);
1472 
1473 	/* All CGX mapped PFs are set with assigned NIX block during init */
1474 	if (is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) {
1475 		blkaddr = pf->nix_blkaddr;
1476 	} else if (is_afvf(pcifunc)) {
1477 		vf = pcifunc - 1;
1478 		/* Assign NIX based on VF number. All even numbered VFs get
1479 		 * NIX0 and odd numbered gets NIX1
1480 		 */
1481 		blkaddr = (vf & 1) ? BLKADDR_NIX1 : BLKADDR_NIX0;
1482 		/* NIX1 is not present on all silicons */
1483 		if (!is_block_implemented(rvu->hw, BLKADDR_NIX1))
1484 			blkaddr = BLKADDR_NIX0;
1485 	}
1486 
1487 	/* if SDP1 then the blkaddr is NIX1 */
1488 	if (is_sdp_pfvf(pcifunc) && pf->sdp_info->node_id == 1)
1489 		blkaddr = BLKADDR_NIX1;
1490 
1491 	switch (blkaddr) {
1492 	case BLKADDR_NIX1:
1493 		pfvf->nix_blkaddr = BLKADDR_NIX1;
1494 		pfvf->nix_rx_intf = NIX_INTFX_RX(1);
1495 		pfvf->nix_tx_intf = NIX_INTFX_TX(1);
1496 		break;
1497 	case BLKADDR_NIX0:
1498 	default:
1499 		pfvf->nix_blkaddr = BLKADDR_NIX0;
1500 		pfvf->nix_rx_intf = NIX_INTFX_RX(0);
1501 		pfvf->nix_tx_intf = NIX_INTFX_TX(0);
1502 		break;
1503 	}
1504 
1505 	return pfvf->nix_blkaddr;
1506 }
1507 
rvu_get_attach_blkaddr(struct rvu * rvu,int blktype,u16 pcifunc,struct rsrc_attach * attach)1508 static int rvu_get_attach_blkaddr(struct rvu *rvu, int blktype,
1509 				  u16 pcifunc, struct rsrc_attach *attach)
1510 {
1511 	int blkaddr;
1512 
1513 	switch (blktype) {
1514 	case BLKTYPE_NIX:
1515 		blkaddr = rvu_get_nix_blkaddr(rvu, pcifunc);
1516 		break;
1517 	case BLKTYPE_CPT:
1518 		if (attach->hdr.ver < RVU_MULTI_BLK_VER)
1519 			return rvu_get_blkaddr(rvu, blktype, 0);
1520 		blkaddr = attach->cpt_blkaddr ? attach->cpt_blkaddr :
1521 			  BLKADDR_CPT0;
1522 		if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1)
1523 			return -ENODEV;
1524 		break;
1525 	default:
1526 		return rvu_get_blkaddr(rvu, blktype, 0);
1527 	}
1528 
1529 	if (is_block_implemented(rvu->hw, blkaddr))
1530 		return blkaddr;
1531 
1532 	return -ENODEV;
1533 }
1534 
rvu_attach_block(struct rvu * rvu,int pcifunc,int blktype,int num_lfs,struct rsrc_attach * attach)1535 static void rvu_attach_block(struct rvu *rvu, int pcifunc, int blktype,
1536 			     int num_lfs, struct rsrc_attach *attach)
1537 {
1538 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1539 	struct rvu_hwinfo *hw = rvu->hw;
1540 	struct rvu_block *block;
1541 	int slot, lf;
1542 	int blkaddr;
1543 	u64 cfg;
1544 
1545 	if (!num_lfs)
1546 		return;
1547 
1548 	blkaddr = rvu_get_attach_blkaddr(rvu, blktype, pcifunc, attach);
1549 	if (blkaddr < 0)
1550 		return;
1551 
1552 	block = &hw->block[blkaddr];
1553 	if (!block->lf.bmap)
1554 		return;
1555 
1556 	for (slot = 0; slot < num_lfs; slot++) {
1557 		/* Allocate the resource */
1558 		lf = rvu_alloc_rsrc(&block->lf);
1559 		if (lf < 0)
1560 			return;
1561 
1562 		cfg = (1ULL << 63) | (pcifunc << 8) | slot;
1563 		rvu_write64(rvu, blkaddr, block->lfcfg_reg |
1564 			    (lf << block->lfshift), cfg);
1565 		rvu_update_rsrc_map(rvu, pfvf, block,
1566 				    pcifunc, lf, true);
1567 
1568 		/* Set start MSIX vector for this LF within this PF/VF */
1569 		rvu_set_msix_offset(rvu, pfvf, block, lf);
1570 	}
1571 }
1572 
rvu_check_rsrc_availability(struct rvu * rvu,struct rsrc_attach * req,u16 pcifunc)1573 static int rvu_check_rsrc_availability(struct rvu *rvu,
1574 				       struct rsrc_attach *req, u16 pcifunc)
1575 {
1576 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1577 	int free_lfs, mappedlfs, blkaddr;
1578 	struct rvu_hwinfo *hw = rvu->hw;
1579 	struct rvu_block *block;
1580 
1581 	/* Only one NPA LF can be attached */
1582 	if (req->npalf && !is_blktype_attached(pfvf, BLKTYPE_NPA)) {
1583 		block = &hw->block[BLKADDR_NPA];
1584 		free_lfs = rvu_rsrc_free_count(&block->lf);
1585 		if (!free_lfs)
1586 			goto fail;
1587 	} else if (req->npalf) {
1588 		dev_err(&rvu->pdev->dev,
1589 			"Func 0x%x: Invalid req, already has NPA\n",
1590 			 pcifunc);
1591 		return -EINVAL;
1592 	}
1593 
1594 	/* Only one NIX LF can be attached */
1595 	if (req->nixlf && !is_blktype_attached(pfvf, BLKTYPE_NIX)) {
1596 		blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_NIX,
1597 						 pcifunc, req);
1598 		if (blkaddr < 0)
1599 			return blkaddr;
1600 		block = &hw->block[blkaddr];
1601 		free_lfs = rvu_rsrc_free_count(&block->lf);
1602 		if (!free_lfs)
1603 			goto fail;
1604 	} else if (req->nixlf) {
1605 		dev_err(&rvu->pdev->dev,
1606 			"Func 0x%x: Invalid req, already has NIX\n",
1607 			pcifunc);
1608 		return -EINVAL;
1609 	}
1610 
1611 	if (req->sso) {
1612 		block = &hw->block[BLKADDR_SSO];
1613 		/* Is request within limits ? */
1614 		if (req->sso > block->lf.max) {
1615 			dev_err(&rvu->pdev->dev,
1616 				"Func 0x%x: Invalid SSO req, %d > max %d\n",
1617 				 pcifunc, req->sso, block->lf.max);
1618 			return -EINVAL;
1619 		}
1620 		mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1621 		free_lfs = rvu_rsrc_free_count(&block->lf);
1622 		/* Check if additional resources are available */
1623 		if (req->sso > mappedlfs &&
1624 		    ((req->sso - mappedlfs) > free_lfs))
1625 			goto fail;
1626 	}
1627 
1628 	if (req->ssow) {
1629 		block = &hw->block[BLKADDR_SSOW];
1630 		if (req->ssow > block->lf.max) {
1631 			dev_err(&rvu->pdev->dev,
1632 				"Func 0x%x: Invalid SSOW req, %d > max %d\n",
1633 				 pcifunc, req->sso, block->lf.max);
1634 			return -EINVAL;
1635 		}
1636 		mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1637 		free_lfs = rvu_rsrc_free_count(&block->lf);
1638 		if (req->ssow > mappedlfs &&
1639 		    ((req->ssow - mappedlfs) > free_lfs))
1640 			goto fail;
1641 	}
1642 
1643 	if (req->timlfs) {
1644 		block = &hw->block[BLKADDR_TIM];
1645 		if (req->timlfs > block->lf.max) {
1646 			dev_err(&rvu->pdev->dev,
1647 				"Func 0x%x: Invalid TIMLF req, %d > max %d\n",
1648 				 pcifunc, req->timlfs, block->lf.max);
1649 			return -EINVAL;
1650 		}
1651 		mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1652 		free_lfs = rvu_rsrc_free_count(&block->lf);
1653 		if (req->timlfs > mappedlfs &&
1654 		    ((req->timlfs - mappedlfs) > free_lfs))
1655 			goto fail;
1656 	}
1657 
1658 	if (req->cptlfs) {
1659 		blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_CPT,
1660 						 pcifunc, req);
1661 		if (blkaddr < 0)
1662 			return blkaddr;
1663 		block = &hw->block[blkaddr];
1664 		if (req->cptlfs > block->lf.max) {
1665 			dev_err(&rvu->pdev->dev,
1666 				"Func 0x%x: Invalid CPTLF req, %d > max %d\n",
1667 				 pcifunc, req->cptlfs, block->lf.max);
1668 			return -EINVAL;
1669 		}
1670 		mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1671 		free_lfs = rvu_rsrc_free_count(&block->lf);
1672 		if (req->cptlfs > mappedlfs &&
1673 		    ((req->cptlfs - mappedlfs) > free_lfs))
1674 			goto fail;
1675 	}
1676 
1677 	return 0;
1678 
1679 fail:
1680 	dev_info(rvu->dev, "Request for %s failed\n", block->name);
1681 	return -ENOSPC;
1682 }
1683 
rvu_attach_from_same_block(struct rvu * rvu,int blktype,struct rsrc_attach * attach)1684 static bool rvu_attach_from_same_block(struct rvu *rvu, int blktype,
1685 				       struct rsrc_attach *attach)
1686 {
1687 	int blkaddr, num_lfs;
1688 
1689 	blkaddr = rvu_get_attach_blkaddr(rvu, blktype,
1690 					 attach->hdr.pcifunc, attach);
1691 	if (blkaddr < 0)
1692 		return false;
1693 
1694 	num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, attach->hdr.pcifunc),
1695 					blkaddr);
1696 	/* Requester already has LFs from given block ? */
1697 	return !!num_lfs;
1698 }
1699 
rvu_mbox_handler_attach_resources(struct rvu * rvu,struct rsrc_attach * attach,struct msg_rsp * rsp)1700 int rvu_mbox_handler_attach_resources(struct rvu *rvu,
1701 				      struct rsrc_attach *attach,
1702 				      struct msg_rsp *rsp)
1703 {
1704 	u16 pcifunc = attach->hdr.pcifunc;
1705 	int err;
1706 
1707 	/* If first request, detach all existing attached resources */
1708 	if (!attach->modify)
1709 		rvu_detach_rsrcs(rvu, NULL, pcifunc);
1710 
1711 	mutex_lock(&rvu->rsrc_lock);
1712 
1713 	/* Check if the request can be accommodated */
1714 	err = rvu_check_rsrc_availability(rvu, attach, pcifunc);
1715 	if (err)
1716 		goto exit;
1717 
1718 	/* Now attach the requested resources */
1719 	if (attach->npalf)
1720 		rvu_attach_block(rvu, pcifunc, BLKTYPE_NPA, 1, attach);
1721 
1722 	if (attach->nixlf)
1723 		rvu_attach_block(rvu, pcifunc, BLKTYPE_NIX, 1, attach);
1724 
1725 	if (attach->sso) {
1726 		/* RVU func doesn't know which exact LF or slot is attached
1727 		 * to it, it always sees as slot 0,1,2. So for a 'modify'
1728 		 * request, simply detach all existing attached LFs/slots
1729 		 * and attach a fresh.
1730 		 */
1731 		if (attach->modify)
1732 			rvu_detach_block(rvu, pcifunc, BLKTYPE_SSO);
1733 		rvu_attach_block(rvu, pcifunc, BLKTYPE_SSO,
1734 				 attach->sso, attach);
1735 	}
1736 
1737 	if (attach->ssow) {
1738 		if (attach->modify)
1739 			rvu_detach_block(rvu, pcifunc, BLKTYPE_SSOW);
1740 		rvu_attach_block(rvu, pcifunc, BLKTYPE_SSOW,
1741 				 attach->ssow, attach);
1742 	}
1743 
1744 	if (attach->timlfs) {
1745 		if (attach->modify)
1746 			rvu_detach_block(rvu, pcifunc, BLKTYPE_TIM);
1747 		rvu_attach_block(rvu, pcifunc, BLKTYPE_TIM,
1748 				 attach->timlfs, attach);
1749 	}
1750 
1751 	if (attach->cptlfs) {
1752 		if (attach->modify &&
1753 		    rvu_attach_from_same_block(rvu, BLKTYPE_CPT, attach))
1754 			rvu_detach_block(rvu, pcifunc, BLKTYPE_CPT);
1755 		rvu_attach_block(rvu, pcifunc, BLKTYPE_CPT,
1756 				 attach->cptlfs, attach);
1757 	}
1758 
1759 exit:
1760 	mutex_unlock(&rvu->rsrc_lock);
1761 	return err;
1762 }
1763 
rvu_get_msix_offset(struct rvu * rvu,struct rvu_pfvf * pfvf,int blkaddr,int lf)1764 static u16 rvu_get_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
1765 			       int blkaddr, int lf)
1766 {
1767 	u16 vec;
1768 
1769 	if (lf < 0)
1770 		return MSIX_VECTOR_INVALID;
1771 
1772 	for (vec = 0; vec < pfvf->msix.max; vec++) {
1773 		if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf))
1774 			return vec;
1775 	}
1776 	return MSIX_VECTOR_INVALID;
1777 }
1778 
rvu_set_msix_offset(struct rvu * rvu,struct rvu_pfvf * pfvf,struct rvu_block * block,int lf)1779 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
1780 				struct rvu_block *block, int lf)
1781 {
1782 	u16 nvecs, vec, offset;
1783 	u64 cfg;
1784 
1785 	cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg |
1786 			 (lf << block->lfshift));
1787 	nvecs = (cfg >> 12) & 0xFF;
1788 
1789 	/* Check and alloc MSIX vectors, must be contiguous */
1790 	if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs))
1791 		return;
1792 
1793 	offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
1794 
1795 	/* Config MSIX offset in LF */
1796 	rvu_write64(rvu, block->addr, block->msixcfg_reg |
1797 		    (lf << block->lfshift), (cfg & ~0x7FFULL) | offset);
1798 
1799 	/* Update the bitmap as well */
1800 	for (vec = 0; vec < nvecs; vec++)
1801 		pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf);
1802 }
1803 
rvu_clear_msix_offset(struct rvu * rvu,struct rvu_pfvf * pfvf,struct rvu_block * block,int lf)1804 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
1805 				  struct rvu_block *block, int lf)
1806 {
1807 	u16 nvecs, vec, offset;
1808 	u64 cfg;
1809 
1810 	cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg |
1811 			 (lf << block->lfshift));
1812 	nvecs = (cfg >> 12) & 0xFF;
1813 
1814 	/* Clear MSIX offset in LF */
1815 	rvu_write64(rvu, block->addr, block->msixcfg_reg |
1816 		    (lf << block->lfshift), cfg & ~0x7FFULL);
1817 
1818 	offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf);
1819 
1820 	/* Update the mapping */
1821 	for (vec = 0; vec < nvecs; vec++)
1822 		pfvf->msix_lfmap[offset + vec] = 0;
1823 
1824 	/* Free the same in MSIX bitmap */
1825 	rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset);
1826 }
1827 
rvu_mbox_handler_msix_offset(struct rvu * rvu,struct msg_req * req,struct msix_offset_rsp * rsp)1828 int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req,
1829 				 struct msix_offset_rsp *rsp)
1830 {
1831 	struct rvu_hwinfo *hw = rvu->hw;
1832 	u16 pcifunc = req->hdr.pcifunc;
1833 	struct rvu_pfvf *pfvf;
1834 	int lf, slot, blkaddr;
1835 
1836 	pfvf = rvu_get_pfvf(rvu, pcifunc);
1837 	if (!pfvf->msix.bmap)
1838 		return 0;
1839 
1840 	/* Set MSIX offsets for each block's LFs attached to this PF/VF */
1841 	lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0);
1842 	rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf);
1843 
1844 	/* Get BLKADDR from which LFs are attached to pcifunc */
1845 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
1846 	if (blkaddr < 0) {
1847 		rsp->nix_msixoff = MSIX_VECTOR_INVALID;
1848 	} else {
1849 		lf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0);
1850 		rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, blkaddr, lf);
1851 	}
1852 
1853 	rsp->sso = pfvf->sso;
1854 	for (slot = 0; slot < rsp->sso; slot++) {
1855 		lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot);
1856 		rsp->sso_msixoff[slot] =
1857 			rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSO, lf);
1858 	}
1859 
1860 	rsp->ssow = pfvf->ssow;
1861 	for (slot = 0; slot < rsp->ssow; slot++) {
1862 		lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot);
1863 		rsp->ssow_msixoff[slot] =
1864 			rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSOW, lf);
1865 	}
1866 
1867 	rsp->timlfs = pfvf->timlfs;
1868 	for (slot = 0; slot < rsp->timlfs; slot++) {
1869 		lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot);
1870 		rsp->timlf_msixoff[slot] =
1871 			rvu_get_msix_offset(rvu, pfvf, BLKADDR_TIM, lf);
1872 	}
1873 
1874 	rsp->cptlfs = pfvf->cptlfs;
1875 	for (slot = 0; slot < rsp->cptlfs; slot++) {
1876 		lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot);
1877 		rsp->cptlf_msixoff[slot] =
1878 			rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT0, lf);
1879 	}
1880 
1881 	rsp->cpt1_lfs = pfvf->cpt1_lfs;
1882 	for (slot = 0; slot < rsp->cpt1_lfs; slot++) {
1883 		lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT1], pcifunc, slot);
1884 		rsp->cpt1_lf_msixoff[slot] =
1885 			rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT1, lf);
1886 	}
1887 
1888 	return 0;
1889 }
1890 
rvu_mbox_handler_free_rsrc_cnt(struct rvu * rvu,struct msg_req * req,struct free_rsrcs_rsp * rsp)1891 int rvu_mbox_handler_free_rsrc_cnt(struct rvu *rvu, struct msg_req *req,
1892 				   struct free_rsrcs_rsp *rsp)
1893 {
1894 	struct rvu_hwinfo *hw = rvu->hw;
1895 	struct rvu_block *block;
1896 	struct nix_txsch *txsch;
1897 	struct nix_hw *nix_hw;
1898 
1899 	mutex_lock(&rvu->rsrc_lock);
1900 
1901 	block = &hw->block[BLKADDR_NPA];
1902 	rsp->npa = rvu_rsrc_free_count(&block->lf);
1903 
1904 	block = &hw->block[BLKADDR_NIX0];
1905 	rsp->nix = rvu_rsrc_free_count(&block->lf);
1906 
1907 	block = &hw->block[BLKADDR_NIX1];
1908 	rsp->nix1 = rvu_rsrc_free_count(&block->lf);
1909 
1910 	block = &hw->block[BLKADDR_SSO];
1911 	rsp->sso = rvu_rsrc_free_count(&block->lf);
1912 
1913 	block = &hw->block[BLKADDR_SSOW];
1914 	rsp->ssow = rvu_rsrc_free_count(&block->lf);
1915 
1916 	block = &hw->block[BLKADDR_TIM];
1917 	rsp->tim = rvu_rsrc_free_count(&block->lf);
1918 
1919 	block = &hw->block[BLKADDR_CPT0];
1920 	rsp->cpt = rvu_rsrc_free_count(&block->lf);
1921 
1922 	block = &hw->block[BLKADDR_CPT1];
1923 	rsp->cpt1 = rvu_rsrc_free_count(&block->lf);
1924 
1925 	if (rvu->hw->cap.nix_fixed_txschq_mapping) {
1926 		rsp->schq[NIX_TXSCH_LVL_SMQ] = 1;
1927 		rsp->schq[NIX_TXSCH_LVL_TL4] = 1;
1928 		rsp->schq[NIX_TXSCH_LVL_TL3] = 1;
1929 		rsp->schq[NIX_TXSCH_LVL_TL2] = 1;
1930 		/* NIX1 */
1931 		if (!is_block_implemented(rvu->hw, BLKADDR_NIX1))
1932 			goto out;
1933 		rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] = 1;
1934 		rsp->schq_nix1[NIX_TXSCH_LVL_TL4] = 1;
1935 		rsp->schq_nix1[NIX_TXSCH_LVL_TL3] = 1;
1936 		rsp->schq_nix1[NIX_TXSCH_LVL_TL2] = 1;
1937 	} else {
1938 		nix_hw = get_nix_hw(hw, BLKADDR_NIX0);
1939 		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ];
1940 		rsp->schq[NIX_TXSCH_LVL_SMQ] =
1941 				rvu_rsrc_free_count(&txsch->schq);
1942 
1943 		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4];
1944 		rsp->schq[NIX_TXSCH_LVL_TL4] =
1945 				rvu_rsrc_free_count(&txsch->schq);
1946 
1947 		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3];
1948 		rsp->schq[NIX_TXSCH_LVL_TL3] =
1949 				rvu_rsrc_free_count(&txsch->schq);
1950 
1951 		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2];
1952 		rsp->schq[NIX_TXSCH_LVL_TL2] =
1953 				rvu_rsrc_free_count(&txsch->schq);
1954 
1955 		if (!is_block_implemented(rvu->hw, BLKADDR_NIX1))
1956 			goto out;
1957 
1958 		nix_hw = get_nix_hw(hw, BLKADDR_NIX1);
1959 		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ];
1960 		rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] =
1961 				rvu_rsrc_free_count(&txsch->schq);
1962 
1963 		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4];
1964 		rsp->schq_nix1[NIX_TXSCH_LVL_TL4] =
1965 				rvu_rsrc_free_count(&txsch->schq);
1966 
1967 		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3];
1968 		rsp->schq_nix1[NIX_TXSCH_LVL_TL3] =
1969 				rvu_rsrc_free_count(&txsch->schq);
1970 
1971 		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2];
1972 		rsp->schq_nix1[NIX_TXSCH_LVL_TL2] =
1973 				rvu_rsrc_free_count(&txsch->schq);
1974 	}
1975 
1976 	rsp->schq_nix1[NIX_TXSCH_LVL_TL1] = 1;
1977 out:
1978 	rsp->schq[NIX_TXSCH_LVL_TL1] = 1;
1979 	mutex_unlock(&rvu->rsrc_lock);
1980 
1981 	return 0;
1982 }
1983 
rvu_mbox_handler_vf_flr(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)1984 int rvu_mbox_handler_vf_flr(struct rvu *rvu, struct msg_req *req,
1985 			    struct msg_rsp *rsp)
1986 {
1987 	u16 pcifunc = req->hdr.pcifunc;
1988 	u16 vf, numvfs;
1989 	u64 cfg;
1990 
1991 	vf = pcifunc & RVU_PFVF_FUNC_MASK;
1992 	cfg = rvu_read64(rvu, BLKADDR_RVUM,
1993 			 RVU_PRIV_PFX_CFG(rvu_get_pf(pcifunc)));
1994 	numvfs = (cfg >> 12) & 0xFF;
1995 
1996 	if (vf && vf <= numvfs)
1997 		__rvu_flr_handler(rvu, pcifunc);
1998 	else
1999 		return RVU_INVALID_VF_ID;
2000 
2001 	return 0;
2002 }
2003 
rvu_mbox_handler_get_hw_cap(struct rvu * rvu,struct msg_req * req,struct get_hw_cap_rsp * rsp)2004 int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req,
2005 				struct get_hw_cap_rsp *rsp)
2006 {
2007 	struct rvu_hwinfo *hw = rvu->hw;
2008 
2009 	rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping;
2010 	rsp->nix_shaping = hw->cap.nix_shaping;
2011 	rsp->npc_hash_extract = hw->cap.npc_hash_extract;
2012 
2013 	return 0;
2014 }
2015 
rvu_mbox_handler_set_vf_perm(struct rvu * rvu,struct set_vf_perm * req,struct msg_rsp * rsp)2016 int rvu_mbox_handler_set_vf_perm(struct rvu *rvu, struct set_vf_perm *req,
2017 				 struct msg_rsp *rsp)
2018 {
2019 	struct rvu_hwinfo *hw = rvu->hw;
2020 	u16 pcifunc = req->hdr.pcifunc;
2021 	struct rvu_pfvf *pfvf;
2022 	int blkaddr, nixlf;
2023 	u16 target;
2024 
2025 	/* Only PF can add VF permissions */
2026 	if ((pcifunc & RVU_PFVF_FUNC_MASK) || is_afvf(pcifunc))
2027 		return -EOPNOTSUPP;
2028 
2029 	target = (pcifunc & ~RVU_PFVF_FUNC_MASK) | (req->vf + 1);
2030 	pfvf = rvu_get_pfvf(rvu, target);
2031 
2032 	if (req->flags & RESET_VF_PERM) {
2033 		pfvf->flags &= RVU_CLEAR_VF_PERM;
2034 	} else if (test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) ^
2035 		 (req->flags & VF_TRUSTED)) {
2036 		change_bit(PF_SET_VF_TRUSTED, &pfvf->flags);
2037 		/* disable multicast and promisc entries */
2038 		if (!test_bit(PF_SET_VF_TRUSTED, &pfvf->flags)) {
2039 			blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, target);
2040 			if (blkaddr < 0)
2041 				return 0;
2042 			nixlf = rvu_get_lf(rvu, &hw->block[blkaddr],
2043 					   target, 0);
2044 			if (nixlf < 0)
2045 				return 0;
2046 			npc_enadis_default_mce_entry(rvu, target, nixlf,
2047 						     NIXLF_ALLMULTI_ENTRY,
2048 						     false);
2049 			npc_enadis_default_mce_entry(rvu, target, nixlf,
2050 						     NIXLF_PROMISC_ENTRY,
2051 						     false);
2052 		}
2053 	}
2054 
2055 	return 0;
2056 }
2057 
rvu_process_mbox_msg(struct otx2_mbox * mbox,int devid,struct mbox_msghdr * req)2058 static int rvu_process_mbox_msg(struct otx2_mbox *mbox, int devid,
2059 				struct mbox_msghdr *req)
2060 {
2061 	struct rvu *rvu = pci_get_drvdata(mbox->pdev);
2062 
2063 	/* Check if valid, if not reply with a invalid msg */
2064 	if (req->sig != OTX2_MBOX_REQ_SIG)
2065 		goto bad_message;
2066 
2067 	switch (req->id) {
2068 #define M(_name, _id, _fn_name, _req_type, _rsp_type)			\
2069 	case _id: {							\
2070 		struct _rsp_type *rsp;					\
2071 		int err;						\
2072 									\
2073 		rsp = (struct _rsp_type *)otx2_mbox_alloc_msg(		\
2074 			mbox, devid,					\
2075 			sizeof(struct _rsp_type));			\
2076 		/* some handlers should complete even if reply */	\
2077 		/* could not be allocated */				\
2078 		if (!rsp &&						\
2079 		    _id != MBOX_MSG_DETACH_RESOURCES &&			\
2080 		    _id != MBOX_MSG_NIX_TXSCH_FREE &&			\
2081 		    _id != MBOX_MSG_VF_FLR)				\
2082 			return -ENOMEM;					\
2083 		if (rsp) {						\
2084 			rsp->hdr.id = _id;				\
2085 			rsp->hdr.sig = OTX2_MBOX_RSP_SIG;		\
2086 			rsp->hdr.pcifunc = req->pcifunc;		\
2087 			rsp->hdr.rc = 0;				\
2088 		}							\
2089 									\
2090 		err = rvu_mbox_handler_ ## _fn_name(rvu,		\
2091 						    (struct _req_type *)req, \
2092 						    rsp);		\
2093 		if (rsp && err)						\
2094 			rsp->hdr.rc = err;				\
2095 									\
2096 		trace_otx2_msg_process(mbox->pdev, _id, err);		\
2097 		return rsp ? err : -ENOMEM;				\
2098 	}
2099 MBOX_MESSAGES
2100 #undef M
2101 
2102 bad_message:
2103 	default:
2104 		otx2_reply_invalid_msg(mbox, devid, req->pcifunc, req->id);
2105 		return -ENODEV;
2106 	}
2107 }
2108 
__rvu_mbox_handler(struct rvu_work * mwork,int type)2109 static void __rvu_mbox_handler(struct rvu_work *mwork, int type)
2110 {
2111 	struct rvu *rvu = mwork->rvu;
2112 	int offset, err, id, devid;
2113 	struct otx2_mbox_dev *mdev;
2114 	struct mbox_hdr *req_hdr;
2115 	struct mbox_msghdr *msg;
2116 	struct mbox_wq_info *mw;
2117 	struct otx2_mbox *mbox;
2118 
2119 	switch (type) {
2120 	case TYPE_AFPF:
2121 		mw = &rvu->afpf_wq_info;
2122 		break;
2123 	case TYPE_AFVF:
2124 		mw = &rvu->afvf_wq_info;
2125 		break;
2126 	default:
2127 		return;
2128 	}
2129 
2130 	devid = mwork - mw->mbox_wrk;
2131 	mbox = &mw->mbox;
2132 	mdev = &mbox->dev[devid];
2133 
2134 	/* Process received mbox messages */
2135 	req_hdr = mdev->mbase + mbox->rx_start;
2136 	if (mw->mbox_wrk[devid].num_msgs == 0)
2137 		return;
2138 
2139 	offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
2140 
2141 	for (id = 0; id < mw->mbox_wrk[devid].num_msgs; id++) {
2142 		msg = mdev->mbase + offset;
2143 
2144 		/* Set which PF/VF sent this message based on mbox IRQ */
2145 		switch (type) {
2146 		case TYPE_AFPF:
2147 			msg->pcifunc &=
2148 				~(RVU_PFVF_PF_MASK << RVU_PFVF_PF_SHIFT);
2149 			msg->pcifunc |= (devid << RVU_PFVF_PF_SHIFT);
2150 			break;
2151 		case TYPE_AFVF:
2152 			msg->pcifunc &=
2153 				~(RVU_PFVF_FUNC_MASK << RVU_PFVF_FUNC_SHIFT);
2154 			msg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1;
2155 			break;
2156 		}
2157 
2158 		err = rvu_process_mbox_msg(mbox, devid, msg);
2159 		if (!err) {
2160 			offset = mbox->rx_start + msg->next_msgoff;
2161 			continue;
2162 		}
2163 
2164 		if (msg->pcifunc & RVU_PFVF_FUNC_MASK)
2165 			dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n",
2166 				 err, otx2_mbox_id2name(msg->id),
2167 				 msg->id, rvu_get_pf(msg->pcifunc),
2168 				 (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1);
2169 		else
2170 			dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n",
2171 				 err, otx2_mbox_id2name(msg->id),
2172 				 msg->id, devid);
2173 	}
2174 	mw->mbox_wrk[devid].num_msgs = 0;
2175 
2176 	/* Send mbox responses to VF/PF */
2177 	otx2_mbox_msg_send(mbox, devid);
2178 }
2179 
rvu_afpf_mbox_handler(struct work_struct * work)2180 static inline void rvu_afpf_mbox_handler(struct work_struct *work)
2181 {
2182 	struct rvu_work *mwork = container_of(work, struct rvu_work, work);
2183 
2184 	__rvu_mbox_handler(mwork, TYPE_AFPF);
2185 }
2186 
rvu_afvf_mbox_handler(struct work_struct * work)2187 static inline void rvu_afvf_mbox_handler(struct work_struct *work)
2188 {
2189 	struct rvu_work *mwork = container_of(work, struct rvu_work, work);
2190 
2191 	__rvu_mbox_handler(mwork, TYPE_AFVF);
2192 }
2193 
__rvu_mbox_up_handler(struct rvu_work * mwork,int type)2194 static void __rvu_mbox_up_handler(struct rvu_work *mwork, int type)
2195 {
2196 	struct rvu *rvu = mwork->rvu;
2197 	struct otx2_mbox_dev *mdev;
2198 	struct mbox_hdr *rsp_hdr;
2199 	struct mbox_msghdr *msg;
2200 	struct mbox_wq_info *mw;
2201 	struct otx2_mbox *mbox;
2202 	int offset, id, devid;
2203 
2204 	switch (type) {
2205 	case TYPE_AFPF:
2206 		mw = &rvu->afpf_wq_info;
2207 		break;
2208 	case TYPE_AFVF:
2209 		mw = &rvu->afvf_wq_info;
2210 		break;
2211 	default:
2212 		return;
2213 	}
2214 
2215 	devid = mwork - mw->mbox_wrk_up;
2216 	mbox = &mw->mbox_up;
2217 	mdev = &mbox->dev[devid];
2218 
2219 	rsp_hdr = mdev->mbase + mbox->rx_start;
2220 	if (mw->mbox_wrk_up[devid].up_num_msgs == 0) {
2221 		dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n");
2222 		return;
2223 	}
2224 
2225 	offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
2226 
2227 	for (id = 0; id < mw->mbox_wrk_up[devid].up_num_msgs; id++) {
2228 		msg = mdev->mbase + offset;
2229 
2230 		if (msg->id >= MBOX_MSG_MAX) {
2231 			dev_err(rvu->dev,
2232 				"Mbox msg with unknown ID 0x%x\n", msg->id);
2233 			goto end;
2234 		}
2235 
2236 		if (msg->sig != OTX2_MBOX_RSP_SIG) {
2237 			dev_err(rvu->dev,
2238 				"Mbox msg with wrong signature %x, ID 0x%x\n",
2239 				msg->sig, msg->id);
2240 			goto end;
2241 		}
2242 
2243 		switch (msg->id) {
2244 		case MBOX_MSG_CGX_LINK_EVENT:
2245 			break;
2246 		default:
2247 			if (msg->rc)
2248 				dev_err(rvu->dev,
2249 					"Mbox msg response has err %d, ID 0x%x\n",
2250 					msg->rc, msg->id);
2251 			break;
2252 		}
2253 end:
2254 		offset = mbox->rx_start + msg->next_msgoff;
2255 		mdev->msgs_acked++;
2256 	}
2257 	mw->mbox_wrk_up[devid].up_num_msgs = 0;
2258 
2259 	otx2_mbox_reset(mbox, devid);
2260 }
2261 
rvu_afpf_mbox_up_handler(struct work_struct * work)2262 static inline void rvu_afpf_mbox_up_handler(struct work_struct *work)
2263 {
2264 	struct rvu_work *mwork = container_of(work, struct rvu_work, work);
2265 
2266 	__rvu_mbox_up_handler(mwork, TYPE_AFPF);
2267 }
2268 
rvu_afvf_mbox_up_handler(struct work_struct * work)2269 static inline void rvu_afvf_mbox_up_handler(struct work_struct *work)
2270 {
2271 	struct rvu_work *mwork = container_of(work, struct rvu_work, work);
2272 
2273 	__rvu_mbox_up_handler(mwork, TYPE_AFVF);
2274 }
2275 
rvu_get_mbox_regions(struct rvu * rvu,void ** mbox_addr,int num,int type)2276 static int rvu_get_mbox_regions(struct rvu *rvu, void **mbox_addr,
2277 				int num, int type)
2278 {
2279 	struct rvu_hwinfo *hw = rvu->hw;
2280 	int region;
2281 	u64 bar4;
2282 
2283 	/* For cn10k platform VF mailbox regions of a PF follows after the
2284 	 * PF <-> AF mailbox region. Whereas for Octeontx2 it is read from
2285 	 * RVU_PF_VF_BAR4_ADDR register.
2286 	 */
2287 	if (type == TYPE_AFVF) {
2288 		for (region = 0; region < num; region++) {
2289 			if (hw->cap.per_pf_mbox_regs) {
2290 				bar4 = rvu_read64(rvu, BLKADDR_RVUM,
2291 						  RVU_AF_PFX_BAR4_ADDR(0)) +
2292 						  MBOX_SIZE;
2293 				bar4 += region * MBOX_SIZE;
2294 			} else {
2295 				bar4 = rvupf_read64(rvu, RVU_PF_VF_BAR4_ADDR);
2296 				bar4 += region * MBOX_SIZE;
2297 			}
2298 			mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE);
2299 			if (!mbox_addr[region])
2300 				goto error;
2301 		}
2302 		return 0;
2303 	}
2304 
2305 	/* For cn10k platform AF <-> PF mailbox region of a PF is read from per
2306 	 * PF registers. Whereas for Octeontx2 it is read from
2307 	 * RVU_AF_PF_BAR4_ADDR register.
2308 	 */
2309 	for (region = 0; region < num; region++) {
2310 		if (hw->cap.per_pf_mbox_regs) {
2311 			bar4 = rvu_read64(rvu, BLKADDR_RVUM,
2312 					  RVU_AF_PFX_BAR4_ADDR(region));
2313 		} else {
2314 			bar4 = rvu_read64(rvu, BLKADDR_RVUM,
2315 					  RVU_AF_PF_BAR4_ADDR);
2316 			bar4 += region * MBOX_SIZE;
2317 		}
2318 		mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE);
2319 		if (!mbox_addr[region])
2320 			goto error;
2321 	}
2322 	return 0;
2323 
2324 error:
2325 	while (region--)
2326 		iounmap((void __iomem *)mbox_addr[region]);
2327 	return -ENOMEM;
2328 }
2329 
rvu_mbox_init(struct rvu * rvu,struct mbox_wq_info * mw,int type,int num,void (mbox_handler)(struct work_struct *),void (mbox_up_handler)(struct work_struct *))2330 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw,
2331 			 int type, int num,
2332 			 void (mbox_handler)(struct work_struct *),
2333 			 void (mbox_up_handler)(struct work_struct *))
2334 {
2335 	int err = -EINVAL, i, dir, dir_up;
2336 	void __iomem *reg_base;
2337 	struct rvu_work *mwork;
2338 	void **mbox_regions;
2339 	const char *name;
2340 
2341 	mbox_regions = kcalloc(num, sizeof(void *), GFP_KERNEL);
2342 	if (!mbox_regions)
2343 		return -ENOMEM;
2344 
2345 	switch (type) {
2346 	case TYPE_AFPF:
2347 		name = "rvu_afpf_mailbox";
2348 		dir = MBOX_DIR_AFPF;
2349 		dir_up = MBOX_DIR_AFPF_UP;
2350 		reg_base = rvu->afreg_base;
2351 		err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFPF);
2352 		if (err)
2353 			goto free_regions;
2354 		break;
2355 	case TYPE_AFVF:
2356 		name = "rvu_afvf_mailbox";
2357 		dir = MBOX_DIR_PFVF;
2358 		dir_up = MBOX_DIR_PFVF_UP;
2359 		reg_base = rvu->pfreg_base;
2360 		err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFVF);
2361 		if (err)
2362 			goto free_regions;
2363 		break;
2364 	default:
2365 		goto free_regions;
2366 	}
2367 
2368 	mw->mbox_wq = alloc_workqueue(name,
2369 				      WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM,
2370 				      num);
2371 	if (!mw->mbox_wq) {
2372 		err = -ENOMEM;
2373 		goto unmap_regions;
2374 	}
2375 
2376 	mw->mbox_wrk = devm_kcalloc(rvu->dev, num,
2377 				    sizeof(struct rvu_work), GFP_KERNEL);
2378 	if (!mw->mbox_wrk) {
2379 		err = -ENOMEM;
2380 		goto exit;
2381 	}
2382 
2383 	mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num,
2384 				       sizeof(struct rvu_work), GFP_KERNEL);
2385 	if (!mw->mbox_wrk_up) {
2386 		err = -ENOMEM;
2387 		goto exit;
2388 	}
2389 
2390 	err = otx2_mbox_regions_init(&mw->mbox, mbox_regions, rvu->pdev,
2391 				     reg_base, dir, num);
2392 	if (err)
2393 		goto exit;
2394 
2395 	err = otx2_mbox_regions_init(&mw->mbox_up, mbox_regions, rvu->pdev,
2396 				     reg_base, dir_up, num);
2397 	if (err)
2398 		goto exit;
2399 
2400 	for (i = 0; i < num; i++) {
2401 		mwork = &mw->mbox_wrk[i];
2402 		mwork->rvu = rvu;
2403 		INIT_WORK(&mwork->work, mbox_handler);
2404 
2405 		mwork = &mw->mbox_wrk_up[i];
2406 		mwork->rvu = rvu;
2407 		INIT_WORK(&mwork->work, mbox_up_handler);
2408 	}
2409 	kfree(mbox_regions);
2410 	return 0;
2411 
2412 exit:
2413 	destroy_workqueue(mw->mbox_wq);
2414 unmap_regions:
2415 	while (num--)
2416 		iounmap((void __iomem *)mbox_regions[num]);
2417 free_regions:
2418 	kfree(mbox_regions);
2419 	return err;
2420 }
2421 
rvu_mbox_destroy(struct mbox_wq_info * mw)2422 static void rvu_mbox_destroy(struct mbox_wq_info *mw)
2423 {
2424 	struct otx2_mbox *mbox = &mw->mbox;
2425 	struct otx2_mbox_dev *mdev;
2426 	int devid;
2427 
2428 	if (mw->mbox_wq) {
2429 		destroy_workqueue(mw->mbox_wq);
2430 		mw->mbox_wq = NULL;
2431 	}
2432 
2433 	for (devid = 0; devid < mbox->ndevs; devid++) {
2434 		mdev = &mbox->dev[devid];
2435 		if (mdev->hwbase)
2436 			iounmap((void __iomem *)mdev->hwbase);
2437 	}
2438 
2439 	otx2_mbox_destroy(&mw->mbox);
2440 	otx2_mbox_destroy(&mw->mbox_up);
2441 }
2442 
rvu_queue_work(struct mbox_wq_info * mw,int first,int mdevs,u64 intr)2443 static void rvu_queue_work(struct mbox_wq_info *mw, int first,
2444 			   int mdevs, u64 intr)
2445 {
2446 	struct otx2_mbox_dev *mdev;
2447 	struct otx2_mbox *mbox;
2448 	struct mbox_hdr *hdr;
2449 	int i;
2450 
2451 	for (i = first; i < mdevs; i++) {
2452 		/* start from 0 */
2453 		if (!(intr & BIT_ULL(i - first)))
2454 			continue;
2455 
2456 		mbox = &mw->mbox;
2457 		mdev = &mbox->dev[i];
2458 		hdr = mdev->mbase + mbox->rx_start;
2459 
2460 		/*The hdr->num_msgs is set to zero immediately in the interrupt
2461 		 * handler to  ensure that it holds a correct value next time
2462 		 * when the interrupt handler is called.
2463 		 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler
2464 		 * pf>mbox.up_num_msgs holds the data for use in
2465 		 * pfaf_mbox_up_handler.
2466 		 */
2467 
2468 		if (hdr->num_msgs) {
2469 			mw->mbox_wrk[i].num_msgs = hdr->num_msgs;
2470 			hdr->num_msgs = 0;
2471 			queue_work(mw->mbox_wq, &mw->mbox_wrk[i].work);
2472 		}
2473 		mbox = &mw->mbox_up;
2474 		mdev = &mbox->dev[i];
2475 		hdr = mdev->mbase + mbox->rx_start;
2476 		if (hdr->num_msgs) {
2477 			mw->mbox_wrk_up[i].up_num_msgs = hdr->num_msgs;
2478 			hdr->num_msgs = 0;
2479 			queue_work(mw->mbox_wq, &mw->mbox_wrk_up[i].work);
2480 		}
2481 	}
2482 }
2483 
rvu_mbox_intr_handler(int irq,void * rvu_irq)2484 static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq)
2485 {
2486 	struct rvu *rvu = (struct rvu *)rvu_irq;
2487 	int vfs = rvu->vfs;
2488 	u64 intr;
2489 
2490 	intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT);
2491 	/* Clear interrupts */
2492 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr);
2493 	if (intr)
2494 		trace_otx2_msg_interrupt(rvu->pdev, "PF(s) to AF", intr);
2495 
2496 	/* Sync with mbox memory region */
2497 	rmb();
2498 
2499 	rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr);
2500 
2501 	/* Handle VF interrupts */
2502 	if (vfs > 64) {
2503 		intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1));
2504 		rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), intr);
2505 
2506 		rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr);
2507 		vfs -= 64;
2508 	}
2509 
2510 	intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(0));
2511 	rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), intr);
2512 	if (intr)
2513 		trace_otx2_msg_interrupt(rvu->pdev, "VF(s) to AF", intr);
2514 
2515 	rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr);
2516 
2517 	return IRQ_HANDLED;
2518 }
2519 
rvu_enable_mbox_intr(struct rvu * rvu)2520 static void rvu_enable_mbox_intr(struct rvu *rvu)
2521 {
2522 	struct rvu_hwinfo *hw = rvu->hw;
2523 
2524 	/* Clear spurious irqs, if any */
2525 	rvu_write64(rvu, BLKADDR_RVUM,
2526 		    RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs));
2527 
2528 	/* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */
2529 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S,
2530 		    INTR_MASK(hw->total_pfs) & ~1ULL);
2531 }
2532 
rvu_blklf_teardown(struct rvu * rvu,u16 pcifunc,u8 blkaddr)2533 static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr)
2534 {
2535 	struct rvu_block *block;
2536 	int slot, lf, num_lfs;
2537 	int err;
2538 
2539 	block = &rvu->hw->block[blkaddr];
2540 	num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc),
2541 					block->addr);
2542 	if (!num_lfs)
2543 		return;
2544 	for (slot = 0; slot < num_lfs; slot++) {
2545 		lf = rvu_get_lf(rvu, block, pcifunc, slot);
2546 		if (lf < 0)
2547 			continue;
2548 
2549 		/* Cleanup LF and reset it */
2550 		if (block->addr == BLKADDR_NIX0 || block->addr == BLKADDR_NIX1)
2551 			rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf);
2552 		else if (block->addr == BLKADDR_NPA)
2553 			rvu_npa_lf_teardown(rvu, pcifunc, lf);
2554 		else if ((block->addr == BLKADDR_CPT0) ||
2555 			 (block->addr == BLKADDR_CPT1))
2556 			rvu_cpt_lf_teardown(rvu, pcifunc, block->addr, lf,
2557 					    slot);
2558 
2559 		err = rvu_lf_reset(rvu, block, lf);
2560 		if (err) {
2561 			dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n",
2562 				block->addr, lf);
2563 		}
2564 	}
2565 }
2566 
__rvu_flr_handler(struct rvu * rvu,u16 pcifunc)2567 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc)
2568 {
2569 	if (rvu_npc_exact_has_match_table(rvu))
2570 		rvu_npc_exact_reset(rvu, pcifunc);
2571 
2572 	mutex_lock(&rvu->flr_lock);
2573 	/* Reset order should reflect inter-block dependencies:
2574 	 * 1. Reset any packet/work sources (NIX, CPT, TIM)
2575 	 * 2. Flush and reset SSO/SSOW
2576 	 * 3. Cleanup pools (NPA)
2577 	 */
2578 	rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX0);
2579 	rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX1);
2580 	rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT0);
2581 	rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT1);
2582 	rvu_blklf_teardown(rvu, pcifunc, BLKADDR_TIM);
2583 	rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSOW);
2584 	rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSO);
2585 	rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NPA);
2586 	rvu_reset_lmt_map_tbl(rvu, pcifunc);
2587 	rvu_detach_rsrcs(rvu, NULL, pcifunc);
2588 	/* In scenarios where PF/VF drivers detach NIXLF without freeing MCAM
2589 	 * entries, check and free the MCAM entries explicitly to avoid leak.
2590 	 * Since LF is detached use LF number as -1.
2591 	 */
2592 	rvu_npc_free_mcam_entries(rvu, pcifunc, -1);
2593 
2594 	mutex_unlock(&rvu->flr_lock);
2595 }
2596 
rvu_afvf_flr_handler(struct rvu * rvu,int vf)2597 static void rvu_afvf_flr_handler(struct rvu *rvu, int vf)
2598 {
2599 	int reg = 0;
2600 
2601 	/* pcifunc = 0(PF0) | (vf + 1) */
2602 	__rvu_flr_handler(rvu, vf + 1);
2603 
2604 	if (vf >= 64) {
2605 		reg = 1;
2606 		vf = vf - 64;
2607 	}
2608 
2609 	/* Signal FLR finish and enable IRQ */
2610 	rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
2611 	rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf));
2612 }
2613 
rvu_flr_handler(struct work_struct * work)2614 static void rvu_flr_handler(struct work_struct *work)
2615 {
2616 	struct rvu_work *flrwork = container_of(work, struct rvu_work, work);
2617 	struct rvu *rvu = flrwork->rvu;
2618 	u16 pcifunc, numvfs, vf;
2619 	u64 cfg;
2620 	int pf;
2621 
2622 	pf = flrwork - rvu->flr_wrk;
2623 	if (pf >= rvu->hw->total_pfs) {
2624 		rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs);
2625 		return;
2626 	}
2627 
2628 	cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
2629 	numvfs = (cfg >> 12) & 0xFF;
2630 	pcifunc  = pf << RVU_PFVF_PF_SHIFT;
2631 
2632 	for (vf = 0; vf < numvfs; vf++)
2633 		__rvu_flr_handler(rvu, (pcifunc | (vf + 1)));
2634 
2635 	__rvu_flr_handler(rvu, pcifunc);
2636 
2637 	/* Signal FLR finish */
2638 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf));
2639 
2640 	/* Enable interrupt */
2641 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S,  BIT_ULL(pf));
2642 }
2643 
rvu_afvf_queue_flr_work(struct rvu * rvu,int start_vf,int numvfs)2644 static void rvu_afvf_queue_flr_work(struct rvu *rvu, int start_vf, int numvfs)
2645 {
2646 	int dev, vf, reg = 0;
2647 	u64 intr;
2648 
2649 	if (start_vf >= 64)
2650 		reg = 1;
2651 
2652 	intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg));
2653 	if (!intr)
2654 		return;
2655 
2656 	for (vf = 0; vf < numvfs; vf++) {
2657 		if (!(intr & BIT_ULL(vf)))
2658 			continue;
2659 		/* Clear and disable the interrupt */
2660 		rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf));
2661 		rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf));
2662 
2663 		dev = vf + start_vf + rvu->hw->total_pfs;
2664 		queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work);
2665 	}
2666 }
2667 
rvu_flr_intr_handler(int irq,void * rvu_irq)2668 static irqreturn_t rvu_flr_intr_handler(int irq, void *rvu_irq)
2669 {
2670 	struct rvu *rvu = (struct rvu *)rvu_irq;
2671 	u64 intr;
2672 	u8  pf;
2673 
2674 	intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT);
2675 	if (!intr)
2676 		goto afvf_flr;
2677 
2678 	for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
2679 		if (intr & (1ULL << pf)) {
2680 			/* clear interrupt */
2681 			rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT,
2682 				    BIT_ULL(pf));
2683 			/* Disable the interrupt */
2684 			rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C,
2685 				    BIT_ULL(pf));
2686 			/* PF is already dead do only AF related operations */
2687 			queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work);
2688 		}
2689 	}
2690 
2691 afvf_flr:
2692 	rvu_afvf_queue_flr_work(rvu, 0, 64);
2693 	if (rvu->vfs > 64)
2694 		rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64);
2695 
2696 	return IRQ_HANDLED;
2697 }
2698 
rvu_me_handle_vfset(struct rvu * rvu,int idx,u64 intr)2699 static void rvu_me_handle_vfset(struct rvu *rvu, int idx, u64 intr)
2700 {
2701 	int vf;
2702 
2703 	/* Nothing to be done here other than clearing the
2704 	 * TRPEND bit.
2705 	 */
2706 	for (vf = 0; vf < 64; vf++) {
2707 		if (intr & (1ULL << vf)) {
2708 			/* clear the trpend due to ME(master enable) */
2709 			rvupf_write64(rvu, RVU_PF_VFTRPENDX(idx), BIT_ULL(vf));
2710 			/* clear interrupt */
2711 			rvupf_write64(rvu, RVU_PF_VFME_INTX(idx), BIT_ULL(vf));
2712 		}
2713 	}
2714 }
2715 
2716 /* Handles ME interrupts from VFs of AF */
rvu_me_vf_intr_handler(int irq,void * rvu_irq)2717 static irqreturn_t rvu_me_vf_intr_handler(int irq, void *rvu_irq)
2718 {
2719 	struct rvu *rvu = (struct rvu *)rvu_irq;
2720 	int vfset;
2721 	u64 intr;
2722 
2723 	intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT);
2724 
2725 	for (vfset = 0; vfset <= 1; vfset++) {
2726 		intr = rvupf_read64(rvu, RVU_PF_VFME_INTX(vfset));
2727 		if (intr)
2728 			rvu_me_handle_vfset(rvu, vfset, intr);
2729 	}
2730 
2731 	return IRQ_HANDLED;
2732 }
2733 
2734 /* Handles ME interrupts from PFs */
rvu_me_pf_intr_handler(int irq,void * rvu_irq)2735 static irqreturn_t rvu_me_pf_intr_handler(int irq, void *rvu_irq)
2736 {
2737 	struct rvu *rvu = (struct rvu *)rvu_irq;
2738 	u64 intr;
2739 	u8  pf;
2740 
2741 	intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT);
2742 
2743 	/* Nothing to be done here other than clearing the
2744 	 * TRPEND bit.
2745 	 */
2746 	for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
2747 		if (intr & (1ULL << pf)) {
2748 			/* clear the trpend due to ME(master enable) */
2749 			rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND,
2750 				    BIT_ULL(pf));
2751 			/* clear interrupt */
2752 			rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT,
2753 				    BIT_ULL(pf));
2754 		}
2755 	}
2756 
2757 	return IRQ_HANDLED;
2758 }
2759 
rvu_unregister_interrupts(struct rvu * rvu)2760 static void rvu_unregister_interrupts(struct rvu *rvu)
2761 {
2762 	int irq;
2763 
2764 	rvu_cpt_unregister_interrupts(rvu);
2765 
2766 	/* Disable the Mbox interrupt */
2767 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C,
2768 		    INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2769 
2770 	/* Disable the PF FLR interrupt */
2771 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C,
2772 		    INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2773 
2774 	/* Disable the PF ME interrupt */
2775 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1C,
2776 		    INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2777 
2778 	for (irq = 0; irq < rvu->num_vec; irq++) {
2779 		if (rvu->irq_allocated[irq]) {
2780 			free_irq(pci_irq_vector(rvu->pdev, irq), rvu);
2781 			rvu->irq_allocated[irq] = false;
2782 		}
2783 	}
2784 
2785 	pci_free_irq_vectors(rvu->pdev);
2786 	rvu->num_vec = 0;
2787 }
2788 
rvu_afvf_msix_vectors_num_ok(struct rvu * rvu)2789 static int rvu_afvf_msix_vectors_num_ok(struct rvu *rvu)
2790 {
2791 	struct rvu_pfvf *pfvf = &rvu->pf[0];
2792 	int offset;
2793 
2794 	pfvf = &rvu->pf[0];
2795 	offset = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff;
2796 
2797 	/* Make sure there are enough MSIX vectors configured so that
2798 	 * VF interrupts can be handled. Offset equal to zero means
2799 	 * that PF vectors are not configured and overlapping AF vectors.
2800 	 */
2801 	return (pfvf->msix.max >= RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT) &&
2802 	       offset;
2803 }
2804 
rvu_register_interrupts(struct rvu * rvu)2805 static int rvu_register_interrupts(struct rvu *rvu)
2806 {
2807 	int ret, offset, pf_vec_start;
2808 
2809 	rvu->num_vec = pci_msix_vec_count(rvu->pdev);
2810 
2811 	rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec,
2812 					   NAME_SIZE, GFP_KERNEL);
2813 	if (!rvu->irq_name)
2814 		return -ENOMEM;
2815 
2816 	rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec,
2817 					  sizeof(bool), GFP_KERNEL);
2818 	if (!rvu->irq_allocated)
2819 		return -ENOMEM;
2820 
2821 	/* Enable MSI-X */
2822 	ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec,
2823 				    rvu->num_vec, PCI_IRQ_MSIX);
2824 	if (ret < 0) {
2825 		dev_err(rvu->dev,
2826 			"RVUAF: Request for %d msix vectors failed, ret %d\n",
2827 			rvu->num_vec, ret);
2828 		return ret;
2829 	}
2830 
2831 	/* Register mailbox interrupt handler */
2832 	sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox");
2833 	ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX),
2834 			  rvu_mbox_intr_handler, 0,
2835 			  &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu);
2836 	if (ret) {
2837 		dev_err(rvu->dev,
2838 			"RVUAF: IRQ registration failed for mbox irq\n");
2839 		goto fail;
2840 	}
2841 
2842 	rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true;
2843 
2844 	/* Enable mailbox interrupts from all PFs */
2845 	rvu_enable_mbox_intr(rvu);
2846 
2847 	/* Register FLR interrupt handler */
2848 	sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE],
2849 		"RVUAF FLR");
2850 	ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR),
2851 			  rvu_flr_intr_handler, 0,
2852 			  &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE],
2853 			  rvu);
2854 	if (ret) {
2855 		dev_err(rvu->dev,
2856 			"RVUAF: IRQ registration failed for FLR\n");
2857 		goto fail;
2858 	}
2859 	rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true;
2860 
2861 	/* Enable FLR interrupt for all PFs*/
2862 	rvu_write64(rvu, BLKADDR_RVUM,
2863 		    RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs));
2864 
2865 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S,
2866 		    INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2867 
2868 	/* Register ME interrupt handler */
2869 	sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE],
2870 		"RVUAF ME");
2871 	ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME),
2872 			  rvu_me_pf_intr_handler, 0,
2873 			  &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE],
2874 			  rvu);
2875 	if (ret) {
2876 		dev_err(rvu->dev,
2877 			"RVUAF: IRQ registration failed for ME\n");
2878 	}
2879 	rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true;
2880 
2881 	/* Clear TRPEND bit for all PF */
2882 	rvu_write64(rvu, BLKADDR_RVUM,
2883 		    RVU_AF_PFTRPEND, INTR_MASK(rvu->hw->total_pfs));
2884 	/* Enable ME interrupt for all PFs*/
2885 	rvu_write64(rvu, BLKADDR_RVUM,
2886 		    RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs));
2887 
2888 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1S,
2889 		    INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2890 
2891 	if (!rvu_afvf_msix_vectors_num_ok(rvu))
2892 		return 0;
2893 
2894 	/* Get PF MSIX vectors offset. */
2895 	pf_vec_start = rvu_read64(rvu, BLKADDR_RVUM,
2896 				  RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff;
2897 
2898 	/* Register MBOX0 interrupt. */
2899 	offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX0;
2900 	sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0");
2901 	ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2902 			  rvu_mbox_intr_handler, 0,
2903 			  &rvu->irq_name[offset * NAME_SIZE],
2904 			  rvu);
2905 	if (ret)
2906 		dev_err(rvu->dev,
2907 			"RVUAF: IRQ registration failed for Mbox0\n");
2908 
2909 	rvu->irq_allocated[offset] = true;
2910 
2911 	/* Register MBOX1 interrupt. MBOX1 IRQ number follows MBOX0 so
2912 	 * simply increment current offset by 1.
2913 	 */
2914 	offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX1;
2915 	sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1");
2916 	ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2917 			  rvu_mbox_intr_handler, 0,
2918 			  &rvu->irq_name[offset * NAME_SIZE],
2919 			  rvu);
2920 	if (ret)
2921 		dev_err(rvu->dev,
2922 			"RVUAF: IRQ registration failed for Mbox1\n");
2923 
2924 	rvu->irq_allocated[offset] = true;
2925 
2926 	/* Register FLR interrupt handler for AF's VFs */
2927 	offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR0;
2928 	sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0");
2929 	ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2930 			  rvu_flr_intr_handler, 0,
2931 			  &rvu->irq_name[offset * NAME_SIZE], rvu);
2932 	if (ret) {
2933 		dev_err(rvu->dev,
2934 			"RVUAF: IRQ registration failed for RVUAFVF FLR0\n");
2935 		goto fail;
2936 	}
2937 	rvu->irq_allocated[offset] = true;
2938 
2939 	offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR1;
2940 	sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1");
2941 	ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2942 			  rvu_flr_intr_handler, 0,
2943 			  &rvu->irq_name[offset * NAME_SIZE], rvu);
2944 	if (ret) {
2945 		dev_err(rvu->dev,
2946 			"RVUAF: IRQ registration failed for RVUAFVF FLR1\n");
2947 		goto fail;
2948 	}
2949 	rvu->irq_allocated[offset] = true;
2950 
2951 	/* Register ME interrupt handler for AF's VFs */
2952 	offset = pf_vec_start + RVU_PF_INT_VEC_VFME0;
2953 	sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0");
2954 	ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2955 			  rvu_me_vf_intr_handler, 0,
2956 			  &rvu->irq_name[offset * NAME_SIZE], rvu);
2957 	if (ret) {
2958 		dev_err(rvu->dev,
2959 			"RVUAF: IRQ registration failed for RVUAFVF ME0\n");
2960 		goto fail;
2961 	}
2962 	rvu->irq_allocated[offset] = true;
2963 
2964 	offset = pf_vec_start + RVU_PF_INT_VEC_VFME1;
2965 	sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1");
2966 	ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2967 			  rvu_me_vf_intr_handler, 0,
2968 			  &rvu->irq_name[offset * NAME_SIZE], rvu);
2969 	if (ret) {
2970 		dev_err(rvu->dev,
2971 			"RVUAF: IRQ registration failed for RVUAFVF ME1\n");
2972 		goto fail;
2973 	}
2974 	rvu->irq_allocated[offset] = true;
2975 
2976 	ret = rvu_cpt_register_interrupts(rvu);
2977 	if (ret)
2978 		goto fail;
2979 
2980 	return 0;
2981 
2982 fail:
2983 	rvu_unregister_interrupts(rvu);
2984 	return ret;
2985 }
2986 
rvu_flr_wq_destroy(struct rvu * rvu)2987 static void rvu_flr_wq_destroy(struct rvu *rvu)
2988 {
2989 	if (rvu->flr_wq) {
2990 		destroy_workqueue(rvu->flr_wq);
2991 		rvu->flr_wq = NULL;
2992 	}
2993 }
2994 
rvu_flr_init(struct rvu * rvu)2995 static int rvu_flr_init(struct rvu *rvu)
2996 {
2997 	int dev, num_devs;
2998 	u64 cfg;
2999 	int pf;
3000 
3001 	/* Enable FLR for all PFs*/
3002 	for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
3003 		cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
3004 		rvu_write64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf),
3005 			    cfg | BIT_ULL(22));
3006 	}
3007 
3008 	rvu->flr_wq = alloc_workqueue("rvu_afpf_flr",
3009 				      WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM,
3010 				       1);
3011 	if (!rvu->flr_wq)
3012 		return -ENOMEM;
3013 
3014 	num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev);
3015 	rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs,
3016 				    sizeof(struct rvu_work), GFP_KERNEL);
3017 	if (!rvu->flr_wrk) {
3018 		destroy_workqueue(rvu->flr_wq);
3019 		return -ENOMEM;
3020 	}
3021 
3022 	for (dev = 0; dev < num_devs; dev++) {
3023 		rvu->flr_wrk[dev].rvu = rvu;
3024 		INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler);
3025 	}
3026 
3027 	mutex_init(&rvu->flr_lock);
3028 
3029 	return 0;
3030 }
3031 
rvu_disable_afvf_intr(struct rvu * rvu)3032 static void rvu_disable_afvf_intr(struct rvu *rvu)
3033 {
3034 	int vfs = rvu->vfs;
3035 
3036 	rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), INTR_MASK(vfs));
3037 	rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs));
3038 	rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs));
3039 	if (vfs <= 64)
3040 		return;
3041 
3042 	rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1),
3043 		      INTR_MASK(vfs - 64));
3044 	rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
3045 	rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
3046 }
3047 
rvu_enable_afvf_intr(struct rvu * rvu)3048 static void rvu_enable_afvf_intr(struct rvu *rvu)
3049 {
3050 	int vfs = rvu->vfs;
3051 
3052 	/* Clear any pending interrupts and enable AF VF interrupts for
3053 	 * the first 64 VFs.
3054 	 */
3055 	/* Mbox */
3056 	rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), INTR_MASK(vfs));
3057 	rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(vfs));
3058 
3059 	/* FLR */
3060 	rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs));
3061 	rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs));
3062 	rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(vfs));
3063 
3064 	/* Same for remaining VFs, if any. */
3065 	if (vfs <= 64)
3066 		return;
3067 
3068 	rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64));
3069 	rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1),
3070 		      INTR_MASK(vfs - 64));
3071 
3072 	rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64));
3073 	rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64));
3074 	rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64));
3075 }
3076 
rvu_get_num_lbk_chans(void)3077 int rvu_get_num_lbk_chans(void)
3078 {
3079 	struct pci_dev *pdev;
3080 	void __iomem *base;
3081 	int ret = -EIO;
3082 
3083 	pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_LBK,
3084 			      NULL);
3085 	if (!pdev)
3086 		goto err;
3087 
3088 	base = pci_ioremap_bar(pdev, 0);
3089 	if (!base)
3090 		goto err_put;
3091 
3092 	/* Read number of available LBK channels from LBK(0)_CONST register. */
3093 	ret = (readq(base + 0x10) >> 32) & 0xffff;
3094 	iounmap(base);
3095 err_put:
3096 	pci_dev_put(pdev);
3097 err:
3098 	return ret;
3099 }
3100 
rvu_enable_sriov(struct rvu * rvu)3101 static int rvu_enable_sriov(struct rvu *rvu)
3102 {
3103 	struct pci_dev *pdev = rvu->pdev;
3104 	int err, chans, vfs;
3105 
3106 	if (!rvu_afvf_msix_vectors_num_ok(rvu)) {
3107 		dev_warn(&pdev->dev,
3108 			 "Skipping SRIOV enablement since not enough IRQs are available\n");
3109 		return 0;
3110 	}
3111 
3112 	chans = rvu_get_num_lbk_chans();
3113 	if (chans < 0)
3114 		return chans;
3115 
3116 	vfs = pci_sriov_get_totalvfs(pdev);
3117 
3118 	/* Limit VFs in case we have more VFs than LBK channels available. */
3119 	if (vfs > chans)
3120 		vfs = chans;
3121 
3122 	if (!vfs)
3123 		return 0;
3124 
3125 	/* LBK channel number 63 is used for switching packets between
3126 	 * CGX mapped VFs. Hence limit LBK pairs till 62 only.
3127 	 */
3128 	if (vfs > 62)
3129 		vfs = 62;
3130 
3131 	/* Save VFs number for reference in VF interrupts handlers.
3132 	 * Since interrupts might start arriving during SRIOV enablement
3133 	 * ordinary API cannot be used to get number of enabled VFs.
3134 	 */
3135 	rvu->vfs = vfs;
3136 
3137 	err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs,
3138 			    rvu_afvf_mbox_handler, rvu_afvf_mbox_up_handler);
3139 	if (err)
3140 		return err;
3141 
3142 	rvu_enable_afvf_intr(rvu);
3143 	/* Make sure IRQs are enabled before SRIOV. */
3144 	mb();
3145 
3146 	err = pci_enable_sriov(pdev, vfs);
3147 	if (err) {
3148 		rvu_disable_afvf_intr(rvu);
3149 		rvu_mbox_destroy(&rvu->afvf_wq_info);
3150 		return err;
3151 	}
3152 
3153 	return 0;
3154 }
3155 
rvu_disable_sriov(struct rvu * rvu)3156 static void rvu_disable_sriov(struct rvu *rvu)
3157 {
3158 	rvu_disable_afvf_intr(rvu);
3159 	rvu_mbox_destroy(&rvu->afvf_wq_info);
3160 	pci_disable_sriov(rvu->pdev);
3161 }
3162 
rvu_update_module_params(struct rvu * rvu)3163 static void rvu_update_module_params(struct rvu *rvu)
3164 {
3165 	const char *default_pfl_name = "default";
3166 
3167 	strscpy(rvu->mkex_pfl_name,
3168 		mkex_profile ? mkex_profile : default_pfl_name, MKEX_NAME_LEN);
3169 	strscpy(rvu->kpu_pfl_name,
3170 		kpu_profile ? kpu_profile : default_pfl_name, KPU_NAME_LEN);
3171 }
3172 
rvu_probe(struct pci_dev * pdev,const struct pci_device_id * id)3173 static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3174 {
3175 	struct device *dev = &pdev->dev;
3176 	struct rvu *rvu;
3177 	int    err;
3178 
3179 	rvu = devm_kzalloc(dev, sizeof(*rvu), GFP_KERNEL);
3180 	if (!rvu)
3181 		return -ENOMEM;
3182 
3183 	rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL);
3184 	if (!rvu->hw) {
3185 		devm_kfree(dev, rvu);
3186 		return -ENOMEM;
3187 	}
3188 
3189 	pci_set_drvdata(pdev, rvu);
3190 	rvu->pdev = pdev;
3191 	rvu->dev = &pdev->dev;
3192 
3193 	err = pci_enable_device(pdev);
3194 	if (err) {
3195 		dev_err(dev, "Failed to enable PCI device\n");
3196 		goto err_freemem;
3197 	}
3198 
3199 	err = pci_request_regions(pdev, DRV_NAME);
3200 	if (err) {
3201 		dev_err(dev, "PCI request regions failed 0x%x\n", err);
3202 		goto err_disable_device;
3203 	}
3204 
3205 	err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
3206 	if (err) {
3207 		dev_err(dev, "DMA mask config failed, abort\n");
3208 		goto err_release_regions;
3209 	}
3210 
3211 	pci_set_master(pdev);
3212 
3213 	rvu->ptp = ptp_get();
3214 	if (IS_ERR(rvu->ptp)) {
3215 		err = PTR_ERR(rvu->ptp);
3216 		if (err == -EPROBE_DEFER)
3217 			goto err_release_regions;
3218 		rvu->ptp = NULL;
3219 	}
3220 
3221 	/* Map Admin function CSRs */
3222 	rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0);
3223 	rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0);
3224 	if (!rvu->afreg_base || !rvu->pfreg_base) {
3225 		dev_err(dev, "Unable to map admin function CSRs, aborting\n");
3226 		err = -ENOMEM;
3227 		goto err_put_ptp;
3228 	}
3229 
3230 	/* Store module params in rvu structure */
3231 	rvu_update_module_params(rvu);
3232 
3233 	/* Check which blocks the HW supports */
3234 	rvu_check_block_implemented(rvu);
3235 
3236 	rvu_reset_all_blocks(rvu);
3237 
3238 	rvu_setup_hw_capabilities(rvu);
3239 
3240 	err = rvu_setup_hw_resources(rvu);
3241 	if (err)
3242 		goto err_put_ptp;
3243 
3244 	/* Init mailbox btw AF and PFs */
3245 	err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF,
3246 			    rvu->hw->total_pfs, rvu_afpf_mbox_handler,
3247 			    rvu_afpf_mbox_up_handler);
3248 	if (err) {
3249 		dev_err(dev, "%s: Failed to initialize mbox\n", __func__);
3250 		goto err_hwsetup;
3251 	}
3252 
3253 	err = rvu_flr_init(rvu);
3254 	if (err) {
3255 		dev_err(dev, "%s: Failed to initialize flr\n", __func__);
3256 		goto err_mbox;
3257 	}
3258 
3259 	err = rvu_register_interrupts(rvu);
3260 	if (err) {
3261 		dev_err(dev, "%s: Failed to register interrupts\n", __func__);
3262 		goto err_flr;
3263 	}
3264 
3265 	err = rvu_register_dl(rvu);
3266 	if (err) {
3267 		dev_err(dev, "%s: Failed to register devlink\n", __func__);
3268 		goto err_irq;
3269 	}
3270 
3271 	rvu_setup_rvum_blk_revid(rvu);
3272 
3273 	/* Enable AF's VFs (if any) */
3274 	err = rvu_enable_sriov(rvu);
3275 	if (err) {
3276 		dev_err(dev, "%s: Failed to enable sriov\n", __func__);
3277 		goto err_dl;
3278 	}
3279 
3280 	/* Initialize debugfs */
3281 	rvu_dbg_init(rvu);
3282 
3283 	mutex_init(&rvu->rswitch.switch_lock);
3284 
3285 	if (rvu->fwdata)
3286 		ptp_start(rvu->ptp, rvu->fwdata->sclk, rvu->fwdata->ptp_ext_clk_rate,
3287 			  rvu->fwdata->ptp_ext_tstamp);
3288 
3289 	return 0;
3290 err_dl:
3291 	rvu_unregister_dl(rvu);
3292 err_irq:
3293 	rvu_unregister_interrupts(rvu);
3294 err_flr:
3295 	rvu_flr_wq_destroy(rvu);
3296 err_mbox:
3297 	rvu_mbox_destroy(&rvu->afpf_wq_info);
3298 err_hwsetup:
3299 	rvu_cgx_exit(rvu);
3300 	rvu_fwdata_exit(rvu);
3301 	rvu_mcs_exit(rvu);
3302 	rvu_reset_all_blocks(rvu);
3303 	rvu_free_hw_resources(rvu);
3304 	rvu_clear_rvum_blk_revid(rvu);
3305 err_put_ptp:
3306 	ptp_put(rvu->ptp);
3307 err_release_regions:
3308 	pci_release_regions(pdev);
3309 err_disable_device:
3310 	pci_disable_device(pdev);
3311 err_freemem:
3312 	pci_set_drvdata(pdev, NULL);
3313 	devm_kfree(&pdev->dev, rvu->hw);
3314 	devm_kfree(dev, rvu);
3315 	return err;
3316 }
3317 
rvu_remove(struct pci_dev * pdev)3318 static void rvu_remove(struct pci_dev *pdev)
3319 {
3320 	struct rvu *rvu = pci_get_drvdata(pdev);
3321 
3322 	rvu_dbg_exit(rvu);
3323 	rvu_unregister_dl(rvu);
3324 	rvu_unregister_interrupts(rvu);
3325 	rvu_flr_wq_destroy(rvu);
3326 	rvu_cgx_exit(rvu);
3327 	rvu_fwdata_exit(rvu);
3328 	rvu_mcs_exit(rvu);
3329 	rvu_mbox_destroy(&rvu->afpf_wq_info);
3330 	rvu_disable_sriov(rvu);
3331 	rvu_reset_all_blocks(rvu);
3332 	rvu_free_hw_resources(rvu);
3333 	rvu_clear_rvum_blk_revid(rvu);
3334 	ptp_put(rvu->ptp);
3335 	pci_release_regions(pdev);
3336 	pci_disable_device(pdev);
3337 	pci_set_drvdata(pdev, NULL);
3338 
3339 	devm_kfree(&pdev->dev, rvu->hw);
3340 	devm_kfree(&pdev->dev, rvu);
3341 }
3342 
3343 static struct pci_driver rvu_driver = {
3344 	.name = DRV_NAME,
3345 	.id_table = rvu_id_table,
3346 	.probe = rvu_probe,
3347 	.remove = rvu_remove,
3348 };
3349 
rvu_init_module(void)3350 static int __init rvu_init_module(void)
3351 {
3352 	int err;
3353 
3354 	pr_info("%s: %s\n", DRV_NAME, DRV_STRING);
3355 
3356 	err = pci_register_driver(&cgx_driver);
3357 	if (err < 0)
3358 		return err;
3359 
3360 	err = pci_register_driver(&ptp_driver);
3361 	if (err < 0)
3362 		goto ptp_err;
3363 
3364 	err = pci_register_driver(&mcs_driver);
3365 	if (err < 0)
3366 		goto mcs_err;
3367 
3368 	err =  pci_register_driver(&rvu_driver);
3369 	if (err < 0)
3370 		goto rvu_err;
3371 
3372 	return 0;
3373 rvu_err:
3374 	pci_unregister_driver(&mcs_driver);
3375 mcs_err:
3376 	pci_unregister_driver(&ptp_driver);
3377 ptp_err:
3378 	pci_unregister_driver(&cgx_driver);
3379 
3380 	return err;
3381 }
3382 
rvu_cleanup_module(void)3383 static void __exit rvu_cleanup_module(void)
3384 {
3385 	pci_unregister_driver(&rvu_driver);
3386 	pci_unregister_driver(&mcs_driver);
3387 	pci_unregister_driver(&ptp_driver);
3388 	pci_unregister_driver(&cgx_driver);
3389 }
3390 
3391 module_init(rvu_init_module);
3392 module_exit(rvu_cleanup_module);
3393