1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * gpio-reg: single register individually fixed-direction GPIOs
4 *
5 * Copyright (C) 2016 Russell King
6 */
7 #include <linux/gpio/driver.h>
8 #include <linux/gpio/gpio-reg.h>
9 #include <linux/io.h>
10 #include <linux/slab.h>
11 #include <linux/spinlock.h>
12
13 struct gpio_reg {
14 struct gpio_chip gc;
15 spinlock_t lock;
16 u32 direction;
17 u32 out;
18 void __iomem *reg;
19 struct irq_domain *irqdomain;
20 const int *irqs;
21 };
22
23 #define to_gpio_reg(x) container_of(x, struct gpio_reg, gc)
24
gpio_reg_get_direction(struct gpio_chip * gc,unsigned offset)25 static int gpio_reg_get_direction(struct gpio_chip *gc, unsigned offset)
26 {
27 struct gpio_reg *r = to_gpio_reg(gc);
28
29 return r->direction & BIT(offset) ? GPIO_LINE_DIRECTION_IN :
30 GPIO_LINE_DIRECTION_OUT;
31 }
32
gpio_reg_direction_output(struct gpio_chip * gc,unsigned offset,int value)33 static int gpio_reg_direction_output(struct gpio_chip *gc, unsigned offset,
34 int value)
35 {
36 struct gpio_reg *r = to_gpio_reg(gc);
37
38 if (r->direction & BIT(offset))
39 return -ENOTSUPP;
40
41 gc->set(gc, offset, value);
42 return 0;
43 }
44
gpio_reg_direction_input(struct gpio_chip * gc,unsigned offset)45 static int gpio_reg_direction_input(struct gpio_chip *gc, unsigned offset)
46 {
47 struct gpio_reg *r = to_gpio_reg(gc);
48
49 return r->direction & BIT(offset) ? 0 : -ENOTSUPP;
50 }
51
gpio_reg_set(struct gpio_chip * gc,unsigned offset,int value)52 static void gpio_reg_set(struct gpio_chip *gc, unsigned offset, int value)
53 {
54 struct gpio_reg *r = to_gpio_reg(gc);
55 unsigned long flags;
56 u32 val, mask = BIT(offset);
57
58 spin_lock_irqsave(&r->lock, flags);
59 val = r->out;
60 if (value)
61 val |= mask;
62 else
63 val &= ~mask;
64 r->out = val;
65 writel_relaxed(val, r->reg);
66 spin_unlock_irqrestore(&r->lock, flags);
67 }
68
gpio_reg_get(struct gpio_chip * gc,unsigned offset)69 static int gpio_reg_get(struct gpio_chip *gc, unsigned offset)
70 {
71 struct gpio_reg *r = to_gpio_reg(gc);
72 u32 val, mask = BIT(offset);
73
74 if (r->direction & mask) {
75 /*
76 * double-read the value, some registers latch after the
77 * first read.
78 */
79 readl_relaxed(r->reg);
80 val = readl_relaxed(r->reg);
81 } else {
82 val = r->out;
83 }
84 return !!(val & mask);
85 }
86
gpio_reg_set_multiple(struct gpio_chip * gc,unsigned long * mask,unsigned long * bits)87 static void gpio_reg_set_multiple(struct gpio_chip *gc, unsigned long *mask,
88 unsigned long *bits)
89 {
90 struct gpio_reg *r = to_gpio_reg(gc);
91 unsigned long flags;
92
93 spin_lock_irqsave(&r->lock, flags);
94 r->out = (r->out & ~*mask) | (*bits & *mask);
95 writel_relaxed(r->out, r->reg);
96 spin_unlock_irqrestore(&r->lock, flags);
97 }
98
gpio_reg_to_irq(struct gpio_chip * gc,unsigned offset)99 static int gpio_reg_to_irq(struct gpio_chip *gc, unsigned offset)
100 {
101 struct gpio_reg *r = to_gpio_reg(gc);
102 int irq = r->irqs[offset];
103
104 if (irq >= 0 && r->irqdomain)
105 irq = irq_find_mapping(r->irqdomain, irq);
106
107 return irq;
108 }
109
110 /**
111 * gpio_reg_init - add a fixed in/out register as gpio
112 * @dev: optional struct device associated with this register
113 * @base: start gpio number, or -1 to allocate
114 * @num: number of GPIOs, maximum 32
115 * @label: GPIO chip label
116 * @direction: bitmask of fixed direction, one per GPIO signal, 1 = in
117 * @def_out: initial GPIO output value
118 * @names: array of %num strings describing each GPIO signal or %NULL
119 * @irqdom: irq domain or %NULL
120 * @irqs: array of %num ints describing the interrupt mapping for each
121 * GPIO signal, or %NULL. If @irqdom is %NULL, then this
122 * describes the Linux interrupt number, otherwise it describes
123 * the hardware interrupt number in the specified irq domain.
124 *
125 * Add a single-register GPIO device containing up to 32 GPIO signals,
126 * where each GPIO has a fixed input or output configuration. Only
127 * input GPIOs are assumed to be readable from the register, and only
128 * then after a double-read. Output values are assumed not to be
129 * readable.
130 */
gpio_reg_init(struct device * dev,void __iomem * reg,int base,int num,const char * label,u32 direction,u32 def_out,const char * const * names,struct irq_domain * irqdom,const int * irqs)131 struct gpio_chip *gpio_reg_init(struct device *dev, void __iomem *reg,
132 int base, int num, const char *label, u32 direction, u32 def_out,
133 const char *const *names, struct irq_domain *irqdom, const int *irqs)
134 {
135 struct gpio_reg *r;
136 int ret;
137
138 if (dev)
139 r = devm_kzalloc(dev, sizeof(*r), GFP_KERNEL);
140 else
141 r = kzalloc(sizeof(*r), GFP_KERNEL);
142
143 if (!r)
144 return ERR_PTR(-ENOMEM);
145
146 spin_lock_init(&r->lock);
147
148 r->gc.label = label;
149 r->gc.get_direction = gpio_reg_get_direction;
150 r->gc.direction_input = gpio_reg_direction_input;
151 r->gc.direction_output = gpio_reg_direction_output;
152 r->gc.set = gpio_reg_set;
153 r->gc.get = gpio_reg_get;
154 r->gc.set_multiple = gpio_reg_set_multiple;
155 if (irqs)
156 r->gc.to_irq = gpio_reg_to_irq;
157 r->gc.base = base;
158 r->gc.ngpio = num;
159 r->gc.names = names;
160 r->direction = direction;
161 r->out = def_out;
162 r->reg = reg;
163 r->irqs = irqs;
164
165 if (dev)
166 ret = devm_gpiochip_add_data(dev, &r->gc, r);
167 else
168 ret = gpiochip_add_data(&r->gc, r);
169
170 return ret ? ERR_PTR(ret) : &r->gc;
171 }
172
gpio_reg_resume(struct gpio_chip * gc)173 int gpio_reg_resume(struct gpio_chip *gc)
174 {
175 struct gpio_reg *r = to_gpio_reg(gc);
176 unsigned long flags;
177
178 spin_lock_irqsave(&r->lock, flags);
179 writel_relaxed(r->out, r->reg);
180 spin_unlock_irqrestore(&r->lock, flags);
181
182 return 0;
183 }
184