1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * QLogic iSCSI HBA Driver
4  * Copyright (c)  2003-2013 QLogic Corporation
5  */
6 
7 #ifndef __QL4_DEF_H
8 #define __QL4_DEF_H
9 
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/workqueue.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/mutex.h>
26 #include <linux/bsg-lib.h>
27 #include <linux/vmalloc.h>
28 
29 #include <net/tcp.h>
30 #include <scsi/scsi.h>
31 #include <scsi/scsi_host.h>
32 #include <scsi/scsi_device.h>
33 #include <scsi/scsi_cmnd.h>
34 #include <scsi/scsi_transport.h>
35 #include <scsi/scsi_transport_iscsi.h>
36 #include <scsi/scsi_bsg_iscsi.h>
37 #include <scsi/scsi_netlink.h>
38 #include <scsi/libiscsi.h>
39 
40 #include "ql4_dbg.h"
41 #include "ql4_nx.h"
42 #include "ql4_fw.h"
43 #include "ql4_nvram.h"
44 #include "ql4_83xx.h"
45 
46 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
47 #define PCI_DEVICE_ID_QLOGIC_ISP4010	0x4010
48 #endif
49 
50 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
51 #define PCI_DEVICE_ID_QLOGIC_ISP4022	0x4022
52 #endif
53 
54 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
55 #define PCI_DEVICE_ID_QLOGIC_ISP4032	0x4032
56 #endif
57 
58 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
59 #define PCI_DEVICE_ID_QLOGIC_ISP8022	0x8022
60 #endif
61 
62 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8324
63 #define PCI_DEVICE_ID_QLOGIC_ISP8324	0x8032
64 #endif
65 
66 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8042
67 #define PCI_DEVICE_ID_QLOGIC_ISP8042	0x8042
68 #endif
69 
70 #define ISP4XXX_PCI_FN_1	0x1
71 #define ISP4XXX_PCI_FN_2	0x3
72 
73 #define QLA_SUCCESS			0
74 #define QLA_ERROR			1
75 #define STATUS(status)		status == QLA_ERROR ? "FAILED" : "SUCCEEDED"
76 
77 /*
78  * Data bit definitions
79  */
80 #define BIT_0	0x1
81 #define BIT_1	0x2
82 #define BIT_2	0x4
83 #define BIT_3	0x8
84 #define BIT_4	0x10
85 #define BIT_5	0x20
86 #define BIT_6	0x40
87 #define BIT_7	0x80
88 #define BIT_8	0x100
89 #define BIT_9	0x200
90 #define BIT_10	0x400
91 #define BIT_11	0x800
92 #define BIT_12	0x1000
93 #define BIT_13	0x2000
94 #define BIT_14	0x4000
95 #define BIT_15	0x8000
96 #define BIT_16	0x10000
97 #define BIT_17	0x20000
98 #define BIT_18	0x40000
99 #define BIT_19	0x80000
100 #define BIT_20	0x100000
101 #define BIT_21	0x200000
102 #define BIT_22	0x400000
103 #define BIT_23	0x800000
104 #define BIT_24	0x1000000
105 #define BIT_25	0x2000000
106 #define BIT_26	0x4000000
107 #define BIT_27	0x8000000
108 #define BIT_28	0x10000000
109 #define BIT_29	0x20000000
110 #define BIT_30	0x40000000
111 #define BIT_31	0x80000000
112 
113 /**
114  * Macros to help code, maintain, etc.
115  **/
116 #define ql4_printk(level, ha, format, arg...) \
117 	dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
118 
119 
120 /*
121  * Host adapter default definitions
122  ***********************************/
123 #define MAX_HBAS		16
124 #define MAX_BUSES		1
125 #define MAX_TARGETS		MAX_DEV_DB_ENTRIES
126 #define MAX_LUNS		0xffff
127 #define MAX_AEN_ENTRIES		MAX_DEV_DB_ENTRIES
128 #define MAX_DDB_ENTRIES		MAX_DEV_DB_ENTRIES
129 #define MAX_PDU_ENTRIES		32
130 #define INVALID_ENTRY		0xFFFF
131 #define MAX_CMDS_TO_RISC	1024
132 #define MAX_SRBS		MAX_CMDS_TO_RISC
133 #define MBOX_AEN_REG_COUNT	8
134 #define MAX_INIT_RETRIES	5
135 
136 /*
137  * Buffer sizes
138  */
139 #define REQUEST_QUEUE_DEPTH		MAX_CMDS_TO_RISC
140 #define RESPONSE_QUEUE_DEPTH		64
141 #define QUEUE_SIZE			64
142 #define DMA_BUFFER_SIZE			512
143 #define IOCB_HIWAT_CUSHION		4
144 
145 /*
146  * Misc
147  */
148 #define MAC_ADDR_LEN			6	/* in bytes */
149 #define IP_ADDR_LEN			4	/* in bytes */
150 #define IPv6_ADDR_LEN			16	/* IPv6 address size */
151 #define DRIVER_NAME			"qla4xxx"
152 
153 #define MAX_LINKED_CMDS_PER_LUN		3
154 #define MAX_REQS_SERVICED_PER_INTR	1
155 
156 #define ISCSI_IPADDR_SIZE		4	/* IP address size */
157 #define ISCSI_ALIAS_SIZE		32	/* ISCSI Alias name size */
158 #define ISCSI_NAME_SIZE			0xE0	/* ISCSI Name size */
159 
160 #define QL4_SESS_RECOVERY_TMO		120	/* iSCSI session */
161 						/* recovery timeout */
162 
163 #define LSDW(x) ((u32)((u64)(x)))
164 #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
165 
166 #define DEV_DB_NON_PERSISTENT	0
167 #define DEV_DB_PERSISTENT	1
168 
169 #define QL4_ISP_REG_DISCONNECT 0xffffffffU
170 
171 #define COPY_ISID(dst_isid, src_isid) {			\
172 	int i, j;					\
173 	for (i = 0, j = ISID_SIZE - 1; i < ISID_SIZE;)	\
174 		dst_isid[i++] = src_isid[j--];		\
175 }
176 
177 #define SET_BITVAL(o, n, v) {	\
178 	if (o)			\
179 		n |= v;		\
180 	else			\
181 		n &= ~v;	\
182 }
183 
184 #define OP_STATE(o, f, p) {			\
185 	p = (o & f) ? "enable" : "disable";	\
186 }
187 
188 /*
189  * Retry & Timeout Values
190  */
191 #define MBOX_TOV			60
192 #define SOFT_RESET_TOV			30
193 #define RESET_INTR_TOV			3
194 #define SEMAPHORE_TOV			10
195 #define ADAPTER_INIT_TOV		30
196 #define ADAPTER_RESET_TOV		180
197 #define EXTEND_CMD_TOV			60
198 #define WAIT_CMD_TOV			5
199 #define EH_WAIT_CMD_TOV			120
200 #define FIRMWARE_UP_TOV			60
201 #define RESET_FIRMWARE_TOV		30
202 #define LOGOUT_TOV			10
203 #define IOCB_TOV_MARGIN			10
204 #define RELOGIN_TOV			18
205 #define ISNS_DEREG_TOV			5
206 #define HBA_ONLINE_TOV			30
207 #define DISABLE_ACB_TOV			30
208 #define IP_CONFIG_TOV			30
209 #define LOGIN_TOV			12
210 #define BOOT_LOGIN_RESP_TOV		60
211 
212 #define MAX_RESET_HA_RETRIES		2
213 #define FW_ALIVE_WAIT_TOV		3
214 #define IDC_EXTEND_TOV			8
215 #define IDC_COMP_TOV			5
216 #define LINK_UP_COMP_TOV		30
217 
218 /*
219  * Note: the data structure below does not have a struct iscsi_cmd member since
220  * the qla4xxx driver does not use libiscsi for SCSI I/O.
221  */
222 struct qla4xxx_cmd_priv {
223 	struct srb *srb;
224 };
225 
qla4xxx_cmd_priv(struct scsi_cmnd * cmd)226 static inline struct qla4xxx_cmd_priv *qla4xxx_cmd_priv(struct scsi_cmnd *cmd)
227 {
228 	return scsi_cmd_priv(cmd);
229 }
230 
231 /*
232  * SCSI Request Block structure (srb) that is associated with each scsi_cmnd.
233  */
234 struct srb {
235 	struct list_head list;	/* (8)	 */
236 	struct scsi_qla_host *ha;	/* HA the SP is queued on */
237 	struct ddb_entry *ddb;
238 	uint16_t flags;		/* (1) Status flags. */
239 
240 #define SRB_DMA_VALID		BIT_3	/* DMA Buffer mapped. */
241 #define SRB_GOT_SENSE		BIT_4	/* sense data received. */
242 	uint8_t state;		/* (1) Status flags. */
243 
244 #define SRB_NO_QUEUE_STATE	 0	/* Request is in between states */
245 #define SRB_FREE_STATE		 1
246 #define SRB_ACTIVE_STATE	 3
247 #define SRB_ACTIVE_TIMEOUT_STATE 4
248 #define SRB_SUSPENDED_STATE	 7	/* Request in suspended state */
249 
250 	struct scsi_cmnd *cmd;	/* (4) SCSI command block */
251 	dma_addr_t dma_handle;	/* (4) for unmap of single transfers */
252 	struct kref srb_ref;	/* reference count for this srb */
253 	uint8_t err_id;		/* error id */
254 #define SRB_ERR_PORT	   1	/* Request failed because "port down" */
255 #define SRB_ERR_LOOP	   2	/* Request failed because "loop down" */
256 #define SRB_ERR_DEVICE	   3	/* Request failed because "device error" */
257 #define SRB_ERR_OTHER	   4
258 
259 	uint16_t reserved;
260 	uint16_t iocb_tov;
261 	uint16_t iocb_cnt;	/* Number of used iocbs */
262 	uint16_t cc_stat;
263 
264 	/* Used for extended sense / status continuation */
265 	uint8_t *req_sense_ptr;
266 	uint16_t req_sense_len;
267 	uint16_t reserved2;
268 };
269 
270 /* Mailbox request block structure */
271 struct mrb {
272 	struct scsi_qla_host *ha;
273 	struct mbox_cmd_iocb *mbox;
274 	uint32_t mbox_cmd;
275 	uint16_t iocb_cnt;		/* Number of used iocbs */
276 	uint32_t pid;
277 };
278 
279 /*
280  * Asynchronous Event Queue structure
281  */
282 struct aen {
283         uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
284 };
285 
286 struct ql4_aen_log {
287         int count;
288         struct aen entry[MAX_AEN_ENTRIES];
289 };
290 
291 /*
292  * Device Database (DDB) structure
293  */
294 struct ddb_entry {
295 	struct scsi_qla_host *ha;
296 	struct iscsi_cls_session *sess;
297 	struct iscsi_cls_conn *conn;
298 
299 	uint16_t fw_ddb_index;	/* DDB firmware index */
300 	uint32_t fw_ddb_device_state; /* F/W Device State  -- see ql4_fw.h */
301 	uint16_t ddb_type;
302 #define FLASH_DDB 0x01
303 
304 	struct dev_db_entry fw_ddb_entry;
305 	int (*unblock_sess)(struct iscsi_cls_session *cls_session);
306 	int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index,
307 			  struct ddb_entry *ddb_entry, uint32_t state);
308 
309 	/* Driver Re-login  */
310 	unsigned long flags;		  /* DDB Flags */
311 #define DDB_CONN_CLOSE_FAILURE		0 /* 0x00000001 */
312 
313 	uint16_t default_relogin_timeout; /*  Max time to wait for
314 					   *  relogin to complete */
315 	atomic_t retry_relogin_timer;	  /* Min Time between relogins
316 					   * (4000 only) */
317 	atomic_t relogin_timer;		  /* Max Time to wait for
318 					   * relogin to complete */
319 	atomic_t relogin_retry_count;	  /* Num of times relogin has been
320 					   * retried */
321 	uint32_t default_time2wait;	  /* Default Min time between
322 					   * relogins (+aens) */
323 	uint16_t chap_tbl_idx;
324 };
325 
326 struct qla_ddb_index {
327 	struct list_head list;
328 	uint16_t fw_ddb_idx;
329 	uint16_t flash_ddb_idx;
330 	struct dev_db_entry fw_ddb;
331 	uint8_t flash_isid[6];
332 };
333 
334 #define DDB_IPADDR_LEN 64
335 
336 struct ql4_tuple_ddb {
337 	int port;
338 	int tpgt;
339 	char ip_addr[DDB_IPADDR_LEN];
340 	char iscsi_name[ISCSI_NAME_SIZE];
341 	uint16_t options;
342 #define DDB_OPT_IPV6 0x0e0e
343 #define DDB_OPT_IPV4 0x0f0f
344 	uint8_t isid[6];
345 };
346 
347 /*
348  * DDB states.
349  */
350 #define DDB_STATE_DEAD		0	/* We can no longer talk to
351 					 * this device */
352 #define DDB_STATE_ONLINE	1	/* Device ready to accept
353 					 * commands */
354 #define DDB_STATE_MISSING	2	/* Device logged off, trying
355 					 * to re-login */
356 
357 /*
358  * DDB flags.
359  */
360 #define DF_RELOGIN		0	/* Relogin to device */
361 #define DF_BOOT_TGT		1	/* Boot target entry */
362 #define DF_ISNS_DISCOVERED	2	/* Device was discovered via iSNS */
363 #define DF_FO_MASKED		3
364 #define DF_DISABLE_RELOGIN		4	/* Disable relogin to device */
365 
366 enum qla4_work_type {
367 	QLA4_EVENT_AEN,
368 	QLA4_EVENT_PING_STATUS,
369 };
370 
371 struct qla4_work_evt {
372 	struct list_head list;
373 	enum qla4_work_type type;
374 	union {
375 		struct {
376 			enum iscsi_host_event_code code;
377 			uint32_t data_size;
378 			uint8_t data[];
379 		} aen;
380 		struct {
381 			uint32_t status;
382 			uint32_t pid;
383 			uint32_t data_size;
384 			uint8_t data[];
385 		} ping;
386 	} u;
387 };
388 
389 struct ql82xx_hw_data {
390 	/* Offsets for flash/nvram access (set to ~0 if not used). */
391 	uint32_t flash_conf_off;
392 	uint32_t flash_data_off;
393 
394 	uint32_t fdt_wrt_disable;
395 	uint32_t fdt_erase_cmd;
396 	uint32_t fdt_block_size;
397 	uint32_t fdt_unprotect_sec_cmd;
398 	uint32_t fdt_protect_sec_cmd;
399 
400 	uint32_t flt_region_flt;
401 	uint32_t flt_region_fdt;
402 	uint32_t flt_region_boot;
403 	uint32_t flt_region_bootload;
404 	uint32_t flt_region_fw;
405 
406 	uint32_t flt_iscsi_param;
407 	uint32_t flt_region_chap;
408 	uint32_t flt_chap_size;
409 	uint32_t flt_region_ddb;
410 	uint32_t flt_ddb_size;
411 };
412 
413 struct qla4_8xxx_legacy_intr_set {
414 	uint32_t int_vec_bit;
415 	uint32_t tgt_status_reg;
416 	uint32_t tgt_mask_reg;
417 	uint32_t pci_int_reg;
418 };
419 
420 /* MSI-X Support */
421 #define QLA_MSIX_ENTRIES	2
422 
423 /*
424  * ISP Operations
425  */
426 struct isp_operations {
427 	int (*iospace_config) (struct scsi_qla_host *ha);
428 	void (*pci_config) (struct scsi_qla_host *);
429 	void (*disable_intrs) (struct scsi_qla_host *);
430 	void (*enable_intrs) (struct scsi_qla_host *);
431 	int (*start_firmware) (struct scsi_qla_host *);
432 	int (*restart_firmware) (struct scsi_qla_host *);
433 	irqreturn_t (*intr_handler) (int , void *);
434 	void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
435 	int (*need_reset) (struct scsi_qla_host *);
436 	int (*reset_chip) (struct scsi_qla_host *);
437 	int (*reset_firmware) (struct scsi_qla_host *);
438 	void (*queue_iocb) (struct scsi_qla_host *);
439 	void (*complete_iocb) (struct scsi_qla_host *);
440 	uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *);
441 	uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *);
442 	int (*get_sys_info) (struct scsi_qla_host *);
443 	uint32_t (*rd_reg_direct) (struct scsi_qla_host *, ulong);
444 	void (*wr_reg_direct) (struct scsi_qla_host *, ulong, uint32_t);
445 	int (*rd_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t *);
446 	int (*wr_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t);
447 	int (*idc_lock) (struct scsi_qla_host *); /* Context: task, can sleep */
448 	void (*idc_unlock) (struct scsi_qla_host *);
449 	void (*rom_lock_recovery) (struct scsi_qla_host *); /* Context: task, can sleep */
450 	void (*queue_mailbox_command) (struct scsi_qla_host *, uint32_t *, int);
451 	void (*process_mailbox_interrupt) (struct scsi_qla_host *, int);
452 };
453 
454 struct ql4_mdump_size_table {
455 	uint32_t size;
456 	uint32_t size_cmask_02;
457 	uint32_t size_cmask_04;
458 	uint32_t size_cmask_08;
459 	uint32_t size_cmask_10;
460 	uint32_t size_cmask_FF;
461 	uint32_t version;
462 };
463 
464 /*qla4xxx ipaddress configuration details */
465 struct ipaddress_config {
466 	uint16_t ipv4_options;
467 	uint16_t tcp_options;
468 	uint16_t ipv4_vlan_tag;
469 	uint8_t ipv4_addr_state;
470 	uint8_t ip_address[IP_ADDR_LEN];
471 	uint8_t subnet_mask[IP_ADDR_LEN];
472 	uint8_t gateway[IP_ADDR_LEN];
473 	uint32_t ipv6_options;
474 	uint32_t ipv6_addl_options;
475 	uint8_t ipv6_link_local_state;
476 	uint8_t ipv6_addr0_state;
477 	uint8_t ipv6_addr1_state;
478 	uint8_t ipv6_default_router_state;
479 	uint16_t ipv6_vlan_tag;
480 	struct in6_addr ipv6_link_local_addr;
481 	struct in6_addr ipv6_addr0;
482 	struct in6_addr ipv6_addr1;
483 	struct in6_addr ipv6_default_router_addr;
484 	uint16_t eth_mtu_size;
485 	uint16_t ipv4_port;
486 	uint16_t ipv6_port;
487 	uint8_t control;
488 	uint16_t ipv6_tcp_options;
489 	uint8_t tcp_wsf;
490 	uint8_t ipv6_tcp_wsf;
491 	uint8_t ipv4_tos;
492 	uint8_t ipv4_cache_id;
493 	uint8_t ipv6_cache_id;
494 	uint8_t ipv4_alt_cid_len;
495 	uint8_t ipv4_alt_cid[11];
496 	uint8_t ipv4_vid_len;
497 	uint8_t ipv4_vid[11];
498 	uint8_t ipv4_ttl;
499 	uint16_t ipv6_flow_lbl;
500 	uint8_t ipv6_traffic_class;
501 	uint8_t ipv6_hop_limit;
502 	uint32_t ipv6_nd_reach_time;
503 	uint32_t ipv6_nd_rexmit_timer;
504 	uint32_t ipv6_nd_stale_timeout;
505 	uint8_t ipv6_dup_addr_detect_count;
506 	uint32_t ipv6_gw_advrt_mtu;
507 	uint16_t def_timeout;
508 	uint8_t abort_timer;
509 	uint16_t iscsi_options;
510 	uint16_t iscsi_max_pdu_size;
511 	uint16_t iscsi_first_burst_len;
512 	uint16_t iscsi_max_outstnd_r2t;
513 	uint16_t iscsi_max_burst_len;
514 	uint8_t iscsi_name[224];
515 };
516 
517 #define QL4_CHAP_MAX_NAME_LEN 256
518 #define QL4_CHAP_MAX_SECRET_LEN 100
519 #define LOCAL_CHAP	0
520 #define BIDI_CHAP	1
521 
522 struct ql4_chap_format {
523 	u8  intr_chap_name[QL4_CHAP_MAX_NAME_LEN];
524 	u8  intr_secret[QL4_CHAP_MAX_SECRET_LEN];
525 	u8  target_chap_name[QL4_CHAP_MAX_NAME_LEN];
526 	u8  target_secret[QL4_CHAP_MAX_SECRET_LEN];
527 	u16 intr_chap_name_length;
528 	u16 intr_secret_length;
529 	u16 target_chap_name_length;
530 	u16 target_secret_length;
531 };
532 
533 struct ip_address_format {
534 	u8 ip_type;
535 	u8 ip_address[16];
536 };
537 
538 struct	ql4_conn_info {
539 	u16	dest_port;
540 	struct	ip_address_format dest_ipaddr;
541 	struct	ql4_chap_format chap;
542 };
543 
544 struct ql4_boot_session_info {
545 	u8	target_name[224];
546 	struct	ql4_conn_info conn_list[1];
547 };
548 
549 struct ql4_boot_tgt_info {
550 	struct ql4_boot_session_info boot_pri_sess;
551 	struct ql4_boot_session_info boot_sec_sess;
552 };
553 
554 /*
555  * Linux Host Adapter structure
556  */
557 struct scsi_qla_host {
558 	/* Linux adapter configuration data */
559 	unsigned long flags;
560 
561 #define AF_ONLINE			0 /* 0x00000001 */
562 #define AF_INIT_DONE			1 /* 0x00000002 */
563 #define AF_MBOX_COMMAND			2 /* 0x00000004 */
564 #define AF_MBOX_COMMAND_DONE		3 /* 0x00000008 */
565 #define AF_ST_DISCOVERY_IN_PROGRESS	4 /* 0x00000010 */
566 #define AF_INTERRUPTS_ON		6 /* 0x00000040 */
567 #define AF_GET_CRASH_RECORD		7 /* 0x00000080 */
568 #define AF_LINK_UP			8 /* 0x00000100 */
569 #define AF_LOOPBACK			9 /* 0x00000200 */
570 #define AF_IRQ_ATTACHED			10 /* 0x00000400 */
571 #define AF_DISABLE_ACB_COMPLETE		11 /* 0x00000800 */
572 #define AF_HA_REMOVAL			12 /* 0x00001000 */
573 #define AF_MBOX_COMMAND_NOPOLL		18 /* 0x00040000 */
574 #define AF_FW_RECOVERY			19 /* 0x00080000 */
575 #define AF_EEH_BUSY			20 /* 0x00100000 */
576 #define AF_PCI_CHANNEL_IO_PERM_FAILURE	21 /* 0x00200000 */
577 #define AF_BUILD_DDB_LIST		22 /* 0x00400000 */
578 #define AF_82XX_FW_DUMPED		24 /* 0x01000000 */
579 #define AF_8XXX_RST_OWNER		25 /* 0x02000000 */
580 #define AF_82XX_DUMP_READING		26 /* 0x04000000 */
581 #define AF_83XX_IOCB_INTR_ON		28 /* 0x10000000 */
582 #define AF_83XX_MBOX_INTR_ON		29 /* 0x20000000 */
583 
584 	unsigned long dpc_flags;
585 
586 #define DPC_RESET_HA			1 /* 0x00000002 */
587 #define DPC_RETRY_RESET_HA		2 /* 0x00000004 */
588 #define DPC_RELOGIN_DEVICE		3 /* 0x00000008 */
589 #define DPC_RESET_HA_FW_CONTEXT		4 /* 0x00000010 */
590 #define DPC_RESET_HA_INTR		5 /* 0x00000020 */
591 #define DPC_ISNS_RESTART		7 /* 0x00000080 */
592 #define DPC_AEN				9 /* 0x00000200 */
593 #define DPC_GET_DHCP_IP_ADDR		15 /* 0x00008000 */
594 #define DPC_LINK_CHANGED		18 /* 0x00040000 */
595 #define DPC_RESET_ACTIVE		20 /* 0x00100000 */
596 #define DPC_HA_UNRECOVERABLE		21 /* 0x00200000 ISP-82xx only*/
597 #define DPC_HA_NEED_QUIESCENT		22 /* 0x00400000 ISP-82xx only*/
598 #define DPC_POST_IDC_ACK		23 /* 0x00800000 */
599 #define DPC_RESTORE_ACB			24 /* 0x01000000 */
600 #define DPC_SYSFS_DDB_EXPORT		25 /* 0x02000000 */
601 
602 	struct Scsi_Host *host; /* pointer to host data */
603 	uint32_t tot_ddbs;
604 
605 	uint16_t iocb_cnt;
606 	uint16_t iocb_hiwat;
607 
608 	/* SRB cache. */
609 #define SRB_MIN_REQ	128
610 	mempool_t *srb_mempool;
611 
612 	/* pci information */
613 	struct pci_dev *pdev;
614 
615 	struct isp_reg __iomem *reg; /* Base I/O address */
616 	unsigned long pio_address;
617 	unsigned long pio_length;
618 #define MIN_IOBASE_LEN		0x100
619 
620 	uint16_t req_q_count;
621 
622 	unsigned long host_no;
623 
624 	/* NVRAM registers */
625 	struct eeprom_data *nvram;
626 	spinlock_t hardware_lock ____cacheline_aligned;
627 	uint32_t eeprom_cmd_data;
628 
629 	/* Counters for general statistics */
630 	uint64_t isr_count;
631 	uint64_t adapter_error_count;
632 	uint64_t device_error_count;
633 	uint64_t total_io_count;
634 	uint64_t total_mbytes_xferred;
635 	uint64_t link_failure_count;
636 	uint64_t invalid_crc_count;
637 	uint32_t bytes_xfered;
638 	uint32_t spurious_int_count;
639 	uint32_t aborted_io_count;
640 	uint32_t io_timeout_count;
641 	uint32_t mailbox_timeout_count;
642 	uint32_t seconds_since_last_intr;
643 	uint32_t seconds_since_last_heartbeat;
644 	uint32_t mac_index;
645 
646 	/* Info Needed for Management App */
647 	/* --- From GetFwVersion --- */
648 	uint32_t firmware_version[2];
649 	uint32_t patch_number;
650 	uint32_t build_number;
651 	uint32_t board_id;
652 
653 	/* --- From Init_FW --- */
654 	/* init_cb_t *init_cb; */
655 	uint16_t firmware_options;
656 	uint8_t alias[32];
657 	uint8_t name_string[256];
658 	uint8_t heartbeat_interval;
659 
660 	/* --- From FlashSysInfo --- */
661 	uint8_t my_mac[MAC_ADDR_LEN];
662 	uint8_t serial_number[16];
663 	uint16_t port_num;
664 	/* --- From GetFwState --- */
665 	uint32_t firmware_state;
666 	uint32_t addl_fw_state;
667 
668 	/* Linux kernel thread */
669 	struct workqueue_struct *dpc_thread;
670 	struct work_struct dpc_work;
671 
672 	/* Linux timer thread */
673 	struct timer_list timer;
674 	uint32_t timer_active;
675 
676 	/* Recovery Timers */
677 	atomic_t check_relogin_timeouts;
678 	uint32_t retry_reset_ha_cnt;
679 	uint32_t isp_reset_timer;	/* reset test timer */
680 	uint32_t nic_reset_timer;	/* simulated nic reset test timer */
681 	int eh_start;
682 	struct list_head free_srb_q;
683 	uint16_t free_srb_q_count;
684 	uint16_t num_srbs_allocated;
685 
686 	/* DMA Memory Block */
687 	void *queues;
688 	dma_addr_t queues_dma;
689 	unsigned long queues_len;
690 
691 #define MEM_ALIGN_VALUE \
692 	    ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
693 	     sizeof(struct queue_entry))
694 	/* request and response queue variables */
695 	dma_addr_t request_dma;
696 	struct queue_entry *request_ring;
697 	struct queue_entry *request_ptr;
698 	dma_addr_t response_dma;
699 	struct queue_entry *response_ring;
700 	struct queue_entry *response_ptr;
701 	dma_addr_t shadow_regs_dma;
702 	struct shadow_regs *shadow_regs;
703 	uint16_t request_in;	/* Current indexes. */
704 	uint16_t request_out;
705 	uint16_t response_in;
706 	uint16_t response_out;
707 
708 	/* aen queue variables */
709 	uint16_t aen_q_count;	/* Number of available aen_q entries */
710 	uint16_t aen_in;	/* Current indexes */
711 	uint16_t aen_out;
712 	struct aen aen_q[MAX_AEN_ENTRIES];
713 
714 	struct ql4_aen_log aen_log;/* tracks all aens */
715 
716 	/* This mutex protects several threads to do mailbox commands
717 	 * concurrently.
718 	 */
719 	struct mutex  mbox_sem;
720 
721 	/* temporary mailbox status registers */
722 	volatile uint8_t mbox_status_count;
723 	volatile uint32_t mbox_status[MBOX_REG_COUNT];
724 
725 	/* FW ddb index map */
726 	struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
727 
728 	/* Saved srb for status continuation entry processing */
729 	struct srb *status_srb;
730 
731 	uint8_t acb_version;
732 
733 	/* qla82xx specific fields */
734 	struct device_reg_82xx  __iomem *qla4_82xx_reg; /* Base I/O address */
735 	unsigned long nx_pcibase;	/* Base I/O address */
736 	uint8_t *nx_db_rd_ptr;		/* Doorbell read pointer */
737 	unsigned long nx_db_wr_ptr;	/* Door bell write pointer */
738 	unsigned long first_page_group_start;
739 	unsigned long first_page_group_end;
740 
741 	uint32_t crb_win;
742 	uint32_t curr_window;
743 	uint32_t ddr_mn_window;
744 	unsigned long mn_win_crb;
745 	unsigned long ms_win_crb;
746 	int qdr_sn_window;
747 	rwlock_t hw_lock;
748 	uint16_t func_num;
749 	int link_width;
750 
751 	struct qla4_8xxx_legacy_intr_set nx_legacy_intr;
752 	u32 nx_crb_mask;
753 
754 	uint8_t revision_id;
755 	uint32_t fw_heartbeat_counter;
756 
757 	struct isp_operations *isp_ops;
758 	struct ql82xx_hw_data hw;
759 
760 	uint32_t nx_dev_init_timeout;
761 	uint32_t nx_reset_timeout;
762 	void *fw_dump;
763 	uint32_t fw_dump_size;
764 	uint32_t fw_dump_capture_mask;
765 	void *fw_dump_tmplt_hdr;
766 	uint32_t fw_dump_tmplt_size;
767 	uint32_t fw_dump_skip_size;
768 
769 	struct completion mbx_intr_comp;
770 
771 	struct ipaddress_config ip_config;
772 	struct iscsi_iface *iface_ipv4;
773 	struct iscsi_iface *iface_ipv6_0;
774 	struct iscsi_iface *iface_ipv6_1;
775 
776 	/* --- From About Firmware --- */
777 	struct about_fw_info fw_info;
778 	uint32_t fw_uptime_secs;  /* seconds elapsed since fw bootup */
779 	uint32_t fw_uptime_msecs; /* milliseconds beyond elapsed seconds */
780 	uint16_t def_timeout; /* Default login timeout */
781 
782 	uint32_t flash_state;
783 #define	QLFLASH_WAITING		0
784 #define	QLFLASH_READING		1
785 #define	QLFLASH_WRITING		2
786 	struct dma_pool *chap_dma_pool;
787 	uint8_t *chap_list; /* CHAP table cache */
788 	struct mutex  chap_sem;
789 
790 #define CHAP_DMA_BLOCK_SIZE    512
791 	struct workqueue_struct *task_wq;
792 	unsigned long ddb_idx_map[MAX_DDB_ENTRIES / BITS_PER_LONG];
793 #define SYSFS_FLAG_FW_SEL_BOOT 2
794 	struct iscsi_boot_kset *boot_kset;
795 	struct ql4_boot_tgt_info boot_tgt;
796 	uint16_t phy_port_num;
797 	uint16_t phy_port_cnt;
798 	uint16_t iscsi_pci_func_cnt;
799 	uint8_t model_name[16];
800 	struct completion disable_acb_comp;
801 	struct dma_pool *fw_ddb_dma_pool;
802 #define DDB_DMA_BLOCK_SIZE 512
803 	uint16_t pri_ddb_idx;
804 	uint16_t sec_ddb_idx;
805 	int is_reset;
806 	uint16_t temperature;
807 
808 	/* event work list */
809 	struct list_head work_list;
810 	spinlock_t work_lock;
811 
812 	/* mbox iocb */
813 #define MAX_MRB		128
814 	struct mrb *active_mrb_array[MAX_MRB];
815 	uint32_t mrb_index;
816 
817 	uint32_t *reg_tbl;
818 	struct qla4_83xx_reset_template reset_tmplt;
819 	struct device_reg_83xx  __iomem *qla4_83xx_reg; /* Base I/O address
820 							   for ISP8324 and
821 							   and ISP8042 */
822 	uint32_t pf_bit;
823 	struct qla4_83xx_idc_information idc_info;
824 	struct addr_ctrl_blk *saved_acb;
825 	int notify_idc_comp;
826 	int notify_link_up_comp;
827 	int idc_extend_tmo;
828 	struct completion idc_comp;
829 	struct completion link_up_comp;
830 };
831 
832 struct ql4_task_data {
833 	struct scsi_qla_host *ha;
834 	uint8_t iocb_req_cnt;
835 	dma_addr_t data_dma;
836 	void *req_buffer;
837 	dma_addr_t req_dma;
838 	uint32_t req_len;
839 	void *resp_buffer;
840 	dma_addr_t resp_dma;
841 	uint32_t resp_len;
842 	struct iscsi_task *task;
843 	struct passthru_status sts;
844 	struct work_struct task_work;
845 };
846 
847 struct qla_endpoint {
848 	struct Scsi_Host *host;
849 	struct sockaddr_storage dst_addr;
850 };
851 
852 struct qla_conn {
853 	struct qla_endpoint *qla_ep;
854 };
855 
is_ipv4_enabled(struct scsi_qla_host * ha)856 static inline int is_ipv4_enabled(struct scsi_qla_host *ha)
857 {
858 	return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0);
859 }
860 
is_ipv6_enabled(struct scsi_qla_host * ha)861 static inline int is_ipv6_enabled(struct scsi_qla_host *ha)
862 {
863 	return ((ha->ip_config.ipv6_options &
864 		IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0);
865 }
866 
is_qla4010(struct scsi_qla_host * ha)867 static inline int is_qla4010(struct scsi_qla_host *ha)
868 {
869 	return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
870 }
871 
is_qla4022(struct scsi_qla_host * ha)872 static inline int is_qla4022(struct scsi_qla_host *ha)
873 {
874 	return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
875 }
876 
is_qla4032(struct scsi_qla_host * ha)877 static inline int is_qla4032(struct scsi_qla_host *ha)
878 {
879 	return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;
880 }
881 
is_qla40XX(struct scsi_qla_host * ha)882 static inline int is_qla40XX(struct scsi_qla_host *ha)
883 {
884 	return is_qla4032(ha) || is_qla4022(ha) || is_qla4010(ha);
885 }
886 
is_qla8022(struct scsi_qla_host * ha)887 static inline int is_qla8022(struct scsi_qla_host *ha)
888 {
889 	return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
890 }
891 
is_qla8032(struct scsi_qla_host * ha)892 static inline int is_qla8032(struct scsi_qla_host *ha)
893 {
894 	return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324;
895 }
896 
is_qla8042(struct scsi_qla_host * ha)897 static inline int is_qla8042(struct scsi_qla_host *ha)
898 {
899 	return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8042;
900 }
901 
is_qla80XX(struct scsi_qla_host * ha)902 static inline int is_qla80XX(struct scsi_qla_host *ha)
903 {
904 	return is_qla8022(ha) || is_qla8032(ha) || is_qla8042(ha);
905 }
906 
is_aer_supported(struct scsi_qla_host * ha)907 static inline int is_aer_supported(struct scsi_qla_host *ha)
908 {
909 	return ((ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022) ||
910 		(ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324) ||
911 		(ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8042));
912 }
913 
adapter_up(struct scsi_qla_host * ha)914 static inline int adapter_up(struct scsi_qla_host *ha)
915 {
916 	return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
917 	       (test_bit(AF_LINK_UP, &ha->flags) != 0) &&
918 	       (!test_bit(AF_LOOPBACK, &ha->flags));
919 }
920 
to_qla_host(struct Scsi_Host * shost)921 static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
922 {
923 	return (struct scsi_qla_host *)iscsi_host_priv(shost);
924 }
925 
isp_semaphore(struct scsi_qla_host * ha)926 static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
927 {
928 	return (is_qla4010(ha) ?
929 		&ha->reg->u1.isp4010.nvram :
930 		&ha->reg->u1.isp4022.semaphore);
931 }
932 
isp_nvram(struct scsi_qla_host * ha)933 static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
934 {
935 	return (is_qla4010(ha) ?
936 		&ha->reg->u1.isp4010.nvram :
937 		&ha->reg->u1.isp4022.nvram);
938 }
939 
isp_ext_hw_conf(struct scsi_qla_host * ha)940 static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
941 {
942 	return (is_qla4010(ha) ?
943 		&ha->reg->u2.isp4010.ext_hw_conf :
944 		&ha->reg->u2.isp4022.p0.ext_hw_conf);
945 }
946 
isp_port_status(struct scsi_qla_host * ha)947 static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
948 {
949 	return (is_qla4010(ha) ?
950 		&ha->reg->u2.isp4010.port_status :
951 		&ha->reg->u2.isp4022.p0.port_status);
952 }
953 
isp_port_ctrl(struct scsi_qla_host * ha)954 static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
955 {
956 	return (is_qla4010(ha) ?
957 		&ha->reg->u2.isp4010.port_ctrl :
958 		&ha->reg->u2.isp4022.p0.port_ctrl);
959 }
960 
isp_port_error_status(struct scsi_qla_host * ha)961 static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
962 {
963 	return (is_qla4010(ha) ?
964 		&ha->reg->u2.isp4010.port_err_status :
965 		&ha->reg->u2.isp4022.p0.port_err_status);
966 }
967 
isp_gp_out(struct scsi_qla_host * ha)968 static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
969 {
970 	return (is_qla4010(ha) ?
971 		&ha->reg->u2.isp4010.gp_out :
972 		&ha->reg->u2.isp4022.p0.gp_out);
973 }
974 
eeprom_ext_hw_conf_offset(struct scsi_qla_host * ha)975 static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
976 {
977 	return (is_qla4010(ha) ?
978 		offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 :
979 		offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2);
980 }
981 
982 int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
983 void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
984 int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
985 
ql4xxx_lock_flash(struct scsi_qla_host * a)986 static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
987 {
988 	if (is_qla4010(a))
989 		return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
990 					   QL4010_FLASH_SEM_BITS);
991 	else
992 		return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
993 					   (QL4022_RESOURCE_BITS_BASE_CODE |
994 					    (a->mac_index)) << 13);
995 }
996 
ql4xxx_unlock_flash(struct scsi_qla_host * a)997 static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
998 {
999 	if (is_qla4010(a))
1000 		ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
1001 	else
1002 		ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
1003 }
1004 
ql4xxx_lock_nvram(struct scsi_qla_host * a)1005 static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
1006 {
1007 	if (is_qla4010(a))
1008 		return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
1009 					   QL4010_NVRAM_SEM_BITS);
1010 	else
1011 		return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
1012 					   (QL4022_RESOURCE_BITS_BASE_CODE |
1013 					    (a->mac_index)) << 10);
1014 }
1015 
ql4xxx_unlock_nvram(struct scsi_qla_host * a)1016 static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
1017 {
1018 	if (is_qla4010(a))
1019 		ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
1020 	else
1021 		ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
1022 }
1023 
ql4xxx_lock_drvr(struct scsi_qla_host * a)1024 static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
1025 {
1026 	if (is_qla4010(a))
1027 		return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
1028 				       QL4010_DRVR_SEM_BITS);
1029 	else
1030 		return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
1031 				       (QL4022_RESOURCE_BITS_BASE_CODE |
1032 					(a->mac_index)) << 1);
1033 }
1034 
ql4xxx_unlock_drvr(struct scsi_qla_host * a)1035 static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
1036 {
1037 	if (is_qla4010(a))
1038 		ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
1039 	else
1040 		ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
1041 }
1042 
ql4xxx_reset_active(struct scsi_qla_host * ha)1043 static inline int ql4xxx_reset_active(struct scsi_qla_host *ha)
1044 {
1045 	return test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) ||
1046 	       test_bit(DPC_RESET_HA, &ha->dpc_flags) ||
1047 	       test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags) ||
1048 	       test_bit(DPC_RESET_HA_INTR, &ha->dpc_flags) ||
1049 	       test_bit(DPC_RESET_HA_FW_CONTEXT, &ha->dpc_flags) ||
1050 	       test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags);
1051 
1052 }
1053 
qla4_8xxx_rd_direct(struct scsi_qla_host * ha,const uint32_t crb_reg)1054 static inline int qla4_8xxx_rd_direct(struct scsi_qla_host *ha,
1055 				      const uint32_t crb_reg)
1056 {
1057 	return ha->isp_ops->rd_reg_direct(ha, ha->reg_tbl[crb_reg]);
1058 }
1059 
qla4_8xxx_wr_direct(struct scsi_qla_host * ha,const uint32_t crb_reg,const uint32_t value)1060 static inline void qla4_8xxx_wr_direct(struct scsi_qla_host *ha,
1061 				       const uint32_t crb_reg,
1062 				       const uint32_t value)
1063 {
1064 	ha->isp_ops->wr_reg_direct(ha, ha->reg_tbl[crb_reg], value);
1065 }
1066 
1067 /*---------------------------------------------------------------------------*/
1068 
1069 /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
1070 
1071 #define INIT_ADAPTER    0
1072 #define RESET_ADAPTER   1
1073 
1074 #define PRESERVE_DDB_LIST	0
1075 #define REBUILD_DDB_LIST	1
1076 
1077 /* Defines for process_aen() */
1078 #define PROCESS_ALL_AENS	 0
1079 #define FLUSH_DDB_CHANGED_AENS	 1
1080 
1081 /* Defines for udev events */
1082 #define QL4_UEVENT_CODE_FW_DUMP		0
1083 
1084 #endif	/*_QLA4XXX_H */
1085