1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * i.MX IPUv3 DP Overlay Planes
4 *
5 * Copyright (C) 2013 Philipp Zabel, Pengutronix
6 */
7
8 #include <drm/drm_atomic.h>
9 #include <drm/drm_atomic_helper.h>
10 #include <drm/drm_fb_cma_helper.h>
11 #include <drm/drm_fourcc.h>
12 #include <drm/drm_gem_atomic_helper.h>
13 #include <drm/drm_gem_cma_helper.h>
14 #include <drm/drm_managed.h>
15 #include <drm/drm_plane_helper.h>
16
17 #include <video/imx-ipu-v3.h>
18
19 #include "imx-drm.h"
20 #include "ipuv3-plane.h"
21
22 struct ipu_plane_state {
23 struct drm_plane_state base;
24 bool use_pre;
25 };
26
27 static inline struct ipu_plane_state *
to_ipu_plane_state(struct drm_plane_state * p)28 to_ipu_plane_state(struct drm_plane_state *p)
29 {
30 return container_of(p, struct ipu_plane_state, base);
31 }
32
ipu_src_rect_width(const struct drm_plane_state * state)33 static unsigned int ipu_src_rect_width(const struct drm_plane_state *state)
34 {
35 return ALIGN(drm_rect_width(&state->src) >> 16, 8);
36 }
37
to_ipu_plane(struct drm_plane * p)38 static inline struct ipu_plane *to_ipu_plane(struct drm_plane *p)
39 {
40 return container_of(p, struct ipu_plane, base);
41 }
42
43 static const uint32_t ipu_plane_all_formats[] = {
44 DRM_FORMAT_ARGB1555,
45 DRM_FORMAT_XRGB1555,
46 DRM_FORMAT_ABGR1555,
47 DRM_FORMAT_XBGR1555,
48 DRM_FORMAT_RGBA5551,
49 DRM_FORMAT_BGRA5551,
50 DRM_FORMAT_ARGB4444,
51 DRM_FORMAT_ARGB8888,
52 DRM_FORMAT_XRGB8888,
53 DRM_FORMAT_ABGR8888,
54 DRM_FORMAT_XBGR8888,
55 DRM_FORMAT_RGBA8888,
56 DRM_FORMAT_RGBX8888,
57 DRM_FORMAT_BGRA8888,
58 DRM_FORMAT_BGRX8888,
59 DRM_FORMAT_UYVY,
60 DRM_FORMAT_VYUY,
61 DRM_FORMAT_YUYV,
62 DRM_FORMAT_YVYU,
63 DRM_FORMAT_YUV420,
64 DRM_FORMAT_YVU420,
65 DRM_FORMAT_YUV422,
66 DRM_FORMAT_YVU422,
67 DRM_FORMAT_YUV444,
68 DRM_FORMAT_YVU444,
69 DRM_FORMAT_NV12,
70 DRM_FORMAT_NV16,
71 DRM_FORMAT_RGB565,
72 DRM_FORMAT_RGB565_A8,
73 DRM_FORMAT_BGR565_A8,
74 DRM_FORMAT_RGB888_A8,
75 DRM_FORMAT_BGR888_A8,
76 DRM_FORMAT_RGBX8888_A8,
77 DRM_FORMAT_BGRX8888_A8,
78 };
79
80 static const uint32_t ipu_plane_rgb_formats[] = {
81 DRM_FORMAT_ARGB1555,
82 DRM_FORMAT_XRGB1555,
83 DRM_FORMAT_ABGR1555,
84 DRM_FORMAT_XBGR1555,
85 DRM_FORMAT_RGBA5551,
86 DRM_FORMAT_BGRA5551,
87 DRM_FORMAT_ARGB4444,
88 DRM_FORMAT_ARGB8888,
89 DRM_FORMAT_XRGB8888,
90 DRM_FORMAT_ABGR8888,
91 DRM_FORMAT_XBGR8888,
92 DRM_FORMAT_RGBA8888,
93 DRM_FORMAT_RGBX8888,
94 DRM_FORMAT_BGRA8888,
95 DRM_FORMAT_BGRX8888,
96 DRM_FORMAT_RGB565,
97 DRM_FORMAT_RGB565_A8,
98 DRM_FORMAT_BGR565_A8,
99 DRM_FORMAT_RGB888_A8,
100 DRM_FORMAT_BGR888_A8,
101 DRM_FORMAT_RGBX8888_A8,
102 DRM_FORMAT_BGRX8888_A8,
103 };
104
105 static const uint64_t ipu_format_modifiers[] = {
106 DRM_FORMAT_MOD_LINEAR,
107 DRM_FORMAT_MOD_INVALID
108 };
109
110 static const uint64_t pre_format_modifiers[] = {
111 DRM_FORMAT_MOD_LINEAR,
112 DRM_FORMAT_MOD_VIVANTE_TILED,
113 DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
114 DRM_FORMAT_MOD_INVALID
115 };
116
ipu_plane_irq(struct ipu_plane * ipu_plane)117 int ipu_plane_irq(struct ipu_plane *ipu_plane)
118 {
119 return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
120 IPU_IRQ_EOF);
121 }
122
123 static inline unsigned long
drm_plane_state_to_eba(struct drm_plane_state * state,int plane)124 drm_plane_state_to_eba(struct drm_plane_state *state, int plane)
125 {
126 struct drm_framebuffer *fb = state->fb;
127 struct drm_gem_cma_object *cma_obj;
128 int x = state->src.x1 >> 16;
129 int y = state->src.y1 >> 16;
130
131 cma_obj = drm_fb_cma_get_gem_obj(fb, plane);
132 BUG_ON(!cma_obj);
133
134 return cma_obj->paddr + fb->offsets[plane] + fb->pitches[plane] * y +
135 fb->format->cpp[plane] * x;
136 }
137
138 static inline unsigned long
drm_plane_state_to_ubo(struct drm_plane_state * state)139 drm_plane_state_to_ubo(struct drm_plane_state *state)
140 {
141 struct drm_framebuffer *fb = state->fb;
142 struct drm_gem_cma_object *cma_obj;
143 unsigned long eba = drm_plane_state_to_eba(state, 0);
144 int x = state->src.x1 >> 16;
145 int y = state->src.y1 >> 16;
146
147 cma_obj = drm_fb_cma_get_gem_obj(fb, 1);
148 BUG_ON(!cma_obj);
149
150 x /= fb->format->hsub;
151 y /= fb->format->vsub;
152
153 return cma_obj->paddr + fb->offsets[1] + fb->pitches[1] * y +
154 fb->format->cpp[1] * x - eba;
155 }
156
157 static inline unsigned long
drm_plane_state_to_vbo(struct drm_plane_state * state)158 drm_plane_state_to_vbo(struct drm_plane_state *state)
159 {
160 struct drm_framebuffer *fb = state->fb;
161 struct drm_gem_cma_object *cma_obj;
162 unsigned long eba = drm_plane_state_to_eba(state, 0);
163 int x = state->src.x1 >> 16;
164 int y = state->src.y1 >> 16;
165
166 cma_obj = drm_fb_cma_get_gem_obj(fb, 2);
167 BUG_ON(!cma_obj);
168
169 x /= fb->format->hsub;
170 y /= fb->format->vsub;
171
172 return cma_obj->paddr + fb->offsets[2] + fb->pitches[2] * y +
173 fb->format->cpp[2] * x - eba;
174 }
175
ipu_plane_put_resources(struct drm_device * dev,void * ptr)176 static void ipu_plane_put_resources(struct drm_device *dev, void *ptr)
177 {
178 struct ipu_plane *ipu_plane = ptr;
179
180 if (!IS_ERR_OR_NULL(ipu_plane->dp))
181 ipu_dp_put(ipu_plane->dp);
182 if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
183 ipu_dmfc_put(ipu_plane->dmfc);
184 if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
185 ipu_idmac_put(ipu_plane->ipu_ch);
186 if (!IS_ERR_OR_NULL(ipu_plane->alpha_ch))
187 ipu_idmac_put(ipu_plane->alpha_ch);
188 }
189
ipu_plane_get_resources(struct drm_device * dev,struct ipu_plane * ipu_plane)190 static int ipu_plane_get_resources(struct drm_device *dev,
191 struct ipu_plane *ipu_plane)
192 {
193 int ret;
194 int alpha_ch;
195
196 ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
197 if (IS_ERR(ipu_plane->ipu_ch)) {
198 ret = PTR_ERR(ipu_plane->ipu_ch);
199 DRM_ERROR("failed to get idmac channel: %d\n", ret);
200 return ret;
201 }
202
203 ret = drmm_add_action_or_reset(dev, ipu_plane_put_resources, ipu_plane);
204 if (ret)
205 return ret;
206
207 alpha_ch = ipu_channel_alpha_channel(ipu_plane->dma);
208 if (alpha_ch >= 0) {
209 ipu_plane->alpha_ch = ipu_idmac_get(ipu_plane->ipu, alpha_ch);
210 if (IS_ERR(ipu_plane->alpha_ch)) {
211 ret = PTR_ERR(ipu_plane->alpha_ch);
212 DRM_ERROR("failed to get alpha idmac channel %d: %d\n",
213 alpha_ch, ret);
214 return ret;
215 }
216 }
217
218 ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
219 if (IS_ERR(ipu_plane->dmfc)) {
220 ret = PTR_ERR(ipu_plane->dmfc);
221 DRM_ERROR("failed to get dmfc: ret %d\n", ret);
222 return ret;
223 }
224
225 if (ipu_plane->dp_flow >= 0) {
226 ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
227 if (IS_ERR(ipu_plane->dp)) {
228 ret = PTR_ERR(ipu_plane->dp);
229 DRM_ERROR("failed to get dp flow: %d\n", ret);
230 return ret;
231 }
232 }
233
234 return 0;
235 }
236
ipu_plane_separate_alpha(struct ipu_plane * ipu_plane)237 static bool ipu_plane_separate_alpha(struct ipu_plane *ipu_plane)
238 {
239 switch (ipu_plane->base.state->fb->format->format) {
240 case DRM_FORMAT_RGB565_A8:
241 case DRM_FORMAT_BGR565_A8:
242 case DRM_FORMAT_RGB888_A8:
243 case DRM_FORMAT_BGR888_A8:
244 case DRM_FORMAT_RGBX8888_A8:
245 case DRM_FORMAT_BGRX8888_A8:
246 return true;
247 default:
248 return false;
249 }
250 }
251
ipu_plane_enable(struct ipu_plane * ipu_plane)252 static void ipu_plane_enable(struct ipu_plane *ipu_plane)
253 {
254 if (ipu_plane->dp)
255 ipu_dp_enable(ipu_plane->ipu);
256 ipu_dmfc_enable_channel(ipu_plane->dmfc);
257 ipu_idmac_enable_channel(ipu_plane->ipu_ch);
258 if (ipu_plane_separate_alpha(ipu_plane))
259 ipu_idmac_enable_channel(ipu_plane->alpha_ch);
260 if (ipu_plane->dp)
261 ipu_dp_enable_channel(ipu_plane->dp);
262 }
263
ipu_plane_disable(struct ipu_plane * ipu_plane,bool disable_dp_channel)264 void ipu_plane_disable(struct ipu_plane *ipu_plane, bool disable_dp_channel)
265 {
266 int ret;
267
268 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
269
270 ret = ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
271 if (ret == -ETIMEDOUT) {
272 DRM_ERROR("[PLANE:%d] IDMAC timeout\n",
273 ipu_plane->base.base.id);
274 }
275
276 if (ipu_plane->dp && disable_dp_channel)
277 ipu_dp_disable_channel(ipu_plane->dp, false);
278 ipu_idmac_disable_channel(ipu_plane->ipu_ch);
279 if (ipu_plane->alpha_ch)
280 ipu_idmac_disable_channel(ipu_plane->alpha_ch);
281 ipu_dmfc_disable_channel(ipu_plane->dmfc);
282 if (ipu_plane->dp)
283 ipu_dp_disable(ipu_plane->ipu);
284 if (ipu_prg_present(ipu_plane->ipu))
285 ipu_prg_channel_disable(ipu_plane->ipu_ch);
286 }
287
ipu_plane_disable_deferred(struct drm_plane * plane)288 void ipu_plane_disable_deferred(struct drm_plane *plane)
289 {
290 struct ipu_plane *ipu_plane = to_ipu_plane(plane);
291
292 if (ipu_plane->disabling) {
293 ipu_plane->disabling = false;
294 ipu_plane_disable(ipu_plane, false);
295 }
296 }
297
ipu_plane_state_reset(struct drm_plane * plane)298 static void ipu_plane_state_reset(struct drm_plane *plane)
299 {
300 struct ipu_plane_state *ipu_state;
301
302 if (plane->state) {
303 ipu_state = to_ipu_plane_state(plane->state);
304 __drm_atomic_helper_plane_destroy_state(plane->state);
305 kfree(ipu_state);
306 plane->state = NULL;
307 }
308
309 ipu_state = kzalloc(sizeof(*ipu_state), GFP_KERNEL);
310
311 if (ipu_state)
312 __drm_atomic_helper_plane_reset(plane, &ipu_state->base);
313 }
314
315 static struct drm_plane_state *
ipu_plane_duplicate_state(struct drm_plane * plane)316 ipu_plane_duplicate_state(struct drm_plane *plane)
317 {
318 struct ipu_plane_state *state;
319
320 if (WARN_ON(!plane->state))
321 return NULL;
322
323 state = kmalloc(sizeof(*state), GFP_KERNEL);
324 if (state)
325 __drm_atomic_helper_plane_duplicate_state(plane, &state->base);
326
327 return &state->base;
328 }
329
ipu_plane_destroy_state(struct drm_plane * plane,struct drm_plane_state * state)330 static void ipu_plane_destroy_state(struct drm_plane *plane,
331 struct drm_plane_state *state)
332 {
333 struct ipu_plane_state *ipu_state = to_ipu_plane_state(state);
334
335 __drm_atomic_helper_plane_destroy_state(state);
336 kfree(ipu_state);
337 }
338
ipu_plane_format_mod_supported(struct drm_plane * plane,uint32_t format,uint64_t modifier)339 static bool ipu_plane_format_mod_supported(struct drm_plane *plane,
340 uint32_t format, uint64_t modifier)
341 {
342 struct ipu_soc *ipu = to_ipu_plane(plane)->ipu;
343
344 /* linear is supported for all planes and formats */
345 if (modifier == DRM_FORMAT_MOD_LINEAR)
346 return true;
347
348 /*
349 * Without a PRG the possible modifiers list only includes the linear
350 * modifier, so we always take the early return from this function and
351 * only end up here if the PRG is present.
352 */
353 return ipu_prg_format_supported(ipu, format, modifier);
354 }
355
356 static const struct drm_plane_funcs ipu_plane_funcs = {
357 .update_plane = drm_atomic_helper_update_plane,
358 .disable_plane = drm_atomic_helper_disable_plane,
359 .reset = ipu_plane_state_reset,
360 .atomic_duplicate_state = ipu_plane_duplicate_state,
361 .atomic_destroy_state = ipu_plane_destroy_state,
362 .format_mod_supported = ipu_plane_format_mod_supported,
363 };
364
ipu_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)365 static int ipu_plane_atomic_check(struct drm_plane *plane,
366 struct drm_atomic_state *state)
367 {
368 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
369 plane);
370 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
371 plane);
372 struct drm_crtc_state *crtc_state;
373 struct device *dev = plane->dev->dev;
374 struct drm_framebuffer *fb = new_state->fb;
375 struct drm_framebuffer *old_fb = old_state->fb;
376 unsigned long eba, ubo, vbo, old_ubo, old_vbo, alpha_eba;
377 bool can_position = (plane->type == DRM_PLANE_TYPE_OVERLAY);
378 int ret;
379
380 /* Ok to disable */
381 if (!fb)
382 return 0;
383
384 if (WARN_ON(!new_state->crtc))
385 return -EINVAL;
386
387 crtc_state =
388 drm_atomic_get_existing_crtc_state(state,
389 new_state->crtc);
390 if (WARN_ON(!crtc_state))
391 return -EINVAL;
392
393 ret = drm_atomic_helper_check_plane_state(new_state, crtc_state,
394 DRM_PLANE_HELPER_NO_SCALING,
395 DRM_PLANE_HELPER_NO_SCALING,
396 can_position, true);
397 if (ret)
398 return ret;
399
400 /* nothing to check when disabling or disabled */
401 if (!crtc_state->enable)
402 return 0;
403
404 switch (plane->type) {
405 case DRM_PLANE_TYPE_PRIMARY:
406 /* full plane minimum width is 13 pixels */
407 if (drm_rect_width(&new_state->dst) < 13)
408 return -EINVAL;
409 break;
410 case DRM_PLANE_TYPE_OVERLAY:
411 break;
412 default:
413 dev_warn(dev, "Unsupported plane type %d\n", plane->type);
414 return -EINVAL;
415 }
416
417 if (drm_rect_height(&new_state->dst) < 2)
418 return -EINVAL;
419
420 /*
421 * We support resizing active plane or changing its format by
422 * forcing CRTC mode change in plane's ->atomic_check callback
423 * and disabling all affected active planes in CRTC's ->atomic_disable
424 * callback. The planes will be reenabled in plane's ->atomic_update
425 * callback.
426 */
427 if (old_fb &&
428 (drm_rect_width(&new_state->dst) != drm_rect_width(&old_state->dst) ||
429 drm_rect_height(&new_state->dst) != drm_rect_height(&old_state->dst) ||
430 fb->format != old_fb->format))
431 crtc_state->mode_changed = true;
432
433 eba = drm_plane_state_to_eba(new_state, 0);
434
435 if (eba & 0x7)
436 return -EINVAL;
437
438 if (fb->pitches[0] < 1 || fb->pitches[0] > 16384)
439 return -EINVAL;
440
441 if (old_fb && fb->pitches[0] != old_fb->pitches[0])
442 crtc_state->mode_changed = true;
443
444 if (ALIGN(fb->width, 8) * fb->format->cpp[0] >
445 fb->pitches[0] + fb->offsets[0]) {
446 dev_warn(dev, "pitch is not big enough for 8 pixels alignment");
447 return -EINVAL;
448 }
449
450 switch (fb->format->format) {
451 case DRM_FORMAT_YUV420:
452 case DRM_FORMAT_YVU420:
453 case DRM_FORMAT_YUV422:
454 case DRM_FORMAT_YVU422:
455 case DRM_FORMAT_YUV444:
456 case DRM_FORMAT_YVU444:
457 /*
458 * Multiplanar formats have to meet the following restrictions:
459 * - The (up to) three plane addresses are EBA, EBA+UBO, EBA+VBO
460 * - EBA, UBO and VBO are a multiple of 8
461 * - UBO and VBO are unsigned and not larger than 0xfffff8
462 * - Only EBA may be changed while scanout is active
463 * - The strides of U and V planes must be identical.
464 */
465 vbo = drm_plane_state_to_vbo(new_state);
466
467 if (vbo & 0x7 || vbo > 0xfffff8)
468 return -EINVAL;
469
470 if (old_fb && (fb->format == old_fb->format)) {
471 old_vbo = drm_plane_state_to_vbo(old_state);
472 if (vbo != old_vbo)
473 crtc_state->mode_changed = true;
474 }
475
476 if (fb->pitches[1] != fb->pitches[2])
477 return -EINVAL;
478
479 fallthrough;
480 case DRM_FORMAT_NV12:
481 case DRM_FORMAT_NV16:
482 ubo = drm_plane_state_to_ubo(new_state);
483
484 if (ubo & 0x7 || ubo > 0xfffff8)
485 return -EINVAL;
486
487 if (old_fb && (fb->format == old_fb->format)) {
488 old_ubo = drm_plane_state_to_ubo(old_state);
489 if (ubo != old_ubo)
490 crtc_state->mode_changed = true;
491 }
492
493 if (fb->pitches[1] < 1 || fb->pitches[1] > 16384)
494 return -EINVAL;
495
496 if (old_fb && old_fb->pitches[1] != fb->pitches[1])
497 crtc_state->mode_changed = true;
498
499 /*
500 * The x/y offsets must be even in case of horizontal/vertical
501 * chroma subsampling.
502 */
503 if (((new_state->src.x1 >> 16) & (fb->format->hsub - 1)) ||
504 ((new_state->src.y1 >> 16) & (fb->format->vsub - 1)))
505 return -EINVAL;
506 break;
507 case DRM_FORMAT_RGB565_A8:
508 case DRM_FORMAT_BGR565_A8:
509 case DRM_FORMAT_RGB888_A8:
510 case DRM_FORMAT_BGR888_A8:
511 case DRM_FORMAT_RGBX8888_A8:
512 case DRM_FORMAT_BGRX8888_A8:
513 alpha_eba = drm_plane_state_to_eba(new_state, 1);
514 if (alpha_eba & 0x7)
515 return -EINVAL;
516
517 if (fb->pitches[1] < 1 || fb->pitches[1] > 16384)
518 return -EINVAL;
519
520 if (old_fb && old_fb->pitches[1] != fb->pitches[1])
521 crtc_state->mode_changed = true;
522 break;
523 }
524
525 return 0;
526 }
527
ipu_plane_atomic_disable(struct drm_plane * plane,struct drm_atomic_state * state)528 static void ipu_plane_atomic_disable(struct drm_plane *plane,
529 struct drm_atomic_state *state)
530 {
531 struct ipu_plane *ipu_plane = to_ipu_plane(plane);
532
533 if (ipu_plane->dp)
534 ipu_dp_disable_channel(ipu_plane->dp, true);
535 ipu_plane->disabling = true;
536 }
537
ipu_chan_assign_axi_id(int ipu_chan)538 static int ipu_chan_assign_axi_id(int ipu_chan)
539 {
540 switch (ipu_chan) {
541 case IPUV3_CHANNEL_MEM_BG_SYNC:
542 return 1;
543 case IPUV3_CHANNEL_MEM_FG_SYNC:
544 return 2;
545 case IPUV3_CHANNEL_MEM_DC_SYNC:
546 return 3;
547 default:
548 return 0;
549 }
550 }
551
ipu_calculate_bursts(u32 width,u32 cpp,u32 stride,u8 * burstsize,u8 * num_bursts)552 static void ipu_calculate_bursts(u32 width, u32 cpp, u32 stride,
553 u8 *burstsize, u8 *num_bursts)
554 {
555 const unsigned int width_bytes = width * cpp;
556 unsigned int npb, bursts;
557
558 /* Maximum number of pixels per burst without overshooting stride */
559 for (npb = 64 / cpp; npb > 0; --npb) {
560 if (round_up(width_bytes, npb * cpp) <= stride)
561 break;
562 }
563 *burstsize = npb;
564
565 /* Maximum number of consecutive bursts without overshooting stride */
566 for (bursts = 8; bursts > 1; bursts /= 2) {
567 if (round_up(width_bytes, npb * cpp * bursts) <= stride)
568 break;
569 }
570 *num_bursts = bursts;
571 }
572
ipu_plane_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)573 static void ipu_plane_atomic_update(struct drm_plane *plane,
574 struct drm_atomic_state *state)
575 {
576 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
577 plane);
578 struct ipu_plane *ipu_plane = to_ipu_plane(plane);
579 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
580 plane);
581 struct ipu_plane_state *ipu_state = to_ipu_plane_state(new_state);
582 struct drm_crtc_state *crtc_state = new_state->crtc->state;
583 struct drm_framebuffer *fb = new_state->fb;
584 struct drm_rect *dst = &new_state->dst;
585 unsigned long eba, ubo, vbo;
586 unsigned long alpha_eba = 0;
587 enum ipu_color_space ics;
588 unsigned int axi_id = 0;
589 const struct drm_format_info *info;
590 u8 burstsize, num_bursts;
591 u32 width, height;
592 int active;
593
594 if (ipu_plane->dp_flow == IPU_DP_FLOW_SYNC_FG)
595 ipu_dp_set_window_pos(ipu_plane->dp, dst->x1, dst->y1);
596
597 switch (ipu_plane->dp_flow) {
598 case IPU_DP_FLOW_SYNC_BG:
599 if (new_state->normalized_zpos == 1) {
600 ipu_dp_set_global_alpha(ipu_plane->dp,
601 !fb->format->has_alpha, 0xff,
602 true);
603 } else {
604 ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true);
605 }
606 break;
607 case IPU_DP_FLOW_SYNC_FG:
608 if (new_state->normalized_zpos == 1) {
609 ipu_dp_set_global_alpha(ipu_plane->dp,
610 !fb->format->has_alpha, 0xff,
611 false);
612 }
613 break;
614 }
615
616 eba = drm_plane_state_to_eba(new_state, 0);
617
618 /*
619 * Configure PRG channel and attached PRE, this changes the EBA to an
620 * internal SRAM location.
621 */
622 if (ipu_state->use_pre) {
623 axi_id = ipu_chan_assign_axi_id(ipu_plane->dma);
624 ipu_prg_channel_configure(ipu_plane->ipu_ch, axi_id,
625 ipu_src_rect_width(new_state),
626 drm_rect_height(&new_state->src) >> 16,
627 fb->pitches[0], fb->format->format,
628 fb->modifier, &eba);
629 }
630
631 if (!old_state->fb ||
632 old_state->fb->format->format != fb->format->format ||
633 old_state->color_encoding != new_state->color_encoding ||
634 old_state->color_range != new_state->color_range) {
635 ics = ipu_drm_fourcc_to_colorspace(fb->format->format);
636 switch (ipu_plane->dp_flow) {
637 case IPU_DP_FLOW_SYNC_BG:
638 ipu_dp_setup_channel(ipu_plane->dp, new_state->color_encoding,
639 new_state->color_range, ics,
640 IPUV3_COLORSPACE_RGB);
641 break;
642 case IPU_DP_FLOW_SYNC_FG:
643 ipu_dp_setup_channel(ipu_plane->dp, new_state->color_encoding,
644 new_state->color_range, ics,
645 IPUV3_COLORSPACE_UNKNOWN);
646 break;
647 }
648 }
649
650 if (old_state->fb && !drm_atomic_crtc_needs_modeset(crtc_state)) {
651 /* nothing to do if PRE is used */
652 if (ipu_state->use_pre)
653 return;
654 active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch);
655 ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba);
656 ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active);
657 if (ipu_plane_separate_alpha(ipu_plane)) {
658 active = ipu_idmac_get_current_buffer(ipu_plane->alpha_ch);
659 ipu_cpmem_set_buffer(ipu_plane->alpha_ch, !active,
660 alpha_eba);
661 ipu_idmac_select_buffer(ipu_plane->alpha_ch, !active);
662 }
663 return;
664 }
665
666 ics = ipu_drm_fourcc_to_colorspace(fb->format->format);
667 switch (ipu_plane->dp_flow) {
668 case IPU_DP_FLOW_SYNC_BG:
669 ipu_dp_setup_channel(ipu_plane->dp, DRM_COLOR_YCBCR_BT601,
670 DRM_COLOR_YCBCR_LIMITED_RANGE, ics,
671 IPUV3_COLORSPACE_RGB);
672 break;
673 case IPU_DP_FLOW_SYNC_FG:
674 ipu_dp_setup_channel(ipu_plane->dp, DRM_COLOR_YCBCR_BT601,
675 DRM_COLOR_YCBCR_LIMITED_RANGE, ics,
676 IPUV3_COLORSPACE_UNKNOWN);
677 break;
678 }
679
680 ipu_dmfc_config_wait4eot(ipu_plane->dmfc, ALIGN(drm_rect_width(dst), 8));
681
682 width = ipu_src_rect_width(new_state);
683 height = drm_rect_height(&new_state->src) >> 16;
684 info = drm_format_info(fb->format->format);
685 ipu_calculate_bursts(width, info->cpp[0], fb->pitches[0],
686 &burstsize, &num_bursts);
687
688 ipu_cpmem_zero(ipu_plane->ipu_ch);
689 ipu_cpmem_set_resolution(ipu_plane->ipu_ch, width, height);
690 ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->format->format);
691 ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, burstsize);
692 ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
693 ipu_idmac_enable_watermark(ipu_plane->ipu_ch, true);
694 ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1);
695 ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]);
696 ipu_cpmem_set_axi_id(ipu_plane->ipu_ch, axi_id);
697
698 switch (fb->format->format) {
699 case DRM_FORMAT_YUV420:
700 case DRM_FORMAT_YVU420:
701 case DRM_FORMAT_YUV422:
702 case DRM_FORMAT_YVU422:
703 case DRM_FORMAT_YUV444:
704 case DRM_FORMAT_YVU444:
705 ubo = drm_plane_state_to_ubo(new_state);
706 vbo = drm_plane_state_to_vbo(new_state);
707 if (fb->format->format == DRM_FORMAT_YVU420 ||
708 fb->format->format == DRM_FORMAT_YVU422 ||
709 fb->format->format == DRM_FORMAT_YVU444)
710 swap(ubo, vbo);
711
712 ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
713 fb->pitches[1], ubo, vbo);
714
715 dev_dbg(ipu_plane->base.dev->dev,
716 "phy = %lu %lu %lu, x = %d, y = %d", eba, ubo, vbo,
717 new_state->src.x1 >> 16, new_state->src.y1 >> 16);
718 break;
719 case DRM_FORMAT_NV12:
720 case DRM_FORMAT_NV16:
721 ubo = drm_plane_state_to_ubo(new_state);
722
723 ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
724 fb->pitches[1], ubo, ubo);
725
726 dev_dbg(ipu_plane->base.dev->dev,
727 "phy = %lu %lu, x = %d, y = %d", eba, ubo,
728 new_state->src.x1 >> 16, new_state->src.y1 >> 16);
729 break;
730 case DRM_FORMAT_RGB565_A8:
731 case DRM_FORMAT_BGR565_A8:
732 case DRM_FORMAT_RGB888_A8:
733 case DRM_FORMAT_BGR888_A8:
734 case DRM_FORMAT_RGBX8888_A8:
735 case DRM_FORMAT_BGRX8888_A8:
736 alpha_eba = drm_plane_state_to_eba(new_state, 1);
737 num_bursts = 0;
738
739 dev_dbg(ipu_plane->base.dev->dev, "phys = %lu %lu, x = %d, y = %d",
740 eba, alpha_eba, new_state->src.x1 >> 16,
741 new_state->src.y1 >> 16);
742
743 ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, 16);
744
745 ipu_cpmem_zero(ipu_plane->alpha_ch);
746 ipu_cpmem_set_resolution(ipu_plane->alpha_ch,
747 ipu_src_rect_width(new_state),
748 drm_rect_height(&new_state->src) >> 16);
749 ipu_cpmem_set_format_passthrough(ipu_plane->alpha_ch, 8);
750 ipu_cpmem_set_high_priority(ipu_plane->alpha_ch);
751 ipu_idmac_set_double_buffer(ipu_plane->alpha_ch, 1);
752 ipu_cpmem_set_stride(ipu_plane->alpha_ch, fb->pitches[1]);
753 ipu_cpmem_set_burstsize(ipu_plane->alpha_ch, 16);
754 ipu_cpmem_set_buffer(ipu_plane->alpha_ch, 0, alpha_eba);
755 ipu_cpmem_set_buffer(ipu_plane->alpha_ch, 1, alpha_eba);
756 break;
757 default:
758 dev_dbg(ipu_plane->base.dev->dev, "phys = %lu, x = %d, y = %d",
759 eba, new_state->src.x1 >> 16, new_state->src.y1 >> 16);
760 break;
761 }
762 ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba);
763 ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);
764 ipu_idmac_lock_enable(ipu_plane->ipu_ch, num_bursts);
765 ipu_plane_enable(ipu_plane);
766 }
767
768 static const struct drm_plane_helper_funcs ipu_plane_helper_funcs = {
769 .atomic_check = ipu_plane_atomic_check,
770 .atomic_disable = ipu_plane_atomic_disable,
771 .atomic_update = ipu_plane_atomic_update,
772 };
773
ipu_plane_atomic_update_pending(struct drm_plane * plane)774 bool ipu_plane_atomic_update_pending(struct drm_plane *plane)
775 {
776 struct ipu_plane *ipu_plane = to_ipu_plane(plane);
777 struct drm_plane_state *state = plane->state;
778 struct ipu_plane_state *ipu_state = to_ipu_plane_state(state);
779
780 /* disabled crtcs must not block the update */
781 if (!state->crtc)
782 return false;
783
784 if (ipu_state->use_pre)
785 return ipu_prg_channel_configure_pending(ipu_plane->ipu_ch);
786
787 /*
788 * Pretend no update is pending in the non-PRE/PRG case. For this to
789 * happen, an atomic update would have to be deferred until after the
790 * start of the next frame and simultaneously interrupt latency would
791 * have to be high enough to let the atomic update finish and issue an
792 * event before the previous end of frame interrupt handler can be
793 * executed.
794 */
795 return false;
796 }
ipu_planes_assign_pre(struct drm_device * dev,struct drm_atomic_state * state)797 int ipu_planes_assign_pre(struct drm_device *dev,
798 struct drm_atomic_state *state)
799 {
800 struct drm_crtc_state *old_crtc_state, *crtc_state;
801 struct drm_plane_state *plane_state;
802 struct ipu_plane_state *ipu_state;
803 struct ipu_plane *ipu_plane;
804 struct drm_plane *plane;
805 struct drm_crtc *crtc;
806 int available_pres = ipu_prg_max_active_channels();
807 int ret, i;
808
809 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
810 ret = drm_atomic_add_affected_planes(state, crtc);
811 if (ret)
812 return ret;
813 }
814
815 /*
816 * We are going over the planes in 2 passes: first we assign PREs to
817 * planes with a tiling modifier, which need the PREs to resolve into
818 * linear. Any failure to assign a PRE there is fatal. In the second
819 * pass we try to assign PREs to linear FBs, to improve memory access
820 * patterns for them. Failure at this point is non-fatal, as we can
821 * scan out linear FBs without a PRE.
822 */
823 for_each_new_plane_in_state(state, plane, plane_state, i) {
824 ipu_state = to_ipu_plane_state(plane_state);
825 ipu_plane = to_ipu_plane(plane);
826
827 if (!plane_state->fb) {
828 ipu_state->use_pre = false;
829 continue;
830 }
831
832 if (!(plane_state->fb->flags & DRM_MODE_FB_MODIFIERS) ||
833 plane_state->fb->modifier == DRM_FORMAT_MOD_LINEAR)
834 continue;
835
836 if (!ipu_prg_present(ipu_plane->ipu) || !available_pres)
837 return -EINVAL;
838
839 if (!ipu_prg_format_supported(ipu_plane->ipu,
840 plane_state->fb->format->format,
841 plane_state->fb->modifier))
842 return -EINVAL;
843
844 ipu_state->use_pre = true;
845 available_pres--;
846 }
847
848 for_each_new_plane_in_state(state, plane, plane_state, i) {
849 ipu_state = to_ipu_plane_state(plane_state);
850 ipu_plane = to_ipu_plane(plane);
851
852 if (!plane_state->fb) {
853 ipu_state->use_pre = false;
854 continue;
855 }
856
857 if ((plane_state->fb->flags & DRM_MODE_FB_MODIFIERS) &&
858 plane_state->fb->modifier != DRM_FORMAT_MOD_LINEAR)
859 continue;
860
861 /* make sure that modifier is initialized */
862 plane_state->fb->modifier = DRM_FORMAT_MOD_LINEAR;
863
864 if (ipu_prg_present(ipu_plane->ipu) && available_pres &&
865 ipu_prg_format_supported(ipu_plane->ipu,
866 plane_state->fb->format->format,
867 plane_state->fb->modifier)) {
868 ipu_state->use_pre = true;
869 available_pres--;
870 } else {
871 ipu_state->use_pre = false;
872 }
873 }
874
875 return 0;
876 }
877
ipu_plane_init(struct drm_device * dev,struct ipu_soc * ipu,int dma,int dp,unsigned int possible_crtcs,enum drm_plane_type type)878 struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
879 int dma, int dp, unsigned int possible_crtcs,
880 enum drm_plane_type type)
881 {
882 struct ipu_plane *ipu_plane;
883 const uint64_t *modifiers = ipu_format_modifiers;
884 unsigned int zpos = (type == DRM_PLANE_TYPE_PRIMARY) ? 0 : 1;
885 unsigned int format_count;
886 const uint32_t *formats;
887 int ret;
888
889 DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
890 dma, dp, possible_crtcs);
891
892 if (dp == IPU_DP_FLOW_SYNC_BG || dp == IPU_DP_FLOW_SYNC_FG) {
893 formats = ipu_plane_all_formats;
894 format_count = ARRAY_SIZE(ipu_plane_all_formats);
895 } else {
896 formats = ipu_plane_rgb_formats;
897 format_count = ARRAY_SIZE(ipu_plane_rgb_formats);
898 }
899
900 if (ipu_prg_present(ipu))
901 modifiers = pre_format_modifiers;
902
903 ipu_plane = drmm_universal_plane_alloc(dev, struct ipu_plane, base,
904 possible_crtcs, &ipu_plane_funcs,
905 formats, format_count, modifiers,
906 type, NULL);
907 if (IS_ERR(ipu_plane)) {
908 DRM_ERROR("failed to allocate and initialize %s plane\n",
909 zpos ? "overlay" : "primary");
910 return ipu_plane;
911 }
912
913 ipu_plane->ipu = ipu;
914 ipu_plane->dma = dma;
915 ipu_plane->dp_flow = dp;
916
917 drm_plane_helper_add(&ipu_plane->base, &ipu_plane_helper_funcs);
918
919 if (dp == IPU_DP_FLOW_SYNC_BG || dp == IPU_DP_FLOW_SYNC_FG)
920 ret = drm_plane_create_zpos_property(&ipu_plane->base, zpos, 0,
921 1);
922 else
923 ret = drm_plane_create_zpos_immutable_property(&ipu_plane->base,
924 0);
925 if (ret)
926 return ERR_PTR(ret);
927
928 ret = drm_plane_create_color_properties(&ipu_plane->base,
929 BIT(DRM_COLOR_YCBCR_BT601) |
930 BIT(DRM_COLOR_YCBCR_BT709),
931 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE),
932 DRM_COLOR_YCBCR_BT601,
933 DRM_COLOR_YCBCR_LIMITED_RANGE);
934 if (ret)
935 return ERR_PTR(ret);
936
937 ret = ipu_plane_get_resources(dev, ipu_plane);
938 if (ret) {
939 DRM_ERROR("failed to get %s plane resources: %pe\n",
940 zpos ? "overlay" : "primary", &ret);
941 return ERR_PTR(ret);
942 }
943
944 return ipu_plane;
945 }
946