1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #ifndef __RTL_WIFI_H__
31 #define __RTL_WIFI_H__
32
33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
35 #include <linux/sched.h>
36 #include <linux/firmware.h>
37 #include <linux/etherdevice.h>
38 #include <linux/vmalloc.h>
39 #include <linux/usb.h>
40 #include <net/mac80211.h>
41 #include <linux/completion.h>
42 #include "debug.h"
43
44 #define RF_CHANGE_BY_INIT 0
45 #define RF_CHANGE_BY_IPS BIT(28)
46 #define RF_CHANGE_BY_PS BIT(29)
47 #define RF_CHANGE_BY_HW BIT(30)
48 #define RF_CHANGE_BY_SW BIT(31)
49
50 #define IQK_ADDA_REG_NUM 16
51 #define IQK_MAC_REG_NUM 4
52
53 #define MAX_KEY_LEN 61
54 #define KEY_BUF_SIZE 5
55
56 /* QoS related. */
57 /*aci: 0x00 Best Effort*/
58 /*aci: 0x01 Background*/
59 /*aci: 0x10 Video*/
60 /*aci: 0x11 Voice*/
61 /*Max: define total number.*/
62 #define AC0_BE 0
63 #define AC1_BK 1
64 #define AC2_VI 2
65 #define AC3_VO 3
66 #define AC_MAX 4
67 #define QOS_QUEUE_NUM 4
68 #define RTL_MAC80211_NUM_QUEUE 5
69 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
70 #define RTL_USB_MAX_RX_COUNT 100
71 #define QBSS_LOAD_SIZE 5
72 #define MAX_WMMELE_LENGTH 64
73
74 #define TOTAL_CAM_ENTRY 32
75
76 /*slot time for 11g. */
77 #define RTL_SLOT_TIME_9 9
78 #define RTL_SLOT_TIME_20 20
79
80 /*related to tcp/ip. */
81 #define SNAP_SIZE 6
82 #define PROTOC_TYPE_SIZE 2
83
84 /*related with 802.11 frame*/
85 #define MAC80211_3ADDR_LEN 24
86 #define MAC80211_4ADDR_LEN 30
87
88 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
89 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
90 #define MAX_PG_GROUP 13
91 #define CHANNEL_GROUP_MAX_2G 3
92 #define CHANNEL_GROUP_IDX_5GL 3
93 #define CHANNEL_GROUP_IDX_5GM 6
94 #define CHANNEL_GROUP_IDX_5GH 9
95 #define CHANNEL_GROUP_MAX_5G 9
96 #define CHANNEL_MAX_NUMBER_2G 14
97 #define AVG_THERMAL_NUM 8
98 #define MAX_TID_COUNT 9
99
100 /* for early mode */
101 #define FCS_LEN 4
102 #define EM_HDR_LEN 8
103 enum intf_type {
104 INTF_PCI = 0,
105 INTF_USB = 1,
106 };
107
108 enum radio_path {
109 RF90_PATH_A = 0,
110 RF90_PATH_B = 1,
111 RF90_PATH_C = 2,
112 RF90_PATH_D = 3,
113 };
114
115 enum rt_eeprom_type {
116 EEPROM_93C46,
117 EEPROM_93C56,
118 EEPROM_BOOT_EFUSE,
119 };
120
121 enum rtl_status {
122 RTL_STATUS_INTERFACE_START = 0,
123 };
124
125 enum hardware_type {
126 HARDWARE_TYPE_RTL8192E,
127 HARDWARE_TYPE_RTL8192U,
128 HARDWARE_TYPE_RTL8192SE,
129 HARDWARE_TYPE_RTL8192SU,
130 HARDWARE_TYPE_RTL8192CE,
131 HARDWARE_TYPE_RTL8192CU,
132 HARDWARE_TYPE_RTL8192DE,
133 HARDWARE_TYPE_RTL8192DU,
134 HARDWARE_TYPE_RTL8723E,
135 HARDWARE_TYPE_RTL8723U,
136
137 /* keep it last */
138 HARDWARE_TYPE_NUM
139 };
140
141 #define IS_HARDWARE_TYPE_8192SU(rtlhal) \
142 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
143 #define IS_HARDWARE_TYPE_8192SE(rtlhal) \
144 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
145 #define IS_HARDWARE_TYPE_8192CE(rtlhal) \
146 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
147 #define IS_HARDWARE_TYPE_8192CU(rtlhal) \
148 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
149 #define IS_HARDWARE_TYPE_8192DE(rtlhal) \
150 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
151 #define IS_HARDWARE_TYPE_8192DU(rtlhal) \
152 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
153 #define IS_HARDWARE_TYPE_8723E(rtlhal) \
154 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
155 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
156 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
157 #define IS_HARDWARE_TYPE_8192S(rtlhal) \
158 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
159 #define IS_HARDWARE_TYPE_8192C(rtlhal) \
160 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
161 #define IS_HARDWARE_TYPE_8192D(rtlhal) \
162 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
163 #define IS_HARDWARE_TYPE_8723(rtlhal) \
164 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
165 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
166 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
167
168 #define RX_HAL_IS_CCK_RATE(_pdesc)\
169 (_pdesc->rxmcs == DESC92_RATE1M || \
170 _pdesc->rxmcs == DESC92_RATE2M || \
171 _pdesc->rxmcs == DESC92_RATE5_5M || \
172 _pdesc->rxmcs == DESC92_RATE11M)
173
174 enum scan_operation_backup_opt {
175 SCAN_OPT_BACKUP = 0,
176 SCAN_OPT_RESTORE,
177 SCAN_OPT_MAX
178 };
179
180 /*RF state.*/
181 enum rf_pwrstate {
182 ERFON,
183 ERFSLEEP,
184 ERFOFF
185 };
186
187 struct bb_reg_def {
188 u32 rfintfs;
189 u32 rfintfi;
190 u32 rfintfo;
191 u32 rfintfe;
192 u32 rf3wire_offset;
193 u32 rflssi_select;
194 u32 rftxgain_stage;
195 u32 rfhssi_para1;
196 u32 rfhssi_para2;
197 u32 rfswitch_control;
198 u32 rfagc_control1;
199 u32 rfagc_control2;
200 u32 rfrxiq_imbalance;
201 u32 rfrx_afe;
202 u32 rftxiq_imbalance;
203 u32 rftx_afe;
204 u32 rflssi_readback;
205 u32 rflssi_readbackpi;
206 };
207
208 enum io_type {
209 IO_CMD_PAUSE_DM_BY_SCAN = 0,
210 IO_CMD_RESUME_DM_BY_SCAN = 1,
211 };
212
213 enum hw_variables {
214 HW_VAR_ETHER_ADDR,
215 HW_VAR_MULTICAST_REG,
216 HW_VAR_BASIC_RATE,
217 HW_VAR_BSSID,
218 HW_VAR_MEDIA_STATUS,
219 HW_VAR_SECURITY_CONF,
220 HW_VAR_BEACON_INTERVAL,
221 HW_VAR_ATIM_WINDOW,
222 HW_VAR_LISTEN_INTERVAL,
223 HW_VAR_CS_COUNTER,
224 HW_VAR_DEFAULTKEY0,
225 HW_VAR_DEFAULTKEY1,
226 HW_VAR_DEFAULTKEY2,
227 HW_VAR_DEFAULTKEY3,
228 HW_VAR_SIFS,
229 HW_VAR_DIFS,
230 HW_VAR_EIFS,
231 HW_VAR_SLOT_TIME,
232 HW_VAR_ACK_PREAMBLE,
233 HW_VAR_CW_CONFIG,
234 HW_VAR_CW_VALUES,
235 HW_VAR_RATE_FALLBACK_CONTROL,
236 HW_VAR_CONTENTION_WINDOW,
237 HW_VAR_RETRY_COUNT,
238 HW_VAR_TR_SWITCH,
239 HW_VAR_COMMAND,
240 HW_VAR_WPA_CONFIG,
241 HW_VAR_AMPDU_MIN_SPACE,
242 HW_VAR_SHORTGI_DENSITY,
243 HW_VAR_AMPDU_FACTOR,
244 HW_VAR_MCS_RATE_AVAILABLE,
245 HW_VAR_AC_PARAM,
246 HW_VAR_ACM_CTRL,
247 HW_VAR_DIS_Req_Qsize,
248 HW_VAR_CCX_CHNL_LOAD,
249 HW_VAR_CCX_NOISE_HISTOGRAM,
250 HW_VAR_CCX_CLM_NHM,
251 HW_VAR_TxOPLimit,
252 HW_VAR_TURBO_MODE,
253 HW_VAR_RF_STATE,
254 HW_VAR_RF_OFF_BY_HW,
255 HW_VAR_BUS_SPEED,
256 HW_VAR_SET_DEV_POWER,
257
258 HW_VAR_RCR,
259 HW_VAR_RATR_0,
260 HW_VAR_RRSR,
261 HW_VAR_CPU_RST,
262 HW_VAR_CECHK_BSSID,
263 HW_VAR_LBK_MODE,
264 HW_VAR_AES_11N_FIX,
265 HW_VAR_USB_RX_AGGR,
266 HW_VAR_USER_CONTROL_TURBO_MODE,
267 HW_VAR_RETRY_LIMIT,
268 HW_VAR_INIT_TX_RATE,
269 HW_VAR_TX_RATE_REG,
270 HW_VAR_EFUSE_USAGE,
271 HW_VAR_EFUSE_BYTES,
272 HW_VAR_AUTOLOAD_STATUS,
273 HW_VAR_RF_2R_DISABLE,
274 HW_VAR_SET_RPWM,
275 HW_VAR_H2C_FW_PWRMODE,
276 HW_VAR_H2C_FW_JOINBSSRPT,
277 HW_VAR_FW_PSMODE_STATUS,
278 HW_VAR_1X1_RECV_COMBINE,
279 HW_VAR_STOP_SEND_BEACON,
280 HW_VAR_TSF_TIMER,
281 HW_VAR_IO_CMD,
282
283 HW_VAR_RF_RECOVERY,
284 HW_VAR_H2C_FW_UPDATE_GTK,
285 HW_VAR_WF_MASK,
286 HW_VAR_WF_CRC,
287 HW_VAR_WF_IS_MAC_ADDR,
288 HW_VAR_H2C_FW_OFFLOAD,
289 HW_VAR_RESET_WFCRC,
290
291 HW_VAR_HANDLE_FW_C2H,
292 HW_VAR_DL_FW_RSVD_PAGE,
293 HW_VAR_AID,
294 HW_VAR_HW_SEQ_ENABLE,
295 HW_VAR_CORRECT_TSF,
296 HW_VAR_BCN_VALID,
297 HW_VAR_FWLPS_RF_ON,
298 HW_VAR_DUAL_TSF_RST,
299 HW_VAR_SWITCH_EPHY_WoWLAN,
300 HW_VAR_INT_MIGRATION,
301 HW_VAR_INT_AC,
302 HW_VAR_RF_TIMING,
303
304 HW_VAR_MRC,
305
306 HW_VAR_MGT_FILTER,
307 HW_VAR_CTRL_FILTER,
308 HW_VAR_DATA_FILTER,
309 };
310
311 enum _RT_MEDIA_STATUS {
312 RT_MEDIA_DISCONNECT = 0,
313 RT_MEDIA_CONNECT = 1
314 };
315
316 enum rt_oem_id {
317 RT_CID_DEFAULT = 0,
318 RT_CID_8187_ALPHA0 = 1,
319 RT_CID_8187_SERCOMM_PS = 2,
320 RT_CID_8187_HW_LED = 3,
321 RT_CID_8187_NETGEAR = 4,
322 RT_CID_WHQL = 5,
323 RT_CID_819x_CAMEO = 6,
324 RT_CID_819x_RUNTOP = 7,
325 RT_CID_819x_Senao = 8,
326 RT_CID_TOSHIBA = 9,
327 RT_CID_819x_Netcore = 10,
328 RT_CID_Nettronix = 11,
329 RT_CID_DLINK = 12,
330 RT_CID_PRONET = 13,
331 RT_CID_COREGA = 14,
332 RT_CID_819x_ALPHA = 15,
333 RT_CID_819x_Sitecom = 16,
334 RT_CID_CCX = 17,
335 RT_CID_819x_Lenovo = 18,
336 RT_CID_819x_QMI = 19,
337 RT_CID_819x_Edimax_Belkin = 20,
338 RT_CID_819x_Sercomm_Belkin = 21,
339 RT_CID_819x_CAMEO1 = 22,
340 RT_CID_819x_MSI = 23,
341 RT_CID_819x_Acer = 24,
342 RT_CID_819x_HP = 27,
343 RT_CID_819x_CLEVO = 28,
344 RT_CID_819x_Arcadyan_Belkin = 29,
345 RT_CID_819x_SAMSUNG = 30,
346 RT_CID_819x_WNC_COREGA = 31,
347 RT_CID_819x_Foxcoon = 32,
348 RT_CID_819x_DELL = 33,
349 };
350
351 enum hw_descs {
352 HW_DESC_OWN,
353 HW_DESC_RXOWN,
354 HW_DESC_TX_NEXTDESC_ADDR,
355 HW_DESC_TXBUFF_ADDR,
356 HW_DESC_RXBUFF_ADDR,
357 HW_DESC_RXPKT_LEN,
358 HW_DESC_RXERO,
359 };
360
361 enum prime_sc {
362 PRIME_CHNL_OFFSET_DONT_CARE = 0,
363 PRIME_CHNL_OFFSET_LOWER = 1,
364 PRIME_CHNL_OFFSET_UPPER = 2,
365 };
366
367 enum rf_type {
368 RF_1T1R = 0,
369 RF_1T2R = 1,
370 RF_2T2R = 2,
371 RF_2T2R_GREEN = 3,
372 };
373
374 enum ht_channel_width {
375 HT_CHANNEL_WIDTH_20 = 0,
376 HT_CHANNEL_WIDTH_20_40 = 1,
377 };
378
379 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
380 Cipher Suites Encryption Algorithms */
381 enum rt_enc_alg {
382 NO_ENCRYPTION = 0,
383 WEP40_ENCRYPTION = 1,
384 TKIP_ENCRYPTION = 2,
385 RSERVED_ENCRYPTION = 3,
386 AESCCMP_ENCRYPTION = 4,
387 WEP104_ENCRYPTION = 5,
388 };
389
390 enum rtl_hal_state {
391 _HAL_STATE_STOP = 0,
392 _HAL_STATE_START = 1,
393 };
394
395 enum rtl_desc92_rate {
396 DESC92_RATE1M = 0x00,
397 DESC92_RATE2M = 0x01,
398 DESC92_RATE5_5M = 0x02,
399 DESC92_RATE11M = 0x03,
400
401 DESC92_RATE6M = 0x04,
402 DESC92_RATE9M = 0x05,
403 DESC92_RATE12M = 0x06,
404 DESC92_RATE18M = 0x07,
405 DESC92_RATE24M = 0x08,
406 DESC92_RATE36M = 0x09,
407 DESC92_RATE48M = 0x0a,
408 DESC92_RATE54M = 0x0b,
409
410 DESC92_RATEMCS0 = 0x0c,
411 DESC92_RATEMCS1 = 0x0d,
412 DESC92_RATEMCS2 = 0x0e,
413 DESC92_RATEMCS3 = 0x0f,
414 DESC92_RATEMCS4 = 0x10,
415 DESC92_RATEMCS5 = 0x11,
416 DESC92_RATEMCS6 = 0x12,
417 DESC92_RATEMCS7 = 0x13,
418 DESC92_RATEMCS8 = 0x14,
419 DESC92_RATEMCS9 = 0x15,
420 DESC92_RATEMCS10 = 0x16,
421 DESC92_RATEMCS11 = 0x17,
422 DESC92_RATEMCS12 = 0x18,
423 DESC92_RATEMCS13 = 0x19,
424 DESC92_RATEMCS14 = 0x1a,
425 DESC92_RATEMCS15 = 0x1b,
426 DESC92_RATEMCS15_SG = 0x1c,
427 DESC92_RATEMCS32 = 0x20,
428 };
429
430 enum rtl_var_map {
431 /*reg map */
432 SYS_ISO_CTRL = 0,
433 SYS_FUNC_EN,
434 SYS_CLK,
435 MAC_RCR_AM,
436 MAC_RCR_AB,
437 MAC_RCR_ACRC32,
438 MAC_RCR_ACF,
439 MAC_RCR_AAP,
440
441 /*efuse map */
442 EFUSE_TEST,
443 EFUSE_CTRL,
444 EFUSE_CLK,
445 EFUSE_CLK_CTRL,
446 EFUSE_PWC_EV12V,
447 EFUSE_FEN_ELDR,
448 EFUSE_LOADER_CLK_EN,
449 EFUSE_ANA8M,
450 EFUSE_HWSET_MAX_SIZE,
451 EFUSE_MAX_SECTION_MAP,
452 EFUSE_REAL_CONTENT_SIZE,
453 EFUSE_OOB_PROTECT_BYTES_LEN,
454
455 /*CAM map */
456 RWCAM,
457 WCAMI,
458 RCAMO,
459 CAMDBG,
460 SECR,
461 SEC_CAM_NONE,
462 SEC_CAM_WEP40,
463 SEC_CAM_TKIP,
464 SEC_CAM_AES,
465 SEC_CAM_WEP104,
466
467 /*IMR map */
468 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
469 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
470 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
471 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
472 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
473 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
474 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
475 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
476 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
477 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
478 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
479 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
480 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
481 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
482 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
483 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
484 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
485 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
486 RTL_IMR_BcnInt, /*Beacon DMA Interrupt 0 */
487 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
488 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
489 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
490 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
491 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
492 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
493 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
494 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
495 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
496 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
497 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
498 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
499 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
500 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
501 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BcnInt | RTL_IMR_TBDOK |
502 * RTL_IMR_TBDER) */
503
504 /*CCK Rates, TxHT = 0 */
505 RTL_RC_CCK_RATE1M,
506 RTL_RC_CCK_RATE2M,
507 RTL_RC_CCK_RATE5_5M,
508 RTL_RC_CCK_RATE11M,
509
510 /*OFDM Rates, TxHT = 0 */
511 RTL_RC_OFDM_RATE6M,
512 RTL_RC_OFDM_RATE9M,
513 RTL_RC_OFDM_RATE12M,
514 RTL_RC_OFDM_RATE18M,
515 RTL_RC_OFDM_RATE24M,
516 RTL_RC_OFDM_RATE36M,
517 RTL_RC_OFDM_RATE48M,
518 RTL_RC_OFDM_RATE54M,
519
520 RTL_RC_HT_RATEMCS7,
521 RTL_RC_HT_RATEMCS15,
522
523 /*keep it last */
524 RTL_VAR_MAP_MAX,
525 };
526
527 /*Firmware PS mode for control LPS.*/
528 enum _fw_ps_mode {
529 FW_PS_ACTIVE_MODE = 0,
530 FW_PS_MIN_MODE = 1,
531 FW_PS_MAX_MODE = 2,
532 FW_PS_DTIM_MODE = 3,
533 FW_PS_VOIP_MODE = 4,
534 FW_PS_UAPSD_WMM_MODE = 5,
535 FW_PS_UAPSD_MODE = 6,
536 FW_PS_IBSS_MODE = 7,
537 FW_PS_WWLAN_MODE = 8,
538 FW_PS_PM_Radio_Off = 9,
539 FW_PS_PM_Card_Disable = 10,
540 };
541
542 enum rt_psmode {
543 EACTIVE, /*Active/Continuous access. */
544 EMAXPS, /*Max power save mode. */
545 EFASTPS, /*Fast power save mode. */
546 EAUTOPS, /*Auto power save mode. */
547 };
548
549 /*LED related.*/
550 enum led_ctl_mode {
551 LED_CTL_POWER_ON = 1,
552 LED_CTL_LINK = 2,
553 LED_CTL_NO_LINK = 3,
554 LED_CTL_TX = 4,
555 LED_CTL_RX = 5,
556 LED_CTL_SITE_SURVEY = 6,
557 LED_CTL_POWER_OFF = 7,
558 LED_CTL_START_TO_LINK = 8,
559 LED_CTL_START_WPS = 9,
560 LED_CTL_STOP_WPS = 10,
561 };
562
563 enum rtl_led_pin {
564 LED_PIN_GPIO0,
565 LED_PIN_LED0,
566 LED_PIN_LED1,
567 LED_PIN_LED2
568 };
569
570 /*QoS related.*/
571 /*acm implementation method.*/
572 enum acm_method {
573 eAcmWay0_SwAndHw = 0,
574 eAcmWay1_HW = 1,
575 eAcmWay2_SW = 2,
576 };
577
578 enum macphy_mode {
579 SINGLEMAC_SINGLEPHY = 0,
580 DUALMAC_DUALPHY,
581 DUALMAC_SINGLEPHY,
582 };
583
584 enum band_type {
585 BAND_ON_2_4G = 0,
586 BAND_ON_5G,
587 BAND_ON_BOTH,
588 BANDMAX
589 };
590
591 /*aci/aifsn Field.
592 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
593 union aci_aifsn {
594 u8 char_data;
595
596 struct {
597 u8 aifsn:4;
598 u8 acm:1;
599 u8 aci:2;
600 u8 reserved:1;
601 } f; /* Field */
602 };
603
604 /*mlme related.*/
605 enum wireless_mode {
606 WIRELESS_MODE_UNKNOWN = 0x00,
607 WIRELESS_MODE_A = 0x01,
608 WIRELESS_MODE_B = 0x02,
609 WIRELESS_MODE_G = 0x04,
610 WIRELESS_MODE_AUTO = 0x08,
611 WIRELESS_MODE_N_24G = 0x10,
612 WIRELESS_MODE_N_5G = 0x20
613 };
614
615 #define IS_WIRELESS_MODE_A(wirelessmode) \
616 (wirelessmode == WIRELESS_MODE_A)
617 #define IS_WIRELESS_MODE_B(wirelessmode) \
618 (wirelessmode == WIRELESS_MODE_B)
619 #define IS_WIRELESS_MODE_G(wirelessmode) \
620 (wirelessmode == WIRELESS_MODE_G)
621 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
622 (wirelessmode == WIRELESS_MODE_N_24G)
623 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
624 (wirelessmode == WIRELESS_MODE_N_5G)
625
626 enum ratr_table_mode {
627 RATR_INX_WIRELESS_NGB = 0,
628 RATR_INX_WIRELESS_NG = 1,
629 RATR_INX_WIRELESS_NB = 2,
630 RATR_INX_WIRELESS_N = 3,
631 RATR_INX_WIRELESS_GB = 4,
632 RATR_INX_WIRELESS_G = 5,
633 RATR_INX_WIRELESS_B = 6,
634 RATR_INX_WIRELESS_MC = 7,
635 RATR_INX_WIRELESS_A = 8,
636 };
637
638 enum rtl_link_state {
639 MAC80211_NOLINK = 0,
640 MAC80211_LINKING = 1,
641 MAC80211_LINKED = 2,
642 MAC80211_LINKED_SCANNING = 3,
643 };
644
645 enum act_category {
646 ACT_CAT_QOS = 1,
647 ACT_CAT_DLS = 2,
648 ACT_CAT_BA = 3,
649 ACT_CAT_HT = 7,
650 ACT_CAT_WMM = 17,
651 };
652
653 enum ba_action {
654 ACT_ADDBAREQ = 0,
655 ACT_ADDBARSP = 1,
656 ACT_DELBA = 2,
657 };
658
659 struct octet_string {
660 u8 *octet;
661 u16 length;
662 };
663
664 struct rtl_hdr_3addr {
665 __le16 frame_ctl;
666 __le16 duration_id;
667 u8 addr1[ETH_ALEN];
668 u8 addr2[ETH_ALEN];
669 u8 addr3[ETH_ALEN];
670 __le16 seq_ctl;
671 u8 payload[0];
672 } __packed;
673
674 struct rtl_info_element {
675 u8 id;
676 u8 len;
677 u8 data[0];
678 } __packed;
679
680 struct rtl_probe_rsp {
681 struct rtl_hdr_3addr header;
682 u32 time_stamp[2];
683 __le16 beacon_interval;
684 __le16 capability;
685 /*SSID, supported rates, FH params, DS params,
686 CF params, IBSS params, TIM (if beacon), RSN */
687 struct rtl_info_element info_element[0];
688 } __packed;
689
690 /*LED related.*/
691 /*ledpin Identify how to implement this SW led.*/
692 struct rtl_led {
693 void *hw;
694 enum rtl_led_pin ledpin;
695 bool ledon;
696 };
697
698 struct rtl_led_ctl {
699 bool led_opendrain;
700 struct rtl_led sw_led0;
701 struct rtl_led sw_led1;
702 };
703
704 struct rtl_qos_parameters {
705 __le16 cw_min;
706 __le16 cw_max;
707 u8 aifs;
708 u8 flag;
709 __le16 tx_op;
710 } __packed;
711
712 struct rt_smooth_data {
713 u32 elements[100]; /*array to store values */
714 u32 index; /*index to current array to store */
715 u32 total_num; /*num of valid elements */
716 u32 total_val; /*sum of valid elements */
717 };
718
719 struct false_alarm_statistics {
720 u32 cnt_parity_fail;
721 u32 cnt_rate_illegal;
722 u32 cnt_crc8_fail;
723 u32 cnt_mcs_fail;
724 u32 cnt_fast_fsync_fail;
725 u32 cnt_sb_search_fail;
726 u32 cnt_ofdm_fail;
727 u32 cnt_cck_fail;
728 u32 cnt_all;
729 };
730
731 struct init_gain {
732 u8 xaagccore1;
733 u8 xbagccore1;
734 u8 xcagccore1;
735 u8 xdagccore1;
736 u8 cca;
737
738 };
739
740 struct wireless_stats {
741 unsigned long txbytesunicast;
742 unsigned long txbytesmulticast;
743 unsigned long txbytesbroadcast;
744 unsigned long rxbytesunicast;
745
746 long rx_snr_db[4];
747 /*Correct smoothed ss in Dbm, only used
748 in driver to report real power now. */
749 long recv_signal_power;
750 long signal_quality;
751 long last_sigstrength_inpercent;
752
753 u32 rssi_calculate_cnt;
754
755 /*Transformed, in dbm. Beautified signal
756 strength for UI, not correct. */
757 long signal_strength;
758
759 u8 rx_rssi_percentage[4];
760 u8 rx_evm_percentage[2];
761
762 struct rt_smooth_data ui_rssi;
763 struct rt_smooth_data ui_link_quality;
764 };
765
766 struct rate_adaptive {
767 u8 rate_adaptive_disabled;
768 u8 ratr_state;
769 u16 reserve;
770
771 u32 high_rssi_thresh_for_ra;
772 u32 high2low_rssi_thresh_for_ra;
773 u8 low2high_rssi_thresh_for_ra40m;
774 u32 low_rssi_thresh_for_ra40M;
775 u8 low2high_rssi_thresh_for_ra20m;
776 u32 low_rssi_thresh_for_ra20M;
777 u32 upper_rssi_threshold_ratr;
778 u32 middleupper_rssi_threshold_ratr;
779 u32 middle_rssi_threshold_ratr;
780 u32 middlelow_rssi_threshold_ratr;
781 u32 low_rssi_threshold_ratr;
782 u32 ultralow_rssi_threshold_ratr;
783 u32 low_rssi_threshold_ratr_40m;
784 u32 low_rssi_threshold_ratr_20m;
785 u8 ping_rssi_enable;
786 u32 ping_rssi_ratr;
787 u32 ping_rssi_thresh_for_ra;
788 u32 last_ratr;
789 u8 pre_ratr_state;
790 };
791
792 struct regd_pair_mapping {
793 u16 reg_dmnenum;
794 u16 reg_5ghz_ctl;
795 u16 reg_2ghz_ctl;
796 };
797
798 struct rtl_regulatory {
799 char alpha2[2];
800 u16 country_code;
801 u16 max_power_level;
802 u32 tp_scale;
803 u16 current_rd;
804 u16 current_rd_ext;
805 int16_t power_limit;
806 struct regd_pair_mapping *regpair;
807 };
808
809 struct rtl_rfkill {
810 bool rfkill_state; /*0 is off, 1 is on */
811 };
812
813 #define IQK_MATRIX_REG_NUM 8
814 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
815 struct iqk_matrix_regs {
816 bool iqk_done;
817 long value[1][IQK_MATRIX_REG_NUM];
818 };
819
820 struct phy_parameters {
821 u16 length;
822 u32 *pdata;
823 };
824
825 enum hw_param_tab_index {
826 PHY_REG_2T,
827 PHY_REG_1T,
828 PHY_REG_PG,
829 RADIOA_2T,
830 RADIOB_2T,
831 RADIOA_1T,
832 RADIOB_1T,
833 MAC_REG,
834 AGCTAB_2T,
835 AGCTAB_1T,
836 MAX_TAB
837 };
838
839 struct rtl_phy {
840 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
841 struct init_gain initgain_backup;
842 enum io_type current_io_type;
843
844 u8 rf_mode;
845 u8 rf_type;
846 u8 current_chan_bw;
847 u8 set_bwmode_inprogress;
848 u8 sw_chnl_inprogress;
849 u8 sw_chnl_stage;
850 u8 sw_chnl_step;
851 u8 current_channel;
852 u8 h2c_box_num;
853 u8 set_io_inprogress;
854 u8 lck_inprogress;
855
856 /* record for power tracking */
857 s32 reg_e94;
858 s32 reg_e9c;
859 s32 reg_ea4;
860 s32 reg_eac;
861 s32 reg_eb4;
862 s32 reg_ebc;
863 s32 reg_ec4;
864 s32 reg_ecc;
865 u8 rfpienable;
866 u8 reserve_0;
867 u16 reserve_1;
868 u32 reg_c04, reg_c08, reg_874;
869 u32 adda_backup[16];
870 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
871 u32 iqk_bb_backup[10];
872
873 /* Dual mac */
874 bool need_iqk;
875 struct iqk_matrix_regs iqk_matrix_regsetting[IQK_MATRIX_SETTINGS_NUM];
876
877 bool rfpi_enable;
878
879 u8 pwrgroup_cnt;
880 u8 cck_high_power;
881 /* MAX_PG_GROUP groups of pwr diff by rates */
882 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
883 u8 default_initialgain[4];
884
885 /* the current Tx power level */
886 u8 cur_cck_txpwridx;
887 u8 cur_ofdm24g_txpwridx;
888
889 u32 rfreg_chnlval[2];
890 bool apk_done;
891 u32 reg_rf3c[2]; /* pathA / pathB */
892
893 /* bfsync */
894 u8 framesync;
895 u32 framesync_c34;
896
897 u8 num_total_rfpath;
898 struct phy_parameters hwparam_tables[MAX_TAB];
899 u16 rf_pathmap;
900 };
901
902 #define MAX_TID_COUNT 9
903 #define RTL_AGG_STOP 0
904 #define RTL_AGG_PROGRESS 1
905 #define RTL_AGG_START 2
906 #define RTL_AGG_OPERATIONAL 3
907 #define RTL_AGG_OFF 0
908 #define RTL_AGG_ON 1
909 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
910 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
911
912 struct rtl_ht_agg {
913 u16 txq_id;
914 u16 wait_for_ba;
915 u16 start_idx;
916 u64 bitmap;
917 u32 rate_n_flags;
918 u8 agg_state;
919 };
920
921 struct rtl_tid_data {
922 u16 seq_number;
923 struct rtl_ht_agg agg;
924 };
925
926 struct rtl_sta_info {
927 u8 ratr_index;
928 u8 wireless_mode;
929 u8 mimo_ps;
930 struct rtl_tid_data tids[MAX_TID_COUNT];
931 } __packed;
932
933 struct rtl_priv;
934 struct rtl_io {
935 struct device *dev;
936 struct mutex bb_mutex;
937
938 /*PCI MEM map */
939 unsigned long pci_mem_end; /*shared mem end */
940 unsigned long pci_mem_start; /*shared mem start */
941
942 /*PCI IO map */
943 unsigned long pci_base_addr; /*device I/O address */
944
945 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
946 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
947 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
948 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf,
949 u16 len);
950
951 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
952 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
953 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
954
955 };
956
957 struct rtl_mac {
958 u8 mac_addr[ETH_ALEN];
959 u8 mac80211_registered;
960 u8 beacon_enabled;
961
962 u32 tx_ss_num;
963 u32 rx_ss_num;
964
965 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
966 struct ieee80211_hw *hw;
967 struct ieee80211_vif *vif;
968 enum nl80211_iftype opmode;
969
970 /*Probe Beacon management */
971 struct rtl_tid_data tids[MAX_TID_COUNT];
972 enum rtl_link_state link_state;
973
974 int n_channels;
975 int n_bitrates;
976
977 bool offchan_delay;
978
979 /*filters */
980 u32 rx_conf;
981 u16 rx_mgt_filter;
982 u16 rx_ctrl_filter;
983 u16 rx_data_filter;
984
985 bool act_scanning;
986 u8 cnt_after_linked;
987
988 /* early mode */
989 /* skb wait queue */
990 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
991 u8 earlymode_threshold;
992
993 /*RDG*/
994 bool rdg_en;
995
996 /*AP*/
997 u8 bssid[6];
998 u32 vendor;
999 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1000 u32 basic_rates; /* b/g rates */
1001 u8 ht_enable;
1002 u8 sgi_40;
1003 u8 sgi_20;
1004 u8 bw_40;
1005 u8 mode; /* wireless mode */
1006 u8 slot_time;
1007 u8 short_preamble;
1008 u8 use_cts_protect;
1009 u8 cur_40_prime_sc;
1010 u8 cur_40_prime_sc_bk;
1011 u64 tsf;
1012 u8 retry_short;
1013 u8 retry_long;
1014 u16 assoc_id;
1015
1016 /*IBSS*/
1017 int beacon_interval;
1018
1019 /*AMPDU*/
1020 u8 min_space_cfg; /*For Min spacing configurations */
1021 u8 max_mss_density;
1022 u8 current_ampdu_factor;
1023 u8 current_ampdu_density;
1024
1025 /*QOS & EDCA */
1026 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1027 struct rtl_qos_parameters ac[AC_MAX];
1028 };
1029
1030 struct rtl_hal {
1031 struct ieee80211_hw *hw;
1032
1033 enum intf_type interface;
1034 u16 hw_type; /*92c or 92d or 92s and so on */
1035 u8 ic_class;
1036 u8 oem_id;
1037 u32 version; /*version of chip */
1038 u8 state; /*stop 0, start 1 */
1039
1040 /*firmware */
1041 u32 fwsize;
1042 u8 *pfirmware;
1043 u16 fw_version;
1044 u16 fw_subversion;
1045 bool h2c_setinprogress;
1046 u8 last_hmeboxnum;
1047 /*Reserve page start offset except beacon in TxQ. */
1048 u8 fw_rsvdpage_startoffset;
1049 u8 h2c_txcmd_seq;
1050
1051 /* FW Cmd IO related */
1052 u16 fwcmd_iomap;
1053 u32 fwcmd_ioparam;
1054 bool set_fwcmd_inprogress;
1055 u8 current_fwcmd_io;
1056
1057 /**/
1058 bool driver_going2unload;
1059
1060 /*AMPDU init min space*/
1061 u8 minspace_cfg; /*For Min spacing configurations */
1062
1063 /* Dual mac */
1064 enum macphy_mode macphymode;
1065 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1066 enum band_type current_bandtypebackup;
1067 enum band_type bandset;
1068 /* dual MAC 0--Mac0 1--Mac1 */
1069 u32 interfaceindex;
1070 /* just for DualMac S3S4 */
1071 u8 macphyctl_reg;
1072 bool earlymode_enable;
1073 /* Dual mac*/
1074 bool during_mac0init_radiob;
1075 bool during_mac1init_radioa;
1076 bool reloadtxpowerindex;
1077 /* True if IMR or IQK have done
1078 for 2.4G in scan progress */
1079 bool load_imrandiqk_setting_for2g;
1080
1081 bool disable_amsdu_8k;
1082 };
1083
1084 struct rtl_security {
1085 /*default 0 */
1086 bool use_sw_sec;
1087
1088 bool being_setkey;
1089 bool use_defaultkey;
1090 /*Encryption Algorithm for Unicast Packet */
1091 enum rt_enc_alg pairwise_enc_algorithm;
1092 /*Encryption Algorithm for Brocast/Multicast */
1093 enum rt_enc_alg group_enc_algorithm;
1094 /*Cam Entry Bitmap */
1095 u32 hwsec_cam_bitmap;
1096 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1097 /*local Key buffer, indx 0 is for
1098 pairwise key 1-4 is for agoup key. */
1099 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1100 u8 key_len[KEY_BUF_SIZE];
1101
1102 /*The pointer of Pairwise Key,
1103 it always points to KeyBuf[4] */
1104 u8 *pairwise_key;
1105 };
1106
1107 struct rtl_dm {
1108 /*PHY status for Dynamic Management */
1109 long entry_min_undecoratedsmoothed_pwdb;
1110 long undecorated_smoothed_pwdb; /*out dm */
1111 long entry_max_undecoratedsmoothed_pwdb;
1112 bool dm_initialgain_enable;
1113 bool dynamic_txpower_enable;
1114 bool current_turbo_edca;
1115 bool is_any_nonbepkts; /*out dm */
1116 bool is_cur_rdlstate;
1117 bool txpower_trackinginit;
1118 bool disable_framebursting;
1119 bool cck_inch14;
1120 bool txpower_tracking;
1121 bool useramask;
1122 bool rfpath_rxenable[4];
1123 bool inform_fw_driverctrldm;
1124 bool current_mrc_switch;
1125 u8 txpowercount;
1126
1127 u8 thermalvalue_rxgain;
1128 u8 thermalvalue_iqk;
1129 u8 thermalvalue_lck;
1130 u8 thermalvalue;
1131 u8 last_dtp_lvl;
1132 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1133 u8 thermalvalue_avg_index;
1134 bool done_txpower;
1135 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1136 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1137 u8 dm_type;
1138 u8 txpower_track_control;
1139 bool interrupt_migration;
1140 bool disable_tx_int;
1141 char ofdm_index[2];
1142 char cck_index;
1143 };
1144
1145 #define EFUSE_MAX_LOGICAL_SIZE 256
1146
1147 struct rtl_efuse {
1148 bool autoLoad_ok;
1149 bool bootfromefuse;
1150 u16 max_physical_size;
1151
1152 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1153 u16 efuse_usedbytes;
1154 u8 efuse_usedpercentage;
1155 #ifdef EFUSE_REPG_WORKAROUND
1156 bool efuse_re_pg_sec1flag;
1157 u8 efuse_re_pg_data[8];
1158 #endif
1159
1160 u8 autoload_failflag;
1161 u8 autoload_status;
1162
1163 short epromtype;
1164 u16 eeprom_vid;
1165 u16 eeprom_did;
1166 u16 eeprom_svid;
1167 u16 eeprom_smid;
1168 u8 eeprom_oemid;
1169 u16 eeprom_channelplan;
1170 u8 eeprom_version;
1171 u8 board_type;
1172 u8 external_pa;
1173
1174 u8 dev_addr[6];
1175
1176 bool txpwr_fromeprom;
1177 u8 eeprom_crystalcap;
1178 u8 eeprom_tssi[2];
1179 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1180 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1181 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1182 u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
1183 u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
1184 u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][CHANNEL_GROUP_MAX];
1185 u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
1186 u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1187 u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1188
1189 u8 internal_pa_5g[2]; /* pathA / pathB */
1190 u8 eeprom_c9;
1191 u8 eeprom_cc;
1192
1193 /*For power group */
1194 u8 eeprom_pwrgroup[2][3];
1195 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1196 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1197
1198 char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */
1199 /*For HT<->legacy pwr diff*/
1200 u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER];
1201 u8 txpwr_safetyflag; /* Band edge enable flag */
1202 u16 eeprom_txpowerdiff;
1203 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1204 u8 antenna_txpwdiff[3];
1205
1206 u8 eeprom_regulatory;
1207 u8 eeprom_thermalmeter;
1208 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1209 u16 tssi_13dbm;
1210 u8 crystalcap; /* CrystalCap. */
1211 u8 delta_iqk;
1212 u8 delta_lck;
1213
1214 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1215 bool apk_thermalmeterignore;
1216
1217 bool b1x1_recvcombine;
1218 bool b1ss_support;
1219
1220 /*channel plan */
1221 u8 channel_plan;
1222 };
1223
1224 struct rtl_ps_ctl {
1225 bool pwrdomain_protect;
1226 bool in_powersavemode;
1227 bool rfchange_inprogress;
1228 bool swrf_processing;
1229 bool hwradiooff;
1230
1231 /*
1232 * just for PCIE ASPM
1233 * If it supports ASPM, Offset[560h] = 0x40,
1234 * otherwise Offset[560h] = 0x00.
1235 * */
1236 bool support_aspm;
1237
1238 bool support_backdoor;
1239
1240 /*for LPS */
1241 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1242 bool swctrl_lps;
1243 bool leisure_ps;
1244 bool fwctrl_lps;
1245 u8 fwctrl_psmode;
1246 /*For Fw control LPS mode */
1247 u8 reg_fwctrl_lps;
1248 /*Record Fw PS mode status. */
1249 bool fw_current_inpsmode;
1250 u8 reg_max_lps_awakeintvl;
1251 bool report_linked;
1252
1253 /*for IPS */
1254 bool inactiveps;
1255
1256 u32 rfoff_reason;
1257
1258 /*RF OFF Level */
1259 u32 cur_ps_level;
1260 u32 reg_rfps_level;
1261
1262 /*just for PCIE ASPM */
1263 u8 const_amdpci_aspm;
1264 bool pwrdown_mode;
1265
1266 enum rf_pwrstate inactive_pwrstate;
1267 enum rf_pwrstate rfpwr_state; /*cur power state */
1268
1269 /* for SW LPS*/
1270 bool sw_ps_enabled;
1271 bool state;
1272 bool state_inap;
1273 bool multi_buffered;
1274 u16 nullfunc_seq;
1275 unsigned int dtim_counter;
1276 unsigned int sleep_ms;
1277 unsigned long last_sleep_jiffies;
1278 unsigned long last_awake_jiffies;
1279 unsigned long last_delaylps_stamp_jiffies;
1280 unsigned long last_dtim;
1281 unsigned long last_beacon;
1282 unsigned long last_action;
1283 unsigned long last_slept;
1284 };
1285
1286 struct rtl_stats {
1287 u32 mac_time[2];
1288 s8 rssi;
1289 u8 signal;
1290 u8 noise;
1291 u16 rate; /*in 100 kbps */
1292 u8 received_channel;
1293 u8 control;
1294 u8 mask;
1295 u8 freq;
1296 u16 len;
1297 u64 tsf;
1298 u32 beacon_time;
1299 u8 nic_type;
1300 u16 length;
1301 u8 signalquality; /*in 0-100 index. */
1302 /*
1303 * Real power in dBm for this packet,
1304 * no beautification and aggregation.
1305 * */
1306 s32 recvsignalpower;
1307 s8 rxpower; /*in dBm Translate from PWdB */
1308 u8 signalstrength; /*in 0-100 index. */
1309 u16 hwerror:1;
1310 u16 crc:1;
1311 u16 icv:1;
1312 u16 shortpreamble:1;
1313 u16 antenna:1;
1314 u16 decrypted:1;
1315 u16 wakeup:1;
1316 u32 timestamp_low;
1317 u32 timestamp_high;
1318
1319 u8 rx_drvinfo_size;
1320 u8 rx_bufshift;
1321 bool isampdu;
1322 bool isfirst_ampdu;
1323 bool rx_is40Mhzpacket;
1324 u32 rx_pwdb_all;
1325 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1326 s8 rx_mimo_signalquality[2];
1327 bool packet_matchbssid;
1328 bool is_cck;
1329 bool is_ht;
1330 bool packet_toself;
1331 bool packet_beacon; /*for rssi */
1332 char cck_adc_pwdb[4]; /*for rx path selection */
1333 };
1334
1335 struct rt_link_detect {
1336 u32 num_tx_in4period[4];
1337 u32 num_rx_in4period[4];
1338
1339 u32 num_tx_inperiod;
1340 u32 num_rx_inperiod;
1341
1342 bool busytraffic;
1343 bool higher_busytraffic;
1344 bool higher_busyrxtraffic;
1345
1346 u32 tidtx_in4period[MAX_TID_COUNT][4];
1347 u32 tidtx_inperiod[MAX_TID_COUNT];
1348 bool higher_busytxtraffic[MAX_TID_COUNT];
1349 };
1350
1351 struct rtl_tcb_desc {
1352 u8 packet_bw:1;
1353 u8 multicast:1;
1354 u8 broadcast:1;
1355
1356 u8 rts_stbc:1;
1357 u8 rts_enable:1;
1358 u8 cts_enable:1;
1359 u8 rts_use_shortpreamble:1;
1360 u8 rts_use_shortgi:1;
1361 u8 rts_sc:1;
1362 u8 rts_bw:1;
1363 u8 rts_rate;
1364
1365 u8 use_shortgi:1;
1366 u8 use_shortpreamble:1;
1367 u8 use_driver_rate:1;
1368 u8 disable_ratefallback:1;
1369
1370 u8 ratr_index;
1371 u8 mac_id;
1372 u8 hw_rate;
1373
1374 u8 last_inipkt:1;
1375 u8 cmd_or_init:1;
1376 u8 queue_index;
1377
1378 /* early mode */
1379 u8 empkt_num;
1380 /* The max value by HW */
1381 u32 empkt_len[5];
1382 };
1383
1384 struct rtl_hal_ops {
1385 int (*init_sw_vars) (struct ieee80211_hw *hw);
1386 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
1387 void (*read_chip_version)(struct ieee80211_hw *hw);
1388 void (*read_eeprom_info) (struct ieee80211_hw *hw);
1389 void (*interrupt_recognized) (struct ieee80211_hw *hw,
1390 u32 *p_inta, u32 *p_intb);
1391 int (*hw_init) (struct ieee80211_hw *hw);
1392 void (*hw_disable) (struct ieee80211_hw *hw);
1393 void (*hw_suspend) (struct ieee80211_hw *hw);
1394 void (*hw_resume) (struct ieee80211_hw *hw);
1395 void (*enable_interrupt) (struct ieee80211_hw *hw);
1396 void (*disable_interrupt) (struct ieee80211_hw *hw);
1397 int (*set_network_type) (struct ieee80211_hw *hw,
1398 enum nl80211_iftype type);
1399 void (*set_chk_bssid)(struct ieee80211_hw *hw,
1400 bool check_bssid);
1401 void (*set_bw_mode) (struct ieee80211_hw *hw,
1402 enum nl80211_channel_type ch_type);
1403 u8(*switch_channel) (struct ieee80211_hw *hw);
1404 void (*set_qos) (struct ieee80211_hw *hw, int aci);
1405 void (*set_bcn_reg) (struct ieee80211_hw *hw);
1406 void (*set_bcn_intv) (struct ieee80211_hw *hw);
1407 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1408 u32 add_msr, u32 rm_msr);
1409 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1410 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1411 void (*update_rate_tbl) (struct ieee80211_hw *hw,
1412 struct ieee80211_sta *sta, u8 rssi_level);
1413 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1414 void (*fill_tx_desc) (struct ieee80211_hw *hw,
1415 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1416 struct ieee80211_tx_info *info,
1417 struct sk_buff *skb, u8 hw_queue,
1418 struct rtl_tcb_desc *ptcb_desc);
1419 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
1420 u32 buffer_len, bool bIsPsPoll);
1421 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
1422 bool firstseg, bool lastseg,
1423 struct sk_buff *skb);
1424 bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
1425 bool (*query_rx_desc) (struct ieee80211_hw *hw,
1426 struct rtl_stats *stats,
1427 struct ieee80211_rx_status *rx_status,
1428 u8 *pdesc, struct sk_buff *skb);
1429 void (*set_channel_access) (struct ieee80211_hw *hw);
1430 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
1431 void (*dm_watchdog) (struct ieee80211_hw *hw);
1432 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
1433 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
1434 enum rf_pwrstate rfpwr_state);
1435 void (*led_control) (struct ieee80211_hw *hw,
1436 enum led_ctl_mode ledaction);
1437 void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
1438 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
1439 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
1440 void (*enable_hw_sec) (struct ieee80211_hw *hw);
1441 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
1442 u8 *macaddr, bool is_group, u8 enc_algo,
1443 bool is_wepkey, bool clear_all);
1444 void (*init_sw_leds) (struct ieee80211_hw *hw);
1445 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
1446 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1447 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1448 u32 data);
1449 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1450 u32 regaddr, u32 bitmask);
1451 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1452 u32 regaddr, u32 bitmask, u32 data);
1453 void (*linked_set_reg) (struct ieee80211_hw *hw);
1454 bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
1455 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
1456 u8 *powerlevel);
1457 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
1458 u8 *ppowerlevel, u8 channel);
1459 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
1460 u8 configtype);
1461 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
1462 u8 configtype);
1463 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
1464 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
1465 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
1466 };
1467
1468 struct rtl_intf_ops {
1469 /*com */
1470 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
1471 int (*adapter_start) (struct ieee80211_hw *hw);
1472 void (*adapter_stop) (struct ieee80211_hw *hw);
1473
1474 int (*adapter_tx) (struct ieee80211_hw *hw, struct sk_buff *skb,
1475 struct rtl_tcb_desc *ptcb_desc);
1476 void (*flush)(struct ieee80211_hw *hw, bool drop);
1477 int (*reset_trx_ring) (struct ieee80211_hw *hw);
1478 bool (*waitq_insert) (struct ieee80211_hw *hw, struct sk_buff *skb);
1479
1480 /*pci */
1481 void (*disable_aspm) (struct ieee80211_hw *hw);
1482 void (*enable_aspm) (struct ieee80211_hw *hw);
1483
1484 /*usb */
1485 };
1486
1487 struct rtl_mod_params {
1488 /* default: 0 = using hardware encryption */
1489 bool sw_crypto;
1490
1491 /* default: 0 = DBG_EMERG (0)*/
1492 int debug;
1493
1494 /* default: 1 = using no linked power save */
1495 bool inactiveps;
1496
1497 /* default: 1 = using linked sw power save */
1498 bool swctrl_lps;
1499
1500 /* default: 1 = using linked fw power save */
1501 bool fwctrl_lps;
1502 };
1503
1504 struct rtl_hal_usbint_cfg {
1505 /* data - rx */
1506 u32 in_ep_num;
1507 u32 rx_urb_num;
1508 u32 rx_max_size;
1509
1510 /* op - rx */
1511 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1512 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1513 struct sk_buff_head *);
1514
1515 /* tx */
1516 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1517 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1518 struct sk_buff *);
1519 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1520 struct sk_buff_head *);
1521
1522 /* endpoint mapping */
1523 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
1524 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
1525 };
1526
1527 struct rtl_hal_cfg {
1528 u8 bar_id;
1529 bool write_readback;
1530 char *name;
1531 char *fw_name;
1532 struct rtl_hal_ops *ops;
1533 struct rtl_mod_params *mod_params;
1534 struct rtl_hal_usbint_cfg *usb_interface_cfg;
1535
1536 /*this map used for some registers or vars
1537 defined int HAL but used in MAIN */
1538 u32 maps[RTL_VAR_MAP_MAX];
1539
1540 };
1541
1542 struct rtl_locks {
1543 /* mutex */
1544 struct mutex conf_mutex;
1545 struct mutex ps_mutex;
1546
1547 /*spin lock */
1548 spinlock_t ips_lock;
1549 spinlock_t irq_th_lock;
1550 spinlock_t h2c_lock;
1551 spinlock_t rf_ps_lock;
1552 spinlock_t rf_lock;
1553 spinlock_t waitq_lock;
1554 spinlock_t usb_lock;
1555
1556 /*Dual mac*/
1557 spinlock_t cck_and_rw_pagea_lock;
1558 };
1559
1560 struct rtl_works {
1561 struct ieee80211_hw *hw;
1562
1563 /*timer */
1564 struct timer_list watchdog_timer;
1565
1566 /*task */
1567 struct tasklet_struct irq_tasklet;
1568 struct tasklet_struct irq_prepare_bcn_tasklet;
1569
1570 /*work queue */
1571 struct workqueue_struct *rtl_wq;
1572 struct delayed_work watchdog_wq;
1573 struct delayed_work ips_nic_off_wq;
1574
1575 /* For SW LPS */
1576 struct delayed_work ps_work;
1577 struct delayed_work ps_rfon_wq;
1578
1579 struct work_struct lps_leave_work;
1580 };
1581
1582 struct rtl_debug {
1583 u32 dbgp_type[DBGP_TYPE_MAX];
1584 u32 global_debuglevel;
1585 u64 global_debugcomponents;
1586
1587 /* add for proc debug */
1588 struct proc_dir_entry *proc_dir;
1589 char proc_name[20];
1590 };
1591
1592 struct rtl_priv {
1593 struct completion firmware_loading_complete;
1594 struct rtl_locks locks;
1595 struct rtl_works works;
1596 struct rtl_mac mac80211;
1597 struct rtl_hal rtlhal;
1598 struct rtl_regulatory regd;
1599 struct rtl_rfkill rfkill;
1600 struct rtl_io io;
1601 struct rtl_phy phy;
1602 struct rtl_dm dm;
1603 struct rtl_security sec;
1604 struct rtl_efuse efuse;
1605
1606 struct rtl_ps_ctl psc;
1607 struct rate_adaptive ra;
1608 struct wireless_stats stats;
1609 struct rt_link_detect link_info;
1610 struct false_alarm_statistics falsealm_cnt;
1611
1612 struct rtl_rate_priv *rate_priv;
1613
1614 struct rtl_debug dbg;
1615 int max_fw_size;
1616
1617 /*
1618 *hal_cfg : for diff cards
1619 *intf_ops : for diff interrface usb/pcie
1620 */
1621 struct rtl_hal_cfg *cfg;
1622 struct rtl_intf_ops *intf_ops;
1623
1624 /*this var will be set by set_bit,
1625 and was used to indicate status of
1626 interface or hardware */
1627 unsigned long status;
1628
1629 /* data buffer pointer for USB reads */
1630 __le32 *usb_data;
1631 int usb_data_index;
1632
1633 /*This must be the last item so
1634 that it points to the data allocated
1635 beyond this structure like:
1636 rtl_pci_priv or rtl_usb_priv */
1637 u8 priv[0] __aligned(sizeof(void *));
1638 };
1639
1640 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
1641 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
1642 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
1643 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
1644 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
1645
1646
1647 /***************************************
1648 Bluetooth Co-existence Related
1649 ****************************************/
1650
1651 enum bt_ant_num {
1652 ANT_X2 = 0,
1653 ANT_X1 = 1,
1654 };
1655
1656 enum bt_co_type {
1657 BT_2WIRE = 0,
1658 BT_ISSC_3WIRE = 1,
1659 BT_ACCEL = 2,
1660 BT_CSR_BC4 = 3,
1661 BT_CSR_BC8 = 4,
1662 BT_RTL8756 = 5,
1663 };
1664
1665 enum bt_cur_state {
1666 BT_OFF = 0,
1667 BT_ON = 1,
1668 };
1669
1670 enum bt_service_type {
1671 BT_SCO = 0,
1672 BT_A2DP = 1,
1673 BT_HID = 2,
1674 BT_HID_IDLE = 3,
1675 BT_SCAN = 4,
1676 BT_IDLE = 5,
1677 BT_OTHER_ACTION = 6,
1678 BT_BUSY = 7,
1679 BT_OTHERBUSY = 8,
1680 BT_PAN = 9,
1681 };
1682
1683 enum bt_radio_shared {
1684 BT_RADIO_SHARED = 0,
1685 BT_RADIO_INDIVIDUAL = 1,
1686 };
1687
1688 struct bt_coexist_info {
1689
1690 /* EEPROM BT info. */
1691 u8 eeprom_bt_coexist;
1692 u8 eeprom_bt_type;
1693 u8 eeprom_bt_ant_num;
1694 u8 eeprom_bt_ant_isolation;
1695 u8 eeprom_bt_radio_shared;
1696
1697 u8 bt_coexistence;
1698 u8 bt_ant_num;
1699 u8 bt_coexist_type;
1700 u8 bt_state;
1701 u8 bt_cur_state; /* 0:on, 1:off */
1702 u8 bt_ant_isolation; /* 0:good, 1:bad */
1703 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
1704 u8 bt_service;
1705 u8 bt_radio_shared_type;
1706 u8 bt_rfreg_origin_1e;
1707 u8 bt_rfreg_origin_1f;
1708 u8 bt_rssi_state;
1709 u32 ratio_tx;
1710 u32 ratio_pri;
1711 u32 bt_edca_ul;
1712 u32 bt_edca_dl;
1713
1714 bool init_set;
1715 bool bt_busy_traffic;
1716 bool bt_traffic_mode_set;
1717 bool bt_non_traffic_mode_set;
1718
1719 bool fw_coexist_all_off;
1720 bool sw_coexist_all_off;
1721 u32 current_state;
1722 u32 previous_state;
1723 u8 bt_pre_rssi_state;
1724
1725 u8 reg_bt_iso;
1726 u8 reg_bt_sco;
1727
1728 };
1729
1730
1731 /****************************************
1732 mem access macro define start
1733 Call endian free function when
1734 1. Read/write packet content.
1735 2. Before write integer to IO.
1736 3. After read integer from IO.
1737 ****************************************/
1738 /* Convert little data endian to host ordering */
1739 #define EF1BYTE(_val) \
1740 ((u8)(_val))
1741 #define EF2BYTE(_val) \
1742 (le16_to_cpu(_val))
1743 #define EF4BYTE(_val) \
1744 (le32_to_cpu(_val))
1745
1746 /* Read data from memory */
1747 #define READEF1BYTE(_ptr) \
1748 EF1BYTE(*((u8 *)(_ptr)))
1749 /* Read le16 data from memory and convert to host ordering */
1750 #define READEF2BYTE(_ptr) \
1751 EF2BYTE(*((u16 *)(_ptr)))
1752 #define READEF4BYTE(_ptr) \
1753 EF4BYTE(*((u32 *)(_ptr)))
1754
1755 /* Write data to memory */
1756 #define WRITEEF1BYTE(_ptr, _val) \
1757 (*((u8 *)(_ptr))) = EF1BYTE(_val)
1758 /* Write le16 data to memory in host ordering */
1759 #define WRITEEF2BYTE(_ptr, _val) \
1760 (*((u16 *)(_ptr))) = EF2BYTE(_val)
1761 #define WRITEEF4BYTE(_ptr, _val) \
1762 (*((u16 *)(_ptr))) = EF2BYTE(_val)
1763
1764 /* Create a bit mask
1765 * Examples:
1766 * BIT_LEN_MASK_32(0) => 0x00000000
1767 * BIT_LEN_MASK_32(1) => 0x00000001
1768 * BIT_LEN_MASK_32(2) => 0x00000003
1769 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
1770 */
1771 #define BIT_LEN_MASK_32(__bitlen) \
1772 (0xFFFFFFFF >> (32 - (__bitlen)))
1773 #define BIT_LEN_MASK_16(__bitlen) \
1774 (0xFFFF >> (16 - (__bitlen)))
1775 #define BIT_LEN_MASK_8(__bitlen) \
1776 (0xFF >> (8 - (__bitlen)))
1777
1778 /* Create an offset bit mask
1779 * Examples:
1780 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
1781 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
1782 */
1783 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
1784 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
1785 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
1786 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
1787 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
1788 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
1789
1790 /*Description:
1791 * Return 4-byte value in host byte ordering from
1792 * 4-byte pointer in little-endian system.
1793 */
1794 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
1795 (EF4BYTE(*((u32 *)(__pstart))))
1796 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
1797 (EF2BYTE(*((u16 *)(__pstart))))
1798 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
1799 (EF1BYTE(*((u8 *)(__pstart))))
1800
1801 /*Description:
1802 Translate subfield (continuous bits in little-endian) of 4-byte
1803 value to host byte ordering.*/
1804 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1805 ( \
1806 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
1807 BIT_LEN_MASK_32(__bitlen) \
1808 )
1809 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1810 ( \
1811 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
1812 BIT_LEN_MASK_16(__bitlen) \
1813 )
1814 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1815 ( \
1816 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
1817 BIT_LEN_MASK_8(__bitlen) \
1818 )
1819
1820 /* Description:
1821 * Mask subfield (continuous bits in little-endian) of 4-byte value
1822 * and return the result in 4-byte value in host byte ordering.
1823 */
1824 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1825 ( \
1826 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
1827 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
1828 )
1829 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1830 ( \
1831 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
1832 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
1833 )
1834 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1835 ( \
1836 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
1837 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
1838 )
1839
1840 /* Description:
1841 * Set subfield of little-endian 4-byte value to specified value.
1842 */
1843 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
1844 *((u32 *)(__pstart)) = EF4BYTE \
1845 ( \
1846 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
1847 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
1848 );
1849 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
1850 *((u16 *)(__pstart)) = EF2BYTE \
1851 ( \
1852 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
1853 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
1854 );
1855 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
1856 *((u8 *)(__pstart)) = EF1BYTE \
1857 ( \
1858 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
1859 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
1860 );
1861
1862 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
1863 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
1864
1865 /****************************************
1866 mem access macro define end
1867 ****************************************/
1868
1869 #define byte(x, n) ((x >> (8 * n)) & 0xff)
1870
1871 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
1872 #define RTL_WATCH_DOG_TIME 2000
1873 #define MSECS(t) msecs_to_jiffies(t)
1874 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
1875 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
1876 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
1877 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
1878 #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
1879 #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
1880 #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
1881
1882 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
1883 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
1884 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
1885 /*NIC halt, re-initialize hw parameters*/
1886 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
1887 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
1888 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
1889 /*Always enable ASPM and Clock Req in initialization.*/
1890 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
1891 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
1892 #define RT_PS_LEVEL_ASPM BIT(7)
1893 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
1894 #define RT_RF_LPS_DISALBE_2R BIT(30)
1895 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
1896 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
1897 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
1898 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
1899 (ppsc->cur_ps_level &= (~(_ps_flg)))
1900 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
1901 (ppsc->cur_ps_level |= _ps_flg)
1902
1903 #define container_of_dwork_rtl(x, y, z) \
1904 container_of(container_of(x, struct delayed_work, work), y, z)
1905
1906 #define FILL_OCTET_STRING(_os, _octet, _len) \
1907 (_os).octet = (u8 *)(_octet); \
1908 (_os).length = (_len);
1909
1910 #define CP_MACADDR(des, src) \
1911 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
1912 (des)[2] = (src)[2], (des)[3] = (src)[3],\
1913 (des)[4] = (src)[4], (des)[5] = (src)[5])
1914
rtl_read_byte(struct rtl_priv * rtlpriv,u32 addr)1915 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
1916 {
1917 return rtlpriv->io.read8_sync(rtlpriv, addr);
1918 }
1919
rtl_read_word(struct rtl_priv * rtlpriv,u32 addr)1920 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
1921 {
1922 return rtlpriv->io.read16_sync(rtlpriv, addr);
1923 }
1924
rtl_read_dword(struct rtl_priv * rtlpriv,u32 addr)1925 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
1926 {
1927 return rtlpriv->io.read32_sync(rtlpriv, addr);
1928 }
1929
rtl_write_byte(struct rtl_priv * rtlpriv,u32 addr,u8 val8)1930 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
1931 {
1932 rtlpriv->io.write8_async(rtlpriv, addr, val8);
1933
1934 if (rtlpriv->cfg->write_readback)
1935 rtlpriv->io.read8_sync(rtlpriv, addr);
1936 }
1937
rtl_write_word(struct rtl_priv * rtlpriv,u32 addr,u16 val16)1938 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
1939 {
1940 rtlpriv->io.write16_async(rtlpriv, addr, val16);
1941
1942 if (rtlpriv->cfg->write_readback)
1943 rtlpriv->io.read16_sync(rtlpriv, addr);
1944 }
1945
rtl_write_dword(struct rtl_priv * rtlpriv,u32 addr,u32 val32)1946 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
1947 u32 addr, u32 val32)
1948 {
1949 rtlpriv->io.write32_async(rtlpriv, addr, val32);
1950
1951 if (rtlpriv->cfg->write_readback)
1952 rtlpriv->io.read32_sync(rtlpriv, addr);
1953 }
1954
rtl_get_bbreg(struct ieee80211_hw * hw,u32 regaddr,u32 bitmask)1955 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
1956 u32 regaddr, u32 bitmask)
1957 {
1958 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_bbreg(hw,
1959 regaddr,
1960 bitmask);
1961 }
1962
rtl_set_bbreg(struct ieee80211_hw * hw,u32 regaddr,u32 bitmask,u32 data)1963 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
1964 u32 bitmask, u32 data)
1965 {
1966 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_bbreg(hw,
1967 regaddr, bitmask,
1968 data);
1969
1970 }
1971
rtl_get_rfreg(struct ieee80211_hw * hw,enum radio_path rfpath,u32 regaddr,u32 bitmask)1972 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
1973 enum radio_path rfpath, u32 regaddr,
1974 u32 bitmask)
1975 {
1976 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_rfreg(hw,
1977 rfpath,
1978 regaddr,
1979 bitmask);
1980 }
1981
rtl_set_rfreg(struct ieee80211_hw * hw,enum radio_path rfpath,u32 regaddr,u32 bitmask,u32 data)1982 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
1983 enum radio_path rfpath, u32 regaddr,
1984 u32 bitmask, u32 data)
1985 {
1986 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_rfreg(hw,
1987 rfpath, regaddr,
1988 bitmask, data);
1989 }
1990
is_hal_stop(struct rtl_hal * rtlhal)1991 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
1992 {
1993 return (_HAL_STATE_STOP == rtlhal->state);
1994 }
1995
set_hal_start(struct rtl_hal * rtlhal)1996 static inline void set_hal_start(struct rtl_hal *rtlhal)
1997 {
1998 rtlhal->state = _HAL_STATE_START;
1999 }
2000
set_hal_stop(struct rtl_hal * rtlhal)2001 static inline void set_hal_stop(struct rtl_hal *rtlhal)
2002 {
2003 rtlhal->state = _HAL_STATE_STOP;
2004 }
2005
get_rf_type(struct rtl_phy * rtlphy)2006 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
2007 {
2008 return rtlphy->rf_type;
2009 }
2010
rtl_get_hdr(struct sk_buff * skb)2011 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
2012 {
2013 return (struct ieee80211_hdr *)(skb->data);
2014 }
2015
rtl_get_fc(struct sk_buff * skb)2016 static inline __le16 rtl_get_fc(struct sk_buff *skb)
2017 {
2018 return rtl_get_hdr(skb)->frame_control;
2019 }
2020
rtl_get_tid_h(struct ieee80211_hdr * hdr)2021 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
2022 {
2023 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
2024 }
2025
rtl_get_tid(struct sk_buff * skb)2026 static inline u16 rtl_get_tid(struct sk_buff *skb)
2027 {
2028 return rtl_get_tid_h(rtl_get_hdr(skb));
2029 }
2030
get_sta(struct ieee80211_hw * hw,struct ieee80211_vif * vif,const u8 * bssid)2031 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
2032 struct ieee80211_vif *vif,
2033 const u8 *bssid)
2034 {
2035 return ieee80211_find_sta(vif, bssid);
2036 }
2037
2038 #endif
2039