1 /* $Id: irq_ipr.c,v 1.1.1.1.2.2 2003/10/14 16:46:10 trent Exp $
2 *
3 * linux/arch/sh/kernel/irq_ipr.c
4 *
5 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
6 * Copyright (C) 2000 Kazumoto Kojima
7 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
8 *
9 * Interrupt handling for IPR-based IRQ.
10 *
11 * Supported system:
12 * On-chip supporting modules (TMU, RTC, etc.).
13 * On-chip supporting modules for SH7300/SH7709/SH7709A/SH7729.
14 * Hitachi SolutionEngine external I/O:
15 * MS7709SE01, MS7709ASE01, and MS7750SE01
16 *
17 */
18
19 #include <linux/config.h>
20 #include <linux/init.h>
21 #include <linux/irq.h>
22
23 #include <asm/system.h>
24 #include <asm/io.h>
25 #include <asm/machvec.h>
26
27 struct ipr_data {
28 unsigned int addr; /* Address of Interrupt Priority Register */
29 int shift; /* Shifts of the 16-bit data */
30 int priority; /* The priority */
31 };
32 static struct ipr_data ipr_data[NR_IRQS];
33
34 static void enable_ipr_irq(unsigned int irq);
35 static void disable_ipr_irq(unsigned int irq);
36
37 /* shutdown is same as "disable" */
38 #define shutdown_ipr_irq disable_ipr_irq
39
40 static void mask_and_ack_ipr(unsigned int);
41 static void end_ipr_irq(unsigned int irq);
42
startup_ipr_irq(unsigned int irq)43 static unsigned int startup_ipr_irq(unsigned int irq)
44 {
45 enable_ipr_irq(irq);
46 return 0; /* never anything pending */
47 }
48
49 static struct hw_interrupt_type ipr_irq_type = {
50 "IPR-IRQ",
51 startup_ipr_irq,
52 shutdown_ipr_irq,
53 enable_ipr_irq,
54 disable_ipr_irq,
55 mask_and_ack_ipr,
56 end_ipr_irq
57 };
58
disable_ipr_irq(unsigned int irq)59 static void disable_ipr_irq(unsigned int irq)
60 {
61 unsigned long val, flags;
62 unsigned int addr = ipr_data[irq].addr;
63 unsigned short mask = 0xffff ^ (0x0f << ipr_data[irq].shift);
64
65 /* Set the priority in IPR to 0 */
66 save_and_cli(flags);
67 val = ctrl_inw(addr);
68 val &= mask;
69 ctrl_outw(val, addr);
70 restore_flags(flags);
71 }
72
enable_ipr_irq(unsigned int irq)73 static void enable_ipr_irq(unsigned int irq)
74 {
75 unsigned long val, flags;
76 unsigned int addr = ipr_data[irq].addr;
77 int priority = ipr_data[irq].priority;
78 unsigned short value = (priority << ipr_data[irq].shift);
79
80 /* Set priority in IPR back to original value */
81 save_and_cli(flags);
82 val = ctrl_inw(addr);
83 val |= value;
84 ctrl_outw(val, addr);
85 restore_flags(flags);
86 }
87
mask_and_ack_ipr(unsigned int irq)88 static void mask_and_ack_ipr(unsigned int irq)
89 {
90 disable_ipr_irq(irq);
91
92 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7707) || \
93 defined(CONFIG_CPU_SUBTYPE_SH7709)
94 /* This is needed when we use edge triggered setting */
95 /* XXX: Is it really needed? */
96 if (IRQ0_IRQ <= irq && irq <= IRQ5_IRQ) {
97 /* Clear external interrupt request */
98 int a = ctrl_inb(INTC_IRR0);
99 a &= ~(1 << (irq - IRQ0_IRQ));
100 ctrl_outb(a, INTC_IRR0);
101 }
102 #endif
103 }
104
end_ipr_irq(unsigned int irq)105 static void end_ipr_irq(unsigned int irq)
106 {
107 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
108 enable_ipr_irq(irq);
109 }
110
make_ipr_irq(unsigned int irq,unsigned int addr,int pos,int priority)111 void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority)
112 {
113 disable_irq_nosync(irq);
114 ipr_data[irq].addr = addr;
115 ipr_data[irq].shift = pos*4; /* POSition (0-3) x 4 means shift */
116 ipr_data[irq].priority = priority;
117
118 irq_desc[irq].handler = &ipr_irq_type;
119 disable_ipr_irq(irq);
120 }
121
122 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
123 static unsigned char pint_map[256];
124 static unsigned long portcr_mask = 0;
125
126 static void enable_pint_irq(unsigned int irq);
127 static void disable_pint_irq(unsigned int irq);
128
129 /* shutdown is same as "disable" */
130 #define shutdown_pint_irq disable_pint_irq
131
132 static void mask_and_ack_pint(unsigned int);
133 static void end_pint_irq(unsigned int irq);
134
startup_pint_irq(unsigned int irq)135 static unsigned int startup_pint_irq(unsigned int irq)
136 {
137 enable_pint_irq(irq);
138 return 0; /* never anything pending */
139 }
140
141 static struct hw_interrupt_type pint_irq_type = {
142 "PINT-IRQ",
143 startup_pint_irq,
144 shutdown_pint_irq,
145 enable_pint_irq,
146 disable_pint_irq,
147 mask_and_ack_pint,
148 end_pint_irq
149 };
150
disable_pint_irq(unsigned int irq)151 static void disable_pint_irq(unsigned int irq)
152 {
153 unsigned long val, flags;
154
155 save_and_cli(flags);
156 val = ctrl_inw(INTC_INTER);
157 val &= ~(1 << (irq - PINT_IRQ_BASE));
158 ctrl_outw(val, INTC_INTER); /* disable PINTn */
159 portcr_mask &= ~(3 << (irq - PINT_IRQ_BASE)*2);
160 restore_flags(flags);
161 }
162
enable_pint_irq(unsigned int irq)163 static void enable_pint_irq(unsigned int irq)
164 {
165 unsigned long val, flags;
166
167 save_and_cli(flags);
168 val = ctrl_inw(INTC_INTER);
169 val |= 1 << (irq - PINT_IRQ_BASE);
170 ctrl_outw(val, INTC_INTER); /* enable PINTn */
171 portcr_mask |= 3 << (irq - PINT_IRQ_BASE)*2;
172 restore_flags(flags);
173 }
174
mask_and_ack_pint(unsigned int irq)175 static void mask_and_ack_pint(unsigned int irq)
176 {
177 disable_pint_irq(irq);
178 }
179
end_pint_irq(unsigned int irq)180 static void end_pint_irq(unsigned int irq)
181 {
182 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
183 enable_pint_irq(irq);
184 }
185
make_pint_irq(unsigned int irq)186 void make_pint_irq(unsigned int irq)
187 {
188 disable_irq_nosync(irq);
189 irq_desc[irq].handler = &pint_irq_type;
190 disable_pint_irq(irq);
191 }
192 #endif
193
init_IRQ(void)194 void __init init_IRQ(void)
195 {
196 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
197 int i;
198 #endif
199
200 make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY);
201
202 #if defined(CONFIG_SH_RTC)
203 make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY);
204 #endif
205
206 #ifdef SCI_ERI_IRQ
207 make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
208 make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
209 make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
210 #endif
211
212 #ifdef SCIF1_ERI_IRQ
213 make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
214 make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
215 make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
216 make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
217 #endif
218
219 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
220 make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY);
221 #endif
222
223 #ifdef SCIF_ERI_IRQ
224 make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
225 make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
226 make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
227 make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
228 #endif
229
230 #ifdef IRDA_ERI_IRQ
231 make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
232 make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
233 make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
234 make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
235 #endif
236
237 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7707) || \
238 defined(CONFIG_CPU_SUBTYPE_SH7709)
239 /*
240 * Initialize the Interrupt Controller (INTC)
241 * registers to their power on values
242 */
243
244 /*
245 * Enable external irq (INTC IRQ mode).
246 * You should set corresponding bits of PFC to "00"
247 * to enable these interrupts.
248 */
249 make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY);
250 make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY);
251 make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY);
252 make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY);
253 make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY);
254 make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY);
255 #if !defined(CONFIG_CPU_SUBTYPE_SH7300)
256 make_ipr_irq(PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY);
257 make_ipr_irq(PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY);
258 enable_ipr_irq(PINT0_IRQ);
259 enable_ipr_irq(PINT8_IRQ);
260
261 for(i = 0; i < 16; i++)
262 make_pint_irq(PINT_IRQ_BASE + i);
263 for(i = 0; i < 256; i++)
264 {
265 if(i & 1) pint_map[i] = 0;
266 else if(i & 2) pint_map[i] = 1;
267 else if(i & 4) pint_map[i] = 2;
268 else if(i & 8) pint_map[i] = 3;
269 else if(i & 0x10) pint_map[i] = 4;
270 else if(i & 0x20) pint_map[i] = 5;
271 else if(i & 0x40) pint_map[i] = 6;
272 else if(i & 0x80) pint_map[i] = 7;
273 }
274 #endif
275 #endif /* CONFIG_CPU_SUBTYPE_SH7300 || CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
276
277 #ifdef CONFIG_CPU_SUBTYPE_ST40
278 init_IRQ_intc2();
279 #endif
280
281 /* Perform the machine specific initialisation */
282 if (sh_mv.mv_init_irq != NULL) {
283 sh_mv.mv_init_irq();
284 }
285 }
286 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7707) || \
287 defined(CONFIG_CPU_SUBTYPE_SH7709)
ipr_irq_demux(int irq)288 int ipr_irq_demux(int irq)
289 {
290 #if !defined(CONFIG_CPU_SUBTYPE_SH7300)
291 unsigned long creg, dreg, d, sav;
292
293 if(irq == PINT0_IRQ)
294 {
295 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
296 creg = PORT_PACR;
297 dreg = PORT_PADR;
298 #else
299 creg = PORT_PCCR;
300 dreg = PORT_PCDR;
301 #endif
302 sav = ctrl_inw(creg);
303 ctrl_outw(sav | portcr_mask, creg);
304 d = (~ctrl_inb(dreg) ^ ctrl_inw(INTC_ICR2)) & ctrl_inw(INTC_INTER) & 0xff;
305 ctrl_outw(sav, creg);
306 if(d == 0) return irq;
307 return PINT_IRQ_BASE + pint_map[d];
308 }
309 else if(irq == PINT8_IRQ)
310 {
311 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
312 creg = PORT_PBCR;
313 dreg = PORT_PBDR;
314 #else
315 creg = PORT_PFCR;
316 dreg = PORT_PFDR;
317 #endif
318 sav = ctrl_inw(creg);
319 ctrl_outw(sav | (portcr_mask >> 16), creg);
320 d = (~ctrl_inb(dreg) ^ (ctrl_inw(INTC_ICR2) >> 8)) & (ctrl_inw(INTC_INTER) >> 8) & 0xff;
321 ctrl_outw(sav, creg);
322 if(d == 0) return irq;
323 return PINT_IRQ_BASE + 8 + pint_map[d];
324 }
325 #endif
326 return irq;
327 }
328 #endif
329