1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
3 
4 #include <linux/kernel.h>
5 #include <linux/types.h>
6 #include <linux/errno.h>
7 #include <linux/io.h>
8 #include <linux/slab.h>
9 #include <linux/etherdevice.h>
10 #include "ionic.h"
11 #include "ionic_dev.h"
12 #include "ionic_lif.h"
13 
ionic_watchdog_cb(struct timer_list * t)14 static void ionic_watchdog_cb(struct timer_list *t)
15 {
16 	struct ionic *ionic = from_timer(ionic, t, watchdog_timer);
17 	struct ionic_lif *lif = ionic->lif;
18 	struct ionic_deferred_work *work;
19 	int hb;
20 
21 	mod_timer(&ionic->watchdog_timer,
22 		  round_jiffies(jiffies + ionic->watchdog_period));
23 
24 	if (!lif)
25 		return;
26 
27 	hb = ionic_heartbeat_check(ionic);
28 	dev_dbg(ionic->dev, "%s: hb %d running %d UP %d\n",
29 		__func__, hb, netif_running(lif->netdev),
30 		test_bit(IONIC_LIF_F_UP, lif->state));
31 
32 	if (hb >= 0 &&
33 	    !test_bit(IONIC_LIF_F_FW_RESET, lif->state))
34 		ionic_link_status_check_request(lif, CAN_NOT_SLEEP);
35 
36 	if (test_bit(IONIC_LIF_F_FILTER_SYNC_NEEDED, lif->state) &&
37 	    !test_bit(IONIC_LIF_F_FW_RESET, lif->state)) {
38 		work = kzalloc(sizeof(*work), GFP_ATOMIC);
39 		if (!work) {
40 			netdev_err(lif->netdev, "rxmode change dropped\n");
41 			return;
42 		}
43 
44 		work->type = IONIC_DW_TYPE_RX_MODE;
45 		netdev_dbg(lif->netdev, "deferred: rx_mode\n");
46 		ionic_lif_deferred_enqueue(&lif->deferred, work);
47 	}
48 }
49 
ionic_watchdog_init(struct ionic * ionic)50 static void ionic_watchdog_init(struct ionic *ionic)
51 {
52 	struct ionic_dev *idev = &ionic->idev;
53 
54 	timer_setup(&ionic->watchdog_timer, ionic_watchdog_cb, 0);
55 	ionic->watchdog_period = IONIC_WATCHDOG_SECS * HZ;
56 
57 	/* set times to ensure the first check will proceed */
58 	atomic_long_set(&idev->last_check_time, jiffies - 2 * HZ);
59 	idev->last_hb_time = jiffies - 2 * ionic->watchdog_period;
60 	/* init as ready, so no transition if the first check succeeds */
61 	idev->last_fw_hb = 0;
62 	idev->fw_hb_ready = true;
63 	idev->fw_status_ready = true;
64 	idev->fw_generation = IONIC_FW_STS_F_GENERATION &
65 			      ioread8(&idev->dev_info_regs->fw_status);
66 }
67 
ionic_init_devinfo(struct ionic * ionic)68 void ionic_init_devinfo(struct ionic *ionic)
69 {
70 	struct ionic_dev *idev = &ionic->idev;
71 
72 	idev->dev_info.asic_type = ioread8(&idev->dev_info_regs->asic_type);
73 	idev->dev_info.asic_rev = ioread8(&idev->dev_info_regs->asic_rev);
74 
75 	memcpy_fromio(idev->dev_info.fw_version,
76 		      idev->dev_info_regs->fw_version,
77 		      IONIC_DEVINFO_FWVERS_BUFLEN);
78 
79 	memcpy_fromio(idev->dev_info.serial_num,
80 		      idev->dev_info_regs->serial_num,
81 		      IONIC_DEVINFO_SERIAL_BUFLEN);
82 
83 	idev->dev_info.fw_version[IONIC_DEVINFO_FWVERS_BUFLEN] = 0;
84 	idev->dev_info.serial_num[IONIC_DEVINFO_SERIAL_BUFLEN] = 0;
85 
86 	dev_dbg(ionic->dev, "fw_version %s\n", idev->dev_info.fw_version);
87 }
88 
ionic_dev_setup(struct ionic * ionic)89 int ionic_dev_setup(struct ionic *ionic)
90 {
91 	struct ionic_dev_bar *bar = ionic->bars;
92 	unsigned int num_bars = ionic->num_bars;
93 	struct ionic_dev *idev = &ionic->idev;
94 	struct device *dev = ionic->dev;
95 	u32 sig;
96 
97 	/* BAR0: dev_cmd and interrupts */
98 	if (num_bars < 1) {
99 		dev_err(dev, "No bars found, aborting\n");
100 		return -EFAULT;
101 	}
102 
103 	if (bar->len < IONIC_BAR0_SIZE) {
104 		dev_err(dev, "Resource bar size %lu too small, aborting\n",
105 			bar->len);
106 		return -EFAULT;
107 	}
108 
109 	idev->dev_info_regs = bar->vaddr + IONIC_BAR0_DEV_INFO_REGS_OFFSET;
110 	idev->dev_cmd_regs = bar->vaddr + IONIC_BAR0_DEV_CMD_REGS_OFFSET;
111 	idev->intr_status = bar->vaddr + IONIC_BAR0_INTR_STATUS_OFFSET;
112 	idev->intr_ctrl = bar->vaddr + IONIC_BAR0_INTR_CTRL_OFFSET;
113 
114 	idev->hwstamp_regs = &idev->dev_info_regs->hwstamp;
115 
116 	sig = ioread32(&idev->dev_info_regs->signature);
117 	if (sig != IONIC_DEV_INFO_SIGNATURE) {
118 		dev_err(dev, "Incompatible firmware signature %x", sig);
119 		return -EFAULT;
120 	}
121 
122 	ionic_init_devinfo(ionic);
123 
124 	/* BAR1: doorbells */
125 	bar++;
126 	if (num_bars < 2) {
127 		dev_err(dev, "Doorbell bar missing, aborting\n");
128 		return -EFAULT;
129 	}
130 
131 	ionic_watchdog_init(ionic);
132 
133 	idev->db_pages = bar->vaddr;
134 	idev->phy_db_pages = bar->bus_addr;
135 
136 	return 0;
137 }
138 
139 /* Devcmd Interface */
ionic_is_fw_running(struct ionic_dev * idev)140 bool ionic_is_fw_running(struct ionic_dev *idev)
141 {
142 	u8 fw_status = ioread8(&idev->dev_info_regs->fw_status);
143 
144 	/* firmware is useful only if the running bit is set and
145 	 * fw_status != 0xff (bad PCI read)
146 	 */
147 	return (fw_status != 0xff) && (fw_status & IONIC_FW_STS_F_RUNNING);
148 }
149 
ionic_heartbeat_check(struct ionic * ionic)150 int ionic_heartbeat_check(struct ionic *ionic)
151 {
152 	unsigned long check_time, last_check_time;
153 	struct ionic_dev *idev = &ionic->idev;
154 	struct ionic_lif *lif = ionic->lif;
155 	bool fw_status_ready = true;
156 	bool fw_hb_ready;
157 	u8 fw_generation;
158 	u8 fw_status;
159 	u32 fw_hb;
160 
161 	/* wait a least one second before testing again */
162 	check_time = jiffies;
163 	last_check_time = atomic_long_read(&idev->last_check_time);
164 do_check_time:
165 	if (time_before(check_time, last_check_time + HZ))
166 		return 0;
167 	if (!atomic_long_try_cmpxchg_relaxed(&idev->last_check_time,
168 					     &last_check_time, check_time)) {
169 		/* if called concurrently, only the first should proceed. */
170 		dev_dbg(ionic->dev, "%s: do_check_time again\n", __func__);
171 		goto do_check_time;
172 	}
173 
174 	fw_status = ioread8(&idev->dev_info_regs->fw_status);
175 
176 	/* If fw_status is not ready don't bother with the generation */
177 	if (!ionic_is_fw_running(idev)) {
178 		fw_status_ready = false;
179 	} else {
180 		fw_generation = fw_status & IONIC_FW_STS_F_GENERATION;
181 		if (idev->fw_generation != fw_generation) {
182 			dev_info(ionic->dev, "FW generation 0x%02x -> 0x%02x\n",
183 				 idev->fw_generation, fw_generation);
184 
185 			idev->fw_generation = fw_generation;
186 
187 			/* If the generation changed, the fw status is not
188 			 * ready so we need to trigger a fw-down cycle.  After
189 			 * the down, the next watchdog will see the fw is up
190 			 * and the generation value stable, so will trigger
191 			 * the fw-up activity.
192 			 *
193 			 * If we had already moved to FW_RESET from a RESET event,
194 			 * it is possible that we never saw the fw_status go to 0,
195 			 * so we fake the current idev->fw_status_ready here to
196 			 * force the transition and get FW up again.
197 			 */
198 			if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
199 				idev->fw_status_ready = false;	/* go to running */
200 			else
201 				fw_status_ready = false;	/* go to down */
202 		}
203 	}
204 
205 	dev_dbg(ionic->dev, "fw_status 0x%02x ready %d idev->ready %d last_hb 0x%x state 0x%02lx\n",
206 		fw_status, fw_status_ready, idev->fw_status_ready,
207 		idev->last_fw_hb, lif->state[0]);
208 
209 	/* is this a transition? */
210 	if (fw_status_ready != idev->fw_status_ready &&
211 	    !test_bit(IONIC_LIF_F_FW_STOPPING, lif->state)) {
212 		bool trigger = false;
213 
214 		idev->fw_status_ready = fw_status_ready;
215 
216 		if (!fw_status_ready &&
217 		    !test_bit(IONIC_LIF_F_FW_RESET, lif->state) &&
218 		    !test_and_set_bit(IONIC_LIF_F_FW_STOPPING, lif->state)) {
219 			dev_info(ionic->dev, "FW stopped 0x%02x\n", fw_status);
220 			trigger = true;
221 
222 		} else if (fw_status_ready &&
223 			   test_bit(IONIC_LIF_F_FW_RESET, lif->state)) {
224 			dev_info(ionic->dev, "FW running 0x%02x\n", fw_status);
225 			trigger = true;
226 		}
227 
228 		if (trigger) {
229 			struct ionic_deferred_work *work;
230 
231 			work = kzalloc(sizeof(*work), GFP_ATOMIC);
232 			if (work) {
233 				work->type = IONIC_DW_TYPE_LIF_RESET;
234 				work->fw_status = fw_status_ready;
235 				ionic_lif_deferred_enqueue(&lif->deferred, work);
236 			}
237 		}
238 	}
239 
240 	if (!idev->fw_status_ready)
241 		return -ENXIO;
242 
243 	/* Because of some variability in the actual FW heartbeat, we
244 	 * wait longer than the DEVCMD_TIMEOUT before checking again.
245 	 */
246 	last_check_time = idev->last_hb_time;
247 	if (time_before(check_time, last_check_time + DEVCMD_TIMEOUT * 2 * HZ))
248 		return 0;
249 
250 	fw_hb = ioread32(&idev->dev_info_regs->fw_heartbeat);
251 	fw_hb_ready = fw_hb != idev->last_fw_hb;
252 
253 	/* early FW version had no heartbeat, so fake it */
254 	if (!fw_hb_ready && !fw_hb)
255 		fw_hb_ready = true;
256 
257 	dev_dbg(ionic->dev, "%s: fw_hb %u last_fw_hb %u ready %u\n",
258 		__func__, fw_hb, idev->last_fw_hb, fw_hb_ready);
259 
260 	idev->last_fw_hb = fw_hb;
261 
262 	/* log a transition */
263 	if (fw_hb_ready != idev->fw_hb_ready) {
264 		idev->fw_hb_ready = fw_hb_ready;
265 		if (!fw_hb_ready)
266 			dev_info(ionic->dev, "FW heartbeat stalled at %d\n", fw_hb);
267 		else
268 			dev_info(ionic->dev, "FW heartbeat restored at %d\n", fw_hb);
269 	}
270 
271 	if (!fw_hb_ready)
272 		return -ENXIO;
273 
274 	idev->last_hb_time = check_time;
275 
276 	return 0;
277 }
278 
ionic_dev_cmd_status(struct ionic_dev * idev)279 u8 ionic_dev_cmd_status(struct ionic_dev *idev)
280 {
281 	return ioread8(&idev->dev_cmd_regs->comp.comp.status);
282 }
283 
ionic_dev_cmd_done(struct ionic_dev * idev)284 bool ionic_dev_cmd_done(struct ionic_dev *idev)
285 {
286 	return ioread32(&idev->dev_cmd_regs->done) & IONIC_DEV_CMD_DONE;
287 }
288 
ionic_dev_cmd_comp(struct ionic_dev * idev,union ionic_dev_cmd_comp * comp)289 void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp)
290 {
291 	memcpy_fromio(comp, &idev->dev_cmd_regs->comp, sizeof(*comp));
292 }
293 
ionic_dev_cmd_go(struct ionic_dev * idev,union ionic_dev_cmd * cmd)294 void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd)
295 {
296 	memcpy_toio(&idev->dev_cmd_regs->cmd, cmd, sizeof(*cmd));
297 	iowrite32(0, &idev->dev_cmd_regs->done);
298 	iowrite32(1, &idev->dev_cmd_regs->doorbell);
299 }
300 
301 /* Device commands */
ionic_dev_cmd_identify(struct ionic_dev * idev,u8 ver)302 void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver)
303 {
304 	union ionic_dev_cmd cmd = {
305 		.identify.opcode = IONIC_CMD_IDENTIFY,
306 		.identify.ver = ver,
307 	};
308 
309 	ionic_dev_cmd_go(idev, &cmd);
310 }
311 
ionic_dev_cmd_init(struct ionic_dev * idev)312 void ionic_dev_cmd_init(struct ionic_dev *idev)
313 {
314 	union ionic_dev_cmd cmd = {
315 		.init.opcode = IONIC_CMD_INIT,
316 		.init.type = 0,
317 	};
318 
319 	ionic_dev_cmd_go(idev, &cmd);
320 }
321 
ionic_dev_cmd_reset(struct ionic_dev * idev)322 void ionic_dev_cmd_reset(struct ionic_dev *idev)
323 {
324 	union ionic_dev_cmd cmd = {
325 		.reset.opcode = IONIC_CMD_RESET,
326 	};
327 
328 	ionic_dev_cmd_go(idev, &cmd);
329 }
330 
331 /* Port commands */
ionic_dev_cmd_port_identify(struct ionic_dev * idev)332 void ionic_dev_cmd_port_identify(struct ionic_dev *idev)
333 {
334 	union ionic_dev_cmd cmd = {
335 		.port_init.opcode = IONIC_CMD_PORT_IDENTIFY,
336 		.port_init.index = 0,
337 	};
338 
339 	ionic_dev_cmd_go(idev, &cmd);
340 }
341 
ionic_dev_cmd_port_init(struct ionic_dev * idev)342 void ionic_dev_cmd_port_init(struct ionic_dev *idev)
343 {
344 	union ionic_dev_cmd cmd = {
345 		.port_init.opcode = IONIC_CMD_PORT_INIT,
346 		.port_init.index = 0,
347 		.port_init.info_pa = cpu_to_le64(idev->port_info_pa),
348 	};
349 
350 	ionic_dev_cmd_go(idev, &cmd);
351 }
352 
ionic_dev_cmd_port_reset(struct ionic_dev * idev)353 void ionic_dev_cmd_port_reset(struct ionic_dev *idev)
354 {
355 	union ionic_dev_cmd cmd = {
356 		.port_reset.opcode = IONIC_CMD_PORT_RESET,
357 		.port_reset.index = 0,
358 	};
359 
360 	ionic_dev_cmd_go(idev, &cmd);
361 }
362 
ionic_dev_cmd_port_state(struct ionic_dev * idev,u8 state)363 void ionic_dev_cmd_port_state(struct ionic_dev *idev, u8 state)
364 {
365 	union ionic_dev_cmd cmd = {
366 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
367 		.port_setattr.index = 0,
368 		.port_setattr.attr = IONIC_PORT_ATTR_STATE,
369 		.port_setattr.state = state,
370 	};
371 
372 	ionic_dev_cmd_go(idev, &cmd);
373 }
374 
ionic_dev_cmd_port_speed(struct ionic_dev * idev,u32 speed)375 void ionic_dev_cmd_port_speed(struct ionic_dev *idev, u32 speed)
376 {
377 	union ionic_dev_cmd cmd = {
378 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
379 		.port_setattr.index = 0,
380 		.port_setattr.attr = IONIC_PORT_ATTR_SPEED,
381 		.port_setattr.speed = cpu_to_le32(speed),
382 	};
383 
384 	ionic_dev_cmd_go(idev, &cmd);
385 }
386 
ionic_dev_cmd_port_autoneg(struct ionic_dev * idev,u8 an_enable)387 void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, u8 an_enable)
388 {
389 	union ionic_dev_cmd cmd = {
390 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
391 		.port_setattr.index = 0,
392 		.port_setattr.attr = IONIC_PORT_ATTR_AUTONEG,
393 		.port_setattr.an_enable = an_enable,
394 	};
395 
396 	ionic_dev_cmd_go(idev, &cmd);
397 }
398 
ionic_dev_cmd_port_fec(struct ionic_dev * idev,u8 fec_type)399 void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type)
400 {
401 	union ionic_dev_cmd cmd = {
402 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
403 		.port_setattr.index = 0,
404 		.port_setattr.attr = IONIC_PORT_ATTR_FEC,
405 		.port_setattr.fec_type = fec_type,
406 	};
407 
408 	ionic_dev_cmd_go(idev, &cmd);
409 }
410 
ionic_dev_cmd_port_pause(struct ionic_dev * idev,u8 pause_type)411 void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type)
412 {
413 	union ionic_dev_cmd cmd = {
414 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
415 		.port_setattr.index = 0,
416 		.port_setattr.attr = IONIC_PORT_ATTR_PAUSE,
417 		.port_setattr.pause_type = pause_type,
418 	};
419 
420 	ionic_dev_cmd_go(idev, &cmd);
421 }
422 
423 /* VF commands */
ionic_set_vf_config(struct ionic * ionic,int vf,struct ionic_vf_setattr_cmd * vfc)424 int ionic_set_vf_config(struct ionic *ionic, int vf,
425 			struct ionic_vf_setattr_cmd *vfc)
426 {
427 	union ionic_dev_cmd cmd = {
428 		.vf_setattr.opcode = IONIC_CMD_VF_SETATTR,
429 		.vf_setattr.attr = vfc->attr,
430 		.vf_setattr.vf_index = cpu_to_le16(vf),
431 	};
432 	int err;
433 
434 	memcpy(cmd.vf_setattr.pad, vfc->pad, sizeof(vfc->pad));
435 
436 	mutex_lock(&ionic->dev_cmd_lock);
437 	ionic_dev_cmd_go(&ionic->idev, &cmd);
438 	err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
439 	mutex_unlock(&ionic->dev_cmd_lock);
440 
441 	return err;
442 }
443 
ionic_dev_cmd_vf_getattr(struct ionic * ionic,int vf,u8 attr,struct ionic_vf_getattr_comp * comp)444 int ionic_dev_cmd_vf_getattr(struct ionic *ionic, int vf, u8 attr,
445 			     struct ionic_vf_getattr_comp *comp)
446 {
447 	union ionic_dev_cmd cmd = {
448 		.vf_getattr.opcode = IONIC_CMD_VF_GETATTR,
449 		.vf_getattr.attr = attr,
450 		.vf_getattr.vf_index = cpu_to_le16(vf),
451 	};
452 	int err;
453 
454 	if (vf >= ionic->num_vfs)
455 		return -EINVAL;
456 
457 	switch (attr) {
458 	case IONIC_VF_ATTR_SPOOFCHK:
459 	case IONIC_VF_ATTR_TRUST:
460 	case IONIC_VF_ATTR_LINKSTATE:
461 	case IONIC_VF_ATTR_MAC:
462 	case IONIC_VF_ATTR_VLAN:
463 	case IONIC_VF_ATTR_RATE:
464 		break;
465 	case IONIC_VF_ATTR_STATSADDR:
466 	default:
467 		return -EINVAL;
468 	}
469 
470 	mutex_lock(&ionic->dev_cmd_lock);
471 	ionic_dev_cmd_go(&ionic->idev, &cmd);
472 	err = ionic_dev_cmd_wait_nomsg(ionic, DEVCMD_TIMEOUT);
473 	memcpy_fromio(comp, &ionic->idev.dev_cmd_regs->comp.vf_getattr,
474 		      sizeof(*comp));
475 	mutex_unlock(&ionic->dev_cmd_lock);
476 
477 	if (err && comp->status != IONIC_RC_ENOSUPP)
478 		ionic_dev_cmd_dev_err_print(ionic, cmd.vf_getattr.opcode,
479 					    comp->status, err);
480 
481 	return err;
482 }
483 
484 /* LIF commands */
ionic_dev_cmd_queue_identify(struct ionic_dev * idev,u16 lif_type,u8 qtype,u8 qver)485 void ionic_dev_cmd_queue_identify(struct ionic_dev *idev,
486 				  u16 lif_type, u8 qtype, u8 qver)
487 {
488 	union ionic_dev_cmd cmd = {
489 		.q_identify.opcode = IONIC_CMD_Q_IDENTIFY,
490 		.q_identify.lif_type = cpu_to_le16(lif_type),
491 		.q_identify.type = qtype,
492 		.q_identify.ver = qver,
493 	};
494 
495 	ionic_dev_cmd_go(idev, &cmd);
496 }
497 
ionic_dev_cmd_lif_identify(struct ionic_dev * idev,u8 type,u8 ver)498 void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver)
499 {
500 	union ionic_dev_cmd cmd = {
501 		.lif_identify.opcode = IONIC_CMD_LIF_IDENTIFY,
502 		.lif_identify.type = type,
503 		.lif_identify.ver = ver,
504 	};
505 
506 	ionic_dev_cmd_go(idev, &cmd);
507 }
508 
ionic_dev_cmd_lif_init(struct ionic_dev * idev,u16 lif_index,dma_addr_t info_pa)509 void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index,
510 			    dma_addr_t info_pa)
511 {
512 	union ionic_dev_cmd cmd = {
513 		.lif_init.opcode = IONIC_CMD_LIF_INIT,
514 		.lif_init.index = cpu_to_le16(lif_index),
515 		.lif_init.info_pa = cpu_to_le64(info_pa),
516 	};
517 
518 	ionic_dev_cmd_go(idev, &cmd);
519 }
520 
ionic_dev_cmd_lif_reset(struct ionic_dev * idev,u16 lif_index)521 void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index)
522 {
523 	union ionic_dev_cmd cmd = {
524 		.lif_init.opcode = IONIC_CMD_LIF_RESET,
525 		.lif_init.index = cpu_to_le16(lif_index),
526 	};
527 
528 	ionic_dev_cmd_go(idev, &cmd);
529 }
530 
ionic_dev_cmd_adminq_init(struct ionic_dev * idev,struct ionic_qcq * qcq,u16 lif_index,u16 intr_index)531 void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq,
532 			       u16 lif_index, u16 intr_index)
533 {
534 	struct ionic_queue *q = &qcq->q;
535 	struct ionic_cq *cq = &qcq->cq;
536 
537 	union ionic_dev_cmd cmd = {
538 		.q_init.opcode = IONIC_CMD_Q_INIT,
539 		.q_init.lif_index = cpu_to_le16(lif_index),
540 		.q_init.type = q->type,
541 		.q_init.ver = qcq->q.lif->qtype_info[q->type].version,
542 		.q_init.index = cpu_to_le32(q->index),
543 		.q_init.flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
544 					    IONIC_QINIT_F_ENA),
545 		.q_init.pid = cpu_to_le16(q->pid),
546 		.q_init.intr_index = cpu_to_le16(intr_index),
547 		.q_init.ring_size = ilog2(q->num_descs),
548 		.q_init.ring_base = cpu_to_le64(q->base_pa),
549 		.q_init.cq_ring_base = cpu_to_le64(cq->base_pa),
550 	};
551 
552 	ionic_dev_cmd_go(idev, &cmd);
553 }
554 
ionic_db_page_num(struct ionic_lif * lif,int pid)555 int ionic_db_page_num(struct ionic_lif *lif, int pid)
556 {
557 	return (lif->hw_index * lif->dbid_count) + pid;
558 }
559 
ionic_cq_init(struct ionic_lif * lif,struct ionic_cq * cq,struct ionic_intr_info * intr,unsigned int num_descs,size_t desc_size)560 int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq,
561 		  struct ionic_intr_info *intr,
562 		  unsigned int num_descs, size_t desc_size)
563 {
564 	unsigned int ring_size;
565 
566 	if (desc_size == 0 || !is_power_of_2(num_descs))
567 		return -EINVAL;
568 
569 	ring_size = ilog2(num_descs);
570 	if (ring_size < 2 || ring_size > 16)
571 		return -EINVAL;
572 
573 	cq->lif = lif;
574 	cq->bound_intr = intr;
575 	cq->num_descs = num_descs;
576 	cq->desc_size = desc_size;
577 	cq->tail_idx = 0;
578 	cq->done_color = 1;
579 
580 	return 0;
581 }
582 
ionic_cq_map(struct ionic_cq * cq,void * base,dma_addr_t base_pa)583 void ionic_cq_map(struct ionic_cq *cq, void *base, dma_addr_t base_pa)
584 {
585 	struct ionic_cq_info *cur;
586 	unsigned int i;
587 
588 	cq->base = base;
589 	cq->base_pa = base_pa;
590 
591 	for (i = 0, cur = cq->info; i < cq->num_descs; i++, cur++)
592 		cur->cq_desc = base + (i * cq->desc_size);
593 }
594 
ionic_cq_bind(struct ionic_cq * cq,struct ionic_queue * q)595 void ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q)
596 {
597 	cq->bound_q = q;
598 }
599 
ionic_cq_service(struct ionic_cq * cq,unsigned int work_to_do,ionic_cq_cb cb,ionic_cq_done_cb done_cb,void * done_arg)600 unsigned int ionic_cq_service(struct ionic_cq *cq, unsigned int work_to_do,
601 			      ionic_cq_cb cb, ionic_cq_done_cb done_cb,
602 			      void *done_arg)
603 {
604 	struct ionic_cq_info *cq_info;
605 	unsigned int work_done = 0;
606 
607 	if (work_to_do == 0)
608 		return 0;
609 
610 	cq_info = &cq->info[cq->tail_idx];
611 	while (cb(cq, cq_info)) {
612 		if (cq->tail_idx == cq->num_descs - 1)
613 			cq->done_color = !cq->done_color;
614 		cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1);
615 		cq_info = &cq->info[cq->tail_idx];
616 
617 		if (++work_done >= work_to_do)
618 			break;
619 	}
620 
621 	if (work_done && done_cb)
622 		done_cb(done_arg);
623 
624 	return work_done;
625 }
626 
ionic_q_init(struct ionic_lif * lif,struct ionic_dev * idev,struct ionic_queue * q,unsigned int index,const char * name,unsigned int num_descs,size_t desc_size,size_t sg_desc_size,unsigned int pid)627 int ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev,
628 		 struct ionic_queue *q, unsigned int index, const char *name,
629 		 unsigned int num_descs, size_t desc_size,
630 		 size_t sg_desc_size, unsigned int pid)
631 {
632 	unsigned int ring_size;
633 
634 	if (desc_size == 0 || !is_power_of_2(num_descs))
635 		return -EINVAL;
636 
637 	ring_size = ilog2(num_descs);
638 	if (ring_size < 2 || ring_size > 16)
639 		return -EINVAL;
640 
641 	q->lif = lif;
642 	q->idev = idev;
643 	q->index = index;
644 	q->num_descs = num_descs;
645 	q->desc_size = desc_size;
646 	q->sg_desc_size = sg_desc_size;
647 	q->tail_idx = 0;
648 	q->head_idx = 0;
649 	q->pid = pid;
650 
651 	snprintf(q->name, sizeof(q->name), "L%d-%s%u", lif->index, name, index);
652 
653 	return 0;
654 }
655 
ionic_q_map(struct ionic_queue * q,void * base,dma_addr_t base_pa)656 void ionic_q_map(struct ionic_queue *q, void *base, dma_addr_t base_pa)
657 {
658 	struct ionic_desc_info *cur;
659 	unsigned int i;
660 
661 	q->base = base;
662 	q->base_pa = base_pa;
663 
664 	for (i = 0, cur = q->info; i < q->num_descs; i++, cur++)
665 		cur->desc = base + (i * q->desc_size);
666 }
667 
ionic_q_sg_map(struct ionic_queue * q,void * base,dma_addr_t base_pa)668 void ionic_q_sg_map(struct ionic_queue *q, void *base, dma_addr_t base_pa)
669 {
670 	struct ionic_desc_info *cur;
671 	unsigned int i;
672 
673 	q->sg_base = base;
674 	q->sg_base_pa = base_pa;
675 
676 	for (i = 0, cur = q->info; i < q->num_descs; i++, cur++)
677 		cur->sg_desc = base + (i * q->sg_desc_size);
678 }
679 
ionic_q_post(struct ionic_queue * q,bool ring_doorbell,ionic_desc_cb cb,void * cb_arg)680 void ionic_q_post(struct ionic_queue *q, bool ring_doorbell, ionic_desc_cb cb,
681 		  void *cb_arg)
682 {
683 	struct ionic_desc_info *desc_info;
684 	struct ionic_lif *lif = q->lif;
685 	struct device *dev = q->dev;
686 
687 	desc_info = &q->info[q->head_idx];
688 	desc_info->cb = cb;
689 	desc_info->cb_arg = cb_arg;
690 
691 	q->head_idx = (q->head_idx + 1) & (q->num_descs - 1);
692 
693 	dev_dbg(dev, "lif=%d qname=%s qid=%d qtype=%d p_index=%d ringdb=%d\n",
694 		q->lif->index, q->name, q->hw_type, q->hw_index,
695 		q->head_idx, ring_doorbell);
696 
697 	if (ring_doorbell)
698 		ionic_dbell_ring(lif->kern_dbpage, q->hw_type,
699 				 q->dbval | q->head_idx);
700 }
701 
ionic_q_is_posted(struct ionic_queue * q,unsigned int pos)702 static bool ionic_q_is_posted(struct ionic_queue *q, unsigned int pos)
703 {
704 	unsigned int mask, tail, head;
705 
706 	mask = q->num_descs - 1;
707 	tail = q->tail_idx;
708 	head = q->head_idx;
709 
710 	return ((pos - tail) & mask) < ((head - tail) & mask);
711 }
712 
ionic_q_service(struct ionic_queue * q,struct ionic_cq_info * cq_info,unsigned int stop_index)713 void ionic_q_service(struct ionic_queue *q, struct ionic_cq_info *cq_info,
714 		     unsigned int stop_index)
715 {
716 	struct ionic_desc_info *desc_info;
717 	ionic_desc_cb cb;
718 	void *cb_arg;
719 	u16 index;
720 
721 	/* check for empty queue */
722 	if (q->tail_idx == q->head_idx)
723 		return;
724 
725 	/* stop index must be for a descriptor that is not yet completed */
726 	if (unlikely(!ionic_q_is_posted(q, stop_index)))
727 		dev_err(q->dev,
728 			"ionic stop is not posted %s stop %u tail %u head %u\n",
729 			q->name, stop_index, q->tail_idx, q->head_idx);
730 
731 	do {
732 		desc_info = &q->info[q->tail_idx];
733 		index = q->tail_idx;
734 		q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
735 
736 		cb = desc_info->cb;
737 		cb_arg = desc_info->cb_arg;
738 
739 		desc_info->cb = NULL;
740 		desc_info->cb_arg = NULL;
741 
742 		if (cb)
743 			cb(q, desc_info, cq_info, cb_arg);
744 	} while (index != stop_index);
745 }
746