1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
3
4 #include <linux/ethtool.h>
5 #include <linux/printk.h>
6 #include <linux/dynamic_debug.h>
7 #include <linux/netdevice.h>
8 #include <linux/etherdevice.h>
9 #include <linux/if_vlan.h>
10 #include <linux/rtnetlink.h>
11 #include <linux/interrupt.h>
12 #include <linux/pci.h>
13 #include <linux/cpumask.h>
14 #include <linux/crash_dump.h>
15 #include <linux/vmalloc.h>
16
17 #include "ionic.h"
18 #include "ionic_bus.h"
19 #include "ionic_lif.h"
20 #include "ionic_txrx.h"
21 #include "ionic_ethtool.h"
22 #include "ionic_debugfs.h"
23
24 /* queuetype support level */
25 static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = {
26 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */
27 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */
28 [IONIC_QTYPE_RXQ] = 0, /* 0 = Base version with CQ+SG support */
29 [IONIC_QTYPE_TXQ] = 1, /* 0 = Base version with CQ+SG support
30 * 1 = ... with Tx SG version 1
31 */
32 };
33
34 static void ionic_link_status_check(struct ionic_lif *lif);
35 static void ionic_lif_handle_fw_down(struct ionic_lif *lif);
36 static void ionic_lif_handle_fw_up(struct ionic_lif *lif);
37 static void ionic_lif_set_netdev_info(struct ionic_lif *lif);
38
39 static void ionic_txrx_deinit(struct ionic_lif *lif);
40 static int ionic_txrx_init(struct ionic_lif *lif);
41 static int ionic_start_queues(struct ionic_lif *lif);
42 static void ionic_stop_queues(struct ionic_lif *lif);
43 static void ionic_lif_queue_identify(struct ionic_lif *lif);
44
ionic_dim_work(struct work_struct * work)45 static void ionic_dim_work(struct work_struct *work)
46 {
47 struct dim *dim = container_of(work, struct dim, work);
48 struct dim_cq_moder cur_moder;
49 struct ionic_qcq *qcq;
50 u32 new_coal;
51
52 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
53 qcq = container_of(dim, struct ionic_qcq, dim);
54 new_coal = ionic_coal_usec_to_hw(qcq->q.lif->ionic, cur_moder.usec);
55 new_coal = new_coal ? new_coal : 1;
56
57 if (qcq->intr.dim_coal_hw != new_coal) {
58 unsigned int qi = qcq->cq.bound_q->index;
59 struct ionic_lif *lif = qcq->q.lif;
60
61 qcq->intr.dim_coal_hw = new_coal;
62
63 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
64 lif->rxqcqs[qi]->intr.index,
65 qcq->intr.dim_coal_hw);
66 }
67
68 dim->state = DIM_START_MEASURE;
69 }
70
ionic_lif_deferred_work(struct work_struct * work)71 static void ionic_lif_deferred_work(struct work_struct *work)
72 {
73 struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work);
74 struct ionic_deferred *def = &lif->deferred;
75 struct ionic_deferred_work *w = NULL;
76
77 do {
78 spin_lock_bh(&def->lock);
79 if (!list_empty(&def->list)) {
80 w = list_first_entry(&def->list,
81 struct ionic_deferred_work, list);
82 list_del(&w->list);
83 }
84 spin_unlock_bh(&def->lock);
85
86 if (!w)
87 break;
88
89 switch (w->type) {
90 case IONIC_DW_TYPE_RX_MODE:
91 ionic_lif_rx_mode(lif);
92 break;
93 case IONIC_DW_TYPE_LINK_STATUS:
94 ionic_link_status_check(lif);
95 break;
96 case IONIC_DW_TYPE_LIF_RESET:
97 if (w->fw_status) {
98 ionic_lif_handle_fw_up(lif);
99 } else {
100 ionic_lif_handle_fw_down(lif);
101
102 /* Fire off another watchdog to see
103 * if the FW is already back rather than
104 * waiting another whole cycle
105 */
106 mod_timer(&lif->ionic->watchdog_timer, jiffies + 1);
107 }
108 break;
109 default:
110 break;
111 }
112 kfree(w);
113 w = NULL;
114 } while (true);
115 }
116
ionic_lif_deferred_enqueue(struct ionic_deferred * def,struct ionic_deferred_work * work)117 void ionic_lif_deferred_enqueue(struct ionic_deferred *def,
118 struct ionic_deferred_work *work)
119 {
120 spin_lock_bh(&def->lock);
121 list_add_tail(&work->list, &def->list);
122 spin_unlock_bh(&def->lock);
123 schedule_work(&def->work);
124 }
125
ionic_link_status_check(struct ionic_lif * lif)126 static void ionic_link_status_check(struct ionic_lif *lif)
127 {
128 struct net_device *netdev = lif->netdev;
129 u16 link_status;
130 bool link_up;
131
132 if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state))
133 return;
134
135 /* Don't put carrier back up if we're in a broken state */
136 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) {
137 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state);
138 return;
139 }
140
141 link_status = le16_to_cpu(lif->info->status.link_status);
142 link_up = link_status == IONIC_PORT_OPER_STATUS_UP;
143
144 if (link_up) {
145 int err = 0;
146
147 if (netdev->flags & IFF_UP && netif_running(netdev)) {
148 mutex_lock(&lif->queue_lock);
149 err = ionic_start_queues(lif);
150 if (err && err != -EBUSY) {
151 netdev_err(lif->netdev,
152 "Failed to start queues: %d\n", err);
153 set_bit(IONIC_LIF_F_BROKEN, lif->state);
154 netif_carrier_off(lif->netdev);
155 }
156 mutex_unlock(&lif->queue_lock);
157 }
158
159 if (!err && !netif_carrier_ok(netdev)) {
160 ionic_port_identify(lif->ionic);
161 netdev_info(netdev, "Link up - %d Gbps\n",
162 le32_to_cpu(lif->info->status.link_speed) / 1000);
163 netif_carrier_on(netdev);
164 }
165 } else {
166 if (netif_carrier_ok(netdev)) {
167 netdev_info(netdev, "Link down\n");
168 netif_carrier_off(netdev);
169 }
170
171 if (netdev->flags & IFF_UP && netif_running(netdev)) {
172 mutex_lock(&lif->queue_lock);
173 ionic_stop_queues(lif);
174 mutex_unlock(&lif->queue_lock);
175 }
176 }
177
178 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state);
179 }
180
ionic_link_status_check_request(struct ionic_lif * lif,bool can_sleep)181 void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep)
182 {
183 struct ionic_deferred_work *work;
184
185 /* we only need one request outstanding at a time */
186 if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state))
187 return;
188
189 if (!can_sleep) {
190 work = kzalloc(sizeof(*work), GFP_ATOMIC);
191 if (!work) {
192 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state);
193 return;
194 }
195
196 work->type = IONIC_DW_TYPE_LINK_STATUS;
197 ionic_lif_deferred_enqueue(&lif->deferred, work);
198 } else {
199 ionic_link_status_check(lif);
200 }
201 }
202
ionic_isr(int irq,void * data)203 static irqreturn_t ionic_isr(int irq, void *data)
204 {
205 struct napi_struct *napi = data;
206
207 napi_schedule_irqoff(napi);
208
209 return IRQ_HANDLED;
210 }
211
ionic_request_irq(struct ionic_lif * lif,struct ionic_qcq * qcq)212 static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq)
213 {
214 struct ionic_intr_info *intr = &qcq->intr;
215 struct device *dev = lif->ionic->dev;
216 struct ionic_queue *q = &qcq->q;
217 const char *name;
218
219 if (lif->registered)
220 name = lif->netdev->name;
221 else
222 name = dev_name(dev);
223
224 snprintf(intr->name, sizeof(intr->name),
225 "%s-%s-%s", IONIC_DRV_NAME, name, q->name);
226
227 return devm_request_irq(dev, intr->vector, ionic_isr,
228 0, intr->name, &qcq->napi);
229 }
230
ionic_intr_alloc(struct ionic_lif * lif,struct ionic_intr_info * intr)231 static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
232 {
233 struct ionic *ionic = lif->ionic;
234 int index;
235
236 index = find_first_zero_bit(ionic->intrs, ionic->nintrs);
237 if (index == ionic->nintrs) {
238 netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n",
239 __func__, index, ionic->nintrs);
240 return -ENOSPC;
241 }
242
243 set_bit(index, ionic->intrs);
244 ionic_intr_init(&ionic->idev, intr, index);
245
246 return 0;
247 }
248
ionic_intr_free(struct ionic * ionic,int index)249 static void ionic_intr_free(struct ionic *ionic, int index)
250 {
251 if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < ionic->nintrs)
252 clear_bit(index, ionic->intrs);
253 }
254
ionic_qcq_enable(struct ionic_qcq * qcq)255 static int ionic_qcq_enable(struct ionic_qcq *qcq)
256 {
257 struct ionic_queue *q = &qcq->q;
258 struct ionic_lif *lif = q->lif;
259 struct ionic_dev *idev;
260 struct device *dev;
261
262 struct ionic_admin_ctx ctx = {
263 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
264 .cmd.q_control = {
265 .opcode = IONIC_CMD_Q_CONTROL,
266 .lif_index = cpu_to_le16(lif->index),
267 .type = q->type,
268 .index = cpu_to_le32(q->index),
269 .oper = IONIC_Q_ENABLE,
270 },
271 };
272
273 idev = &lif->ionic->idev;
274 dev = lif->ionic->dev;
275
276 dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n",
277 ctx.cmd.q_control.index, ctx.cmd.q_control.type);
278
279 if (qcq->flags & IONIC_QCQ_F_INTR) {
280 irq_set_affinity_hint(qcq->intr.vector,
281 &qcq->intr.affinity_mask);
282 napi_enable(&qcq->napi);
283 ionic_intr_clean(idev->intr_ctrl, qcq->intr.index);
284 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
285 IONIC_INTR_MASK_CLEAR);
286 }
287
288 return ionic_adminq_post_wait(lif, &ctx);
289 }
290
ionic_qcq_disable(struct ionic_lif * lif,struct ionic_qcq * qcq,int fw_err)291 static int ionic_qcq_disable(struct ionic_lif *lif, struct ionic_qcq *qcq, int fw_err)
292 {
293 struct ionic_queue *q;
294
295 struct ionic_admin_ctx ctx = {
296 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
297 .cmd.q_control = {
298 .opcode = IONIC_CMD_Q_CONTROL,
299 .oper = IONIC_Q_DISABLE,
300 },
301 };
302
303 if (!qcq) {
304 netdev_err(lif->netdev, "%s: bad qcq\n", __func__);
305 return -ENXIO;
306 }
307
308 q = &qcq->q;
309
310 if (qcq->flags & IONIC_QCQ_F_INTR) {
311 struct ionic_dev *idev = &lif->ionic->idev;
312
313 cancel_work_sync(&qcq->dim.work);
314 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
315 IONIC_INTR_MASK_SET);
316 synchronize_irq(qcq->intr.vector);
317 irq_set_affinity_hint(qcq->intr.vector, NULL);
318 napi_disable(&qcq->napi);
319 }
320
321 /* If there was a previous fw communcation error, don't bother with
322 * sending the adminq command and just return the same error value.
323 */
324 if (fw_err == -ETIMEDOUT || fw_err == -ENXIO)
325 return fw_err;
326
327 ctx.cmd.q_control.lif_index = cpu_to_le16(lif->index);
328 ctx.cmd.q_control.type = q->type;
329 ctx.cmd.q_control.index = cpu_to_le32(q->index);
330 dev_dbg(lif->ionic->dev, "q_disable.index %d q_disable.qtype %d\n",
331 ctx.cmd.q_control.index, ctx.cmd.q_control.type);
332
333 return ionic_adminq_post_wait(lif, &ctx);
334 }
335
ionic_lif_qcq_deinit(struct ionic_lif * lif,struct ionic_qcq * qcq)336 static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq)
337 {
338 struct ionic_dev *idev = &lif->ionic->idev;
339
340 if (!qcq)
341 return;
342
343 if (!(qcq->flags & IONIC_QCQ_F_INITED))
344 return;
345
346 if (qcq->flags & IONIC_QCQ_F_INTR) {
347 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
348 IONIC_INTR_MASK_SET);
349 netif_napi_del(&qcq->napi);
350 }
351
352 qcq->flags &= ~IONIC_QCQ_F_INITED;
353 }
354
ionic_qcq_intr_free(struct ionic_lif * lif,struct ionic_qcq * qcq)355 static void ionic_qcq_intr_free(struct ionic_lif *lif, struct ionic_qcq *qcq)
356 {
357 if (!(qcq->flags & IONIC_QCQ_F_INTR) || qcq->intr.vector == 0)
358 return;
359
360 irq_set_affinity_hint(qcq->intr.vector, NULL);
361 devm_free_irq(lif->ionic->dev, qcq->intr.vector, &qcq->napi);
362 qcq->intr.vector = 0;
363 ionic_intr_free(lif->ionic, qcq->intr.index);
364 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED;
365 }
366
ionic_qcq_free(struct ionic_lif * lif,struct ionic_qcq * qcq)367 static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq)
368 {
369 struct device *dev = lif->ionic->dev;
370
371 if (!qcq)
372 return;
373
374 ionic_debugfs_del_qcq(qcq);
375
376 if (qcq->q_base) {
377 dma_free_coherent(dev, qcq->q_size, qcq->q_base, qcq->q_base_pa);
378 qcq->q_base = NULL;
379 qcq->q_base_pa = 0;
380 }
381
382 if (qcq->cq_base) {
383 dma_free_coherent(dev, qcq->cq_size, qcq->cq_base, qcq->cq_base_pa);
384 qcq->cq_base = NULL;
385 qcq->cq_base_pa = 0;
386 }
387
388 if (qcq->sg_base) {
389 dma_free_coherent(dev, qcq->sg_size, qcq->sg_base, qcq->sg_base_pa);
390 qcq->sg_base = NULL;
391 qcq->sg_base_pa = 0;
392 }
393
394 ionic_qcq_intr_free(lif, qcq);
395
396 if (qcq->cq.info) {
397 vfree(qcq->cq.info);
398 qcq->cq.info = NULL;
399 }
400 if (qcq->q.info) {
401 vfree(qcq->q.info);
402 qcq->q.info = NULL;
403 }
404 }
405
ionic_qcqs_free(struct ionic_lif * lif)406 static void ionic_qcqs_free(struct ionic_lif *lif)
407 {
408 struct device *dev = lif->ionic->dev;
409 struct ionic_qcq *adminqcq;
410 unsigned long irqflags;
411
412 if (lif->notifyqcq) {
413 ionic_qcq_free(lif, lif->notifyqcq);
414 devm_kfree(dev, lif->notifyqcq);
415 lif->notifyqcq = NULL;
416 }
417
418 if (lif->adminqcq) {
419 spin_lock_irqsave(&lif->adminq_lock, irqflags);
420 adminqcq = READ_ONCE(lif->adminqcq);
421 lif->adminqcq = NULL;
422 spin_unlock_irqrestore(&lif->adminq_lock, irqflags);
423 if (adminqcq) {
424 ionic_qcq_free(lif, adminqcq);
425 devm_kfree(dev, adminqcq);
426 }
427 }
428
429 if (lif->rxqcqs) {
430 devm_kfree(dev, lif->rxqstats);
431 lif->rxqstats = NULL;
432 devm_kfree(dev, lif->rxqcqs);
433 lif->rxqcqs = NULL;
434 }
435
436 if (lif->txqcqs) {
437 devm_kfree(dev, lif->txqstats);
438 lif->txqstats = NULL;
439 devm_kfree(dev, lif->txqcqs);
440 lif->txqcqs = NULL;
441 }
442 }
443
ionic_link_qcq_interrupts(struct ionic_qcq * src_qcq,struct ionic_qcq * n_qcq)444 static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq,
445 struct ionic_qcq *n_qcq)
446 {
447 if (WARN_ON(n_qcq->flags & IONIC_QCQ_F_INTR)) {
448 ionic_intr_free(n_qcq->cq.lif->ionic, n_qcq->intr.index);
449 n_qcq->flags &= ~IONIC_QCQ_F_INTR;
450 }
451
452 n_qcq->intr.vector = src_qcq->intr.vector;
453 n_qcq->intr.index = src_qcq->intr.index;
454 }
455
ionic_alloc_qcq_interrupt(struct ionic_lif * lif,struct ionic_qcq * qcq)456 static int ionic_alloc_qcq_interrupt(struct ionic_lif *lif, struct ionic_qcq *qcq)
457 {
458 int err;
459
460 if (!(qcq->flags & IONIC_QCQ_F_INTR)) {
461 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED;
462 return 0;
463 }
464
465 err = ionic_intr_alloc(lif, &qcq->intr);
466 if (err) {
467 netdev_warn(lif->netdev, "no intr for %s: %d\n",
468 qcq->q.name, err);
469 goto err_out;
470 }
471
472 err = ionic_bus_get_irq(lif->ionic, qcq->intr.index);
473 if (err < 0) {
474 netdev_warn(lif->netdev, "no vector for %s: %d\n",
475 qcq->q.name, err);
476 goto err_out_free_intr;
477 }
478 qcq->intr.vector = err;
479 ionic_intr_mask_assert(lif->ionic->idev.intr_ctrl, qcq->intr.index,
480 IONIC_INTR_MASK_SET);
481
482 err = ionic_request_irq(lif, qcq);
483 if (err) {
484 netdev_warn(lif->netdev, "irq request failed %d\n", err);
485 goto err_out_free_intr;
486 }
487
488 /* try to get the irq on the local numa node first */
489 qcq->intr.cpu = cpumask_local_spread(qcq->intr.index,
490 dev_to_node(lif->ionic->dev));
491 if (qcq->intr.cpu != -1)
492 cpumask_set_cpu(qcq->intr.cpu, &qcq->intr.affinity_mask);
493
494 netdev_dbg(lif->netdev, "%s: Interrupt index %d\n", qcq->q.name, qcq->intr.index);
495 return 0;
496
497 err_out_free_intr:
498 ionic_intr_free(lif->ionic, qcq->intr.index);
499 err_out:
500 return err;
501 }
502
ionic_qcq_alloc(struct ionic_lif * lif,unsigned int type,unsigned int index,const char * name,unsigned int flags,unsigned int num_descs,unsigned int desc_size,unsigned int cq_desc_size,unsigned int sg_desc_size,unsigned int pid,struct ionic_qcq ** qcq)503 static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type,
504 unsigned int index,
505 const char *name, unsigned int flags,
506 unsigned int num_descs, unsigned int desc_size,
507 unsigned int cq_desc_size,
508 unsigned int sg_desc_size,
509 unsigned int pid, struct ionic_qcq **qcq)
510 {
511 struct ionic_dev *idev = &lif->ionic->idev;
512 struct device *dev = lif->ionic->dev;
513 void *q_base, *cq_base, *sg_base;
514 dma_addr_t cq_base_pa = 0;
515 dma_addr_t sg_base_pa = 0;
516 dma_addr_t q_base_pa = 0;
517 struct ionic_qcq *new;
518 int err;
519
520 *qcq = NULL;
521
522 new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL);
523 if (!new) {
524 netdev_err(lif->netdev, "Cannot allocate queue structure\n");
525 err = -ENOMEM;
526 goto err_out;
527 }
528
529 new->q.dev = dev;
530 new->flags = flags;
531
532 new->q.info = vzalloc(num_descs * sizeof(*new->q.info));
533 if (!new->q.info) {
534 netdev_err(lif->netdev, "Cannot allocate queue info\n");
535 err = -ENOMEM;
536 goto err_out_free_qcq;
537 }
538
539 new->q.type = type;
540 new->q.max_sg_elems = lif->qtype_info[type].max_sg_elems;
541
542 err = ionic_q_init(lif, idev, &new->q, index, name, num_descs,
543 desc_size, sg_desc_size, pid);
544 if (err) {
545 netdev_err(lif->netdev, "Cannot initialize queue\n");
546 goto err_out_free_q_info;
547 }
548
549 err = ionic_alloc_qcq_interrupt(lif, new);
550 if (err)
551 goto err_out;
552
553 new->cq.info = vzalloc(num_descs * sizeof(*new->cq.info));
554 if (!new->cq.info) {
555 netdev_err(lif->netdev, "Cannot allocate completion queue info\n");
556 err = -ENOMEM;
557 goto err_out_free_irq;
558 }
559
560 err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size);
561 if (err) {
562 netdev_err(lif->netdev, "Cannot initialize completion queue\n");
563 goto err_out_free_cq_info;
564 }
565
566 if (flags & IONIC_QCQ_F_NOTIFYQ) {
567 int q_size, cq_size;
568
569 /* q & cq need to be contiguous in case of notifyq */
570 q_size = ALIGN(num_descs * desc_size, PAGE_SIZE);
571 cq_size = ALIGN(num_descs * cq_desc_size, PAGE_SIZE);
572
573 new->q_size = PAGE_SIZE + q_size + cq_size;
574 new->q_base = dma_alloc_coherent(dev, new->q_size,
575 &new->q_base_pa, GFP_KERNEL);
576 if (!new->q_base) {
577 netdev_err(lif->netdev, "Cannot allocate qcq DMA memory\n");
578 err = -ENOMEM;
579 goto err_out_free_cq_info;
580 }
581 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE);
582 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE);
583 ionic_q_map(&new->q, q_base, q_base_pa);
584
585 cq_base = PTR_ALIGN(q_base + q_size, PAGE_SIZE);
586 cq_base_pa = ALIGN(new->q_base_pa + q_size, PAGE_SIZE);
587 ionic_cq_map(&new->cq, cq_base, cq_base_pa);
588 ionic_cq_bind(&new->cq, &new->q);
589 } else {
590 new->q_size = PAGE_SIZE + (num_descs * desc_size);
591 new->q_base = dma_alloc_coherent(dev, new->q_size, &new->q_base_pa,
592 GFP_KERNEL);
593 if (!new->q_base) {
594 netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n");
595 err = -ENOMEM;
596 goto err_out_free_cq_info;
597 }
598 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE);
599 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE);
600 ionic_q_map(&new->q, q_base, q_base_pa);
601
602 new->cq_size = PAGE_SIZE + (num_descs * cq_desc_size);
603 new->cq_base = dma_alloc_coherent(dev, new->cq_size, &new->cq_base_pa,
604 GFP_KERNEL);
605 if (!new->cq_base) {
606 netdev_err(lif->netdev, "Cannot allocate cq DMA memory\n");
607 err = -ENOMEM;
608 goto err_out_free_q;
609 }
610 cq_base = PTR_ALIGN(new->cq_base, PAGE_SIZE);
611 cq_base_pa = ALIGN(new->cq_base_pa, PAGE_SIZE);
612 ionic_cq_map(&new->cq, cq_base, cq_base_pa);
613 ionic_cq_bind(&new->cq, &new->q);
614 }
615
616 if (flags & IONIC_QCQ_F_SG) {
617 new->sg_size = PAGE_SIZE + (num_descs * sg_desc_size);
618 new->sg_base = dma_alloc_coherent(dev, new->sg_size, &new->sg_base_pa,
619 GFP_KERNEL);
620 if (!new->sg_base) {
621 netdev_err(lif->netdev, "Cannot allocate sg DMA memory\n");
622 err = -ENOMEM;
623 goto err_out_free_cq;
624 }
625 sg_base = PTR_ALIGN(new->sg_base, PAGE_SIZE);
626 sg_base_pa = ALIGN(new->sg_base_pa, PAGE_SIZE);
627 ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
628 }
629
630 INIT_WORK(&new->dim.work, ionic_dim_work);
631 new->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
632
633 *qcq = new;
634
635 return 0;
636
637 err_out_free_cq:
638 dma_free_coherent(dev, new->cq_size, new->cq_base, new->cq_base_pa);
639 err_out_free_q:
640 dma_free_coherent(dev, new->q_size, new->q_base, new->q_base_pa);
641 err_out_free_cq_info:
642 vfree(new->cq.info);
643 err_out_free_irq:
644 if (flags & IONIC_QCQ_F_INTR) {
645 devm_free_irq(dev, new->intr.vector, &new->napi);
646 ionic_intr_free(lif->ionic, new->intr.index);
647 }
648 err_out_free_q_info:
649 vfree(new->q.info);
650 err_out_free_qcq:
651 devm_kfree(dev, new);
652 err_out:
653 dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err);
654 return err;
655 }
656
ionic_qcqs_alloc(struct ionic_lif * lif)657 static int ionic_qcqs_alloc(struct ionic_lif *lif)
658 {
659 struct device *dev = lif->ionic->dev;
660 unsigned int flags;
661 int err;
662
663 flags = IONIC_QCQ_F_INTR;
664 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags,
665 IONIC_ADMINQ_LENGTH,
666 sizeof(struct ionic_admin_cmd),
667 sizeof(struct ionic_admin_comp),
668 0, lif->kern_pid, &lif->adminqcq);
669 if (err)
670 return err;
671 ionic_debugfs_add_qcq(lif, lif->adminqcq);
672
673 if (lif->ionic->nnqs_per_lif) {
674 flags = IONIC_QCQ_F_NOTIFYQ;
675 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq",
676 flags, IONIC_NOTIFYQ_LENGTH,
677 sizeof(struct ionic_notifyq_cmd),
678 sizeof(union ionic_notifyq_comp),
679 0, lif->kern_pid, &lif->notifyqcq);
680 if (err)
681 goto err_out;
682 ionic_debugfs_add_qcq(lif, lif->notifyqcq);
683
684 /* Let the notifyq ride on the adminq interrupt */
685 ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq);
686 }
687
688 err = -ENOMEM;
689 lif->txqcqs = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif,
690 sizeof(*lif->txqcqs), GFP_KERNEL);
691 if (!lif->txqcqs)
692 goto err_out;
693 lif->rxqcqs = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif,
694 sizeof(*lif->rxqcqs), GFP_KERNEL);
695 if (!lif->rxqcqs)
696 goto err_out;
697
698 lif->txqstats = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif + 1,
699 sizeof(*lif->txqstats), GFP_KERNEL);
700 if (!lif->txqstats)
701 goto err_out;
702 lif->rxqstats = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif + 1,
703 sizeof(*lif->rxqstats), GFP_KERNEL);
704 if (!lif->rxqstats)
705 goto err_out;
706
707 return 0;
708
709 err_out:
710 ionic_qcqs_free(lif);
711 return err;
712 }
713
ionic_qcq_sanitize(struct ionic_qcq * qcq)714 static void ionic_qcq_sanitize(struct ionic_qcq *qcq)
715 {
716 qcq->q.tail_idx = 0;
717 qcq->q.head_idx = 0;
718 qcq->cq.tail_idx = 0;
719 qcq->cq.done_color = 1;
720 memset(qcq->q_base, 0, qcq->q_size);
721 memset(qcq->cq_base, 0, qcq->cq_size);
722 memset(qcq->sg_base, 0, qcq->sg_size);
723 }
724
ionic_lif_txq_init(struct ionic_lif * lif,struct ionic_qcq * qcq)725 static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq)
726 {
727 struct device *dev = lif->ionic->dev;
728 struct ionic_queue *q = &qcq->q;
729 struct ionic_cq *cq = &qcq->cq;
730 struct ionic_admin_ctx ctx = {
731 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
732 .cmd.q_init = {
733 .opcode = IONIC_CMD_Q_INIT,
734 .lif_index = cpu_to_le16(lif->index),
735 .type = q->type,
736 .ver = lif->qtype_info[q->type].version,
737 .index = cpu_to_le32(q->index),
738 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
739 IONIC_QINIT_F_SG),
740 .pid = cpu_to_le16(q->pid),
741 .ring_size = ilog2(q->num_descs),
742 .ring_base = cpu_to_le64(q->base_pa),
743 .cq_ring_base = cpu_to_le64(cq->base_pa),
744 .sg_ring_base = cpu_to_le64(q->sg_base_pa),
745 .features = cpu_to_le64(q->features),
746 },
747 };
748 unsigned int intr_index;
749 int err;
750
751 intr_index = qcq->intr.index;
752
753 ctx.cmd.q_init.intr_index = cpu_to_le16(intr_index);
754
755 dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid);
756 dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index);
757 dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
758 dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
759 dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags);
760 dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver);
761 dev_dbg(dev, "txq_init.intr_index %d\n", ctx.cmd.q_init.intr_index);
762
763 ionic_qcq_sanitize(qcq);
764
765 err = ionic_adminq_post_wait(lif, &ctx);
766 if (err)
767 return err;
768
769 q->hw_type = ctx.comp.q_init.hw_type;
770 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
771 q->dbval = IONIC_DBELL_QID(q->hw_index);
772
773 dev_dbg(dev, "txq->hw_type %d\n", q->hw_type);
774 dev_dbg(dev, "txq->hw_index %d\n", q->hw_index);
775
776 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
777 netif_napi_add(lif->netdev, &qcq->napi, ionic_tx_napi,
778 NAPI_POLL_WEIGHT);
779
780 qcq->flags |= IONIC_QCQ_F_INITED;
781
782 return 0;
783 }
784
ionic_lif_rxq_init(struct ionic_lif * lif,struct ionic_qcq * qcq)785 static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq)
786 {
787 struct device *dev = lif->ionic->dev;
788 struct ionic_queue *q = &qcq->q;
789 struct ionic_cq *cq = &qcq->cq;
790 struct ionic_admin_ctx ctx = {
791 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
792 .cmd.q_init = {
793 .opcode = IONIC_CMD_Q_INIT,
794 .lif_index = cpu_to_le16(lif->index),
795 .type = q->type,
796 .ver = lif->qtype_info[q->type].version,
797 .index = cpu_to_le32(q->index),
798 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
799 IONIC_QINIT_F_SG),
800 .intr_index = cpu_to_le16(cq->bound_intr->index),
801 .pid = cpu_to_le16(q->pid),
802 .ring_size = ilog2(q->num_descs),
803 .ring_base = cpu_to_le64(q->base_pa),
804 .cq_ring_base = cpu_to_le64(cq->base_pa),
805 .sg_ring_base = cpu_to_le64(q->sg_base_pa),
806 .features = cpu_to_le64(q->features),
807 },
808 };
809 int err;
810
811 dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid);
812 dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index);
813 dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
814 dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
815 dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags);
816 dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver);
817 dev_dbg(dev, "rxq_init.intr_index %d\n", ctx.cmd.q_init.intr_index);
818
819 ionic_qcq_sanitize(qcq);
820
821 err = ionic_adminq_post_wait(lif, &ctx);
822 if (err)
823 return err;
824
825 q->hw_type = ctx.comp.q_init.hw_type;
826 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
827 q->dbval = IONIC_DBELL_QID(q->hw_index);
828
829 dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type);
830 dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index);
831
832 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
833 netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi,
834 NAPI_POLL_WEIGHT);
835 else
836 netif_napi_add(lif->netdev, &qcq->napi, ionic_txrx_napi,
837 NAPI_POLL_WEIGHT);
838
839 qcq->flags |= IONIC_QCQ_F_INITED;
840
841 return 0;
842 }
843
ionic_lif_create_hwstamp_txq(struct ionic_lif * lif)844 int ionic_lif_create_hwstamp_txq(struct ionic_lif *lif)
845 {
846 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz;
847 unsigned int txq_i, flags;
848 struct ionic_qcq *txq;
849 u64 features;
850 int err;
851
852 if (lif->hwstamp_txq)
853 return 0;
854
855 features = IONIC_Q_F_2X_CQ_DESC | IONIC_TXQ_F_HWSTAMP;
856
857 num_desc = IONIC_MIN_TXRX_DESC;
858 desc_sz = sizeof(struct ionic_txq_desc);
859 comp_sz = 2 * sizeof(struct ionic_txq_comp);
860
861 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 &&
862 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == sizeof(struct ionic_txq_sg_desc_v1))
863 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1);
864 else
865 sg_desc_sz = sizeof(struct ionic_txq_sg_desc);
866
867 txq_i = lif->ionic->ntxqs_per_lif;
868 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG;
869
870 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, txq_i, "hwstamp_tx", flags,
871 num_desc, desc_sz, comp_sz, sg_desc_sz,
872 lif->kern_pid, &txq);
873 if (err)
874 goto err_qcq_alloc;
875
876 txq->q.features = features;
877
878 ionic_link_qcq_interrupts(lif->adminqcq, txq);
879 ionic_debugfs_add_qcq(lif, txq);
880
881 lif->hwstamp_txq = txq;
882
883 if (netif_running(lif->netdev)) {
884 err = ionic_lif_txq_init(lif, txq);
885 if (err)
886 goto err_qcq_init;
887
888 if (test_bit(IONIC_LIF_F_UP, lif->state)) {
889 err = ionic_qcq_enable(txq);
890 if (err)
891 goto err_qcq_enable;
892 }
893 }
894
895 return 0;
896
897 err_qcq_enable:
898 ionic_lif_qcq_deinit(lif, txq);
899 err_qcq_init:
900 lif->hwstamp_txq = NULL;
901 ionic_debugfs_del_qcq(txq);
902 ionic_qcq_free(lif, txq);
903 devm_kfree(lif->ionic->dev, txq);
904 err_qcq_alloc:
905 return err;
906 }
907
ionic_lif_create_hwstamp_rxq(struct ionic_lif * lif)908 int ionic_lif_create_hwstamp_rxq(struct ionic_lif *lif)
909 {
910 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz;
911 unsigned int rxq_i, flags;
912 struct ionic_qcq *rxq;
913 u64 features;
914 int err;
915
916 if (lif->hwstamp_rxq)
917 return 0;
918
919 features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP;
920
921 num_desc = IONIC_MIN_TXRX_DESC;
922 desc_sz = sizeof(struct ionic_rxq_desc);
923 comp_sz = 2 * sizeof(struct ionic_rxq_comp);
924 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc);
925
926 rxq_i = lif->ionic->nrxqs_per_lif;
927 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG;
928
929 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, rxq_i, "hwstamp_rx", flags,
930 num_desc, desc_sz, comp_sz, sg_desc_sz,
931 lif->kern_pid, &rxq);
932 if (err)
933 goto err_qcq_alloc;
934
935 rxq->q.features = features;
936
937 ionic_link_qcq_interrupts(lif->adminqcq, rxq);
938 ionic_debugfs_add_qcq(lif, rxq);
939
940 lif->hwstamp_rxq = rxq;
941
942 if (netif_running(lif->netdev)) {
943 err = ionic_lif_rxq_init(lif, rxq);
944 if (err)
945 goto err_qcq_init;
946
947 if (test_bit(IONIC_LIF_F_UP, lif->state)) {
948 ionic_rx_fill(&rxq->q);
949 err = ionic_qcq_enable(rxq);
950 if (err)
951 goto err_qcq_enable;
952 }
953 }
954
955 return 0;
956
957 err_qcq_enable:
958 ionic_lif_qcq_deinit(lif, rxq);
959 err_qcq_init:
960 lif->hwstamp_rxq = NULL;
961 ionic_debugfs_del_qcq(rxq);
962 ionic_qcq_free(lif, rxq);
963 devm_kfree(lif->ionic->dev, rxq);
964 err_qcq_alloc:
965 return err;
966 }
967
ionic_lif_config_hwstamp_rxq_all(struct ionic_lif * lif,bool rx_all)968 int ionic_lif_config_hwstamp_rxq_all(struct ionic_lif *lif, bool rx_all)
969 {
970 struct ionic_queue_params qparam;
971
972 ionic_init_queue_params(lif, &qparam);
973
974 if (rx_all)
975 qparam.rxq_features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP;
976 else
977 qparam.rxq_features = 0;
978
979 /* if we're not running, just set the values and return */
980 if (!netif_running(lif->netdev)) {
981 lif->rxq_features = qparam.rxq_features;
982 return 0;
983 }
984
985 return ionic_reconfigure_queues(lif, &qparam);
986 }
987
ionic_lif_set_hwstamp_txmode(struct ionic_lif * lif,u16 txstamp_mode)988 int ionic_lif_set_hwstamp_txmode(struct ionic_lif *lif, u16 txstamp_mode)
989 {
990 struct ionic_admin_ctx ctx = {
991 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
992 .cmd.lif_setattr = {
993 .opcode = IONIC_CMD_LIF_SETATTR,
994 .index = cpu_to_le16(lif->index),
995 .attr = IONIC_LIF_ATTR_TXSTAMP,
996 .txstamp_mode = cpu_to_le16(txstamp_mode),
997 },
998 };
999
1000 return ionic_adminq_post_wait(lif, &ctx);
1001 }
1002
ionic_lif_del_hwstamp_rxfilt(struct ionic_lif * lif)1003 static void ionic_lif_del_hwstamp_rxfilt(struct ionic_lif *lif)
1004 {
1005 struct ionic_admin_ctx ctx = {
1006 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1007 .cmd.rx_filter_del = {
1008 .opcode = IONIC_CMD_RX_FILTER_DEL,
1009 .lif_index = cpu_to_le16(lif->index),
1010 },
1011 };
1012 struct ionic_rx_filter *f;
1013 u32 filter_id;
1014 int err;
1015
1016 spin_lock_bh(&lif->rx_filters.lock);
1017
1018 f = ionic_rx_filter_rxsteer(lif);
1019 if (!f) {
1020 spin_unlock_bh(&lif->rx_filters.lock);
1021 return;
1022 }
1023
1024 filter_id = f->filter_id;
1025 ionic_rx_filter_free(lif, f);
1026
1027 spin_unlock_bh(&lif->rx_filters.lock);
1028
1029 netdev_dbg(lif->netdev, "rx_filter del RXSTEER (id %d)\n", filter_id);
1030
1031 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(filter_id);
1032
1033 err = ionic_adminq_post_wait(lif, &ctx);
1034 if (err && err != -EEXIST)
1035 netdev_dbg(lif->netdev, "failed to delete rx_filter RXSTEER (id %d)\n", filter_id);
1036 }
1037
ionic_lif_add_hwstamp_rxfilt(struct ionic_lif * lif,u64 pkt_class)1038 static int ionic_lif_add_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class)
1039 {
1040 struct ionic_admin_ctx ctx = {
1041 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1042 .cmd.rx_filter_add = {
1043 .opcode = IONIC_CMD_RX_FILTER_ADD,
1044 .lif_index = cpu_to_le16(lif->index),
1045 .match = cpu_to_le16(IONIC_RX_FILTER_STEER_PKTCLASS),
1046 .pkt_class = cpu_to_le64(pkt_class),
1047 },
1048 };
1049 u8 qtype;
1050 u32 qid;
1051 int err;
1052
1053 if (!lif->hwstamp_rxq)
1054 return -EINVAL;
1055
1056 qtype = lif->hwstamp_rxq->q.type;
1057 ctx.cmd.rx_filter_add.qtype = qtype;
1058
1059 qid = lif->hwstamp_rxq->q.index;
1060 ctx.cmd.rx_filter_add.qid = cpu_to_le32(qid);
1061
1062 netdev_dbg(lif->netdev, "rx_filter add RXSTEER\n");
1063 err = ionic_adminq_post_wait(lif, &ctx);
1064 if (err && err != -EEXIST)
1065 return err;
1066
1067 spin_lock_bh(&lif->rx_filters.lock);
1068 err = ionic_rx_filter_save(lif, 0, qid, 0, &ctx, IONIC_FILTER_STATE_SYNCED);
1069 spin_unlock_bh(&lif->rx_filters.lock);
1070
1071 return err;
1072 }
1073
ionic_lif_set_hwstamp_rxfilt(struct ionic_lif * lif,u64 pkt_class)1074 int ionic_lif_set_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class)
1075 {
1076 ionic_lif_del_hwstamp_rxfilt(lif);
1077
1078 if (!pkt_class)
1079 return 0;
1080
1081 return ionic_lif_add_hwstamp_rxfilt(lif, pkt_class);
1082 }
1083
ionic_notifyq_service(struct ionic_cq * cq,struct ionic_cq_info * cq_info)1084 static bool ionic_notifyq_service(struct ionic_cq *cq,
1085 struct ionic_cq_info *cq_info)
1086 {
1087 union ionic_notifyq_comp *comp = cq_info->cq_desc;
1088 struct ionic_deferred_work *work;
1089 struct net_device *netdev;
1090 struct ionic_queue *q;
1091 struct ionic_lif *lif;
1092 u64 eid;
1093
1094 q = cq->bound_q;
1095 lif = q->info[0].cb_arg;
1096 netdev = lif->netdev;
1097 eid = le64_to_cpu(comp->event.eid);
1098
1099 /* Have we run out of new completions to process? */
1100 if ((s64)(eid - lif->last_eid) <= 0)
1101 return false;
1102
1103 lif->last_eid = eid;
1104
1105 dev_dbg(lif->ionic->dev, "notifyq event:\n");
1106 dynamic_hex_dump("event ", DUMP_PREFIX_OFFSET, 16, 1,
1107 comp, sizeof(*comp), true);
1108
1109 switch (le16_to_cpu(comp->event.ecode)) {
1110 case IONIC_EVENT_LINK_CHANGE:
1111 ionic_link_status_check_request(lif, CAN_NOT_SLEEP);
1112 break;
1113 case IONIC_EVENT_RESET:
1114 if (lif->ionic->idev.fw_status_ready &&
1115 !test_bit(IONIC_LIF_F_FW_RESET, lif->state) &&
1116 !test_and_set_bit(IONIC_LIF_F_FW_STOPPING, lif->state)) {
1117 work = kzalloc(sizeof(*work), GFP_ATOMIC);
1118 if (!work) {
1119 netdev_err(lif->netdev, "Reset event dropped\n");
1120 clear_bit(IONIC_LIF_F_FW_STOPPING, lif->state);
1121 } else {
1122 work->type = IONIC_DW_TYPE_LIF_RESET;
1123 ionic_lif_deferred_enqueue(&lif->deferred, work);
1124 }
1125 }
1126 break;
1127 default:
1128 netdev_warn(netdev, "Notifyq event ecode=%d eid=%lld\n",
1129 comp->event.ecode, eid);
1130 break;
1131 }
1132
1133 return true;
1134 }
1135
ionic_adminq_service(struct ionic_cq * cq,struct ionic_cq_info * cq_info)1136 static bool ionic_adminq_service(struct ionic_cq *cq,
1137 struct ionic_cq_info *cq_info)
1138 {
1139 struct ionic_admin_comp *comp = cq_info->cq_desc;
1140
1141 if (!color_match(comp->color, cq->done_color))
1142 return false;
1143
1144 ionic_q_service(cq->bound_q, cq_info, le16_to_cpu(comp->comp_index));
1145
1146 return true;
1147 }
1148
ionic_adminq_napi(struct napi_struct * napi,int budget)1149 static int ionic_adminq_napi(struct napi_struct *napi, int budget)
1150 {
1151 struct ionic_intr_info *intr = napi_to_cq(napi)->bound_intr;
1152 struct ionic_lif *lif = napi_to_cq(napi)->lif;
1153 struct ionic_dev *idev = &lif->ionic->idev;
1154 unsigned long irqflags;
1155 unsigned int flags = 0;
1156 int rx_work = 0;
1157 int tx_work = 0;
1158 int n_work = 0;
1159 int a_work = 0;
1160 int work_done;
1161 int credits;
1162
1163 if (lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED)
1164 n_work = ionic_cq_service(&lif->notifyqcq->cq, budget,
1165 ionic_notifyq_service, NULL, NULL);
1166
1167 spin_lock_irqsave(&lif->adminq_lock, irqflags);
1168 if (lif->adminqcq && lif->adminqcq->flags & IONIC_QCQ_F_INITED)
1169 a_work = ionic_cq_service(&lif->adminqcq->cq, budget,
1170 ionic_adminq_service, NULL, NULL);
1171 spin_unlock_irqrestore(&lif->adminq_lock, irqflags);
1172
1173 if (lif->hwstamp_rxq)
1174 rx_work = ionic_cq_service(&lif->hwstamp_rxq->cq, budget,
1175 ionic_rx_service, NULL, NULL);
1176
1177 if (lif->hwstamp_txq)
1178 tx_work = ionic_cq_service(&lif->hwstamp_txq->cq, budget,
1179 ionic_tx_service, NULL, NULL);
1180
1181 work_done = max(max(n_work, a_work), max(rx_work, tx_work));
1182 if (work_done < budget && napi_complete_done(napi, work_done)) {
1183 flags |= IONIC_INTR_CRED_UNMASK;
1184 intr->rearm_count++;
1185 }
1186
1187 if (work_done || flags) {
1188 flags |= IONIC_INTR_CRED_RESET_COALESCE;
1189 credits = n_work + a_work + rx_work + tx_work;
1190 ionic_intr_credits(idev->intr_ctrl, intr->index, credits, flags);
1191 }
1192
1193 return work_done;
1194 }
1195
ionic_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * ns)1196 void ionic_get_stats64(struct net_device *netdev,
1197 struct rtnl_link_stats64 *ns)
1198 {
1199 struct ionic_lif *lif = netdev_priv(netdev);
1200 struct ionic_lif_stats *ls;
1201
1202 memset(ns, 0, sizeof(*ns));
1203 ls = &lif->info->stats;
1204
1205 ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) +
1206 le64_to_cpu(ls->rx_mcast_packets) +
1207 le64_to_cpu(ls->rx_bcast_packets);
1208
1209 ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) +
1210 le64_to_cpu(ls->tx_mcast_packets) +
1211 le64_to_cpu(ls->tx_bcast_packets);
1212
1213 ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) +
1214 le64_to_cpu(ls->rx_mcast_bytes) +
1215 le64_to_cpu(ls->rx_bcast_bytes);
1216
1217 ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) +
1218 le64_to_cpu(ls->tx_mcast_bytes) +
1219 le64_to_cpu(ls->tx_bcast_bytes);
1220
1221 ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) +
1222 le64_to_cpu(ls->rx_mcast_drop_packets) +
1223 le64_to_cpu(ls->rx_bcast_drop_packets);
1224
1225 ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) +
1226 le64_to_cpu(ls->tx_mcast_drop_packets) +
1227 le64_to_cpu(ls->tx_bcast_drop_packets);
1228
1229 ns->multicast = le64_to_cpu(ls->rx_mcast_packets);
1230
1231 ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty);
1232
1233 ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) +
1234 le64_to_cpu(ls->rx_queue_disabled) +
1235 le64_to_cpu(ls->rx_desc_fetch_error) +
1236 le64_to_cpu(ls->rx_desc_data_error);
1237
1238 ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) +
1239 le64_to_cpu(ls->tx_queue_disabled) +
1240 le64_to_cpu(ls->tx_desc_fetch_error) +
1241 le64_to_cpu(ls->tx_desc_data_error);
1242
1243 ns->rx_errors = ns->rx_over_errors +
1244 ns->rx_missed_errors;
1245
1246 ns->tx_errors = ns->tx_aborted_errors;
1247 }
1248
ionic_addr_add(struct net_device * netdev,const u8 * addr)1249 static int ionic_addr_add(struct net_device *netdev, const u8 *addr)
1250 {
1251 return ionic_lif_list_addr(netdev_priv(netdev), addr, ADD_ADDR);
1252 }
1253
ionic_addr_del(struct net_device * netdev,const u8 * addr)1254 static int ionic_addr_del(struct net_device *netdev, const u8 *addr)
1255 {
1256 /* Don't delete our own address from the uc list */
1257 if (ether_addr_equal(addr, netdev->dev_addr))
1258 return 0;
1259
1260 return ionic_lif_list_addr(netdev_priv(netdev), addr, DEL_ADDR);
1261 }
1262
ionic_lif_rx_mode(struct ionic_lif * lif)1263 void ionic_lif_rx_mode(struct ionic_lif *lif)
1264 {
1265 struct net_device *netdev = lif->netdev;
1266 unsigned int nfilters;
1267 unsigned int nd_flags;
1268 char buf[128];
1269 u16 rx_mode;
1270 int i;
1271 #define REMAIN(__x) (sizeof(buf) - (__x))
1272
1273 mutex_lock(&lif->config_lock);
1274
1275 /* grab the flags once for local use */
1276 nd_flags = netdev->flags;
1277
1278 rx_mode = IONIC_RX_MODE_F_UNICAST;
1279 rx_mode |= (nd_flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0;
1280 rx_mode |= (nd_flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0;
1281 rx_mode |= (nd_flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0;
1282 rx_mode |= (nd_flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0;
1283
1284 /* sync the filters */
1285 ionic_rx_filter_sync(lif);
1286
1287 /* check for overflow state
1288 * if so, we track that we overflowed and enable NIC PROMISC
1289 * else if the overflow is set and not needed
1290 * we remove our overflow flag and check the netdev flags
1291 * to see if we can disable NIC PROMISC
1292 */
1293 nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters);
1294
1295 if (((lif->nucast + lif->nmcast) >= nfilters) ||
1296 (lif->max_vlans && lif->nvlans >= lif->max_vlans)) {
1297 rx_mode |= IONIC_RX_MODE_F_PROMISC;
1298 rx_mode |= IONIC_RX_MODE_F_ALLMULTI;
1299 } else {
1300 if (!(nd_flags & IFF_PROMISC))
1301 rx_mode &= ~IONIC_RX_MODE_F_PROMISC;
1302 if (!(nd_flags & IFF_ALLMULTI))
1303 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI;
1304 }
1305
1306 i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:",
1307 lif->rx_mode, rx_mode);
1308 if (rx_mode & IONIC_RX_MODE_F_UNICAST)
1309 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST");
1310 if (rx_mode & IONIC_RX_MODE_F_MULTICAST)
1311 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST");
1312 if (rx_mode & IONIC_RX_MODE_F_BROADCAST)
1313 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST");
1314 if (rx_mode & IONIC_RX_MODE_F_PROMISC)
1315 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC");
1316 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI)
1317 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI");
1318 if (rx_mode & IONIC_RX_MODE_F_RDMA_SNIFFER)
1319 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_RDMA_SNIFFER");
1320 netdev_dbg(netdev, "lif%d %s\n", lif->index, buf);
1321
1322 if (lif->rx_mode != rx_mode) {
1323 struct ionic_admin_ctx ctx = {
1324 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1325 .cmd.rx_mode_set = {
1326 .opcode = IONIC_CMD_RX_MODE_SET,
1327 .lif_index = cpu_to_le16(lif->index),
1328 },
1329 };
1330 int err;
1331
1332 ctx.cmd.rx_mode_set.rx_mode = cpu_to_le16(rx_mode);
1333 err = ionic_adminq_post_wait(lif, &ctx);
1334 if (err)
1335 netdev_warn(netdev, "set rx_mode 0x%04x failed: %d\n",
1336 rx_mode, err);
1337 else
1338 lif->rx_mode = rx_mode;
1339 }
1340
1341 mutex_unlock(&lif->config_lock);
1342 }
1343
ionic_ndo_set_rx_mode(struct net_device * netdev)1344 static void ionic_ndo_set_rx_mode(struct net_device *netdev)
1345 {
1346 struct ionic_lif *lif = netdev_priv(netdev);
1347 struct ionic_deferred_work *work;
1348
1349 /* Sync the kernel filter list with the driver filter list */
1350 __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del);
1351 __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del);
1352
1353 /* Shove off the rest of the rxmode work to the work task
1354 * which will include syncing the filters to the firmware.
1355 */
1356 work = kzalloc(sizeof(*work), GFP_ATOMIC);
1357 if (!work) {
1358 netdev_err(lif->netdev, "rxmode change dropped\n");
1359 return;
1360 }
1361 work->type = IONIC_DW_TYPE_RX_MODE;
1362 netdev_dbg(lif->netdev, "deferred: rx_mode\n");
1363 ionic_lif_deferred_enqueue(&lif->deferred, work);
1364 }
1365
ionic_netdev_features_to_nic(netdev_features_t features)1366 static __le64 ionic_netdev_features_to_nic(netdev_features_t features)
1367 {
1368 u64 wanted = 0;
1369
1370 if (features & NETIF_F_HW_VLAN_CTAG_TX)
1371 wanted |= IONIC_ETH_HW_VLAN_TX_TAG;
1372 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1373 wanted |= IONIC_ETH_HW_VLAN_RX_STRIP;
1374 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1375 wanted |= IONIC_ETH_HW_VLAN_RX_FILTER;
1376 if (features & NETIF_F_RXHASH)
1377 wanted |= IONIC_ETH_HW_RX_HASH;
1378 if (features & NETIF_F_RXCSUM)
1379 wanted |= IONIC_ETH_HW_RX_CSUM;
1380 if (features & NETIF_F_SG)
1381 wanted |= IONIC_ETH_HW_TX_SG;
1382 if (features & NETIF_F_HW_CSUM)
1383 wanted |= IONIC_ETH_HW_TX_CSUM;
1384 if (features & NETIF_F_TSO)
1385 wanted |= IONIC_ETH_HW_TSO;
1386 if (features & NETIF_F_TSO6)
1387 wanted |= IONIC_ETH_HW_TSO_IPV6;
1388 if (features & NETIF_F_TSO_ECN)
1389 wanted |= IONIC_ETH_HW_TSO_ECN;
1390 if (features & NETIF_F_GSO_GRE)
1391 wanted |= IONIC_ETH_HW_TSO_GRE;
1392 if (features & NETIF_F_GSO_GRE_CSUM)
1393 wanted |= IONIC_ETH_HW_TSO_GRE_CSUM;
1394 if (features & NETIF_F_GSO_IPXIP4)
1395 wanted |= IONIC_ETH_HW_TSO_IPXIP4;
1396 if (features & NETIF_F_GSO_IPXIP6)
1397 wanted |= IONIC_ETH_HW_TSO_IPXIP6;
1398 if (features & NETIF_F_GSO_UDP_TUNNEL)
1399 wanted |= IONIC_ETH_HW_TSO_UDP;
1400 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM)
1401 wanted |= IONIC_ETH_HW_TSO_UDP_CSUM;
1402
1403 return cpu_to_le64(wanted);
1404 }
1405
ionic_set_nic_features(struct ionic_lif * lif,netdev_features_t features)1406 static int ionic_set_nic_features(struct ionic_lif *lif,
1407 netdev_features_t features)
1408 {
1409 struct device *dev = lif->ionic->dev;
1410 struct ionic_admin_ctx ctx = {
1411 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1412 .cmd.lif_setattr = {
1413 .opcode = IONIC_CMD_LIF_SETATTR,
1414 .index = cpu_to_le16(lif->index),
1415 .attr = IONIC_LIF_ATTR_FEATURES,
1416 },
1417 };
1418 u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG |
1419 IONIC_ETH_HW_VLAN_RX_STRIP |
1420 IONIC_ETH_HW_VLAN_RX_FILTER;
1421 u64 old_hw_features;
1422 int err;
1423
1424 ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features);
1425
1426 if (lif->phc)
1427 ctx.cmd.lif_setattr.features |= cpu_to_le64(IONIC_ETH_HW_TIMESTAMP);
1428
1429 err = ionic_adminq_post_wait(lif, &ctx);
1430 if (err)
1431 return err;
1432
1433 old_hw_features = lif->hw_features;
1434 lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features &
1435 ctx.comp.lif_setattr.features);
1436
1437 if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH)
1438 ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL);
1439
1440 if ((vlan_flags & le64_to_cpu(ctx.cmd.lif_setattr.features)) &&
1441 !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features)))
1442 dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n");
1443
1444 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1445 dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n");
1446 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1447 dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n");
1448 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1449 dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n");
1450 if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1451 dev_dbg(dev, "feature ETH_HW_RX_HASH\n");
1452 if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1453 dev_dbg(dev, "feature ETH_HW_TX_SG\n");
1454 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1455 dev_dbg(dev, "feature ETH_HW_TX_CSUM\n");
1456 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1457 dev_dbg(dev, "feature ETH_HW_RX_CSUM\n");
1458 if (lif->hw_features & IONIC_ETH_HW_TSO)
1459 dev_dbg(dev, "feature ETH_HW_TSO\n");
1460 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1461 dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n");
1462 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1463 dev_dbg(dev, "feature ETH_HW_TSO_ECN\n");
1464 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1465 dev_dbg(dev, "feature ETH_HW_TSO_GRE\n");
1466 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1467 dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n");
1468 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1469 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n");
1470 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1471 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n");
1472 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1473 dev_dbg(dev, "feature ETH_HW_TSO_UDP\n");
1474 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1475 dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n");
1476 if (lif->hw_features & IONIC_ETH_HW_TIMESTAMP)
1477 dev_dbg(dev, "feature ETH_HW_TIMESTAMP\n");
1478
1479 return 0;
1480 }
1481
ionic_init_nic_features(struct ionic_lif * lif)1482 static int ionic_init_nic_features(struct ionic_lif *lif)
1483 {
1484 struct net_device *netdev = lif->netdev;
1485 netdev_features_t features;
1486 int err;
1487
1488 /* set up what we expect to support by default */
1489 features = NETIF_F_HW_VLAN_CTAG_TX |
1490 NETIF_F_HW_VLAN_CTAG_RX |
1491 NETIF_F_HW_VLAN_CTAG_FILTER |
1492 NETIF_F_SG |
1493 NETIF_F_HW_CSUM |
1494 NETIF_F_RXCSUM |
1495 NETIF_F_TSO |
1496 NETIF_F_TSO6 |
1497 NETIF_F_TSO_ECN;
1498
1499 if (lif->nxqs > 1)
1500 features |= NETIF_F_RXHASH;
1501
1502 err = ionic_set_nic_features(lif, features);
1503 if (err)
1504 return err;
1505
1506 /* tell the netdev what we actually can support */
1507 netdev->features |= NETIF_F_HIGHDMA;
1508
1509 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1510 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
1511 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1512 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1513 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1514 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1515 if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1516 netdev->hw_features |= NETIF_F_RXHASH;
1517 if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1518 netdev->hw_features |= NETIF_F_SG;
1519
1520 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1521 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
1522 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1523 netdev->hw_enc_features |= NETIF_F_RXCSUM;
1524 if (lif->hw_features & IONIC_ETH_HW_TSO)
1525 netdev->hw_enc_features |= NETIF_F_TSO;
1526 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1527 netdev->hw_enc_features |= NETIF_F_TSO6;
1528 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1529 netdev->hw_enc_features |= NETIF_F_TSO_ECN;
1530 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1531 netdev->hw_enc_features |= NETIF_F_GSO_GRE;
1532 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1533 netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM;
1534 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1535 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4;
1536 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1537 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6;
1538 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1539 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
1540 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1541 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
1542
1543 netdev->hw_features |= netdev->hw_enc_features;
1544 netdev->features |= netdev->hw_features;
1545 netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES;
1546
1547 netdev->priv_flags |= IFF_UNICAST_FLT |
1548 IFF_LIVE_ADDR_CHANGE;
1549
1550 return 0;
1551 }
1552
ionic_set_features(struct net_device * netdev,netdev_features_t features)1553 static int ionic_set_features(struct net_device *netdev,
1554 netdev_features_t features)
1555 {
1556 struct ionic_lif *lif = netdev_priv(netdev);
1557 int err;
1558
1559 netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n",
1560 __func__, (u64)lif->netdev->features, (u64)features);
1561
1562 err = ionic_set_nic_features(lif, features);
1563
1564 return err;
1565 }
1566
ionic_set_attr_mac(struct ionic_lif * lif,u8 * mac)1567 static int ionic_set_attr_mac(struct ionic_lif *lif, u8 *mac)
1568 {
1569 struct ionic_admin_ctx ctx = {
1570 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1571 .cmd.lif_setattr = {
1572 .opcode = IONIC_CMD_LIF_SETATTR,
1573 .index = cpu_to_le16(lif->index),
1574 .attr = IONIC_LIF_ATTR_MAC,
1575 },
1576 };
1577
1578 ether_addr_copy(ctx.cmd.lif_setattr.mac, mac);
1579 return ionic_adminq_post_wait(lif, &ctx);
1580 }
1581
ionic_get_attr_mac(struct ionic_lif * lif,u8 * mac_addr)1582 static int ionic_get_attr_mac(struct ionic_lif *lif, u8 *mac_addr)
1583 {
1584 struct ionic_admin_ctx ctx = {
1585 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1586 .cmd.lif_getattr = {
1587 .opcode = IONIC_CMD_LIF_GETATTR,
1588 .index = cpu_to_le16(lif->index),
1589 .attr = IONIC_LIF_ATTR_MAC,
1590 },
1591 };
1592 int err;
1593
1594 err = ionic_adminq_post_wait(lif, &ctx);
1595 if (err)
1596 return err;
1597
1598 ether_addr_copy(mac_addr, ctx.comp.lif_getattr.mac);
1599 return 0;
1600 }
1601
ionic_program_mac(struct ionic_lif * lif,u8 * mac)1602 static int ionic_program_mac(struct ionic_lif *lif, u8 *mac)
1603 {
1604 u8 get_mac[ETH_ALEN];
1605 int err;
1606
1607 err = ionic_set_attr_mac(lif, mac);
1608 if (err)
1609 return err;
1610
1611 err = ionic_get_attr_mac(lif, get_mac);
1612 if (err)
1613 return err;
1614
1615 /* To deal with older firmware that silently ignores the set attr mac:
1616 * doesn't actually change the mac and doesn't return an error, so we
1617 * do the get attr to verify whether or not the set actually happened
1618 */
1619 if (!ether_addr_equal(get_mac, mac))
1620 return 1;
1621
1622 return 0;
1623 }
1624
ionic_set_mac_address(struct net_device * netdev,void * sa)1625 static int ionic_set_mac_address(struct net_device *netdev, void *sa)
1626 {
1627 struct ionic_lif *lif = netdev_priv(netdev);
1628 struct sockaddr *addr = sa;
1629 u8 *mac;
1630 int err;
1631
1632 mac = (u8 *)addr->sa_data;
1633 if (ether_addr_equal(netdev->dev_addr, mac))
1634 return 0;
1635
1636 err = ionic_program_mac(lif, mac);
1637 if (err < 0)
1638 return err;
1639
1640 if (err > 0)
1641 netdev_dbg(netdev, "%s: SET and GET ATTR Mac are not equal-due to old FW running\n",
1642 __func__);
1643
1644 err = eth_prepare_mac_addr_change(netdev, addr);
1645 if (err)
1646 return err;
1647
1648 if (!is_zero_ether_addr(netdev->dev_addr)) {
1649 netdev_info(netdev, "deleting mac addr %pM\n",
1650 netdev->dev_addr);
1651 ionic_lif_addr_del(netdev_priv(netdev), netdev->dev_addr);
1652 }
1653
1654 eth_commit_mac_addr_change(netdev, addr);
1655 netdev_info(netdev, "updating mac addr %pM\n", mac);
1656
1657 return ionic_lif_addr_add(netdev_priv(netdev), mac);
1658 }
1659
ionic_stop_queues_reconfig(struct ionic_lif * lif)1660 static void ionic_stop_queues_reconfig(struct ionic_lif *lif)
1661 {
1662 /* Stop and clean the queues before reconfiguration */
1663 netif_device_detach(lif->netdev);
1664 ionic_stop_queues(lif);
1665 ionic_txrx_deinit(lif);
1666 }
1667
ionic_start_queues_reconfig(struct ionic_lif * lif)1668 static int ionic_start_queues_reconfig(struct ionic_lif *lif)
1669 {
1670 int err;
1671
1672 /* Re-init the queues after reconfiguration */
1673
1674 /* The only way txrx_init can fail here is if communication
1675 * with FW is suddenly broken. There's not much we can do
1676 * at this point - error messages have already been printed,
1677 * so we can continue on and the user can eventually do a
1678 * DOWN and UP to try to reset and clear the issue.
1679 */
1680 err = ionic_txrx_init(lif);
1681 ionic_link_status_check_request(lif, CAN_NOT_SLEEP);
1682 netif_device_attach(lif->netdev);
1683
1684 return err;
1685 }
1686
ionic_change_mtu(struct net_device * netdev,int new_mtu)1687 static int ionic_change_mtu(struct net_device *netdev, int new_mtu)
1688 {
1689 struct ionic_lif *lif = netdev_priv(netdev);
1690 struct ionic_admin_ctx ctx = {
1691 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1692 .cmd.lif_setattr = {
1693 .opcode = IONIC_CMD_LIF_SETATTR,
1694 .index = cpu_to_le16(lif->index),
1695 .attr = IONIC_LIF_ATTR_MTU,
1696 .mtu = cpu_to_le32(new_mtu),
1697 },
1698 };
1699 int err;
1700
1701 err = ionic_adminq_post_wait(lif, &ctx);
1702 if (err)
1703 return err;
1704
1705 /* if we're not running, nothing more to do */
1706 if (!netif_running(netdev)) {
1707 netdev->mtu = new_mtu;
1708 return 0;
1709 }
1710
1711 mutex_lock(&lif->queue_lock);
1712 ionic_stop_queues_reconfig(lif);
1713 netdev->mtu = new_mtu;
1714 err = ionic_start_queues_reconfig(lif);
1715 mutex_unlock(&lif->queue_lock);
1716
1717 return err;
1718 }
1719
ionic_tx_timeout_work(struct work_struct * ws)1720 static void ionic_tx_timeout_work(struct work_struct *ws)
1721 {
1722 struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work);
1723
1724 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
1725 return;
1726
1727 /* if we were stopped before this scheduled job was launched,
1728 * don't bother the queues as they are already stopped.
1729 */
1730 if (!netif_running(lif->netdev))
1731 return;
1732
1733 mutex_lock(&lif->queue_lock);
1734 ionic_stop_queues_reconfig(lif);
1735 ionic_start_queues_reconfig(lif);
1736 mutex_unlock(&lif->queue_lock);
1737 }
1738
ionic_tx_timeout(struct net_device * netdev,unsigned int txqueue)1739 static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue)
1740 {
1741 struct ionic_lif *lif = netdev_priv(netdev);
1742
1743 netdev_info(lif->netdev, "Tx Timeout triggered - txq %d\n", txqueue);
1744 schedule_work(&lif->tx_timeout_work);
1745 }
1746
ionic_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)1747 static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
1748 u16 vid)
1749 {
1750 struct ionic_lif *lif = netdev_priv(netdev);
1751 int err;
1752
1753 err = ionic_lif_vlan_add(lif, vid);
1754 if (err)
1755 return err;
1756
1757 ionic_lif_rx_mode(lif);
1758
1759 return 0;
1760 }
1761
ionic_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)1762 static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
1763 u16 vid)
1764 {
1765 struct ionic_lif *lif = netdev_priv(netdev);
1766 int err;
1767
1768 err = ionic_lif_vlan_del(lif, vid);
1769 if (err)
1770 return err;
1771
1772 ionic_lif_rx_mode(lif);
1773
1774 return 0;
1775 }
1776
ionic_lif_rss_config(struct ionic_lif * lif,const u16 types,const u8 * key,const u32 * indir)1777 int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types,
1778 const u8 *key, const u32 *indir)
1779 {
1780 struct ionic_admin_ctx ctx = {
1781 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1782 .cmd.lif_setattr = {
1783 .opcode = IONIC_CMD_LIF_SETATTR,
1784 .attr = IONIC_LIF_ATTR_RSS,
1785 .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa),
1786 },
1787 };
1788 unsigned int i, tbl_sz;
1789
1790 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) {
1791 lif->rss_types = types;
1792 ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types);
1793 }
1794
1795 if (key)
1796 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE);
1797
1798 if (indir) {
1799 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
1800 for (i = 0; i < tbl_sz; i++)
1801 lif->rss_ind_tbl[i] = indir[i];
1802 }
1803
1804 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key,
1805 IONIC_RSS_HASH_KEY_SIZE);
1806
1807 return ionic_adminq_post_wait(lif, &ctx);
1808 }
1809
ionic_lif_rss_init(struct ionic_lif * lif)1810 static int ionic_lif_rss_init(struct ionic_lif *lif)
1811 {
1812 unsigned int tbl_sz;
1813 unsigned int i;
1814
1815 lif->rss_types = IONIC_RSS_TYPE_IPV4 |
1816 IONIC_RSS_TYPE_IPV4_TCP |
1817 IONIC_RSS_TYPE_IPV4_UDP |
1818 IONIC_RSS_TYPE_IPV6 |
1819 IONIC_RSS_TYPE_IPV6_TCP |
1820 IONIC_RSS_TYPE_IPV6_UDP;
1821
1822 /* Fill indirection table with 'default' values */
1823 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
1824 for (i = 0; i < tbl_sz; i++)
1825 lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs);
1826
1827 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL);
1828 }
1829
ionic_lif_rss_deinit(struct ionic_lif * lif)1830 static void ionic_lif_rss_deinit(struct ionic_lif *lif)
1831 {
1832 int tbl_sz;
1833
1834 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
1835 memset(lif->rss_ind_tbl, 0, tbl_sz);
1836 memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE);
1837
1838 ionic_lif_rss_config(lif, 0x0, NULL, NULL);
1839 }
1840
ionic_lif_quiesce(struct ionic_lif * lif)1841 static void ionic_lif_quiesce(struct ionic_lif *lif)
1842 {
1843 struct ionic_admin_ctx ctx = {
1844 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1845 .cmd.lif_setattr = {
1846 .opcode = IONIC_CMD_LIF_SETATTR,
1847 .index = cpu_to_le16(lif->index),
1848 .attr = IONIC_LIF_ATTR_STATE,
1849 .state = IONIC_LIF_QUIESCE,
1850 },
1851 };
1852 int err;
1853
1854 err = ionic_adminq_post_wait(lif, &ctx);
1855 if (err)
1856 netdev_dbg(lif->netdev, "lif quiesce failed %d\n", err);
1857 }
1858
ionic_txrx_disable(struct ionic_lif * lif)1859 static void ionic_txrx_disable(struct ionic_lif *lif)
1860 {
1861 unsigned int i;
1862 int err = 0;
1863
1864 if (lif->txqcqs) {
1865 for (i = 0; i < lif->nxqs; i++)
1866 err = ionic_qcq_disable(lif, lif->txqcqs[i], err);
1867 }
1868
1869 if (lif->hwstamp_txq)
1870 err = ionic_qcq_disable(lif, lif->hwstamp_txq, err);
1871
1872 if (lif->rxqcqs) {
1873 for (i = 0; i < lif->nxqs; i++)
1874 err = ionic_qcq_disable(lif, lif->rxqcqs[i], err);
1875 }
1876
1877 if (lif->hwstamp_rxq)
1878 err = ionic_qcq_disable(lif, lif->hwstamp_rxq, err);
1879
1880 ionic_lif_quiesce(lif);
1881 }
1882
ionic_txrx_deinit(struct ionic_lif * lif)1883 static void ionic_txrx_deinit(struct ionic_lif *lif)
1884 {
1885 unsigned int i;
1886
1887 if (lif->txqcqs) {
1888 for (i = 0; i < lif->nxqs && lif->txqcqs[i]; i++) {
1889 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]);
1890 ionic_tx_flush(&lif->txqcqs[i]->cq);
1891 ionic_tx_empty(&lif->txqcqs[i]->q);
1892 }
1893 }
1894
1895 if (lif->rxqcqs) {
1896 for (i = 0; i < lif->nxqs && lif->rxqcqs[i]; i++) {
1897 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]);
1898 ionic_rx_empty(&lif->rxqcqs[i]->q);
1899 }
1900 }
1901 lif->rx_mode = 0;
1902
1903 if (lif->hwstamp_txq) {
1904 ionic_lif_qcq_deinit(lif, lif->hwstamp_txq);
1905 ionic_tx_flush(&lif->hwstamp_txq->cq);
1906 ionic_tx_empty(&lif->hwstamp_txq->q);
1907 }
1908
1909 if (lif->hwstamp_rxq) {
1910 ionic_lif_qcq_deinit(lif, lif->hwstamp_rxq);
1911 ionic_rx_empty(&lif->hwstamp_rxq->q);
1912 }
1913 }
1914
ionic_txrx_free(struct ionic_lif * lif)1915 static void ionic_txrx_free(struct ionic_lif *lif)
1916 {
1917 unsigned int i;
1918
1919 if (lif->txqcqs) {
1920 for (i = 0; i < lif->ionic->ntxqs_per_lif && lif->txqcqs[i]; i++) {
1921 ionic_qcq_free(lif, lif->txqcqs[i]);
1922 devm_kfree(lif->ionic->dev, lif->txqcqs[i]);
1923 lif->txqcqs[i] = NULL;
1924 }
1925 }
1926
1927 if (lif->rxqcqs) {
1928 for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) {
1929 ionic_qcq_free(lif, lif->rxqcqs[i]);
1930 devm_kfree(lif->ionic->dev, lif->rxqcqs[i]);
1931 lif->rxqcqs[i] = NULL;
1932 }
1933 }
1934
1935 if (lif->hwstamp_txq) {
1936 ionic_qcq_free(lif, lif->hwstamp_txq);
1937 devm_kfree(lif->ionic->dev, lif->hwstamp_txq);
1938 lif->hwstamp_txq = NULL;
1939 }
1940
1941 if (lif->hwstamp_rxq) {
1942 ionic_qcq_free(lif, lif->hwstamp_rxq);
1943 devm_kfree(lif->ionic->dev, lif->hwstamp_rxq);
1944 lif->hwstamp_rxq = NULL;
1945 }
1946 }
1947
ionic_txrx_alloc(struct ionic_lif * lif)1948 static int ionic_txrx_alloc(struct ionic_lif *lif)
1949 {
1950 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz;
1951 unsigned int flags, i;
1952 int err = 0;
1953
1954 num_desc = lif->ntxq_descs;
1955 desc_sz = sizeof(struct ionic_txq_desc);
1956 comp_sz = sizeof(struct ionic_txq_comp);
1957
1958 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 &&
1959 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz ==
1960 sizeof(struct ionic_txq_sg_desc_v1))
1961 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1);
1962 else
1963 sg_desc_sz = sizeof(struct ionic_txq_sg_desc);
1964
1965 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG;
1966 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
1967 flags |= IONIC_QCQ_F_INTR;
1968 for (i = 0; i < lif->nxqs; i++) {
1969 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags,
1970 num_desc, desc_sz, comp_sz, sg_desc_sz,
1971 lif->kern_pid, &lif->txqcqs[i]);
1972 if (err)
1973 goto err_out;
1974
1975 if (flags & IONIC_QCQ_F_INTR) {
1976 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
1977 lif->txqcqs[i]->intr.index,
1978 lif->tx_coalesce_hw);
1979 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state))
1980 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw;
1981 }
1982
1983 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]);
1984 }
1985
1986 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG | IONIC_QCQ_F_INTR;
1987
1988 num_desc = lif->nrxq_descs;
1989 desc_sz = sizeof(struct ionic_rxq_desc);
1990 comp_sz = sizeof(struct ionic_rxq_comp);
1991 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc);
1992
1993 if (lif->rxq_features & IONIC_Q_F_2X_CQ_DESC)
1994 comp_sz *= 2;
1995
1996 for (i = 0; i < lif->nxqs; i++) {
1997 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags,
1998 num_desc, desc_sz, comp_sz, sg_desc_sz,
1999 lif->kern_pid, &lif->rxqcqs[i]);
2000 if (err)
2001 goto err_out;
2002
2003 lif->rxqcqs[i]->q.features = lif->rxq_features;
2004
2005 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
2006 lif->rxqcqs[i]->intr.index,
2007 lif->rx_coalesce_hw);
2008 if (test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state))
2009 lif->rxqcqs[i]->intr.dim_coal_hw = lif->rx_coalesce_hw;
2010
2011 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
2012 ionic_link_qcq_interrupts(lif->rxqcqs[i],
2013 lif->txqcqs[i]);
2014
2015 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]);
2016 }
2017
2018 return 0;
2019
2020 err_out:
2021 ionic_txrx_free(lif);
2022
2023 return err;
2024 }
2025
ionic_txrx_init(struct ionic_lif * lif)2026 static int ionic_txrx_init(struct ionic_lif *lif)
2027 {
2028 unsigned int i;
2029 int err;
2030
2031 for (i = 0; i < lif->nxqs; i++) {
2032 err = ionic_lif_txq_init(lif, lif->txqcqs[i]);
2033 if (err)
2034 goto err_out;
2035
2036 err = ionic_lif_rxq_init(lif, lif->rxqcqs[i]);
2037 if (err) {
2038 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]);
2039 goto err_out;
2040 }
2041 }
2042
2043 if (lif->netdev->features & NETIF_F_RXHASH)
2044 ionic_lif_rss_init(lif);
2045
2046 ionic_lif_rx_mode(lif);
2047
2048 return 0;
2049
2050 err_out:
2051 while (i--) {
2052 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]);
2053 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]);
2054 }
2055
2056 return err;
2057 }
2058
ionic_txrx_enable(struct ionic_lif * lif)2059 static int ionic_txrx_enable(struct ionic_lif *lif)
2060 {
2061 int derr = 0;
2062 int i, err;
2063
2064 for (i = 0; i < lif->nxqs; i++) {
2065 if (!(lif->rxqcqs[i] && lif->txqcqs[i])) {
2066 dev_err(lif->ionic->dev, "%s: bad qcq %d\n", __func__, i);
2067 err = -ENXIO;
2068 goto err_out;
2069 }
2070
2071 ionic_rx_fill(&lif->rxqcqs[i]->q);
2072 err = ionic_qcq_enable(lif->rxqcqs[i]);
2073 if (err)
2074 goto err_out;
2075
2076 err = ionic_qcq_enable(lif->txqcqs[i]);
2077 if (err) {
2078 derr = ionic_qcq_disable(lif, lif->rxqcqs[i], err);
2079 goto err_out;
2080 }
2081 }
2082
2083 if (lif->hwstamp_rxq) {
2084 ionic_rx_fill(&lif->hwstamp_rxq->q);
2085 err = ionic_qcq_enable(lif->hwstamp_rxq);
2086 if (err)
2087 goto err_out_hwstamp_rx;
2088 }
2089
2090 if (lif->hwstamp_txq) {
2091 err = ionic_qcq_enable(lif->hwstamp_txq);
2092 if (err)
2093 goto err_out_hwstamp_tx;
2094 }
2095
2096 return 0;
2097
2098 err_out_hwstamp_tx:
2099 if (lif->hwstamp_rxq)
2100 derr = ionic_qcq_disable(lif, lif->hwstamp_rxq, derr);
2101 err_out_hwstamp_rx:
2102 i = lif->nxqs;
2103 err_out:
2104 while (i--) {
2105 derr = ionic_qcq_disable(lif, lif->txqcqs[i], derr);
2106 derr = ionic_qcq_disable(lif, lif->rxqcqs[i], derr);
2107 }
2108
2109 return err;
2110 }
2111
ionic_start_queues(struct ionic_lif * lif)2112 static int ionic_start_queues(struct ionic_lif *lif)
2113 {
2114 int err;
2115
2116 if (test_bit(IONIC_LIF_F_BROKEN, lif->state))
2117 return -EIO;
2118
2119 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
2120 return -EBUSY;
2121
2122 if (test_and_set_bit(IONIC_LIF_F_UP, lif->state))
2123 return 0;
2124
2125 err = ionic_txrx_enable(lif);
2126 if (err) {
2127 clear_bit(IONIC_LIF_F_UP, lif->state);
2128 return err;
2129 }
2130 netif_tx_wake_all_queues(lif->netdev);
2131
2132 return 0;
2133 }
2134
ionic_open(struct net_device * netdev)2135 static int ionic_open(struct net_device *netdev)
2136 {
2137 struct ionic_lif *lif = netdev_priv(netdev);
2138 int err;
2139
2140 /* If recovering from a broken state, clear the bit and we'll try again */
2141 if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state))
2142 netdev_info(netdev, "clearing broken state\n");
2143
2144 mutex_lock(&lif->queue_lock);
2145
2146 err = ionic_txrx_alloc(lif);
2147 if (err)
2148 goto err_unlock;
2149
2150 err = ionic_txrx_init(lif);
2151 if (err)
2152 goto err_txrx_free;
2153
2154 err = netif_set_real_num_tx_queues(netdev, lif->nxqs);
2155 if (err)
2156 goto err_txrx_deinit;
2157
2158 err = netif_set_real_num_rx_queues(netdev, lif->nxqs);
2159 if (err)
2160 goto err_txrx_deinit;
2161
2162 /* don't start the queues until we have link */
2163 if (netif_carrier_ok(netdev)) {
2164 err = ionic_start_queues(lif);
2165 if (err)
2166 goto err_txrx_deinit;
2167 }
2168
2169 /* If hardware timestamping is enabled, but the queues were freed by
2170 * ionic_stop, those need to be reallocated and initialized, too.
2171 */
2172 ionic_lif_hwstamp_recreate_queues(lif);
2173
2174 mutex_unlock(&lif->queue_lock);
2175
2176 return 0;
2177
2178 err_txrx_deinit:
2179 ionic_txrx_deinit(lif);
2180 err_txrx_free:
2181 ionic_txrx_free(lif);
2182 err_unlock:
2183 mutex_unlock(&lif->queue_lock);
2184 return err;
2185 }
2186
ionic_stop_queues(struct ionic_lif * lif)2187 static void ionic_stop_queues(struct ionic_lif *lif)
2188 {
2189 if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state))
2190 return;
2191
2192 netif_tx_disable(lif->netdev);
2193 ionic_txrx_disable(lif);
2194 }
2195
ionic_stop(struct net_device * netdev)2196 static int ionic_stop(struct net_device *netdev)
2197 {
2198 struct ionic_lif *lif = netdev_priv(netdev);
2199
2200 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
2201 return 0;
2202
2203 mutex_lock(&lif->queue_lock);
2204 ionic_stop_queues(lif);
2205 ionic_txrx_deinit(lif);
2206 ionic_txrx_free(lif);
2207 mutex_unlock(&lif->queue_lock);
2208
2209 return 0;
2210 }
2211
ionic_eth_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)2212 static int ionic_eth_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2213 {
2214 struct ionic_lif *lif = netdev_priv(netdev);
2215
2216 switch (cmd) {
2217 case SIOCSHWTSTAMP:
2218 return ionic_lif_hwstamp_set(lif, ifr);
2219 case SIOCGHWTSTAMP:
2220 return ionic_lif_hwstamp_get(lif, ifr);
2221 default:
2222 return -EOPNOTSUPP;
2223 }
2224 }
2225
ionic_update_cached_vf_config(struct ionic * ionic,int vf)2226 static int ionic_update_cached_vf_config(struct ionic *ionic, int vf)
2227 {
2228 struct ionic_vf_getattr_comp comp = { 0 };
2229 int err;
2230 u8 attr;
2231
2232 attr = IONIC_VF_ATTR_VLAN;
2233 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp);
2234 if (err && comp.status != IONIC_RC_ENOSUPP)
2235 goto err_out;
2236 if (!err)
2237 ionic->vfs[vf].vlanid = comp.vlanid;
2238
2239 attr = IONIC_VF_ATTR_SPOOFCHK;
2240 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp);
2241 if (err && comp.status != IONIC_RC_ENOSUPP)
2242 goto err_out;
2243 if (!err)
2244 ionic->vfs[vf].spoofchk = comp.spoofchk;
2245
2246 attr = IONIC_VF_ATTR_LINKSTATE;
2247 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp);
2248 if (err && comp.status != IONIC_RC_ENOSUPP)
2249 goto err_out;
2250 if (!err) {
2251 switch (comp.linkstate) {
2252 case IONIC_VF_LINK_STATUS_UP:
2253 ionic->vfs[vf].linkstate = IFLA_VF_LINK_STATE_ENABLE;
2254 break;
2255 case IONIC_VF_LINK_STATUS_DOWN:
2256 ionic->vfs[vf].linkstate = IFLA_VF_LINK_STATE_DISABLE;
2257 break;
2258 case IONIC_VF_LINK_STATUS_AUTO:
2259 ionic->vfs[vf].linkstate = IFLA_VF_LINK_STATE_AUTO;
2260 break;
2261 default:
2262 dev_warn(ionic->dev, "Unexpected link state %u\n", comp.linkstate);
2263 break;
2264 }
2265 }
2266
2267 attr = IONIC_VF_ATTR_RATE;
2268 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp);
2269 if (err && comp.status != IONIC_RC_ENOSUPP)
2270 goto err_out;
2271 if (!err)
2272 ionic->vfs[vf].maxrate = comp.maxrate;
2273
2274 attr = IONIC_VF_ATTR_TRUST;
2275 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp);
2276 if (err && comp.status != IONIC_RC_ENOSUPP)
2277 goto err_out;
2278 if (!err)
2279 ionic->vfs[vf].trusted = comp.trust;
2280
2281 attr = IONIC_VF_ATTR_MAC;
2282 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp);
2283 if (err && comp.status != IONIC_RC_ENOSUPP)
2284 goto err_out;
2285 if (!err)
2286 ether_addr_copy(ionic->vfs[vf].macaddr, comp.macaddr);
2287
2288 err_out:
2289 if (err)
2290 dev_err(ionic->dev, "Failed to get %s for VF %d\n",
2291 ionic_vf_attr_to_str(attr), vf);
2292
2293 return err;
2294 }
2295
ionic_get_vf_config(struct net_device * netdev,int vf,struct ifla_vf_info * ivf)2296 static int ionic_get_vf_config(struct net_device *netdev,
2297 int vf, struct ifla_vf_info *ivf)
2298 {
2299 struct ionic_lif *lif = netdev_priv(netdev);
2300 struct ionic *ionic = lif->ionic;
2301 int ret = 0;
2302
2303 if (!netif_device_present(netdev))
2304 return -EBUSY;
2305
2306 down_read(&ionic->vf_op_lock);
2307
2308 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2309 ret = -EINVAL;
2310 } else {
2311 ivf->vf = vf;
2312 ivf->qos = 0;
2313
2314 ret = ionic_update_cached_vf_config(ionic, vf);
2315 if (!ret) {
2316 ivf->vlan = le16_to_cpu(ionic->vfs[vf].vlanid);
2317 ivf->spoofchk = ionic->vfs[vf].spoofchk;
2318 ivf->linkstate = ionic->vfs[vf].linkstate;
2319 ivf->max_tx_rate = le32_to_cpu(ionic->vfs[vf].maxrate);
2320 ivf->trusted = ionic->vfs[vf].trusted;
2321 ether_addr_copy(ivf->mac, ionic->vfs[vf].macaddr);
2322 }
2323 }
2324
2325 up_read(&ionic->vf_op_lock);
2326 return ret;
2327 }
2328
ionic_get_vf_stats(struct net_device * netdev,int vf,struct ifla_vf_stats * vf_stats)2329 static int ionic_get_vf_stats(struct net_device *netdev, int vf,
2330 struct ifla_vf_stats *vf_stats)
2331 {
2332 struct ionic_lif *lif = netdev_priv(netdev);
2333 struct ionic *ionic = lif->ionic;
2334 struct ionic_lif_stats *vs;
2335 int ret = 0;
2336
2337 if (!netif_device_present(netdev))
2338 return -EBUSY;
2339
2340 down_read(&ionic->vf_op_lock);
2341
2342 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2343 ret = -EINVAL;
2344 } else {
2345 memset(vf_stats, 0, sizeof(*vf_stats));
2346 vs = &ionic->vfs[vf].stats;
2347
2348 vf_stats->rx_packets = le64_to_cpu(vs->rx_ucast_packets);
2349 vf_stats->tx_packets = le64_to_cpu(vs->tx_ucast_packets);
2350 vf_stats->rx_bytes = le64_to_cpu(vs->rx_ucast_bytes);
2351 vf_stats->tx_bytes = le64_to_cpu(vs->tx_ucast_bytes);
2352 vf_stats->broadcast = le64_to_cpu(vs->rx_bcast_packets);
2353 vf_stats->multicast = le64_to_cpu(vs->rx_mcast_packets);
2354 vf_stats->rx_dropped = le64_to_cpu(vs->rx_ucast_drop_packets) +
2355 le64_to_cpu(vs->rx_mcast_drop_packets) +
2356 le64_to_cpu(vs->rx_bcast_drop_packets);
2357 vf_stats->tx_dropped = le64_to_cpu(vs->tx_ucast_drop_packets) +
2358 le64_to_cpu(vs->tx_mcast_drop_packets) +
2359 le64_to_cpu(vs->tx_bcast_drop_packets);
2360 }
2361
2362 up_read(&ionic->vf_op_lock);
2363 return ret;
2364 }
2365
ionic_set_vf_mac(struct net_device * netdev,int vf,u8 * mac)2366 static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
2367 {
2368 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_MAC };
2369 struct ionic_lif *lif = netdev_priv(netdev);
2370 struct ionic *ionic = lif->ionic;
2371 int ret;
2372
2373 if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac)))
2374 return -EINVAL;
2375
2376 if (!netif_device_present(netdev))
2377 return -EBUSY;
2378
2379 down_write(&ionic->vf_op_lock);
2380
2381 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2382 ret = -EINVAL;
2383 } else {
2384 ether_addr_copy(vfc.macaddr, mac);
2385 dev_dbg(ionic->dev, "%s: vf %d macaddr %pM\n",
2386 __func__, vf, vfc.macaddr);
2387
2388 ret = ionic_set_vf_config(ionic, vf, &vfc);
2389 if (!ret)
2390 ether_addr_copy(ionic->vfs[vf].macaddr, mac);
2391 }
2392
2393 up_write(&ionic->vf_op_lock);
2394 return ret;
2395 }
2396
ionic_set_vf_vlan(struct net_device * netdev,int vf,u16 vlan,u8 qos,__be16 proto)2397 static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
2398 u8 qos, __be16 proto)
2399 {
2400 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_VLAN };
2401 struct ionic_lif *lif = netdev_priv(netdev);
2402 struct ionic *ionic = lif->ionic;
2403 int ret;
2404
2405 /* until someday when we support qos */
2406 if (qos)
2407 return -EINVAL;
2408
2409 if (vlan > 4095)
2410 return -EINVAL;
2411
2412 if (proto != htons(ETH_P_8021Q))
2413 return -EPROTONOSUPPORT;
2414
2415 if (!netif_device_present(netdev))
2416 return -EBUSY;
2417
2418 down_write(&ionic->vf_op_lock);
2419
2420 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2421 ret = -EINVAL;
2422 } else {
2423 vfc.vlanid = cpu_to_le16(vlan);
2424 dev_dbg(ionic->dev, "%s: vf %d vlan %d\n",
2425 __func__, vf, le16_to_cpu(vfc.vlanid));
2426
2427 ret = ionic_set_vf_config(ionic, vf, &vfc);
2428 if (!ret)
2429 ionic->vfs[vf].vlanid = cpu_to_le16(vlan);
2430 }
2431
2432 up_write(&ionic->vf_op_lock);
2433 return ret;
2434 }
2435
ionic_set_vf_rate(struct net_device * netdev,int vf,int tx_min,int tx_max)2436 static int ionic_set_vf_rate(struct net_device *netdev, int vf,
2437 int tx_min, int tx_max)
2438 {
2439 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_RATE };
2440 struct ionic_lif *lif = netdev_priv(netdev);
2441 struct ionic *ionic = lif->ionic;
2442 int ret;
2443
2444 /* setting the min just seems silly */
2445 if (tx_min)
2446 return -EINVAL;
2447
2448 if (!netif_device_present(netdev))
2449 return -EBUSY;
2450
2451 down_write(&ionic->vf_op_lock);
2452
2453 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2454 ret = -EINVAL;
2455 } else {
2456 vfc.maxrate = cpu_to_le32(tx_max);
2457 dev_dbg(ionic->dev, "%s: vf %d maxrate %d\n",
2458 __func__, vf, le32_to_cpu(vfc.maxrate));
2459
2460 ret = ionic_set_vf_config(ionic, vf, &vfc);
2461 if (!ret)
2462 lif->ionic->vfs[vf].maxrate = cpu_to_le32(tx_max);
2463 }
2464
2465 up_write(&ionic->vf_op_lock);
2466 return ret;
2467 }
2468
ionic_set_vf_spoofchk(struct net_device * netdev,int vf,bool set)2469 static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set)
2470 {
2471 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_SPOOFCHK };
2472 struct ionic_lif *lif = netdev_priv(netdev);
2473 struct ionic *ionic = lif->ionic;
2474 int ret;
2475
2476 if (!netif_device_present(netdev))
2477 return -EBUSY;
2478
2479 down_write(&ionic->vf_op_lock);
2480
2481 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2482 ret = -EINVAL;
2483 } else {
2484 vfc.spoofchk = set;
2485 dev_dbg(ionic->dev, "%s: vf %d spoof %d\n",
2486 __func__, vf, vfc.spoofchk);
2487
2488 ret = ionic_set_vf_config(ionic, vf, &vfc);
2489 if (!ret)
2490 ionic->vfs[vf].spoofchk = set;
2491 }
2492
2493 up_write(&ionic->vf_op_lock);
2494 return ret;
2495 }
2496
ionic_set_vf_trust(struct net_device * netdev,int vf,bool set)2497 static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set)
2498 {
2499 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_TRUST };
2500 struct ionic_lif *lif = netdev_priv(netdev);
2501 struct ionic *ionic = lif->ionic;
2502 int ret;
2503
2504 if (!netif_device_present(netdev))
2505 return -EBUSY;
2506
2507 down_write(&ionic->vf_op_lock);
2508
2509 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2510 ret = -EINVAL;
2511 } else {
2512 vfc.trust = set;
2513 dev_dbg(ionic->dev, "%s: vf %d trust %d\n",
2514 __func__, vf, vfc.trust);
2515
2516 ret = ionic_set_vf_config(ionic, vf, &vfc);
2517 if (!ret)
2518 ionic->vfs[vf].trusted = set;
2519 }
2520
2521 up_write(&ionic->vf_op_lock);
2522 return ret;
2523 }
2524
ionic_set_vf_link_state(struct net_device * netdev,int vf,int set)2525 static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set)
2526 {
2527 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_LINKSTATE };
2528 struct ionic_lif *lif = netdev_priv(netdev);
2529 struct ionic *ionic = lif->ionic;
2530 u8 vfls;
2531 int ret;
2532
2533 switch (set) {
2534 case IFLA_VF_LINK_STATE_ENABLE:
2535 vfls = IONIC_VF_LINK_STATUS_UP;
2536 break;
2537 case IFLA_VF_LINK_STATE_DISABLE:
2538 vfls = IONIC_VF_LINK_STATUS_DOWN;
2539 break;
2540 case IFLA_VF_LINK_STATE_AUTO:
2541 vfls = IONIC_VF_LINK_STATUS_AUTO;
2542 break;
2543 default:
2544 return -EINVAL;
2545 }
2546
2547 if (!netif_device_present(netdev))
2548 return -EBUSY;
2549
2550 down_write(&ionic->vf_op_lock);
2551
2552 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2553 ret = -EINVAL;
2554 } else {
2555 vfc.linkstate = vfls;
2556 dev_dbg(ionic->dev, "%s: vf %d linkstate %d\n",
2557 __func__, vf, vfc.linkstate);
2558
2559 ret = ionic_set_vf_config(ionic, vf, &vfc);
2560 if (!ret)
2561 ionic->vfs[vf].linkstate = set;
2562 }
2563
2564 up_write(&ionic->vf_op_lock);
2565 return ret;
2566 }
2567
2568 static const struct net_device_ops ionic_netdev_ops = {
2569 .ndo_open = ionic_open,
2570 .ndo_stop = ionic_stop,
2571 .ndo_eth_ioctl = ionic_eth_ioctl,
2572 .ndo_start_xmit = ionic_start_xmit,
2573 .ndo_get_stats64 = ionic_get_stats64,
2574 .ndo_set_rx_mode = ionic_ndo_set_rx_mode,
2575 .ndo_set_features = ionic_set_features,
2576 .ndo_set_mac_address = ionic_set_mac_address,
2577 .ndo_validate_addr = eth_validate_addr,
2578 .ndo_tx_timeout = ionic_tx_timeout,
2579 .ndo_change_mtu = ionic_change_mtu,
2580 .ndo_vlan_rx_add_vid = ionic_vlan_rx_add_vid,
2581 .ndo_vlan_rx_kill_vid = ionic_vlan_rx_kill_vid,
2582 .ndo_set_vf_vlan = ionic_set_vf_vlan,
2583 .ndo_set_vf_trust = ionic_set_vf_trust,
2584 .ndo_set_vf_mac = ionic_set_vf_mac,
2585 .ndo_set_vf_rate = ionic_set_vf_rate,
2586 .ndo_set_vf_spoofchk = ionic_set_vf_spoofchk,
2587 .ndo_get_vf_config = ionic_get_vf_config,
2588 .ndo_set_vf_link_state = ionic_set_vf_link_state,
2589 .ndo_get_vf_stats = ionic_get_vf_stats,
2590 };
2591
ionic_swap_queues(struct ionic_qcq * a,struct ionic_qcq * b)2592 static void ionic_swap_queues(struct ionic_qcq *a, struct ionic_qcq *b)
2593 {
2594 /* only swapping the queues, not the napi, flags, or other stuff */
2595 swap(a->q.features, b->q.features);
2596 swap(a->q.num_descs, b->q.num_descs);
2597 swap(a->q.desc_size, b->q.desc_size);
2598 swap(a->q.base, b->q.base);
2599 swap(a->q.base_pa, b->q.base_pa);
2600 swap(a->q.info, b->q.info);
2601 swap(a->q_base, b->q_base);
2602 swap(a->q_base_pa, b->q_base_pa);
2603 swap(a->q_size, b->q_size);
2604
2605 swap(a->q.sg_desc_size, b->q.sg_desc_size);
2606 swap(a->q.sg_base, b->q.sg_base);
2607 swap(a->q.sg_base_pa, b->q.sg_base_pa);
2608 swap(a->sg_base, b->sg_base);
2609 swap(a->sg_base_pa, b->sg_base_pa);
2610 swap(a->sg_size, b->sg_size);
2611
2612 swap(a->cq.num_descs, b->cq.num_descs);
2613 swap(a->cq.desc_size, b->cq.desc_size);
2614 swap(a->cq.base, b->cq.base);
2615 swap(a->cq.base_pa, b->cq.base_pa);
2616 swap(a->cq.info, b->cq.info);
2617 swap(a->cq_base, b->cq_base);
2618 swap(a->cq_base_pa, b->cq_base_pa);
2619 swap(a->cq_size, b->cq_size);
2620
2621 ionic_debugfs_del_qcq(a);
2622 ionic_debugfs_add_qcq(a->q.lif, a);
2623 }
2624
ionic_reconfigure_queues(struct ionic_lif * lif,struct ionic_queue_params * qparam)2625 int ionic_reconfigure_queues(struct ionic_lif *lif,
2626 struct ionic_queue_params *qparam)
2627 {
2628 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz;
2629 struct ionic_qcq **tx_qcqs = NULL;
2630 struct ionic_qcq **rx_qcqs = NULL;
2631 unsigned int flags, i;
2632 int err = 0;
2633
2634 /* allocate temporary qcq arrays to hold new queue structs */
2635 if (qparam->nxqs != lif->nxqs || qparam->ntxq_descs != lif->ntxq_descs) {
2636 tx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->ntxqs_per_lif,
2637 sizeof(struct ionic_qcq *), GFP_KERNEL);
2638 if (!tx_qcqs) {
2639 err = -ENOMEM;
2640 goto err_out;
2641 }
2642 }
2643 if (qparam->nxqs != lif->nxqs ||
2644 qparam->nrxq_descs != lif->nrxq_descs ||
2645 qparam->rxq_features != lif->rxq_features) {
2646 rx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->nrxqs_per_lif,
2647 sizeof(struct ionic_qcq *), GFP_KERNEL);
2648 if (!rx_qcqs) {
2649 err = -ENOMEM;
2650 goto err_out;
2651 }
2652 }
2653
2654 /* allocate new desc_info and rings, but leave the interrupt setup
2655 * until later so as to not mess with the still-running queues
2656 */
2657 if (tx_qcqs) {
2658 num_desc = qparam->ntxq_descs;
2659 desc_sz = sizeof(struct ionic_txq_desc);
2660 comp_sz = sizeof(struct ionic_txq_comp);
2661
2662 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 &&
2663 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz ==
2664 sizeof(struct ionic_txq_sg_desc_v1))
2665 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1);
2666 else
2667 sg_desc_sz = sizeof(struct ionic_txq_sg_desc);
2668
2669 for (i = 0; i < qparam->nxqs; i++) {
2670 flags = lif->txqcqs[i]->flags & ~IONIC_QCQ_F_INTR;
2671 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags,
2672 num_desc, desc_sz, comp_sz, sg_desc_sz,
2673 lif->kern_pid, &tx_qcqs[i]);
2674 if (err)
2675 goto err_out;
2676 }
2677 }
2678
2679 if (rx_qcqs) {
2680 num_desc = qparam->nrxq_descs;
2681 desc_sz = sizeof(struct ionic_rxq_desc);
2682 comp_sz = sizeof(struct ionic_rxq_comp);
2683 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc);
2684
2685 if (qparam->rxq_features & IONIC_Q_F_2X_CQ_DESC)
2686 comp_sz *= 2;
2687
2688 for (i = 0; i < qparam->nxqs; i++) {
2689 flags = lif->rxqcqs[i]->flags & ~IONIC_QCQ_F_INTR;
2690 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags,
2691 num_desc, desc_sz, comp_sz, sg_desc_sz,
2692 lif->kern_pid, &rx_qcqs[i]);
2693 if (err)
2694 goto err_out;
2695
2696 rx_qcqs[i]->q.features = qparam->rxq_features;
2697 }
2698 }
2699
2700 /* stop and clean the queues */
2701 ionic_stop_queues_reconfig(lif);
2702
2703 if (qparam->nxqs != lif->nxqs) {
2704 err = netif_set_real_num_tx_queues(lif->netdev, qparam->nxqs);
2705 if (err)
2706 goto err_out_reinit_unlock;
2707 err = netif_set_real_num_rx_queues(lif->netdev, qparam->nxqs);
2708 if (err) {
2709 netif_set_real_num_tx_queues(lif->netdev, lif->nxqs);
2710 goto err_out_reinit_unlock;
2711 }
2712 }
2713
2714 /* swap new desc_info and rings, keeping existing interrupt config */
2715 if (tx_qcqs) {
2716 lif->ntxq_descs = qparam->ntxq_descs;
2717 for (i = 0; i < qparam->nxqs; i++)
2718 ionic_swap_queues(lif->txqcqs[i], tx_qcqs[i]);
2719 }
2720
2721 if (rx_qcqs) {
2722 lif->nrxq_descs = qparam->nrxq_descs;
2723 for (i = 0; i < qparam->nxqs; i++)
2724 ionic_swap_queues(lif->rxqcqs[i], rx_qcqs[i]);
2725 }
2726
2727 /* if we need to change the interrupt layout, this is the time */
2728 if (qparam->intr_split != test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) ||
2729 qparam->nxqs != lif->nxqs) {
2730 if (qparam->intr_split) {
2731 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state);
2732 } else {
2733 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state);
2734 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs;
2735 lif->tx_coalesce_hw = lif->rx_coalesce_hw;
2736 }
2737
2738 /* clear existing interrupt assignments */
2739 for (i = 0; i < lif->ionic->ntxqs_per_lif; i++) {
2740 ionic_qcq_intr_free(lif, lif->txqcqs[i]);
2741 ionic_qcq_intr_free(lif, lif->rxqcqs[i]);
2742 }
2743
2744 /* re-assign the interrupts */
2745 for (i = 0; i < qparam->nxqs; i++) {
2746 lif->rxqcqs[i]->flags |= IONIC_QCQ_F_INTR;
2747 err = ionic_alloc_qcq_interrupt(lif, lif->rxqcqs[i]);
2748 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
2749 lif->rxqcqs[i]->intr.index,
2750 lif->rx_coalesce_hw);
2751
2752 if (qparam->intr_split) {
2753 lif->txqcqs[i]->flags |= IONIC_QCQ_F_INTR;
2754 err = ionic_alloc_qcq_interrupt(lif, lif->txqcqs[i]);
2755 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
2756 lif->txqcqs[i]->intr.index,
2757 lif->tx_coalesce_hw);
2758 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state))
2759 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw;
2760 } else {
2761 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
2762 ionic_link_qcq_interrupts(lif->rxqcqs[i], lif->txqcqs[i]);
2763 }
2764 }
2765 }
2766
2767 /* now we can rework the debugfs mappings */
2768 if (tx_qcqs) {
2769 for (i = 0; i < qparam->nxqs; i++) {
2770 ionic_debugfs_del_qcq(lif->txqcqs[i]);
2771 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]);
2772 }
2773 }
2774
2775 if (rx_qcqs) {
2776 for (i = 0; i < qparam->nxqs; i++) {
2777 ionic_debugfs_del_qcq(lif->rxqcqs[i]);
2778 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]);
2779 }
2780 }
2781
2782 swap(lif->nxqs, qparam->nxqs);
2783 swap(lif->rxq_features, qparam->rxq_features);
2784
2785 err_out_reinit_unlock:
2786 /* re-init the queues, but don't lose an error code */
2787 if (err)
2788 ionic_start_queues_reconfig(lif);
2789 else
2790 err = ionic_start_queues_reconfig(lif);
2791
2792 err_out:
2793 /* free old allocs without cleaning intr */
2794 for (i = 0; i < qparam->nxqs; i++) {
2795 if (tx_qcqs && tx_qcqs[i]) {
2796 tx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
2797 ionic_qcq_free(lif, tx_qcqs[i]);
2798 devm_kfree(lif->ionic->dev, tx_qcqs[i]);
2799 tx_qcqs[i] = NULL;
2800 }
2801 if (rx_qcqs && rx_qcqs[i]) {
2802 rx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
2803 ionic_qcq_free(lif, rx_qcqs[i]);
2804 devm_kfree(lif->ionic->dev, rx_qcqs[i]);
2805 rx_qcqs[i] = NULL;
2806 }
2807 }
2808
2809 /* free q array */
2810 if (rx_qcqs) {
2811 devm_kfree(lif->ionic->dev, rx_qcqs);
2812 rx_qcqs = NULL;
2813 }
2814 if (tx_qcqs) {
2815 devm_kfree(lif->ionic->dev, tx_qcqs);
2816 tx_qcqs = NULL;
2817 }
2818
2819 /* clean the unused dma and info allocations when new set is smaller
2820 * than the full array, but leave the qcq shells in place
2821 */
2822 for (i = lif->nxqs; i < lif->ionic->ntxqs_per_lif; i++) {
2823 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
2824 ionic_qcq_free(lif, lif->txqcqs[i]);
2825
2826 lif->rxqcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
2827 ionic_qcq_free(lif, lif->rxqcqs[i]);
2828 }
2829
2830 if (err)
2831 netdev_info(lif->netdev, "%s: failed %d\n", __func__, err);
2832
2833 return err;
2834 }
2835
ionic_lif_alloc(struct ionic * ionic)2836 int ionic_lif_alloc(struct ionic *ionic)
2837 {
2838 struct device *dev = ionic->dev;
2839 union ionic_lif_identity *lid;
2840 struct net_device *netdev;
2841 struct ionic_lif *lif;
2842 int tbl_sz;
2843 int err;
2844
2845 lid = kzalloc(sizeof(*lid), GFP_KERNEL);
2846 if (!lid)
2847 return -ENOMEM;
2848
2849 netdev = alloc_etherdev_mqs(sizeof(*lif),
2850 ionic->ntxqs_per_lif, ionic->ntxqs_per_lif);
2851 if (!netdev) {
2852 dev_err(dev, "Cannot allocate netdev, aborting\n");
2853 err = -ENOMEM;
2854 goto err_out_free_lid;
2855 }
2856
2857 SET_NETDEV_DEV(netdev, dev);
2858
2859 lif = netdev_priv(netdev);
2860 lif->netdev = netdev;
2861 ionic->lif = lif;
2862 netdev->netdev_ops = &ionic_netdev_ops;
2863 ionic_ethtool_set_ops(netdev);
2864
2865 netdev->watchdog_timeo = 2 * HZ;
2866 netif_carrier_off(netdev);
2867
2868 lif->identity = lid;
2869 lif->lif_type = IONIC_LIF_TYPE_CLASSIC;
2870 err = ionic_lif_identify(ionic, lif->lif_type, lif->identity);
2871 if (err) {
2872 dev_err(ionic->dev, "Cannot identify type %d: %d\n",
2873 lif->lif_type, err);
2874 goto err_out_free_netdev;
2875 }
2876 lif->netdev->min_mtu = max_t(unsigned int, ETH_MIN_MTU,
2877 le32_to_cpu(lif->identity->eth.min_frame_size));
2878 lif->netdev->max_mtu =
2879 le32_to_cpu(lif->identity->eth.max_frame_size) - ETH_HLEN - VLAN_HLEN;
2880
2881 lif->neqs = ionic->neqs_per_lif;
2882 lif->nxqs = ionic->ntxqs_per_lif;
2883
2884 lif->ionic = ionic;
2885 lif->index = 0;
2886
2887 if (is_kdump_kernel()) {
2888 lif->ntxq_descs = IONIC_MIN_TXRX_DESC;
2889 lif->nrxq_descs = IONIC_MIN_TXRX_DESC;
2890 } else {
2891 lif->ntxq_descs = IONIC_DEF_TXRX_DESC;
2892 lif->nrxq_descs = IONIC_DEF_TXRX_DESC;
2893 }
2894
2895 /* Convert the default coalesce value to actual hw resolution */
2896 lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT;
2897 lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic,
2898 lif->rx_coalesce_usecs);
2899 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs;
2900 lif->tx_coalesce_hw = lif->rx_coalesce_hw;
2901 set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state);
2902 set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state);
2903
2904 snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index);
2905
2906 mutex_init(&lif->queue_lock);
2907 mutex_init(&lif->config_lock);
2908
2909 spin_lock_init(&lif->adminq_lock);
2910
2911 spin_lock_init(&lif->deferred.lock);
2912 INIT_LIST_HEAD(&lif->deferred.list);
2913 INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work);
2914
2915 /* allocate lif info */
2916 lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE);
2917 lif->info = dma_alloc_coherent(dev, lif->info_sz,
2918 &lif->info_pa, GFP_KERNEL);
2919 if (!lif->info) {
2920 dev_err(dev, "Failed to allocate lif info, aborting\n");
2921 err = -ENOMEM;
2922 goto err_out_free_mutex;
2923 }
2924
2925 ionic_debugfs_add_lif(lif);
2926
2927 /* allocate control queues and txrx queue arrays */
2928 ionic_lif_queue_identify(lif);
2929 err = ionic_qcqs_alloc(lif);
2930 if (err)
2931 goto err_out_free_lif_info;
2932
2933 /* allocate rss indirection table */
2934 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
2935 lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz;
2936 lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz,
2937 &lif->rss_ind_tbl_pa,
2938 GFP_KERNEL);
2939
2940 if (!lif->rss_ind_tbl) {
2941 err = -ENOMEM;
2942 dev_err(dev, "Failed to allocate rss indirection table, aborting\n");
2943 goto err_out_free_qcqs;
2944 }
2945 netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE);
2946
2947 ionic_lif_alloc_phc(lif);
2948
2949 return 0;
2950
2951 err_out_free_qcqs:
2952 ionic_qcqs_free(lif);
2953 err_out_free_lif_info:
2954 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa);
2955 lif->info = NULL;
2956 lif->info_pa = 0;
2957 err_out_free_mutex:
2958 mutex_destroy(&lif->config_lock);
2959 mutex_destroy(&lif->queue_lock);
2960 err_out_free_netdev:
2961 free_netdev(lif->netdev);
2962 lif = NULL;
2963 err_out_free_lid:
2964 kfree(lid);
2965
2966 return err;
2967 }
2968
ionic_lif_reset(struct ionic_lif * lif)2969 static void ionic_lif_reset(struct ionic_lif *lif)
2970 {
2971 struct ionic_dev *idev = &lif->ionic->idev;
2972
2973 mutex_lock(&lif->ionic->dev_cmd_lock);
2974 ionic_dev_cmd_lif_reset(idev, lif->index);
2975 ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT);
2976 mutex_unlock(&lif->ionic->dev_cmd_lock);
2977 }
2978
ionic_lif_handle_fw_down(struct ionic_lif * lif)2979 static void ionic_lif_handle_fw_down(struct ionic_lif *lif)
2980 {
2981 struct ionic *ionic = lif->ionic;
2982
2983 if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state))
2984 return;
2985
2986 dev_info(ionic->dev, "FW Down: Stopping LIFs\n");
2987
2988 netif_device_detach(lif->netdev);
2989
2990 mutex_lock(&lif->queue_lock);
2991 if (test_bit(IONIC_LIF_F_UP, lif->state)) {
2992 dev_info(ionic->dev, "Surprise FW stop, stopping queues\n");
2993 ionic_stop_queues(lif);
2994 }
2995
2996 if (netif_running(lif->netdev)) {
2997 ionic_txrx_deinit(lif);
2998 ionic_txrx_free(lif);
2999 }
3000 ionic_lif_deinit(lif);
3001 ionic_reset(ionic);
3002 ionic_qcqs_free(lif);
3003
3004 mutex_unlock(&lif->queue_lock);
3005
3006 clear_bit(IONIC_LIF_F_FW_STOPPING, lif->state);
3007 dev_info(ionic->dev, "FW Down: LIFs stopped\n");
3008 }
3009
ionic_lif_handle_fw_up(struct ionic_lif * lif)3010 static void ionic_lif_handle_fw_up(struct ionic_lif *lif)
3011 {
3012 struct ionic *ionic = lif->ionic;
3013 int err;
3014
3015 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state))
3016 return;
3017
3018 dev_info(ionic->dev, "FW Up: restarting LIFs\n");
3019
3020 ionic_init_devinfo(ionic);
3021 err = ionic_identify(ionic);
3022 if (err)
3023 goto err_out;
3024 err = ionic_port_identify(ionic);
3025 if (err)
3026 goto err_out;
3027 err = ionic_port_init(ionic);
3028 if (err)
3029 goto err_out;
3030
3031 mutex_lock(&lif->queue_lock);
3032
3033 if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state))
3034 dev_info(ionic->dev, "FW Up: clearing broken state\n");
3035
3036 err = ionic_qcqs_alloc(lif);
3037 if (err)
3038 goto err_unlock;
3039
3040 err = ionic_lif_init(lif);
3041 if (err)
3042 goto err_qcqs_free;
3043
3044 if (lif->registered)
3045 ionic_lif_set_netdev_info(lif);
3046
3047 ionic_rx_filter_replay(lif);
3048
3049 if (netif_running(lif->netdev)) {
3050 err = ionic_txrx_alloc(lif);
3051 if (err)
3052 goto err_lifs_deinit;
3053
3054 err = ionic_txrx_init(lif);
3055 if (err)
3056 goto err_txrx_free;
3057 }
3058
3059 mutex_unlock(&lif->queue_lock);
3060
3061 clear_bit(IONIC_LIF_F_FW_RESET, lif->state);
3062 ionic_link_status_check_request(lif, CAN_SLEEP);
3063 netif_device_attach(lif->netdev);
3064 dev_info(ionic->dev, "FW Up: LIFs restarted\n");
3065
3066 /* restore the hardware timestamping queues */
3067 ionic_lif_hwstamp_replay(lif);
3068
3069 return;
3070
3071 err_txrx_free:
3072 ionic_txrx_free(lif);
3073 err_lifs_deinit:
3074 ionic_lif_deinit(lif);
3075 err_qcqs_free:
3076 ionic_qcqs_free(lif);
3077 err_unlock:
3078 mutex_unlock(&lif->queue_lock);
3079 err_out:
3080 dev_err(ionic->dev, "FW Up: LIFs restart failed - err %d\n", err);
3081 }
3082
ionic_lif_free(struct ionic_lif * lif)3083 void ionic_lif_free(struct ionic_lif *lif)
3084 {
3085 struct device *dev = lif->ionic->dev;
3086
3087 ionic_lif_free_phc(lif);
3088
3089 /* free rss indirection table */
3090 dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl,
3091 lif->rss_ind_tbl_pa);
3092 lif->rss_ind_tbl = NULL;
3093 lif->rss_ind_tbl_pa = 0;
3094
3095 /* free queues */
3096 ionic_qcqs_free(lif);
3097 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state))
3098 ionic_lif_reset(lif);
3099
3100 /* free lif info */
3101 kfree(lif->identity);
3102 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa);
3103 lif->info = NULL;
3104 lif->info_pa = 0;
3105
3106 /* unmap doorbell page */
3107 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage);
3108 lif->kern_dbpage = NULL;
3109
3110 mutex_destroy(&lif->config_lock);
3111 mutex_destroy(&lif->queue_lock);
3112
3113 /* free netdev & lif */
3114 ionic_debugfs_del_lif(lif);
3115 free_netdev(lif->netdev);
3116 }
3117
ionic_lif_deinit(struct ionic_lif * lif)3118 void ionic_lif_deinit(struct ionic_lif *lif)
3119 {
3120 if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state))
3121 return;
3122
3123 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) {
3124 cancel_work_sync(&lif->deferred.work);
3125 cancel_work_sync(&lif->tx_timeout_work);
3126 ionic_rx_filters_deinit(lif);
3127 if (lif->netdev->features & NETIF_F_RXHASH)
3128 ionic_lif_rss_deinit(lif);
3129 }
3130
3131 napi_disable(&lif->adminqcq->napi);
3132 ionic_lif_qcq_deinit(lif, lif->notifyqcq);
3133 ionic_lif_qcq_deinit(lif, lif->adminqcq);
3134
3135 ionic_lif_reset(lif);
3136 }
3137
ionic_lif_adminq_init(struct ionic_lif * lif)3138 static int ionic_lif_adminq_init(struct ionic_lif *lif)
3139 {
3140 struct device *dev = lif->ionic->dev;
3141 struct ionic_q_init_comp comp;
3142 struct ionic_dev *idev;
3143 struct ionic_qcq *qcq;
3144 struct ionic_queue *q;
3145 int err;
3146
3147 idev = &lif->ionic->idev;
3148 qcq = lif->adminqcq;
3149 q = &qcq->q;
3150
3151 mutex_lock(&lif->ionic->dev_cmd_lock);
3152 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index);
3153 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT);
3154 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp);
3155 mutex_unlock(&lif->ionic->dev_cmd_lock);
3156 if (err) {
3157 netdev_err(lif->netdev, "adminq init failed %d\n", err);
3158 return err;
3159 }
3160
3161 q->hw_type = comp.hw_type;
3162 q->hw_index = le32_to_cpu(comp.hw_index);
3163 q->dbval = IONIC_DBELL_QID(q->hw_index);
3164
3165 dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type);
3166 dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index);
3167
3168 netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi,
3169 NAPI_POLL_WEIGHT);
3170
3171 napi_enable(&qcq->napi);
3172
3173 if (qcq->flags & IONIC_QCQ_F_INTR)
3174 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
3175 IONIC_INTR_MASK_CLEAR);
3176
3177 qcq->flags |= IONIC_QCQ_F_INITED;
3178
3179 return 0;
3180 }
3181
ionic_lif_notifyq_init(struct ionic_lif * lif)3182 static int ionic_lif_notifyq_init(struct ionic_lif *lif)
3183 {
3184 struct ionic_qcq *qcq = lif->notifyqcq;
3185 struct device *dev = lif->ionic->dev;
3186 struct ionic_queue *q = &qcq->q;
3187 int err;
3188
3189 struct ionic_admin_ctx ctx = {
3190 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
3191 .cmd.q_init = {
3192 .opcode = IONIC_CMD_Q_INIT,
3193 .lif_index = cpu_to_le16(lif->index),
3194 .type = q->type,
3195 .ver = lif->qtype_info[q->type].version,
3196 .index = cpu_to_le32(q->index),
3197 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
3198 IONIC_QINIT_F_ENA),
3199 .intr_index = cpu_to_le16(lif->adminqcq->intr.index),
3200 .pid = cpu_to_le16(q->pid),
3201 .ring_size = ilog2(q->num_descs),
3202 .ring_base = cpu_to_le64(q->base_pa),
3203 }
3204 };
3205
3206 dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid);
3207 dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index);
3208 dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
3209 dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
3210
3211 err = ionic_adminq_post_wait(lif, &ctx);
3212 if (err)
3213 return err;
3214
3215 lif->last_eid = 0;
3216 q->hw_type = ctx.comp.q_init.hw_type;
3217 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
3218 q->dbval = IONIC_DBELL_QID(q->hw_index);
3219
3220 dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type);
3221 dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index);
3222
3223 /* preset the callback info */
3224 q->info[0].cb_arg = lif;
3225
3226 qcq->flags |= IONIC_QCQ_F_INITED;
3227
3228 return 0;
3229 }
3230
ionic_station_set(struct ionic_lif * lif)3231 static int ionic_station_set(struct ionic_lif *lif)
3232 {
3233 struct net_device *netdev = lif->netdev;
3234 struct ionic_admin_ctx ctx = {
3235 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
3236 .cmd.lif_getattr = {
3237 .opcode = IONIC_CMD_LIF_GETATTR,
3238 .index = cpu_to_le16(lif->index),
3239 .attr = IONIC_LIF_ATTR_MAC,
3240 },
3241 };
3242 u8 mac_address[ETH_ALEN];
3243 struct sockaddr addr;
3244 int err;
3245
3246 err = ionic_adminq_post_wait(lif, &ctx);
3247 if (err)
3248 return err;
3249 netdev_dbg(lif->netdev, "found initial MAC addr %pM\n",
3250 ctx.comp.lif_getattr.mac);
3251 ether_addr_copy(mac_address, ctx.comp.lif_getattr.mac);
3252
3253 if (is_zero_ether_addr(mac_address)) {
3254 eth_hw_addr_random(netdev);
3255 netdev_dbg(netdev, "Random Mac generated: %pM\n", netdev->dev_addr);
3256 ether_addr_copy(mac_address, netdev->dev_addr);
3257
3258 err = ionic_program_mac(lif, mac_address);
3259 if (err < 0)
3260 return err;
3261
3262 if (err > 0) {
3263 netdev_dbg(netdev, "%s:SET/GET ATTR Mac are not same-due to old FW running\n",
3264 __func__);
3265 return 0;
3266 }
3267 }
3268
3269 if (!is_zero_ether_addr(netdev->dev_addr)) {
3270 /* If the netdev mac is non-zero and doesn't match the default
3271 * device address, it was set by something earlier and we're
3272 * likely here again after a fw-upgrade reset. We need to be
3273 * sure the netdev mac is in our filter list.
3274 */
3275 if (!ether_addr_equal(mac_address, netdev->dev_addr))
3276 ionic_lif_addr_add(lif, netdev->dev_addr);
3277 } else {
3278 /* Update the netdev mac with the device's mac */
3279 ether_addr_copy(addr.sa_data, mac_address);
3280 addr.sa_family = AF_INET;
3281 err = eth_prepare_mac_addr_change(netdev, &addr);
3282 if (err) {
3283 netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n",
3284 addr.sa_data, err);
3285 return 0;
3286 }
3287
3288 eth_commit_mac_addr_change(netdev, &addr);
3289 }
3290
3291 netdev_dbg(lif->netdev, "adding station MAC addr %pM\n",
3292 netdev->dev_addr);
3293 ionic_lif_addr_add(lif, netdev->dev_addr);
3294
3295 return 0;
3296 }
3297
ionic_lif_init(struct ionic_lif * lif)3298 int ionic_lif_init(struct ionic_lif *lif)
3299 {
3300 struct ionic_dev *idev = &lif->ionic->idev;
3301 struct device *dev = lif->ionic->dev;
3302 struct ionic_lif_init_comp comp;
3303 int dbpage_num;
3304 int err;
3305
3306 mutex_lock(&lif->ionic->dev_cmd_lock);
3307 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa);
3308 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT);
3309 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp);
3310 mutex_unlock(&lif->ionic->dev_cmd_lock);
3311 if (err)
3312 return err;
3313
3314 lif->hw_index = le16_to_cpu(comp.hw_index);
3315
3316 /* now that we have the hw_index we can figure out our doorbell page */
3317 lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif);
3318 if (!lif->dbid_count) {
3319 dev_err(dev, "No doorbell pages, aborting\n");
3320 return -EINVAL;
3321 }
3322
3323 lif->kern_pid = 0;
3324 dbpage_num = ionic_db_page_num(lif, lif->kern_pid);
3325 lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num);
3326 if (!lif->kern_dbpage) {
3327 dev_err(dev, "Cannot map dbpage, aborting\n");
3328 return -ENOMEM;
3329 }
3330
3331 err = ionic_lif_adminq_init(lif);
3332 if (err)
3333 goto err_out_adminq_deinit;
3334
3335 if (lif->ionic->nnqs_per_lif) {
3336 err = ionic_lif_notifyq_init(lif);
3337 if (err)
3338 goto err_out_notifyq_deinit;
3339 }
3340
3341 err = ionic_init_nic_features(lif);
3342 if (err)
3343 goto err_out_notifyq_deinit;
3344
3345 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) {
3346 err = ionic_rx_filters_init(lif);
3347 if (err)
3348 goto err_out_notifyq_deinit;
3349 }
3350
3351 err = ionic_station_set(lif);
3352 if (err)
3353 goto err_out_notifyq_deinit;
3354
3355 lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT;
3356
3357 set_bit(IONIC_LIF_F_INITED, lif->state);
3358
3359 INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work);
3360
3361 return 0;
3362
3363 err_out_notifyq_deinit:
3364 napi_disable(&lif->adminqcq->napi);
3365 ionic_lif_qcq_deinit(lif, lif->notifyqcq);
3366 err_out_adminq_deinit:
3367 ionic_lif_qcq_deinit(lif, lif->adminqcq);
3368 ionic_lif_reset(lif);
3369 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage);
3370 lif->kern_dbpage = NULL;
3371
3372 return err;
3373 }
3374
ionic_lif_notify_work(struct work_struct * ws)3375 static void ionic_lif_notify_work(struct work_struct *ws)
3376 {
3377 }
3378
ionic_lif_set_netdev_info(struct ionic_lif * lif)3379 static void ionic_lif_set_netdev_info(struct ionic_lif *lif)
3380 {
3381 struct ionic_admin_ctx ctx = {
3382 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
3383 .cmd.lif_setattr = {
3384 .opcode = IONIC_CMD_LIF_SETATTR,
3385 .index = cpu_to_le16(lif->index),
3386 .attr = IONIC_LIF_ATTR_NAME,
3387 },
3388 };
3389
3390 strscpy(ctx.cmd.lif_setattr.name, lif->netdev->name,
3391 sizeof(ctx.cmd.lif_setattr.name));
3392
3393 ionic_adminq_post_wait(lif, &ctx);
3394 }
3395
ionic_netdev_lif(struct net_device * netdev)3396 static struct ionic_lif *ionic_netdev_lif(struct net_device *netdev)
3397 {
3398 if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit)
3399 return NULL;
3400
3401 return netdev_priv(netdev);
3402 }
3403
ionic_lif_notify(struct notifier_block * nb,unsigned long event,void * info)3404 static int ionic_lif_notify(struct notifier_block *nb,
3405 unsigned long event, void *info)
3406 {
3407 struct net_device *ndev = netdev_notifier_info_to_dev(info);
3408 struct ionic *ionic = container_of(nb, struct ionic, nb);
3409 struct ionic_lif *lif = ionic_netdev_lif(ndev);
3410
3411 if (!lif || lif->ionic != ionic)
3412 return NOTIFY_DONE;
3413
3414 switch (event) {
3415 case NETDEV_CHANGENAME:
3416 ionic_lif_set_netdev_info(lif);
3417 break;
3418 }
3419
3420 return NOTIFY_DONE;
3421 }
3422
ionic_lif_register(struct ionic_lif * lif)3423 int ionic_lif_register(struct ionic_lif *lif)
3424 {
3425 int err;
3426
3427 ionic_lif_register_phc(lif);
3428
3429 INIT_WORK(&lif->ionic->nb_work, ionic_lif_notify_work);
3430
3431 lif->ionic->nb.notifier_call = ionic_lif_notify;
3432
3433 err = register_netdevice_notifier(&lif->ionic->nb);
3434 if (err)
3435 lif->ionic->nb.notifier_call = NULL;
3436
3437 /* only register LIF0 for now */
3438 err = register_netdev(lif->netdev);
3439 if (err) {
3440 dev_err(lif->ionic->dev, "Cannot register net device, aborting\n");
3441 ionic_lif_unregister_phc(lif);
3442 return err;
3443 }
3444
3445 ionic_link_status_check_request(lif, CAN_SLEEP);
3446 lif->registered = true;
3447 ionic_lif_set_netdev_info(lif);
3448
3449 return 0;
3450 }
3451
ionic_lif_unregister(struct ionic_lif * lif)3452 void ionic_lif_unregister(struct ionic_lif *lif)
3453 {
3454 if (lif->ionic->nb.notifier_call) {
3455 unregister_netdevice_notifier(&lif->ionic->nb);
3456 cancel_work_sync(&lif->ionic->nb_work);
3457 lif->ionic->nb.notifier_call = NULL;
3458 }
3459
3460 if (lif->netdev->reg_state == NETREG_REGISTERED)
3461 unregister_netdev(lif->netdev);
3462
3463 ionic_lif_unregister_phc(lif);
3464
3465 lif->registered = false;
3466 }
3467
ionic_lif_queue_identify(struct ionic_lif * lif)3468 static void ionic_lif_queue_identify(struct ionic_lif *lif)
3469 {
3470 union ionic_q_identity __iomem *q_ident;
3471 struct ionic *ionic = lif->ionic;
3472 struct ionic_dev *idev;
3473 int qtype;
3474 int err;
3475
3476 idev = &lif->ionic->idev;
3477 q_ident = (union ionic_q_identity __iomem *)&idev->dev_cmd_regs->data;
3478
3479 for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) {
3480 struct ionic_qtype_info *qti = &lif->qtype_info[qtype];
3481
3482 /* filter out the ones we know about */
3483 switch (qtype) {
3484 case IONIC_QTYPE_ADMINQ:
3485 case IONIC_QTYPE_NOTIFYQ:
3486 case IONIC_QTYPE_RXQ:
3487 case IONIC_QTYPE_TXQ:
3488 break;
3489 default:
3490 continue;
3491 }
3492
3493 memset(qti, 0, sizeof(*qti));
3494
3495 mutex_lock(&ionic->dev_cmd_lock);
3496 ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype,
3497 ionic_qtype_versions[qtype]);
3498 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
3499 if (!err) {
3500 qti->version = readb(&q_ident->version);
3501 qti->supported = readb(&q_ident->supported);
3502 qti->features = readq(&q_ident->features);
3503 qti->desc_sz = readw(&q_ident->desc_sz);
3504 qti->comp_sz = readw(&q_ident->comp_sz);
3505 qti->sg_desc_sz = readw(&q_ident->sg_desc_sz);
3506 qti->max_sg_elems = readw(&q_ident->max_sg_elems);
3507 qti->sg_desc_stride = readw(&q_ident->sg_desc_stride);
3508 }
3509 mutex_unlock(&ionic->dev_cmd_lock);
3510
3511 if (err == -EINVAL) {
3512 dev_err(ionic->dev, "qtype %d not supported\n", qtype);
3513 continue;
3514 } else if (err == -EIO) {
3515 dev_err(ionic->dev, "q_ident failed, not supported on older FW\n");
3516 return;
3517 } else if (err) {
3518 dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n",
3519 qtype, err);
3520 return;
3521 }
3522
3523 dev_dbg(ionic->dev, " qtype[%d].version = %d\n",
3524 qtype, qti->version);
3525 dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n",
3526 qtype, qti->supported);
3527 dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n",
3528 qtype, qti->features);
3529 dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n",
3530 qtype, qti->desc_sz);
3531 dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n",
3532 qtype, qti->comp_sz);
3533 dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n",
3534 qtype, qti->sg_desc_sz);
3535 dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n",
3536 qtype, qti->max_sg_elems);
3537 dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n",
3538 qtype, qti->sg_desc_stride);
3539 }
3540 }
3541
ionic_lif_identify(struct ionic * ionic,u8 lif_type,union ionic_lif_identity * lid)3542 int ionic_lif_identify(struct ionic *ionic, u8 lif_type,
3543 union ionic_lif_identity *lid)
3544 {
3545 struct ionic_dev *idev = &ionic->idev;
3546 size_t sz;
3547 int err;
3548
3549 sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data));
3550
3551 mutex_lock(&ionic->dev_cmd_lock);
3552 ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1);
3553 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
3554 memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz);
3555 mutex_unlock(&ionic->dev_cmd_lock);
3556 if (err)
3557 return (err);
3558
3559 dev_dbg(ionic->dev, "capabilities 0x%llx\n",
3560 le64_to_cpu(lid->capabilities));
3561
3562 dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n",
3563 le32_to_cpu(lid->eth.max_ucast_filters));
3564 dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n",
3565 le32_to_cpu(lid->eth.max_mcast_filters));
3566 dev_dbg(ionic->dev, "eth.features 0x%llx\n",
3567 le64_to_cpu(lid->eth.config.features));
3568 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n",
3569 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ]));
3570 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n",
3571 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ]));
3572 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n",
3573 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ]));
3574 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n",
3575 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ]));
3576 dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name);
3577 dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac);
3578 dev_dbg(ionic->dev, "eth.config.mtu %d\n",
3579 le32_to_cpu(lid->eth.config.mtu));
3580
3581 return 0;
3582 }
3583
ionic_lif_size(struct ionic * ionic)3584 int ionic_lif_size(struct ionic *ionic)
3585 {
3586 struct ionic_identity *ident = &ionic->ident;
3587 unsigned int nintrs, dev_nintrs;
3588 union ionic_lif_config *lc;
3589 unsigned int ntxqs_per_lif;
3590 unsigned int nrxqs_per_lif;
3591 unsigned int neqs_per_lif;
3592 unsigned int nnqs_per_lif;
3593 unsigned int nxqs, neqs;
3594 unsigned int min_intrs;
3595 int err;
3596
3597 /* retrieve basic values from FW */
3598 lc = &ident->lif.eth.config;
3599 dev_nintrs = le32_to_cpu(ident->dev.nintrs);
3600 neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count);
3601 nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]);
3602 ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]);
3603 nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]);
3604
3605 /* limit values to play nice with kdump */
3606 if (is_kdump_kernel()) {
3607 dev_nintrs = 2;
3608 neqs_per_lif = 0;
3609 nnqs_per_lif = 0;
3610 ntxqs_per_lif = 1;
3611 nrxqs_per_lif = 1;
3612 }
3613
3614 /* reserve last queue id for hardware timestamping */
3615 if (lc->features & cpu_to_le64(IONIC_ETH_HW_TIMESTAMP)) {
3616 if (ntxqs_per_lif <= 1 || nrxqs_per_lif <= 1) {
3617 lc->features &= cpu_to_le64(~IONIC_ETH_HW_TIMESTAMP);
3618 } else {
3619 ntxqs_per_lif -= 1;
3620 nrxqs_per_lif -= 1;
3621 }
3622 }
3623
3624 nxqs = min(ntxqs_per_lif, nrxqs_per_lif);
3625 nxqs = min(nxqs, num_online_cpus());
3626 neqs = min(neqs_per_lif, num_online_cpus());
3627
3628 try_again:
3629 /* interrupt usage:
3630 * 1 for master lif adminq/notifyq
3631 * 1 for each CPU for master lif TxRx queue pairs
3632 * whatever's left is for RDMA queues
3633 */
3634 nintrs = 1 + nxqs + neqs;
3635 min_intrs = 2; /* adminq + 1 TxRx queue pair */
3636
3637 if (nintrs > dev_nintrs)
3638 goto try_fewer;
3639
3640 err = ionic_bus_alloc_irq_vectors(ionic, nintrs);
3641 if (err < 0 && err != -ENOSPC) {
3642 dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err);
3643 return err;
3644 }
3645 if (err == -ENOSPC)
3646 goto try_fewer;
3647
3648 if (err != nintrs) {
3649 ionic_bus_free_irq_vectors(ionic);
3650 goto try_fewer;
3651 }
3652
3653 ionic->nnqs_per_lif = nnqs_per_lif;
3654 ionic->neqs_per_lif = neqs;
3655 ionic->ntxqs_per_lif = nxqs;
3656 ionic->nrxqs_per_lif = nxqs;
3657 ionic->nintrs = nintrs;
3658
3659 ionic_debugfs_add_sizes(ionic);
3660
3661 return 0;
3662
3663 try_fewer:
3664 if (nnqs_per_lif > 1) {
3665 nnqs_per_lif >>= 1;
3666 goto try_again;
3667 }
3668 if (neqs > 1) {
3669 neqs >>= 1;
3670 goto try_again;
3671 }
3672 if (nxqs > 1) {
3673 nxqs >>= 1;
3674 goto try_again;
3675 }
3676 dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs);
3677 return -ENOSPC;
3678 }
3679