1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
2 /*
3  * Copyright 2014-2022 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  */
23 
24 #ifndef KFD_PRIV_H_INCLUDED
25 #define KFD_PRIV_H_INCLUDED
26 
27 #include <linux/hashtable.h>
28 #include <linux/mmu_notifier.h>
29 #include <linux/memremap.h>
30 #include <linux/mutex.h>
31 #include <linux/types.h>
32 #include <linux/atomic.h>
33 #include <linux/workqueue.h>
34 #include <linux/spinlock.h>
35 #include <linux/kfd_ioctl.h>
36 #include <linux/idr.h>
37 #include <linux/kfifo.h>
38 #include <linux/seq_file.h>
39 #include <linux/kref.h>
40 #include <linux/sysfs.h>
41 #include <linux/device_cgroup.h>
42 #include <drm/drm_file.h>
43 #include <drm/drm_drv.h>
44 #include <drm/drm_device.h>
45 #include <drm/drm_ioctl.h>
46 #include <kgd_kfd_interface.h>
47 #include <linux/swap.h>
48 
49 #include "amd_shared.h"
50 #include "amdgpu.h"
51 
52 #define KFD_MAX_RING_ENTRY_SIZE	8
53 
54 #define KFD_SYSFS_FILE_MODE 0444
55 
56 /* GPU ID hash width in bits */
57 #define KFD_GPU_ID_HASH_WIDTH 16
58 
59 /* Use upper bits of mmap offset to store KFD driver specific information.
60  * BITS[63:62] - Encode MMAP type
61  * BITS[61:46] - Encode gpu_id. To identify to which GPU the offset belongs to
62  * BITS[45:0]  - MMAP offset value
63  *
64  * NOTE: struct vm_area_struct.vm_pgoff uses offset in pages. Hence, these
65  *  defines are w.r.t to PAGE_SIZE
66  */
67 #define KFD_MMAP_TYPE_SHIFT	62
68 #define KFD_MMAP_TYPE_MASK	(0x3ULL << KFD_MMAP_TYPE_SHIFT)
69 #define KFD_MMAP_TYPE_DOORBELL	(0x3ULL << KFD_MMAP_TYPE_SHIFT)
70 #define KFD_MMAP_TYPE_EVENTS	(0x2ULL << KFD_MMAP_TYPE_SHIFT)
71 #define KFD_MMAP_TYPE_RESERVED_MEM	(0x1ULL << KFD_MMAP_TYPE_SHIFT)
72 #define KFD_MMAP_TYPE_MMIO	(0x0ULL << KFD_MMAP_TYPE_SHIFT)
73 
74 #define KFD_MMAP_GPU_ID_SHIFT 46
75 #define KFD_MMAP_GPU_ID_MASK (((1ULL << KFD_GPU_ID_HASH_WIDTH) - 1) \
76 				<< KFD_MMAP_GPU_ID_SHIFT)
77 #define KFD_MMAP_GPU_ID(gpu_id) ((((uint64_t)gpu_id) << KFD_MMAP_GPU_ID_SHIFT)\
78 				& KFD_MMAP_GPU_ID_MASK)
79 #define KFD_MMAP_GET_GPU_ID(offset)    ((offset & KFD_MMAP_GPU_ID_MASK) \
80 				>> KFD_MMAP_GPU_ID_SHIFT)
81 
82 /*
83  * When working with cp scheduler we should assign the HIQ manually or via
84  * the amdgpu driver to a fixed hqd slot, here are the fixed HIQ hqd slot
85  * definitions for Kaveri. In Kaveri only the first ME queues participates
86  * in the cp scheduling taking that in mind we set the HIQ slot in the
87  * second ME.
88  */
89 #define KFD_CIK_HIQ_PIPE 4
90 #define KFD_CIK_HIQ_QUEUE 0
91 
92 /* Macro for allocating structures */
93 #define kfd_alloc_struct(ptr_to_struct)	\
94 	((typeof(ptr_to_struct)) kzalloc(sizeof(*ptr_to_struct), GFP_KERNEL))
95 
96 #define KFD_MAX_NUM_OF_PROCESSES 512
97 #define KFD_MAX_NUM_OF_QUEUES_PER_PROCESS 1024
98 
99 /*
100  * Size of the per-process TBA+TMA buffer: 2 pages
101  *
102  * The first page is the TBA used for the CWSR ISA code. The second
103  * page is used as TMA for user-mode trap handler setup in daisy-chain mode.
104  */
105 #define KFD_CWSR_TBA_TMA_SIZE (PAGE_SIZE * 2)
106 #define KFD_CWSR_TMA_OFFSET PAGE_SIZE
107 
108 #define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE		\
109 	(KFD_MAX_NUM_OF_PROCESSES *			\
110 			KFD_MAX_NUM_OF_QUEUES_PER_PROCESS)
111 
112 #define KFD_KERNEL_QUEUE_SIZE 2048
113 
114 #define KFD_UNMAP_LATENCY_MS	(4000)
115 
116 /*
117  * 512 = 0x200
118  * The doorbell index distance between SDMA RLC (2*i) and (2*i+1) in the
119  * same SDMA engine on SOC15, which has 8-byte doorbells for SDMA.
120  * 512 8-byte doorbell distance (i.e. one page away) ensures that SDMA RLC
121  * (2*i+1) doorbells (in terms of the lower 12 bit address) lie exactly in
122  * the OFFSET and SIZE set in registers like BIF_SDMA0_DOORBELL_RANGE.
123  */
124 #define KFD_QUEUE_DOORBELL_MIRROR_OFFSET 512
125 
126 /**
127  * enum kfd_ioctl_flags - KFD ioctl flags
128  * Various flags that can be set in &amdkfd_ioctl_desc.flags to control how
129  * userspace can use a given ioctl.
130  */
131 enum kfd_ioctl_flags {
132 	/*
133 	 * @KFD_IOC_FLAG_CHECKPOINT_RESTORE:
134 	 * Certain KFD ioctls such as AMDKFD_IOC_CRIU_OP can potentially
135 	 * perform privileged operations and load arbitrary data into MQDs and
136 	 * eventually HQD registers when the queue is mapped by HWS. In order to
137 	 * prevent this we should perform additional security checks.
138 	 *
139 	 * This is equivalent to callers with the CHECKPOINT_RESTORE capability.
140 	 *
141 	 * Note: Since earlier versions of docker do not support CHECKPOINT_RESTORE,
142 	 * we also allow ioctls with SYS_ADMIN capability.
143 	 */
144 	KFD_IOC_FLAG_CHECKPOINT_RESTORE = BIT(0),
145 };
146 /*
147  * Kernel module parameter to specify maximum number of supported queues per
148  * device
149  */
150 extern int max_num_of_queues_per_device;
151 
152 
153 /* Kernel module parameter to specify the scheduling policy */
154 extern int sched_policy;
155 
156 /*
157  * Kernel module parameter to specify the maximum process
158  * number per HW scheduler
159  */
160 extern int hws_max_conc_proc;
161 
162 extern int cwsr_enable;
163 
164 /*
165  * Kernel module parameter to specify whether to send sigterm to HSA process on
166  * unhandled exception
167  */
168 extern int send_sigterm;
169 
170 /*
171  * This kernel module is used to simulate large bar machine on non-large bar
172  * enabled machines.
173  */
174 extern int debug_largebar;
175 
176 /*
177  * Ignore CRAT table during KFD initialization, can be used to work around
178  * broken CRAT tables on some AMD systems
179  */
180 extern int ignore_crat;
181 
182 /* Set sh_mem_config.retry_disable on GFX v9 */
183 extern int amdgpu_noretry;
184 
185 /* Halt if HWS hang is detected */
186 extern int halt_if_hws_hang;
187 
188 /* Whether MEC FW support GWS barriers */
189 extern bool hws_gws_support;
190 
191 /* Queue preemption timeout in ms */
192 extern int queue_preemption_timeout_ms;
193 
194 /*
195  * Don't evict process queues on vm fault
196  */
197 extern int amdgpu_no_queue_eviction_on_vm_fault;
198 
199 /* Enable eviction debug messages */
200 extern bool debug_evictions;
201 
202 enum cache_policy {
203 	cache_policy_coherent,
204 	cache_policy_noncoherent
205 };
206 
207 #define KFD_GC_VERSION(dev) ((dev)->adev->ip_versions[GC_HWIP][0])
208 #define KFD_IS_SOC15(dev)   ((KFD_GC_VERSION(dev)) >= (IP_VERSION(9, 0, 1)))
209 
210 struct kfd_event_interrupt_class {
211 	bool (*interrupt_isr)(struct kfd_dev *dev,
212 			const uint32_t *ih_ring_entry, uint32_t *patched_ihre,
213 			bool *patched_flag);
214 	void (*interrupt_wq)(struct kfd_dev *dev,
215 			const uint32_t *ih_ring_entry);
216 };
217 
218 struct kfd_device_info {
219 	uint32_t gfx_target_version;
220 	const struct kfd_event_interrupt_class *event_interrupt_class;
221 	unsigned int max_pasid_bits;
222 	unsigned int max_no_of_hqd;
223 	unsigned int doorbell_size;
224 	size_t ih_ring_entry_size;
225 	uint8_t num_of_watch_points;
226 	uint16_t mqd_size_aligned;
227 	bool supports_cwsr;
228 	bool needs_iommu_device;
229 	bool needs_pci_atomics;
230 	uint32_t no_atomic_fw_version;
231 	unsigned int num_sdma_queues_per_engine;
232 	unsigned int num_reserved_sdma_queues_per_engine;
233 	uint64_t reserved_sdma_queues_bitmap;
234 };
235 
236 unsigned int kfd_get_num_sdma_engines(struct kfd_dev *kdev);
237 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_dev *kdev);
238 
239 struct kfd_mem_obj {
240 	uint32_t range_start;
241 	uint32_t range_end;
242 	uint64_t gpu_addr;
243 	uint32_t *cpu_ptr;
244 	void *gtt_mem;
245 };
246 
247 struct kfd_vmid_info {
248 	uint32_t first_vmid_kfd;
249 	uint32_t last_vmid_kfd;
250 	uint32_t vmid_num_kfd;
251 };
252 
253 struct kfd_dev {
254 	struct amdgpu_device *adev;
255 
256 	struct kfd_device_info device_info;
257 	struct pci_dev *pdev;
258 	struct drm_device *ddev;
259 
260 	unsigned int id;		/* topology stub index */
261 
262 	phys_addr_t doorbell_base;	/* Start of actual doorbells used by
263 					 * KFD. It is aligned for mapping
264 					 * into user mode
265 					 */
266 	size_t doorbell_base_dw_offset;	/* Offset from the start of the PCI
267 					 * doorbell BAR to the first KFD
268 					 * doorbell in dwords. GFX reserves
269 					 * the segment before this offset.
270 					 */
271 	u32 __iomem *doorbell_kernel_ptr; /* This is a pointer for a doorbells
272 					   * page used by kernel queue
273 					   */
274 
275 	struct kgd2kfd_shared_resources shared_resources;
276 	struct kfd_vmid_info vm_info;
277 	struct kfd_local_mem_info local_mem_info;
278 
279 	const struct kfd2kgd_calls *kfd2kgd;
280 	struct mutex doorbell_mutex;
281 	DECLARE_BITMAP(doorbell_available_index,
282 			KFD_MAX_NUM_OF_QUEUES_PER_PROCESS);
283 
284 	void *gtt_mem;
285 	uint64_t gtt_start_gpu_addr;
286 	void *gtt_start_cpu_ptr;
287 	void *gtt_sa_bitmap;
288 	struct mutex gtt_sa_lock;
289 	unsigned int gtt_sa_chunk_size;
290 	unsigned int gtt_sa_num_of_chunks;
291 
292 	/* Interrupts */
293 	struct kfifo ih_fifo;
294 	struct workqueue_struct *ih_wq;
295 	struct work_struct interrupt_work;
296 	spinlock_t interrupt_lock;
297 
298 	/* QCM Device instance */
299 	struct device_queue_manager *dqm;
300 
301 	bool init_complete;
302 	/*
303 	 * Interrupts of interest to KFD are copied
304 	 * from the HW ring into a SW ring.
305 	 */
306 	bool interrupts_active;
307 
308 	/* Firmware versions */
309 	uint16_t mec_fw_version;
310 	uint16_t mec2_fw_version;
311 	uint16_t sdma_fw_version;
312 
313 	/* Maximum process number mapped to HW scheduler */
314 	unsigned int max_proc_per_quantum;
315 
316 	/* CWSR */
317 	bool cwsr_enabled;
318 	const void *cwsr_isa;
319 	unsigned int cwsr_isa_size;
320 
321 	/* xGMI */
322 	uint64_t hive_id;
323 
324 	bool pci_atomic_requested;
325 
326 	/* Use IOMMU v2 flag */
327 	bool use_iommu_v2;
328 
329 	/* SRAM ECC flag */
330 	atomic_t sram_ecc_flag;
331 
332 	/* Compute Profile ref. count */
333 	atomic_t compute_profile;
334 
335 	/* Global GWS resource shared between processes */
336 	void *gws;
337 
338 	/* Clients watching SMI events */
339 	struct list_head smi_clients;
340 	spinlock_t smi_lock;
341 
342 	uint32_t reset_seq_num;
343 
344 	struct ida doorbell_ida;
345 	unsigned int max_doorbell_slices;
346 
347 	int noretry;
348 
349 	/* HMM page migration MEMORY_DEVICE_PRIVATE mapping */
350 	struct dev_pagemap pgmap;
351 };
352 
353 enum kfd_mempool {
354 	KFD_MEMPOOL_SYSTEM_CACHEABLE = 1,
355 	KFD_MEMPOOL_SYSTEM_WRITECOMBINE = 2,
356 	KFD_MEMPOOL_FRAMEBUFFER = 3,
357 };
358 
359 /* Character device interface */
360 int kfd_chardev_init(void);
361 void kfd_chardev_exit(void);
362 
363 /**
364  * enum kfd_unmap_queues_filter - Enum for queue filters.
365  *
366  * @KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES: Preempts all queues in the
367  *						running queues list.
368  *
369  * @KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES: Preempts all non-static queues
370  *						in the run list.
371  *
372  * @KFD_UNMAP_QUEUES_FILTER_BY_PASID: Preempts queues that belongs to
373  *						specific process.
374  *
375  */
376 enum kfd_unmap_queues_filter {
377 	KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES = 1,
378 	KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES = 2,
379 	KFD_UNMAP_QUEUES_FILTER_BY_PASID = 3
380 };
381 
382 /**
383  * enum kfd_queue_type - Enum for various queue types.
384  *
385  * @KFD_QUEUE_TYPE_COMPUTE: Regular user mode queue type.
386  *
387  * @KFD_QUEUE_TYPE_SDMA: SDMA user mode queue type.
388  *
389  * @KFD_QUEUE_TYPE_HIQ: HIQ queue type.
390  *
391  * @KFD_QUEUE_TYPE_DIQ: DIQ queue type.
392  *
393  * @KFD_QUEUE_TYPE_SDMA_XGMI: Special SDMA queue for XGMI interface.
394  */
395 enum kfd_queue_type  {
396 	KFD_QUEUE_TYPE_COMPUTE,
397 	KFD_QUEUE_TYPE_SDMA,
398 	KFD_QUEUE_TYPE_HIQ,
399 	KFD_QUEUE_TYPE_DIQ,
400 	KFD_QUEUE_TYPE_SDMA_XGMI
401 };
402 
403 enum kfd_queue_format {
404 	KFD_QUEUE_FORMAT_PM4,
405 	KFD_QUEUE_FORMAT_AQL
406 };
407 
408 enum KFD_QUEUE_PRIORITY {
409 	KFD_QUEUE_PRIORITY_MINIMUM = 0,
410 	KFD_QUEUE_PRIORITY_MAXIMUM = 15
411 };
412 
413 /**
414  * struct queue_properties
415  *
416  * @type: The queue type.
417  *
418  * @queue_id: Queue identifier.
419  *
420  * @queue_address: Queue ring buffer address.
421  *
422  * @queue_size: Queue ring buffer size.
423  *
424  * @priority: Defines the queue priority relative to other queues in the
425  * process.
426  * This is just an indication and HW scheduling may override the priority as
427  * necessary while keeping the relative prioritization.
428  * the priority granularity is from 0 to f which f is the highest priority.
429  * currently all queues are initialized with the highest priority.
430  *
431  * @queue_percent: This field is partially implemented and currently a zero in
432  * this field defines that the queue is non active.
433  *
434  * @read_ptr: User space address which points to the number of dwords the
435  * cp read from the ring buffer. This field updates automatically by the H/W.
436  *
437  * @write_ptr: Defines the number of dwords written to the ring buffer.
438  *
439  * @doorbell_ptr: Notifies the H/W of new packet written to the queue ring
440  * buffer. This field should be similar to write_ptr and the user should
441  * update this field after updating the write_ptr.
442  *
443  * @doorbell_off: The doorbell offset in the doorbell pci-bar.
444  *
445  * @is_interop: Defines if this is a interop queue. Interop queue means that
446  * the queue can access both graphics and compute resources.
447  *
448  * @is_evicted: Defines if the queue is evicted. Only active queues
449  * are evicted, rendering them inactive.
450  *
451  * @is_active: Defines if the queue is active or not. @is_active and
452  * @is_evicted are protected by the DQM lock.
453  *
454  * @is_gws: Defines if the queue has been updated to be GWS-capable or not.
455  * @is_gws should be protected by the DQM lock, since changing it can yield the
456  * possibility of updating DQM state on number of GWS queues.
457  *
458  * @vmid: If the scheduling mode is no cp scheduling the field defines the vmid
459  * of the queue.
460  *
461  * This structure represents the queue properties for each queue no matter if
462  * it's user mode or kernel mode queue.
463  *
464  */
465 
466 struct queue_properties {
467 	enum kfd_queue_type type;
468 	enum kfd_queue_format format;
469 	unsigned int queue_id;
470 	uint64_t queue_address;
471 	uint64_t  queue_size;
472 	uint32_t priority;
473 	uint32_t queue_percent;
474 	uint32_t *read_ptr;
475 	uint32_t *write_ptr;
476 	void __iomem *doorbell_ptr;
477 	uint32_t doorbell_off;
478 	bool is_interop;
479 	bool is_evicted;
480 	bool is_active;
481 	bool is_gws;
482 	/* Not relevant for user mode queues in cp scheduling */
483 	unsigned int vmid;
484 	/* Relevant only for sdma queues*/
485 	uint32_t sdma_engine_id;
486 	uint32_t sdma_queue_id;
487 	uint32_t sdma_vm_addr;
488 	/* Relevant only for VI */
489 	uint64_t eop_ring_buffer_address;
490 	uint32_t eop_ring_buffer_size;
491 	uint64_t ctx_save_restore_area_address;
492 	uint32_t ctx_save_restore_area_size;
493 	uint32_t ctl_stack_size;
494 	uint64_t tba_addr;
495 	uint64_t tma_addr;
496 };
497 
498 #define QUEUE_IS_ACTIVE(q) ((q).queue_size > 0 &&	\
499 			    (q).queue_address != 0 &&	\
500 			    (q).queue_percent > 0 &&	\
501 			    !(q).is_evicted)
502 
503 enum mqd_update_flag {
504 	UPDATE_FLAG_CU_MASK = 0,
505 };
506 
507 struct mqd_update_info {
508 	union {
509 		struct {
510 			uint32_t count; /* Must be a multiple of 32 */
511 			uint32_t *ptr;
512 		} cu_mask;
513 	};
514 	enum mqd_update_flag update_flag;
515 };
516 
517 /**
518  * struct queue
519  *
520  * @list: Queue linked list.
521  *
522  * @mqd: The queue MQD (memory queue descriptor).
523  *
524  * @mqd_mem_obj: The MQD local gpu memory object.
525  *
526  * @gart_mqd_addr: The MQD gart mc address.
527  *
528  * @properties: The queue properties.
529  *
530  * @mec: Used only in no cp scheduling mode and identifies to micro engine id
531  *	 that the queue should be executed on.
532  *
533  * @pipe: Used only in no cp scheduling mode and identifies the queue's pipe
534  *	  id.
535  *
536  * @queue: Used only in no cp scheduliong mode and identifies the queue's slot.
537  *
538  * @process: The kfd process that created this queue.
539  *
540  * @device: The kfd device that created this queue.
541  *
542  * @gws: Pointing to gws kgd_mem if this is a gws control queue; NULL
543  * otherwise.
544  *
545  * This structure represents user mode compute queues.
546  * It contains all the necessary data to handle such queues.
547  *
548  */
549 
550 struct queue {
551 	struct list_head list;
552 	void *mqd;
553 	struct kfd_mem_obj *mqd_mem_obj;
554 	uint64_t gart_mqd_addr;
555 	struct queue_properties properties;
556 
557 	uint32_t mec;
558 	uint32_t pipe;
559 	uint32_t queue;
560 
561 	unsigned int sdma_id;
562 	unsigned int doorbell_id;
563 
564 	struct kfd_process	*process;
565 	struct kfd_dev		*device;
566 	void *gws;
567 
568 	/* procfs */
569 	struct kobject kobj;
570 
571 	void *gang_ctx_bo;
572 	uint64_t gang_ctx_gpu_addr;
573 	void *gang_ctx_cpu_ptr;
574 
575 	struct amdgpu_bo *wptr_bo;
576 };
577 
578 enum KFD_MQD_TYPE {
579 	KFD_MQD_TYPE_HIQ = 0,		/* for hiq */
580 	KFD_MQD_TYPE_CP,		/* for cp queues and diq */
581 	KFD_MQD_TYPE_SDMA,		/* for sdma queues */
582 	KFD_MQD_TYPE_DIQ,		/* for diq */
583 	KFD_MQD_TYPE_MAX
584 };
585 
586 enum KFD_PIPE_PRIORITY {
587 	KFD_PIPE_PRIORITY_CS_LOW = 0,
588 	KFD_PIPE_PRIORITY_CS_MEDIUM,
589 	KFD_PIPE_PRIORITY_CS_HIGH
590 };
591 
592 struct scheduling_resources {
593 	unsigned int vmid_mask;
594 	enum kfd_queue_type type;
595 	uint64_t queue_mask;
596 	uint64_t gws_mask;
597 	uint32_t oac_mask;
598 	uint32_t gds_heap_base;
599 	uint32_t gds_heap_size;
600 };
601 
602 struct process_queue_manager {
603 	/* data */
604 	struct kfd_process	*process;
605 	struct list_head	queues;
606 	unsigned long		*queue_slot_bitmap;
607 };
608 
609 struct qcm_process_device {
610 	/* The Device Queue Manager that owns this data */
611 	struct device_queue_manager *dqm;
612 	struct process_queue_manager *pqm;
613 	/* Queues list */
614 	struct list_head queues_list;
615 	struct list_head priv_queue_list;
616 
617 	unsigned int queue_count;
618 	unsigned int vmid;
619 	bool is_debug;
620 	unsigned int evicted; /* eviction counter, 0=active */
621 
622 	/* This flag tells if we should reset all wavefronts on
623 	 * process termination
624 	 */
625 	bool reset_wavefronts;
626 
627 	/* This flag tells us if this process has a GWS-capable
628 	 * queue that will be mapped into the runlist. It's
629 	 * possible to request a GWS BO, but not have the queue
630 	 * currently mapped, and this changes how the MAP_PROCESS
631 	 * PM4 packet is configured.
632 	 */
633 	bool mapped_gws_queue;
634 
635 	/* All the memory management data should be here too */
636 	uint64_t gds_context_area;
637 	/* Contains page table flags such as AMDGPU_PTE_VALID since gfx9 */
638 	uint64_t page_table_base;
639 	uint32_t sh_mem_config;
640 	uint32_t sh_mem_bases;
641 	uint32_t sh_mem_ape1_base;
642 	uint32_t sh_mem_ape1_limit;
643 	uint32_t gds_size;
644 	uint32_t num_gws;
645 	uint32_t num_oac;
646 	uint32_t sh_hidden_private_base;
647 
648 	/* CWSR memory */
649 	struct kgd_mem *cwsr_mem;
650 	void *cwsr_kaddr;
651 	uint64_t cwsr_base;
652 	uint64_t tba_addr;
653 	uint64_t tma_addr;
654 
655 	/* IB memory */
656 	struct kgd_mem *ib_mem;
657 	uint64_t ib_base;
658 	void *ib_kaddr;
659 
660 	/* doorbell resources per process per device */
661 	unsigned long *doorbell_bitmap;
662 };
663 
664 /* KFD Memory Eviction */
665 
666 /* Approx. wait time before attempting to restore evicted BOs */
667 #define PROCESS_RESTORE_TIME_MS 100
668 /* Approx. back off time if restore fails due to lack of memory */
669 #define PROCESS_BACK_OFF_TIME_MS 100
670 /* Approx. time before evicting the process again */
671 #define PROCESS_ACTIVE_TIME_MS 10
672 
673 /* 8 byte handle containing GPU ID in the most significant 4 bytes and
674  * idr_handle in the least significant 4 bytes
675  */
676 #define MAKE_HANDLE(gpu_id, idr_handle) \
677 	(((uint64_t)(gpu_id) << 32) + idr_handle)
678 #define GET_GPU_ID(handle) (handle >> 32)
679 #define GET_IDR_HANDLE(handle) (handle & 0xFFFFFFFF)
680 
681 enum kfd_pdd_bound {
682 	PDD_UNBOUND = 0,
683 	PDD_BOUND,
684 	PDD_BOUND_SUSPENDED,
685 };
686 
687 #define MAX_SYSFS_FILENAME_LEN 15
688 
689 /*
690  * SDMA counter runs at 100MHz frequency.
691  * We display SDMA activity in microsecond granularity in sysfs.
692  * As a result, the divisor is 100.
693  */
694 #define SDMA_ACTIVITY_DIVISOR  100
695 
696 /* Data that is per-process-per device. */
697 struct kfd_process_device {
698 	/* The device that owns this data. */
699 	struct kfd_dev *dev;
700 
701 	/* The process that owns this kfd_process_device. */
702 	struct kfd_process *process;
703 
704 	/* per-process-per device QCM data structure */
705 	struct qcm_process_device qpd;
706 
707 	/*Apertures*/
708 	uint64_t lds_base;
709 	uint64_t lds_limit;
710 	uint64_t gpuvm_base;
711 	uint64_t gpuvm_limit;
712 	uint64_t scratch_base;
713 	uint64_t scratch_limit;
714 
715 	/* VM context for GPUVM allocations */
716 	struct file *drm_file;
717 	void *drm_priv;
718 	atomic64_t tlb_seq;
719 
720 	/* GPUVM allocations storage */
721 	struct idr alloc_idr;
722 
723 	/* Flag used to tell the pdd has dequeued from the dqm.
724 	 * This is used to prevent dev->dqm->ops.process_termination() from
725 	 * being called twice when it is already called in IOMMU callback
726 	 * function.
727 	 */
728 	bool already_dequeued;
729 	bool runtime_inuse;
730 
731 	/* Is this process/pasid bound to this device? (amd_iommu_bind_pasid) */
732 	enum kfd_pdd_bound bound;
733 
734 	/* VRAM usage */
735 	uint64_t vram_usage;
736 	struct attribute attr_vram;
737 	char vram_filename[MAX_SYSFS_FILENAME_LEN];
738 
739 	/* SDMA activity tracking */
740 	uint64_t sdma_past_activity_counter;
741 	struct attribute attr_sdma;
742 	char sdma_filename[MAX_SYSFS_FILENAME_LEN];
743 
744 	/* Eviction activity tracking */
745 	uint64_t last_evict_timestamp;
746 	atomic64_t evict_duration_counter;
747 	struct attribute attr_evict;
748 
749 	struct kobject *kobj_stats;
750 	unsigned int doorbell_index;
751 
752 	/*
753 	 * @cu_occupancy: Reports occupancy of Compute Units (CU) of a process
754 	 * that is associated with device encoded by "this" struct instance. The
755 	 * value reflects CU usage by all of the waves launched by this process
756 	 * on this device. A very important property of occupancy parameter is
757 	 * that its value is a snapshot of current use.
758 	 *
759 	 * Following is to be noted regarding how this parameter is reported:
760 	 *
761 	 *  The number of waves that a CU can launch is limited by couple of
762 	 *  parameters. These are encoded by struct amdgpu_cu_info instance
763 	 *  that is part of every device definition. For GFX9 devices this
764 	 *  translates to 40 waves (simd_per_cu * max_waves_per_simd) when waves
765 	 *  do not use scratch memory and 32 waves (max_scratch_slots_per_cu)
766 	 *  when they do use scratch memory. This could change for future
767 	 *  devices and therefore this example should be considered as a guide.
768 	 *
769 	 *  All CU's of a device are available for the process. This may not be true
770 	 *  under certain conditions - e.g. CU masking.
771 	 *
772 	 *  Finally number of CU's that are occupied by a process is affected by both
773 	 *  number of CU's a device has along with number of other competing processes
774 	 */
775 	struct attribute attr_cu_occupancy;
776 
777 	/* sysfs counters for GPU retry fault and page migration tracking */
778 	struct kobject *kobj_counters;
779 	struct attribute attr_faults;
780 	struct attribute attr_page_in;
781 	struct attribute attr_page_out;
782 	uint64_t faults;
783 	uint64_t page_in;
784 	uint64_t page_out;
785 	/*
786 	 * If this process has been checkpointed before, then the user
787 	 * application will use the original gpu_id on the
788 	 * checkpointed node to refer to this device.
789 	 */
790 	uint32_t user_gpu_id;
791 
792 	void *proc_ctx_bo;
793 	uint64_t proc_ctx_gpu_addr;
794 	void *proc_ctx_cpu_ptr;
795 };
796 
797 #define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd)
798 
799 struct svm_range_list {
800 	struct mutex			lock;
801 	struct rb_root_cached		objects;
802 	struct list_head		list;
803 	struct work_struct		deferred_list_work;
804 	struct list_head		deferred_range_list;
805 	struct list_head                criu_svm_metadata_list;
806 	spinlock_t			deferred_list_lock;
807 	atomic_t			evicted_ranges;
808 	atomic_t			drain_pagefaults;
809 	struct delayed_work		restore_work;
810 	DECLARE_BITMAP(bitmap_supported, MAX_GPU_INSTANCE);
811 	struct task_struct		*faulting_task;
812 };
813 
814 /* Process data */
815 struct kfd_process {
816 	/*
817 	 * kfd_process are stored in an mm_struct*->kfd_process*
818 	 * hash table (kfd_processes in kfd_process.c)
819 	 */
820 	struct hlist_node kfd_processes;
821 
822 	/*
823 	 * Opaque pointer to mm_struct. We don't hold a reference to
824 	 * it so it should never be dereferenced from here. This is
825 	 * only used for looking up processes by their mm.
826 	 */
827 	void *mm;
828 
829 	struct kref ref;
830 	struct work_struct release_work;
831 
832 	struct mutex mutex;
833 
834 	/*
835 	 * In any process, the thread that started main() is the lead
836 	 * thread and outlives the rest.
837 	 * It is here because amd_iommu_bind_pasid wants a task_struct.
838 	 * It can also be used for safely getting a reference to the
839 	 * mm_struct of the process.
840 	 */
841 	struct task_struct *lead_thread;
842 
843 	/* We want to receive a notification when the mm_struct is destroyed */
844 	struct mmu_notifier mmu_notifier;
845 
846 	u32 pasid;
847 
848 	/*
849 	 * Array of kfd_process_device pointers,
850 	 * one for each device the process is using.
851 	 */
852 	struct kfd_process_device *pdds[MAX_GPU_INSTANCE];
853 	uint32_t n_pdds;
854 
855 	struct process_queue_manager pqm;
856 
857 	/*Is the user space process 32 bit?*/
858 	bool is_32bit_user_mode;
859 
860 	/* Event-related data */
861 	struct mutex event_mutex;
862 	/* Event ID allocator and lookup */
863 	struct idr event_idr;
864 	/* Event page */
865 	u64 signal_handle;
866 	struct kfd_signal_page *signal_page;
867 	size_t signal_mapped_size;
868 	size_t signal_event_count;
869 	bool signal_event_limit_reached;
870 
871 	/* Information used for memory eviction */
872 	void *kgd_process_info;
873 	/* Eviction fence that is attached to all the BOs of this process. The
874 	 * fence will be triggered during eviction and new one will be created
875 	 * during restore
876 	 */
877 	struct dma_fence *ef;
878 
879 	/* Work items for evicting and restoring BOs */
880 	struct delayed_work eviction_work;
881 	struct delayed_work restore_work;
882 	/* seqno of the last scheduled eviction */
883 	unsigned int last_eviction_seqno;
884 	/* Approx. the last timestamp (in jiffies) when the process was
885 	 * restored after an eviction
886 	 */
887 	unsigned long last_restore_timestamp;
888 
889 	/* Kobj for our procfs */
890 	struct kobject *kobj;
891 	struct kobject *kobj_queues;
892 	struct attribute attr_pasid;
893 
894 	/* shared virtual memory registered by this process */
895 	struct svm_range_list svms;
896 
897 	bool xnack_enabled;
898 
899 	atomic_t poison;
900 	/* Queues are in paused stated because we are in the process of doing a CRIU checkpoint */
901 	bool queues_paused;
902 };
903 
904 #define KFD_PROCESS_TABLE_SIZE 5 /* bits: 32 entries */
905 extern DECLARE_HASHTABLE(kfd_processes_table, KFD_PROCESS_TABLE_SIZE);
906 extern struct srcu_struct kfd_processes_srcu;
907 
908 /**
909  * typedef amdkfd_ioctl_t - typedef for ioctl function pointer.
910  *
911  * @filep: pointer to file structure.
912  * @p: amdkfd process pointer.
913  * @data: pointer to arg that was copied from user.
914  *
915  * Return: returns ioctl completion code.
916  */
917 typedef int amdkfd_ioctl_t(struct file *filep, struct kfd_process *p,
918 				void *data);
919 
920 struct amdkfd_ioctl_desc {
921 	unsigned int cmd;
922 	int flags;
923 	amdkfd_ioctl_t *func;
924 	unsigned int cmd_drv;
925 	const char *name;
926 };
927 bool kfd_dev_is_large_bar(struct kfd_dev *dev);
928 
929 int kfd_process_create_wq(void);
930 void kfd_process_destroy_wq(void);
931 struct kfd_process *kfd_create_process(struct file *filep);
932 struct kfd_process *kfd_get_process(const struct task_struct *task);
933 struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid);
934 struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm);
935 
936 int kfd_process_gpuidx_from_gpuid(struct kfd_process *p, uint32_t gpu_id);
937 int kfd_process_gpuid_from_adev(struct kfd_process *p,
938 			       struct amdgpu_device *adev, uint32_t *gpuid,
939 			       uint32_t *gpuidx);
kfd_process_gpuid_from_gpuidx(struct kfd_process * p,uint32_t gpuidx,uint32_t * gpuid)940 static inline int kfd_process_gpuid_from_gpuidx(struct kfd_process *p,
941 				uint32_t gpuidx, uint32_t *gpuid) {
942 	return gpuidx < p->n_pdds ? p->pdds[gpuidx]->dev->id : -EINVAL;
943 }
kfd_process_device_from_gpuidx(struct kfd_process * p,uint32_t gpuidx)944 static inline struct kfd_process_device *kfd_process_device_from_gpuidx(
945 				struct kfd_process *p, uint32_t gpuidx) {
946 	return gpuidx < p->n_pdds ? p->pdds[gpuidx] : NULL;
947 }
948 
949 void kfd_unref_process(struct kfd_process *p);
950 int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger);
951 int kfd_process_restore_queues(struct kfd_process *p);
952 void kfd_suspend_all_processes(void);
953 int kfd_resume_all_processes(void);
954 
955 struct kfd_process_device *kfd_process_device_data_by_id(struct kfd_process *process,
956 							 uint32_t gpu_id);
957 
958 int kfd_process_get_user_gpu_id(struct kfd_process *p, uint32_t actual_gpu_id);
959 
960 int kfd_process_device_init_vm(struct kfd_process_device *pdd,
961 			       struct file *drm_file);
962 struct kfd_process_device *kfd_bind_process_to_device(struct kfd_dev *dev,
963 						struct kfd_process *p);
964 struct kfd_process_device *kfd_get_process_device_data(struct kfd_dev *dev,
965 							struct kfd_process *p);
966 struct kfd_process_device *kfd_create_process_device_data(struct kfd_dev *dev,
967 							struct kfd_process *p);
968 
969 bool kfd_process_xnack_mode(struct kfd_process *p, bool supported);
970 
971 int kfd_reserved_mem_mmap(struct kfd_dev *dev, struct kfd_process *process,
972 			  struct vm_area_struct *vma);
973 
974 /* KFD process API for creating and translating handles */
975 int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd,
976 					void *mem);
977 void *kfd_process_device_translate_handle(struct kfd_process_device *p,
978 					int handle);
979 void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd,
980 					int handle);
981 struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid);
982 
983 /* PASIDs */
984 int kfd_pasid_init(void);
985 void kfd_pasid_exit(void);
986 bool kfd_set_pasid_limit(unsigned int new_limit);
987 unsigned int kfd_get_pasid_limit(void);
988 u32 kfd_pasid_alloc(void);
989 void kfd_pasid_free(u32 pasid);
990 
991 /* Doorbells */
992 size_t kfd_doorbell_process_slice(struct kfd_dev *kfd);
993 int kfd_doorbell_init(struct kfd_dev *kfd);
994 void kfd_doorbell_fini(struct kfd_dev *kfd);
995 int kfd_doorbell_mmap(struct kfd_dev *dev, struct kfd_process *process,
996 		      struct vm_area_struct *vma);
997 void __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd,
998 					unsigned int *doorbell_off);
999 void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr);
1000 u32 read_kernel_doorbell(u32 __iomem *db);
1001 void write_kernel_doorbell(void __iomem *db, u32 value);
1002 void write_kernel_doorbell64(void __iomem *db, u64 value);
1003 unsigned int kfd_get_doorbell_dw_offset_in_bar(struct kfd_dev *kfd,
1004 					struct kfd_process_device *pdd,
1005 					unsigned int doorbell_id);
1006 phys_addr_t kfd_get_process_doorbells(struct kfd_process_device *pdd);
1007 int kfd_alloc_process_doorbells(struct kfd_dev *kfd,
1008 				unsigned int *doorbell_index);
1009 void kfd_free_process_doorbells(struct kfd_dev *kfd,
1010 				unsigned int doorbell_index);
1011 /* GTT Sub-Allocator */
1012 
1013 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size,
1014 			struct kfd_mem_obj **mem_obj);
1015 
1016 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj);
1017 
1018 extern struct device *kfd_device;
1019 
1020 /* KFD's procfs */
1021 void kfd_procfs_init(void);
1022 void kfd_procfs_shutdown(void);
1023 int kfd_procfs_add_queue(struct queue *q);
1024 void kfd_procfs_del_queue(struct queue *q);
1025 
1026 /* Topology */
1027 int kfd_topology_init(void);
1028 void kfd_topology_shutdown(void);
1029 int kfd_topology_add_device(struct kfd_dev *gpu);
1030 int kfd_topology_remove_device(struct kfd_dev *gpu);
1031 struct kfd_topology_device *kfd_topology_device_by_proximity_domain(
1032 						uint32_t proximity_domain);
1033 struct kfd_topology_device *kfd_topology_device_by_proximity_domain_no_lock(
1034 						uint32_t proximity_domain);
1035 struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id);
1036 struct kfd_dev *kfd_device_by_id(uint32_t gpu_id);
1037 struct kfd_dev *kfd_device_by_pci_dev(const struct pci_dev *pdev);
1038 struct kfd_dev *kfd_device_by_adev(const struct amdgpu_device *adev);
1039 int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_dev **kdev);
1040 int kfd_numa_node_to_apic_id(int numa_node_id);
1041 void kfd_double_confirm_iommu_support(struct kfd_dev *gpu);
1042 
1043 /* Interrupts */
1044 int kfd_interrupt_init(struct kfd_dev *dev);
1045 void kfd_interrupt_exit(struct kfd_dev *dev);
1046 bool enqueue_ih_ring_entry(struct kfd_dev *kfd,	const void *ih_ring_entry);
1047 bool interrupt_is_wanted(struct kfd_dev *dev,
1048 				const uint32_t *ih_ring_entry,
1049 				uint32_t *patched_ihre, bool *flag);
1050 
1051 /* amdkfd Apertures */
1052 int kfd_init_apertures(struct kfd_process *process);
1053 
1054 void kfd_process_set_trap_handler(struct qcm_process_device *qpd,
1055 				  uint64_t tba_addr,
1056 				  uint64_t tma_addr);
1057 
1058 /* CRIU */
1059 /*
1060  * Need to increment KFD_CRIU_PRIV_VERSION each time a change is made to any of the CRIU private
1061  * structures:
1062  * kfd_criu_process_priv_data
1063  * kfd_criu_device_priv_data
1064  * kfd_criu_bo_priv_data
1065  * kfd_criu_queue_priv_data
1066  * kfd_criu_event_priv_data
1067  * kfd_criu_svm_range_priv_data
1068  */
1069 
1070 #define KFD_CRIU_PRIV_VERSION 1
1071 
1072 struct kfd_criu_process_priv_data {
1073 	uint32_t version;
1074 	uint32_t xnack_mode;
1075 };
1076 
1077 struct kfd_criu_device_priv_data {
1078 	/* For future use */
1079 	uint64_t reserved;
1080 };
1081 
1082 struct kfd_criu_bo_priv_data {
1083 	uint64_t user_addr;
1084 	uint32_t idr_handle;
1085 	uint32_t mapped_gpuids[MAX_GPU_INSTANCE];
1086 };
1087 
1088 /*
1089  * The first 4 bytes of kfd_criu_queue_priv_data, kfd_criu_event_priv_data,
1090  * kfd_criu_svm_range_priv_data is the object type
1091  */
1092 enum kfd_criu_object_type {
1093 	KFD_CRIU_OBJECT_TYPE_QUEUE,
1094 	KFD_CRIU_OBJECT_TYPE_EVENT,
1095 	KFD_CRIU_OBJECT_TYPE_SVM_RANGE,
1096 };
1097 
1098 struct kfd_criu_svm_range_priv_data {
1099 	uint32_t object_type;
1100 	uint64_t start_addr;
1101 	uint64_t size;
1102 	/* Variable length array of attributes */
1103 	struct kfd_ioctl_svm_attribute attrs[];
1104 };
1105 
1106 struct kfd_criu_queue_priv_data {
1107 	uint32_t object_type;
1108 	uint64_t q_address;
1109 	uint64_t q_size;
1110 	uint64_t read_ptr_addr;
1111 	uint64_t write_ptr_addr;
1112 	uint64_t doorbell_off;
1113 	uint64_t eop_ring_buffer_address;
1114 	uint64_t ctx_save_restore_area_address;
1115 	uint32_t gpu_id;
1116 	uint32_t type;
1117 	uint32_t format;
1118 	uint32_t q_id;
1119 	uint32_t priority;
1120 	uint32_t q_percent;
1121 	uint32_t doorbell_id;
1122 	uint32_t gws;
1123 	uint32_t sdma_id;
1124 	uint32_t eop_ring_buffer_size;
1125 	uint32_t ctx_save_restore_area_size;
1126 	uint32_t ctl_stack_size;
1127 	uint32_t mqd_size;
1128 };
1129 
1130 struct kfd_criu_event_priv_data {
1131 	uint32_t object_type;
1132 	uint64_t user_handle;
1133 	uint32_t event_id;
1134 	uint32_t auto_reset;
1135 	uint32_t type;
1136 	uint32_t signaled;
1137 
1138 	union {
1139 		struct kfd_hsa_memory_exception_data memory_exception_data;
1140 		struct kfd_hsa_hw_exception_data hw_exception_data;
1141 	};
1142 };
1143 
1144 int kfd_process_get_queue_info(struct kfd_process *p,
1145 			       uint32_t *num_queues,
1146 			       uint64_t *priv_data_sizes);
1147 
1148 int kfd_criu_checkpoint_queues(struct kfd_process *p,
1149 			 uint8_t __user *user_priv_data,
1150 			 uint64_t *priv_data_offset);
1151 
1152 int kfd_criu_restore_queue(struct kfd_process *p,
1153 			   uint8_t __user *user_priv_data,
1154 			   uint64_t *priv_data_offset,
1155 			   uint64_t max_priv_data_size);
1156 
1157 int kfd_criu_checkpoint_events(struct kfd_process *p,
1158 			 uint8_t __user *user_priv_data,
1159 			 uint64_t *priv_data_offset);
1160 
1161 int kfd_criu_restore_event(struct file *devkfd,
1162 			   struct kfd_process *p,
1163 			   uint8_t __user *user_priv_data,
1164 			   uint64_t *priv_data_offset,
1165 			   uint64_t max_priv_data_size);
1166 /* CRIU - End */
1167 
1168 /* Queue Context Management */
1169 int init_queue(struct queue **q, const struct queue_properties *properties);
1170 void uninit_queue(struct queue *q);
1171 void print_queue_properties(struct queue_properties *q);
1172 void print_queue(struct queue *q);
1173 
1174 struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
1175 		struct kfd_dev *dev);
1176 struct mqd_manager *mqd_manager_init_cik_hawaii(enum KFD_MQD_TYPE type,
1177 		struct kfd_dev *dev);
1178 struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
1179 		struct kfd_dev *dev);
1180 struct mqd_manager *mqd_manager_init_vi_tonga(enum KFD_MQD_TYPE type,
1181 		struct kfd_dev *dev);
1182 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
1183 		struct kfd_dev *dev);
1184 struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
1185 		struct kfd_dev *dev);
1186 struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type,
1187 		struct kfd_dev *dev);
1188 struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev);
1189 void device_queue_manager_uninit(struct device_queue_manager *dqm);
1190 struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
1191 					enum kfd_queue_type type);
1192 void kernel_queue_uninit(struct kernel_queue *kq, bool hanging);
1193 int kfd_dqm_evict_pasid(struct device_queue_manager *dqm, u32 pasid);
1194 
1195 /* Process Queue Manager */
1196 struct process_queue_node {
1197 	struct queue *q;
1198 	struct kernel_queue *kq;
1199 	struct list_head process_queue_list;
1200 };
1201 
1202 void kfd_process_dequeue_from_device(struct kfd_process_device *pdd);
1203 void kfd_process_dequeue_from_all_devices(struct kfd_process *p);
1204 int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p);
1205 void pqm_uninit(struct process_queue_manager *pqm);
1206 int pqm_create_queue(struct process_queue_manager *pqm,
1207 			    struct kfd_dev *dev,
1208 			    struct file *f,
1209 			    struct queue_properties *properties,
1210 			    unsigned int *qid,
1211 			    struct amdgpu_bo *wptr_bo,
1212 			    const struct kfd_criu_queue_priv_data *q_data,
1213 			    const void *restore_mqd,
1214 			    const void *restore_ctl_stack,
1215 			    uint32_t *p_doorbell_offset_in_process);
1216 int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid);
1217 int pqm_update_queue_properties(struct process_queue_manager *pqm, unsigned int qid,
1218 			struct queue_properties *p);
1219 int pqm_update_mqd(struct process_queue_manager *pqm, unsigned int qid,
1220 			struct mqd_update_info *minfo);
1221 int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid,
1222 			void *gws);
1223 struct kernel_queue *pqm_get_kernel_queue(struct process_queue_manager *pqm,
1224 						unsigned int qid);
1225 struct queue *pqm_get_user_queue(struct process_queue_manager *pqm,
1226 						unsigned int qid);
1227 int pqm_get_wave_state(struct process_queue_manager *pqm,
1228 		       unsigned int qid,
1229 		       void __user *ctl_stack,
1230 		       u32 *ctl_stack_used_size,
1231 		       u32 *save_area_used_size);
1232 
1233 int amdkfd_fence_wait_timeout(uint64_t *fence_addr,
1234 			      uint64_t fence_value,
1235 			      unsigned int timeout_ms);
1236 
1237 int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm,
1238 				  unsigned int qid,
1239 				  u32 *mqd_size,
1240 				  u32 *ctl_stack_size);
1241 /* Packet Manager */
1242 
1243 #define KFD_FENCE_COMPLETED (100)
1244 #define KFD_FENCE_INIT   (10)
1245 
1246 struct packet_manager {
1247 	struct device_queue_manager *dqm;
1248 	struct kernel_queue *priv_queue;
1249 	struct mutex lock;
1250 	bool allocated;
1251 	struct kfd_mem_obj *ib_buffer_obj;
1252 	unsigned int ib_size_bytes;
1253 	bool is_over_subscription;
1254 
1255 	const struct packet_manager_funcs *pmf;
1256 };
1257 
1258 struct packet_manager_funcs {
1259 	/* Support ASIC-specific packet formats for PM4 packets */
1260 	int (*map_process)(struct packet_manager *pm, uint32_t *buffer,
1261 			struct qcm_process_device *qpd);
1262 	int (*runlist)(struct packet_manager *pm, uint32_t *buffer,
1263 			uint64_t ib, size_t ib_size_in_dwords, bool chain);
1264 	int (*set_resources)(struct packet_manager *pm, uint32_t *buffer,
1265 			struct scheduling_resources *res);
1266 	int (*map_queues)(struct packet_manager *pm, uint32_t *buffer,
1267 			struct queue *q, bool is_static);
1268 	int (*unmap_queues)(struct packet_manager *pm, uint32_t *buffer,
1269 			enum kfd_unmap_queues_filter mode,
1270 			uint32_t filter_param, bool reset);
1271 	int (*query_status)(struct packet_manager *pm, uint32_t *buffer,
1272 			uint64_t fence_address,	uint64_t fence_value);
1273 	int (*release_mem)(uint64_t gpu_addr, uint32_t *buffer);
1274 
1275 	/* Packet sizes */
1276 	int map_process_size;
1277 	int runlist_size;
1278 	int set_resources_size;
1279 	int map_queues_size;
1280 	int unmap_queues_size;
1281 	int query_status_size;
1282 	int release_mem_size;
1283 };
1284 
1285 extern const struct packet_manager_funcs kfd_vi_pm_funcs;
1286 extern const struct packet_manager_funcs kfd_v9_pm_funcs;
1287 extern const struct packet_manager_funcs kfd_aldebaran_pm_funcs;
1288 
1289 int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm);
1290 void pm_uninit(struct packet_manager *pm, bool hanging);
1291 int pm_send_set_resources(struct packet_manager *pm,
1292 				struct scheduling_resources *res);
1293 int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues);
1294 int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address,
1295 				uint64_t fence_value);
1296 
1297 int pm_send_unmap_queue(struct packet_manager *pm,
1298 			enum kfd_unmap_queues_filter mode,
1299 			uint32_t filter_param, bool reset);
1300 
1301 void pm_release_ib(struct packet_manager *pm);
1302 
1303 /* Following PM funcs can be shared among VI and AI */
1304 unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size);
1305 
1306 uint64_t kfd_get_number_elems(struct kfd_dev *kfd);
1307 
1308 /* Events */
1309 extern const struct kfd_event_interrupt_class event_interrupt_class_cik;
1310 extern const struct kfd_event_interrupt_class event_interrupt_class_v9;
1311 extern const struct kfd_event_interrupt_class event_interrupt_class_v11;
1312 
1313 extern const struct kfd_device_global_init_class device_global_init_class_cik;
1314 
1315 int kfd_event_init_process(struct kfd_process *p);
1316 void kfd_event_free_process(struct kfd_process *p);
1317 int kfd_event_mmap(struct kfd_process *process, struct vm_area_struct *vma);
1318 int kfd_wait_on_events(struct kfd_process *p,
1319 		       uint32_t num_events, void __user *data,
1320 		       bool all, uint32_t *user_timeout_ms,
1321 		       uint32_t *wait_result);
1322 void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id,
1323 				uint32_t valid_id_bits);
1324 void kfd_signal_iommu_event(struct kfd_dev *dev,
1325 			    u32 pasid, unsigned long address,
1326 			    bool is_write_requested, bool is_execute_requested);
1327 void kfd_signal_hw_exception_event(u32 pasid);
1328 int kfd_set_event(struct kfd_process *p, uint32_t event_id);
1329 int kfd_reset_event(struct kfd_process *p, uint32_t event_id);
1330 int kfd_kmap_event_page(struct kfd_process *p, uint64_t event_page_offset);
1331 
1332 int kfd_event_create(struct file *devkfd, struct kfd_process *p,
1333 		     uint32_t event_type, bool auto_reset, uint32_t node_id,
1334 		     uint32_t *event_id, uint32_t *event_trigger_data,
1335 		     uint64_t *event_page_offset, uint32_t *event_slot_index);
1336 
1337 int kfd_get_num_events(struct kfd_process *p);
1338 int kfd_event_destroy(struct kfd_process *p, uint32_t event_id);
1339 
1340 void kfd_signal_vm_fault_event(struct kfd_dev *dev, u32 pasid,
1341 				struct kfd_vm_fault_info *info);
1342 
1343 void kfd_signal_reset_event(struct kfd_dev *dev);
1344 
1345 void kfd_signal_poison_consumed_event(struct kfd_dev *dev, u32 pasid);
1346 
1347 void kfd_flush_tlb(struct kfd_process_device *pdd, enum TLB_FLUSH_TYPE type);
1348 
kfd_flush_tlb_after_unmap(struct kfd_dev * dev)1349 static inline bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev)
1350 {
1351 	return KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2) ||
1352 	       (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 1) &&
1353 	       dev->adev->sdma.instance[0].fw_version >= 18) ||
1354 	       KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 0);
1355 }
1356 
1357 bool kfd_is_locked(void);
1358 
1359 /* Compute profile */
1360 void kfd_inc_compute_active(struct kfd_dev *dev);
1361 void kfd_dec_compute_active(struct kfd_dev *dev);
1362 
1363 /* Cgroup Support */
1364 /* Check with device cgroup if @kfd device is accessible */
kfd_devcgroup_check_permission(struct kfd_dev * kfd)1365 static inline int kfd_devcgroup_check_permission(struct kfd_dev *kfd)
1366 {
1367 #if defined(CONFIG_CGROUP_DEVICE) || defined(CONFIG_CGROUP_BPF)
1368 	struct drm_device *ddev = kfd->ddev;
1369 
1370 	return devcgroup_check_permission(DEVCG_DEV_CHAR, DRM_MAJOR,
1371 					  ddev->render->index,
1372 					  DEVCG_ACC_WRITE | DEVCG_ACC_READ);
1373 #else
1374 	return 0;
1375 #endif
1376 }
1377 
1378 /* Debugfs */
1379 #if defined(CONFIG_DEBUG_FS)
1380 
1381 void kfd_debugfs_init(void);
1382 void kfd_debugfs_fini(void);
1383 int kfd_debugfs_mqds_by_process(struct seq_file *m, void *data);
1384 int pqm_debugfs_mqds(struct seq_file *m, void *data);
1385 int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data);
1386 int dqm_debugfs_hqds(struct seq_file *m, void *data);
1387 int kfd_debugfs_rls_by_device(struct seq_file *m, void *data);
1388 int pm_debugfs_runlist(struct seq_file *m, void *data);
1389 
1390 int kfd_debugfs_hang_hws(struct kfd_dev *dev);
1391 int pm_debugfs_hang_hws(struct packet_manager *pm);
1392 int dqm_debugfs_hang_hws(struct device_queue_manager *dqm);
1393 
1394 #else
1395 
kfd_debugfs_init(void)1396 static inline void kfd_debugfs_init(void) {}
kfd_debugfs_fini(void)1397 static inline void kfd_debugfs_fini(void) {}
1398 
1399 #endif
1400 
1401 #endif
1402