1 /*
2 * intelfb
3 *
4 * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
5 *
6 * Copyright (C) 2002, 2003 David Dawes <dawes@tungstengraphics.com>
7 *
8 * This driver consists of two parts. The first part (intelfbdrv.c) provides
9 * the basic fbdev interfaces, is derived in part from the radeonfb and
10 * vesafb drivers, and is covered by the GPL. The second part (intelfbhw.c)
11 * provides the code to program the hardware. Most of it is derived from
12 * the i810/i830 XFree86 driver. The HW-specific code is covered here
13 * under a dual license (GPL and MIT/XFree86 license).
14 *
15 * Author: David Dawes
16 *
17 */
18
19 /* $DHD: intelfb/intelfbhw.c,v 1.7 2003/02/06 00:53:11 dawes Exp $ */
20 /* $TG$ */
21
22 #include <linux/config.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/errno.h>
26 #include <linux/string.h>
27 #include <linux/mm.h>
28 #include <linux/tty.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
31 #include <linux/fb.h>
32 #include <linux/console.h>
33 #include <linux/selection.h>
34 #include <linux/ioport.h>
35 #include <linux/init.h>
36 #include <linux/pci.h>
37 #include <linux/vmalloc.h>
38 #include <linux/kd.h>
39 #include <linux/vt_kern.h>
40 #include <linux/pagemap.h>
41 #include <linux/version.h>
42
43 #include <asm/io.h>
44
45 #include <video/fbcon.h>
46 #include <video/fbcon-cfb8.h>
47 #include <video/fbcon-cfb16.h>
48 #include <video/fbcon-cfb32.h>
49
50 #include "intelfb.h"
51 #include "intelfbhw.h"
52
53 int
intelfbhw_get_chipset(struct pci_dev * pdev,const char ** name,int * chipset,int * mobile)54 intelfbhw_get_chipset(struct pci_dev *pdev, const char **name, int *chipset,
55 int *mobile)
56 {
57 u32 tmp;
58
59 if (!pdev || !name || !chipset || !mobile)
60 return 1;
61
62 switch (pdev->device) {
63 case PCI_DEVICE_ID_INTEL_830M:
64 *name = "Intel(R) 830M";
65 *chipset = INTEL_830M;
66 *mobile = 1;
67 return 0;
68 case PCI_DEVICE_ID_INTEL_845G:
69 *name = "Intel(R) 845G";
70 *chipset = INTEL_845G;
71 *mobile = 0;
72 return 0;
73 case PCI_DEVICE_ID_INTEL_85XGM:
74 tmp = 0;
75 *mobile = 1;
76 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
77 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
78 INTEL_85X_VARIANT_MASK) {
79 case INTEL_VAR_855GME:
80 *name = "Intel(R) 855GME";
81 *chipset = INTEL_855GME;
82 return 0;
83 case INTEL_VAR_855GM:
84 *name = "Intel(R) 855GM";
85 *chipset = INTEL_855GM;
86 return 0;
87 case INTEL_VAR_852GME:
88 *name = "Intel(R) 852GME";
89 *chipset = INTEL_852GME;
90 return 0;
91 case INTEL_VAR_852GM:
92 *name = "Intel(R) 852GM";
93 *chipset = INTEL_852GM;
94 return 0;
95 default:
96 *name = "Intel(R) 852GM/855GM";
97 *chipset = INTEL_85XGM;
98 return 0;
99 }
100 break;
101 case PCI_DEVICE_ID_INTEL_865G:
102 *name = "Intel(R) 865G";
103 *chipset = INTEL_865G;
104 *mobile = 0;
105 return 0;
106 default:
107 return 1;
108 }
109 }
110
111 int
intelfbhw_get_memory(struct pci_dev * pdev,int * aperture_size,int * stolen_size)112 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
113 int *stolen_size)
114 {
115 struct pci_dev *bridge_dev;
116 u16 tmp;
117
118 if (!pdev || !aperture_size || !stolen_size)
119 return 1;
120
121 /* Find the bridge device. It is always 0:0.0 */
122 if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) {
123 ERR_MSG("cannot find bridge device\n");
124 return 1;
125 }
126
127 /* Get the fb aperture size and "stolen" memory amount. */
128 tmp = 0;
129 pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
130 switch (pdev->device) {
131 case PCI_DEVICE_ID_INTEL_830M:
132 case PCI_DEVICE_ID_INTEL_845G:
133 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
134 *aperture_size = MB(64);
135 else
136 *aperture_size = MB(128);
137 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
138 case INTEL_830_GMCH_GMS_STOLEN_512:
139 *stolen_size = KB(512) - KB(132);
140 return 0;
141 case INTEL_830_GMCH_GMS_STOLEN_1024:
142 *stolen_size = MB(1) - KB(132);
143 return 0;
144 case INTEL_830_GMCH_GMS_STOLEN_8192:
145 *stolen_size = MB(8) - KB(132);
146 return 0;
147 case INTEL_830_GMCH_GMS_LOCAL:
148 ERR_MSG("only local memory found\n");
149 return 1;
150 case INTEL_830_GMCH_GMS_DISABLED:
151 ERR_MSG("video memory is disabled\n");
152 return 1;
153 default:
154 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
155 tmp & INTEL_830_GMCH_GMS_MASK);
156 return 1;
157 }
158 break;
159 default:
160 *aperture_size = MB(128);
161 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
162 case INTEL_855_GMCH_GMS_STOLEN_1M:
163 *stolen_size = MB(1) - KB(132);
164 return 0;
165 case INTEL_855_GMCH_GMS_STOLEN_4M:
166 *stolen_size = MB(4) - KB(132);
167 return 0;
168 case INTEL_855_GMCH_GMS_STOLEN_8M:
169 *stolen_size = MB(8) - KB(132);
170 return 0;
171 case INTEL_855_GMCH_GMS_STOLEN_16M:
172 *stolen_size = MB(16) - KB(132);
173 return 0;
174 case INTEL_855_GMCH_GMS_STOLEN_32M:
175 *stolen_size = MB(32) - KB(132);
176 return 0;
177 case INTEL_855_GMCH_GMS_DISABLED:
178 ERR_MSG("video memory is disabled\n");
179 return 0;
180 default:
181 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
182 tmp & INTEL_855_GMCH_GMS_MASK);
183 return 1;
184 }
185 }
186 }
187
188 const char *
intelfbhw_check_non_crt(struct intelfb_info * dinfo)189 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
190 {
191 if (INREG(LVDS) & PORT_ENABLE)
192 return "LVDS port";
193 else if (INREG(DVOA) & PORT_ENABLE)
194 return "DVO port A";
195 else if (INREG(DVOB) & PORT_ENABLE)
196 return "DVO port B";
197 else if (INREG(DVOC) & PORT_ENABLE)
198 return "DVO port C";
199 else
200 return NULL;
201 }
202
203 int
intelfbhw_validate_mode(struct intelfb_info * dinfo,int con,struct fb_var_screeninfo * var)204 intelfbhw_validate_mode(struct intelfb_info *dinfo, int con,
205 struct fb_var_screeninfo *var)
206 {
207 int bytes_per_pixel;
208 int tmp;
209
210 DBG_MSG("intelfbhw_validate_mode\n");
211
212 bytes_per_pixel = var->bits_per_pixel / 8;
213 if (bytes_per_pixel == 3)
214 bytes_per_pixel = 4;
215
216 /* Check if enough video memory. */
217 tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
218 if (tmp > dinfo->video_ram) {
219 if (con >= 0)
220 WRN_MSG("Not enough video ram for mode "
221 "(%d KByte vs %d KByte).\n",
222 BtoKB(tmp), BtoKB(dinfo->video_ram));
223 return 1;
224 }
225
226 /* Check if x/y limits are OK. */
227 if (var->xres - 1 > HACTIVE_MASK) {
228 if (con >= 0)
229 WRN_MSG("X resolution too large (%d vs %d).\n",
230 var->xres, HACTIVE_MASK + 1);
231 return 1;
232 }
233 if (var->yres - 1 > VACTIVE_MASK) {
234 if (con >= 0)
235 WRN_MSG("Y resolution too large (%d vs %d).\n",
236 var->yres, VACTIVE_MASK + 1);
237 return 1;
238 }
239
240 /* Check for interlaced/doublescan modes. */
241 if (var->vmode & FB_VMODE_INTERLACED) {
242 if (con >= 0)
243 WRN_MSG("Mode is interlaced.\n");
244 return 1;
245 }
246 if (var->vmode & FB_VMODE_DOUBLE) {
247 if (con >= 0)
248 WRN_MSG("Mode is double-scan.\n");
249 return 1;
250 }
251
252 /* Check if clock is OK. */
253 tmp = 1000000000 / var->pixclock;
254 if (tmp < MIN_CLOCK) {
255 if (con >= 0)
256 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
257 (tmp + 500) / 1000, MIN_CLOCK / 1000);
258 return 1;
259 }
260 if (tmp > MAX_CLOCK) {
261 if (con >= 0)
262 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
263 (tmp + 500) / 1000, MAX_CLOCK / 1000);
264 return 1;
265 }
266
267 return 0;
268 }
269
270 int
intelfbhw_pan_display(struct fb_var_screeninfo * var,int con,struct fb_info * info)271 intelfbhw_pan_display(struct fb_var_screeninfo *var, int con,
272 struct fb_info *info)
273 {
274 struct intelfb_info *dinfo = GET_DINFO(info);
275 u32 offset, xoffset, yoffset;
276
277 DBG_MSG("intelfbhw_pan_display\n");
278
279 if (con != dinfo->currcon)
280 return 0;
281
282 xoffset = ROUND_DOWN_TO(var->xoffset, 8);
283 yoffset = var->yoffset;
284
285 if ((xoffset + var->xres > var->xres_virtual) ||
286 (yoffset + var->yres > var->yres_virtual))
287 return EINVAL;
288
289 offset = (yoffset * dinfo->pitch) +
290 (xoffset * var->bits_per_pixel) / 8;
291
292 OUTREG(DSPABASE, offset);
293
294 return 0;
295 }
296
297 /* Blank the screen. */
298 void
intelfbhw_do_blank(int blank,struct fb_info * info)299 intelfbhw_do_blank(int blank, struct fb_info *info)
300 {
301 struct intelfb_info *dinfo = GET_DINFO(info);
302 u32 tmp;
303
304 DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
305
306 /* Turn plane A on or off */
307 tmp = INREG(DSPACNTR);
308 if (blank)
309 tmp &= ~DISPPLANE_PLANE_ENABLE;
310 else
311 tmp |= DISPPLANE_PLANE_ENABLE;
312 OUTREG(DSPACNTR, tmp);
313 /* Flush */
314 tmp = INREG(DSPABASE);
315 OUTREG(DSPABASE, tmp);
316
317 /* Turn off/on the HW cursor */
318 #if VERBOSE > 0
319 DBG_MSG("cursor.enabled is %d\n", dinfo->cursor.enabled);
320 #endif
321 if (dinfo->cursor.enabled) {
322 if (blank) {
323 intelfbhw_cursor_hide(dinfo);
324 } else {
325 intelfbhw_cursor_show(dinfo);
326 }
327 dinfo->cursor.enabled = 1;
328 }
329 dinfo->cursor.blanked = blank;
330
331 /* Set DPMS level */
332 tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
333 switch (blank) {
334 case 0:
335 case 1:
336 tmp |= ADPA_DPMS_D0;
337 break;
338 case 2:
339 tmp |= ADPA_DPMS_D1;
340 break;
341 case 3:
342 tmp |= ADPA_DPMS_D2;
343 break;
344 case 4:
345 tmp |= ADPA_DPMS_D3;
346 break;
347 }
348 OUTREG(ADPA, tmp);
349
350 return;
351 }
352
353
354 void
intelfbhw_setcolreg(struct intelfb_info * dinfo,unsigned regno,unsigned red,unsigned green,unsigned blue,unsigned transp)355 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
356 unsigned red, unsigned green, unsigned blue,
357 unsigned transp)
358 {
359 #if VERBOSE > 1
360 DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
361 regno, red, green, blue);
362 #endif
363
364 u32 palette_reg = (dinfo->pipe == PIPE_A) ?
365 PALETTE_A : PALETTE_B;
366
367 OUTREG(palette_reg + (regno << 2),
368 (red << PALETTE_8_RED_SHIFT) |
369 (green << PALETTE_8_GREEN_SHIFT) |
370 (blue << PALETTE_8_BLUE_SHIFT));
371 }
372
373
374 int
intelfbhw_read_hw_state(struct intelfb_info * dinfo,struct intelfb_hwstate * hw,int flag)375 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
376 int flag)
377 {
378 int i;
379
380 DBG_MSG("intelfbhw_read_hw_state\n");
381
382 if (!hw || !dinfo)
383 return -1;
384
385 /* Read in as much of the HW state as possible. */
386 hw->vga0_divisor = INREG(VGA0_DIVISOR);
387 hw->vga1_divisor = INREG(VGA1_DIVISOR);
388 hw->vga_pd = INREG(VGAPD);
389 hw->dpll_a = INREG(DPLL_A);
390 hw->dpll_b = INREG(DPLL_B);
391 hw->fpa0 = INREG(FPA0);
392 hw->fpa1 = INREG(FPA1);
393 hw->fpb0 = INREG(FPB0);
394 hw->fpb1 = INREG(FPB1);
395
396 if (flag == 1)
397 return flag;
398
399 #if 0
400 /* This seems to be a problem with the 852GM/855GM */
401 for (i = 0; i < PALETTE_8_ENTRIES; i++) {
402 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
403 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
404 }
405 #endif
406
407 if (flag == 2)
408 return flag;
409
410 hw->htotal_a = INREG(HTOTAL_A);
411 hw->hblank_a = INREG(HBLANK_A);
412 hw->hsync_a = INREG(HSYNC_A);
413 hw->vtotal_a = INREG(VTOTAL_A);
414 hw->vblank_a = INREG(VBLANK_A);
415 hw->vsync_a = INREG(VSYNC_A);
416 hw->src_size_a = INREG(SRC_SIZE_A);
417 hw->bclrpat_a = INREG(BCLRPAT_A);
418 hw->htotal_b = INREG(HTOTAL_B);
419 hw->hblank_b = INREG(HBLANK_B);
420 hw->hsync_b = INREG(HSYNC_B);
421 hw->vtotal_b = INREG(VTOTAL_B);
422 hw->vblank_b = INREG(VBLANK_B);
423 hw->vsync_b = INREG(VSYNC_B);
424 hw->src_size_b = INREG(SRC_SIZE_B);
425 hw->bclrpat_b = INREG(BCLRPAT_B);
426
427 if (flag == 3)
428 return flag;
429
430 hw->adpa = INREG(ADPA);
431 hw->dvoa = INREG(DVOA);
432 hw->dvob = INREG(DVOB);
433 hw->dvoc = INREG(DVOC);
434 hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
435 hw->dvob_srcdim = INREG(DVOB_SRCDIM);
436 hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
437 hw->lvds = INREG(LVDS);
438
439 if (flag == 4)
440 return flag;
441
442 hw->pipe_a_conf = INREG(PIPEACONF);
443 hw->pipe_b_conf = INREG(PIPEBCONF);
444 hw->disp_arb = INREG(DISPARB);
445
446 if (flag == 5)
447 return flag;
448
449 hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
450 hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
451 hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
452 hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
453
454 if (flag == 6)
455 return flag;
456
457 for (i = 0; i < 4; i++) {
458 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
459 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
460 }
461
462 if (flag == 7)
463 return flag;
464
465 hw->cursor_size = INREG(CURSOR_SIZE);
466
467 if (flag == 8)
468 return flag;
469
470 hw->disp_a_ctrl = INREG(DSPACNTR);
471 hw->disp_b_ctrl = INREG(DSPBCNTR);
472 hw->disp_a_base = INREG(DSPABASE);
473 hw->disp_b_base = INREG(DSPBBASE);
474 hw->disp_a_stride = INREG(DSPASTRIDE);
475 hw->disp_b_stride = INREG(DSPBSTRIDE);
476
477 if (flag == 9)
478 return flag;
479
480 hw->vgacntrl = INREG(VGACNTRL);
481
482 if (flag == 10)
483 return flag;
484
485 hw->add_id = INREG(ADD_ID);
486
487 if (flag == 11)
488 return flag;
489
490 for (i = 0; i < 7; i++) {
491 hw->swf0x[i] = INREG(SWF00 + (i << 2));
492 hw->swf1x[i] = INREG(SWF10 + (i << 2));
493 if (i < 3)
494 hw->swf3x[i] = INREG(SWF30 + (i << 2));
495 }
496
497 for (i = 0; i < 8; i++)
498 hw->fence[i] = INREG(FENCE + (i << 2));
499
500 hw->instpm = INREG(INSTPM);
501 hw->mem_mode = INREG(MEM_MODE);
502 hw->fw_blc_0 = INREG(FW_BLC_0);
503 hw->fw_blc_1 = INREG(FW_BLC_1);
504
505 return 0;
506 }
507
508
509 void
intelfbhw_print_hw_state(struct intelfb_info * dinfo,struct intelfb_hwstate * hw)510 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
511 {
512 #if REGDUMP
513 int i, m1, m2, n, p1, p2;
514
515 DBG_MSG("intelfbhw_print_hw_state\n");
516
517 if (!hw || !dinfo)
518 return;
519 /* Read in as much of the HW state as possible. */
520 printk("hw state dump start\n");
521 printk(" VGA0_DIVISOR: 0x%08x\n", hw->vga0_divisor);
522 printk(" VGA1_DIVISOR: 0x%08x\n", hw->vga1_divisor);
523 printk(" VGAPD: 0x%08x\n", hw->vga_pd);
524 n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
525 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
526 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
527 if (hw->vga_pd & VGAPD_0_P1_FORCE_DIV2)
528 p1 = 0;
529 else
530 p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
531 p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
532 printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
533 m1, m2, n, p1, p2);
534 printk(" VGA0: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
535
536 n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
537 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
538 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
539 if (hw->vga_pd & VGAPD_1_P1_FORCE_DIV2)
540 p1 = 0;
541 else
542 p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK;
543 p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
544 printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
545 m1, m2, n, p1, p2);
546 printk(" VGA1: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
547
548 printk(" DPLL_A: 0x%08x\n", hw->dpll_a);
549 printk(" DPLL_B: 0x%08x\n", hw->dpll_b);
550 printk(" FPA0: 0x%08x\n", hw->fpa0);
551 printk(" FPA1: 0x%08x\n", hw->fpa1);
552 printk(" FPB0: 0x%08x\n", hw->fpb0);
553 printk(" FPB1: 0x%08x\n", hw->fpb1);
554
555 n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
556 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
557 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
558 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
559 p1 = 0;
560 else
561 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
562 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
563 printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
564 m1, m2, n, p1, p2);
565 printk(" PLLA0: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
566
567 n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
568 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
569 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
570 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
571 p1 = 0;
572 else
573 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
574 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
575 printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
576 m1, m2, n, p1, p2);
577 printk(" PLLA1: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
578
579 #if 0
580 printk(" PALETTE_A:\n");
581 for (i = 0; i < PALETTE_8_ENTRIES)
582 printk(" %3d: 0x%08x\n", i, hw->palette_a[i];
583 printk(" PALETTE_B:\n");
584 for (i = 0; i < PALETTE_8_ENTRIES)
585 printk(" %3d: 0x%08x\n", i, hw->palette_b[i];
586 #endif
587
588 printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a);
589 printk(" HBLANK_A: 0x%08x\n", hw->hblank_a);
590 printk(" HSYNC_A: 0x%08x\n", hw->hsync_a);
591 printk(" VTOTAL_A: 0x%08x\n", hw->vtotal_a);
592 printk(" VBLANK_A: 0x%08x\n", hw->vblank_a);
593 printk(" VSYNC_A: 0x%08x\n", hw->vsync_a);
594 printk(" SRC_SIZE_A: 0x%08x\n", hw->src_size_a);
595 printk(" BCLRPAT_A: 0x%08x\n", hw->bclrpat_a);
596 printk(" HTOTAL_B: 0x%08x\n", hw->htotal_b);
597 printk(" HBLANK_B: 0x%08x\n", hw->hblank_b);
598 printk(" HSYNC_B: 0x%08x\n", hw->hsync_b);
599 printk(" VTOTAL_B: 0x%08x\n", hw->vtotal_b);
600 printk(" VBLANK_B: 0x%08x\n", hw->vblank_b);
601 printk(" VSYNC_B: 0x%08x\n", hw->vsync_b);
602 printk(" SRC_SIZE_B: 0x%08x\n", hw->src_size_b);
603 printk(" BCLRPAT_B: 0x%08x\n", hw->bclrpat_b);
604
605 printk(" ADPA: 0x%08x\n", hw->adpa);
606 printk(" DVOA: 0x%08x\n", hw->dvoa);
607 printk(" DVOB: 0x%08x\n", hw->dvob);
608 printk(" DVOC: 0x%08x\n", hw->dvoc);
609 printk(" DVOA_SRCDIM: 0x%08x\n", hw->dvoa_srcdim);
610 printk(" DVOB_SRCDIM: 0x%08x\n", hw->dvob_srcdim);
611 printk(" DVOC_SRCDIM: 0x%08x\n", hw->dvoc_srcdim);
612 printk(" LVDS: 0x%08x\n", hw->lvds);
613
614 printk(" PIPEACONF: 0x%08x\n", hw->pipe_a_conf);
615 printk(" PIPEBCONF: 0x%08x\n", hw->pipe_b_conf);
616 printk(" DISPARB: 0x%08x\n", hw->disp_arb);
617
618 printk(" CURSOR_A_CONTROL: 0x%08x\n", hw->cursor_a_control);
619 printk(" CURSOR_B_CONTROL: 0x%08x\n", hw->cursor_b_control);
620 printk(" CURSOR_A_BASEADDR: 0x%08x\n", hw->cursor_a_base);
621 printk(" CURSOR_B_BASEADDR: 0x%08x\n", hw->cursor_b_base);
622
623 printk(" CURSOR_A_PALETTE: ");
624 for (i = 0; i < 4; i++) {
625 printk("0x%08x", hw->cursor_a_palette[i]);
626 if (i < 3)
627 printk(", ");
628 }
629 printk("\n");
630 printk(" CURSOR_B_PALETTE: ");
631 for (i = 0; i < 4; i++) {
632 printk("0x%08x", hw->cursor_b_palette[i]);
633 if (i < 3)
634 printk(", ");
635 }
636 printk("\n");
637
638 printk(" CURSOR_SIZE: 0x%08x\n", hw->cursor_size);
639
640 printk(" DSPACNTR: 0x%08x\n", hw->disp_a_ctrl);
641 printk(" DSPBCNTR: 0x%08x\n", hw->disp_b_ctrl);
642 printk(" DSPABASE: 0x%08x\n", hw->disp_a_base);
643 printk(" DSPBBASE: 0x%08x\n", hw->disp_b_base);
644 printk(" DSPASTRIDE: 0x%08x\n", hw->disp_a_stride);
645 printk(" DSPBSTRIDE: 0x%08x\n", hw->disp_b_stride);
646
647 printk(" VGACNTRL: 0x%08x\n", hw->vgacntrl);
648 printk(" ADD_ID: 0x%08x\n", hw->add_id);
649
650 for (i = 0; i < 7; i++) {
651 printk(" SWF0%d 0x%08x\n", i,
652 hw->swf0x[i]);
653 }
654 for (i = 0; i < 7; i++) {
655 printk(" SWF1%d 0x%08x\n", i,
656 hw->swf1x[i]);
657 }
658 for (i = 0; i < 3; i++) {
659 printk(" SWF3%d 0x%08x\n", i,
660 hw->swf3x[i]);
661 }
662 for (i = 0; i < 8; i++)
663 printk(" FENCE%d 0x%08x\n", i,
664 hw->fence[i]);
665
666 printk(" INSTPM 0x%08x\n", hw->instpm);
667 printk(" MEM_MODE 0x%08x\n", hw->mem_mode);
668 printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0);
669 printk(" FW_BLC_1 0x%08x\n", hw->fw_blc_1);
670
671 printk("hw state dump end\n");
672 #endif
673 }
674
675 /* Split the M parameter into M1 and M2. */
676 static int
splitm(unsigned int m,unsigned int * retm1,unsigned int * retm2)677 splitm(unsigned int m, unsigned int *retm1, unsigned int *retm2)
678 {
679 int m1, m2;
680
681 m1 = (m - 2 - (MIN_M2 + MAX_M2) / 2) / 5 - 2;
682 if (m1 < MIN_M1)
683 m1 = MIN_M1;
684 if (m1 > MAX_M1)
685 m1 = MAX_M1;
686 m2 = m - 5 * (m1 + 2) - 2;
687 if (m2 < MIN_M2 || m2 > MAX_M2 || m2 >= m1) {
688 return 1;
689 } else {
690 *retm1 = (unsigned int)m1;
691 *retm2 = (unsigned int)m2;
692 return 0;
693 }
694 }
695
696 /* Split the P parameter into P1 and P2. */
697 static int
splitp(unsigned int p,unsigned int * retp1,unsigned int * retp2)698 splitp(unsigned int p, unsigned int *retp1, unsigned int *retp2)
699 {
700 int p1, p2;
701
702 if (p % 4 == 0)
703 p2 = 1;
704 else
705 p2 = 0;
706 p1 = (p / (1 << (p2 + 1))) - 2;
707 if (p % 4 == 0 && p1 < MIN_P1) {
708 p2 = 0;
709 p1 = (p / (1 << (p2 + 1))) - 2;
710 }
711 if (p1 < MIN_P1 || p1 > MAX_P1 || (p1 + 2) * (1 << (p2 + 1)) != p) {
712 return 1;
713 } else {
714 *retp1 = (unsigned int)p1;
715 *retp2 = (unsigned int)p2;
716 return 0;
717 }
718 }
719
720 static int
calc_pll_params(int clock,u32 * retm1,u32 * retm2,u32 * retn,u32 * retp1,u32 * retp2,u32 * retclock)721 calc_pll_params(int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
722 u32 *retp2, u32 *retclock)
723 {
724 u32 m1, m2, n, p1, p2, n1;
725 u32 f_vco, p, p_best = 0, m, f_out;
726 u32 err_max, err_target, err_best = 10000000;
727 u32 n_best = 0, m_best = 0, f_best, f_err;
728 u32 p_min, p_max, p_inc, div_min, div_max;
729
730 /* Accept 0.5% difference, but aim for 0.1% */
731 err_max = 5 * clock / 1000;
732 err_target = clock / 1000;
733
734 DBG_MSG("Clock is %d\n", clock);
735
736 div_max = MAX_VCO_FREQ / clock;
737 div_min = ROUND_UP_TO(MIN_VCO_FREQ, clock) / clock;
738
739 if (clock <= P_TRANSITION_CLOCK)
740 p_inc = 4;
741 else
742 p_inc = 2;
743 p_min = ROUND_UP_TO(div_min, p_inc);
744 p_max = ROUND_DOWN_TO(div_max, p_inc);
745 if (p_min < MIN_P)
746 p_min = 4;
747 if (p_max > MAX_P)
748 p_max = 128;
749
750 DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
751
752 p = p_min;
753 do {
754 if (splitp(p, &p1, &p2)) {
755 WRN_MSG("cannot split p = %d\n", p);
756 p += p_inc;
757 continue;
758 }
759 n = MIN_N;
760 f_vco = clock * p;
761
762 do {
763 m = ROUND_UP_TO(f_vco * n, PLL_REFCLK) / PLL_REFCLK;
764 if (m < MIN_M)
765 m = MIN_M;
766 if (m > MAX_M)
767 m = MAX_M;
768 f_out = CALC_VCLOCK3(m, n, p);
769 if (splitm(m, &m1, &m2)) {
770 WRN_MSG("cannot split m = %d\n", m);
771 n++;
772 continue;
773 }
774 if (clock > f_out)
775 f_err = clock - f_out;
776 else
777 f_err = f_out - clock;
778
779 if (f_err < err_best) {
780 m_best = m;
781 n_best = n;
782 p_best = p;
783 f_best = f_out;
784 err_best = f_err;
785 }
786 n++;
787 } while ((n <= MAX_N) && (f_out >= clock));
788 p += p_inc;
789 } while ((p <= p_max));
790
791 if (!m_best) {
792 WRN_MSG("cannot find parameters for clock %d\n", clock);
793 return 1;
794 }
795 m = m_best;
796 n = n_best;
797 p = p_best;
798 splitm(m, &m1, &m2);
799 splitp(p, &p1, &p2);
800 n1 = n - 2;
801
802 DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
803 "f: %d (%d), VCO: %d\n",
804 m, m1, m2, n, n1, p, p1, p2,
805 CALC_VCLOCK3(m, n, p), CALC_VCLOCK(m1, m2, n1, p1, p2),
806 CALC_VCLOCK3(m, n, p) * p);
807 *retm1 = m1;
808 *retm2 = m2;
809 *retn = n1;
810 *retp1 = p1;
811 *retp2 = p2;
812 *retclock = CALC_VCLOCK(m1, m2, n1, p1, p2);
813
814 return 0;
815 }
816
817 static __inline__ int
check_overflow(u32 value,u32 limit,const char * description)818 check_overflow(u32 value, u32 limit, const char *description)
819 {
820 if (value > limit) {
821 WRN_MSG("%s value %d exceeds limit %d\n",
822 description, value, limit);
823 return 1;
824 }
825 return 0;
826 }
827
828 /* It is assumed that hw is filled in with the initial state information. */
829 int
intelfbhw_mode_to_hw(struct intelfb_info * dinfo,struct intelfb_hwstate * hw,struct fb_var_screeninfo * var)830 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
831 struct fb_var_screeninfo *var)
832 {
833 int pipe = PIPE_A;
834 u32 *dpll, *fp0, *fp1;
835 u32 m1, m2, n, p1, p2, clock_target, clock;
836 u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
837 u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
838 u32 vsync_pol, hsync_pol;
839 u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
840 struct display *disp;
841
842 DBG_MSG("intelfbhw_mode_to_hw\n");
843
844 disp = GET_DISP(&dinfo->info, dinfo->currcon);
845
846 /* Disable VGA */
847 hw->vgacntrl |= VGA_DISABLE;
848
849 /* Check whether pipe A or pipe B is enabled. */
850 if (hw->pipe_a_conf & PIPECONF_ENABLE)
851 pipe = PIPE_A;
852 else if (hw->pipe_b_conf & PIPECONF_ENABLE)
853 pipe = PIPE_B;
854
855 /* Set which pipe's registers will be set. */
856 if (pipe == PIPE_B) {
857 dpll = &hw->dpll_b;
858 fp0 = &hw->fpb0;
859 fp1 = &hw->fpb1;
860 hs = &hw->hsync_b;
861 hb = &hw->hblank_b;
862 ht = &hw->htotal_b;
863 vs = &hw->vsync_b;
864 vb = &hw->vblank_b;
865 vt = &hw->vtotal_b;
866 ss = &hw->src_size_b;
867 pipe_conf = &hw->pipe_b_conf;
868 } else {
869 dpll = &hw->dpll_a;
870 fp0 = &hw->fpa0;
871 fp1 = &hw->fpa1;
872 hs = &hw->hsync_a;
873 hb = &hw->hblank_a;
874 ht = &hw->htotal_a;
875 vs = &hw->vsync_a;
876 vb = &hw->vblank_a;
877 vt = &hw->vtotal_a;
878 ss = &hw->src_size_a;
879 pipe_conf = &hw->pipe_a_conf;
880 }
881
882 /* Use ADPA register for sync control. */
883 hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
884
885 /* sync polarity */
886 hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
887 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
888 vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
889 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
890 hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
891 (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
892 hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
893 (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
894
895 /* Connect correct pipe to the analog port DAC */
896 hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
897 hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
898
899 /* Set DPMS state to D0 (on) */
900 hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
901 hw->adpa |= ADPA_DPMS_D0;
902
903 *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
904 *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
905 *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
906
907 /* Desired clock in kHz */
908 clock_target = 1000000000 / var->pixclock;
909 if (calc_pll_params(clock_target, &m1, &m2, &n, &p1, &p2, &clock)) {
910 WRN_MSG("calc_pll_params failed\n");
911 return 1;
912 }
913
914 /* Check for overflow. */
915 if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
916 return 1;
917 if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
918 return 1;
919 if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
920 return 1;
921 if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
922 return 1;
923 if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
924 return 1;
925
926 *dpll &= ~DPLL_P1_FORCE_DIV2;
927 *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
928 (DPLL_P1_MASK << DPLL_P1_SHIFT));
929 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
930 *fp0 = (n << FP_N_DIVISOR_SHIFT) |
931 (m1 << FP_M1_DIVISOR_SHIFT) |
932 (m2 << FP_M2_DIVISOR_SHIFT);
933 *fp1 = *fp0;
934
935 /* Make sure DVOB and DVOC are disabled for now. */
936 hw->dvob &= ~PORT_ENABLE;
937 hw->dvoc &= ~PORT_ENABLE;
938
939 /* Use display plane A. */
940 hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
941 hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
942 hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
943 switch (intelfb_var_to_depth(var)) {
944 case 8:
945 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
946 break;
947 case 15:
948 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
949 break;
950 case 16:
951 hw->disp_a_ctrl |= DISPPLANE_16BPP;
952 break;
953 case 24:
954 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
955 break;
956 }
957 hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
958 hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
959
960 /* Set CRTC registers. */
961 hactive = var->xres;
962 hsync_start = hactive + var->right_margin;
963 hsync_end = hsync_start + var->hsync_len;
964 htotal = hsync_end + var->left_margin;
965 hblank_start = hactive;
966 hblank_end = htotal;
967
968 DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
969 hactive, hsync_start, hsync_end, htotal, hblank_start,
970 hblank_end);
971
972 vactive = var->yres;
973 vsync_start = vactive + var->lower_margin;
974 vsync_end = vsync_start + var->vsync_len;
975 vtotal = vsync_end + var->upper_margin;
976 vblank_start = vactive;
977 vblank_end = vtotal;
978 vblank_end = vsync_end + 1;
979
980 DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
981 vactive, vsync_start, vsync_end, vtotal, vblank_start,
982 vblank_end);
983
984 /* Adjust for register values, and check for overflow. */
985 hactive--;
986 if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
987 return 1;
988 hsync_start--;
989 if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
990 return 1;
991 hsync_end--;
992 if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
993 return 1;
994 htotal--;
995 if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
996 return 1;
997 hblank_start--;
998 if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
999 return 1;
1000 hblank_end--;
1001 if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1002 return 1;
1003
1004 vactive--;
1005 if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1006 return 1;
1007 vsync_start--;
1008 if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1009 return 1;
1010 vsync_end--;
1011 if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1012 return 1;
1013 vtotal--;
1014 if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1015 return 1;
1016 vblank_start--;
1017 if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1018 return 1;
1019 vblank_end--;
1020 if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1021 return 1;
1022
1023 *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1024 *hb = (hblank_start << HBLANKSTART_SHIFT) |
1025 (hblank_end << HSYNCEND_SHIFT);
1026 *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1027
1028 *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1029 *vb = (vblank_start << VBLANKSTART_SHIFT) |
1030 (vblank_end << VSYNCEND_SHIFT);
1031 *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1032 *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1033 (vactive << SRC_SIZE_VERT_SHIFT);
1034
1035 /* Start address and stride. */
1036 if (dinfo->pitch)
1037 hw->disp_a_stride = dinfo->pitch;
1038 else
1039 hw->disp_a_stride = var->xres_virtual * var->bits_per_pixel / 8;
1040 DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1041
1042 hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1043 var->xoffset * var->bits_per_pixel / 8;
1044
1045 /* Check stride alignment. */
1046 if (hw->disp_a_stride % STRIDE_ALIGNMENT != 0) {
1047 WRN_MSG("display stride %d has bad alignment %d\n",
1048 hw->disp_a_stride, STRIDE_ALIGNMENT);
1049 return 1;
1050 }
1051
1052 /* Set the palette to 8-bit mode. */
1053 *pipe_conf &= ~PIPECONF_GAMMA;
1054 return 0;
1055 }
1056
1057 /* Program a (non-VGA) video mode. */
1058 int
intelfbhw_program_mode(struct intelfb_info * dinfo,const struct intelfb_hwstate * hw,int blank)1059 intelfbhw_program_mode(struct intelfb_info *dinfo,
1060 const struct intelfb_hwstate *hw, int blank)
1061 {
1062 int pipe = PIPE_A;
1063 u32 tmp;
1064 const u32 *dpll, *fp0, *fp1, *pipe_conf;
1065 const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1066 u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1067 u32 hsync_reg, htotal_reg, hblank_reg;
1068 u32 vsync_reg, vtotal_reg, vblank_reg;
1069 u32 src_size_reg;
1070
1071 /* Assume single pipe, display plane A, analog CRT. */
1072
1073 DBG_MSG("intelfbhw_program_mode\n");
1074
1075 /* Disable VGA */
1076 tmp = INREG(VGACNTRL);
1077 tmp |= VGA_DISABLE;
1078 OUTREG(VGACNTRL, tmp);
1079
1080 /* Check whether pipe A or pipe B is enabled. */
1081 if (hw->pipe_a_conf & PIPECONF_ENABLE)
1082 pipe = PIPE_A;
1083 else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1084 pipe = PIPE_B;
1085
1086 dinfo->pipe = pipe;
1087
1088 if (pipe == PIPE_B) {
1089 dpll = &hw->dpll_b;
1090 fp0 = &hw->fpb0;
1091 fp1 = &hw->fpb1;
1092 pipe_conf = &hw->pipe_b_conf;
1093 hs = &hw->hsync_b;
1094 hb = &hw->hblank_b;
1095 ht = &hw->htotal_b;
1096 vs = &hw->vsync_b;
1097 vb = &hw->vblank_b;
1098 vt = &hw->vtotal_b;
1099 ss = &hw->src_size_b;
1100 dpll_reg = DPLL_B;
1101 fp0_reg = FPB0;
1102 fp1_reg = FPB1;
1103 pipe_conf_reg = PIPEBCONF;
1104 hsync_reg = HSYNC_B;
1105 htotal_reg = HTOTAL_B;
1106 hblank_reg = HBLANK_B;
1107 vsync_reg = VSYNC_B;
1108 vtotal_reg = VTOTAL_B;
1109 vblank_reg = VBLANK_B;
1110 src_size_reg = SRC_SIZE_B;
1111 } else {
1112 dpll = &hw->dpll_a;
1113 fp0 = &hw->fpa0;
1114 fp1 = &hw->fpa1;
1115 pipe_conf = &hw->pipe_a_conf;
1116 hs = &hw->hsync_a;
1117 hb = &hw->hblank_a;
1118 ht = &hw->htotal_a;
1119 vs = &hw->vsync_a;
1120 vb = &hw->vblank_a;
1121 vt = &hw->vtotal_a;
1122 ss = &hw->src_size_a;
1123 dpll_reg = DPLL_A;
1124 fp0_reg = FPA0;
1125 fp1_reg = FPA1;
1126 pipe_conf_reg = PIPEACONF;
1127 hsync_reg = HSYNC_A;
1128 htotal_reg = HTOTAL_A;
1129 hblank_reg = HBLANK_A;
1130 vsync_reg = VSYNC_A;
1131 vtotal_reg = VTOTAL_A;
1132 vblank_reg = VBLANK_A;
1133 src_size_reg = SRC_SIZE_A;
1134 }
1135
1136 /* Disable planes A and B. */
1137 tmp = INREG(DSPACNTR);
1138 tmp &= ~DISPPLANE_PLANE_ENABLE;
1139 OUTREG(DSPACNTR, tmp);
1140 tmp = INREG(DSPBCNTR);
1141 tmp &= ~DISPPLANE_PLANE_ENABLE;
1142 OUTREG(DSPBCNTR, tmp);
1143
1144 /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1145 mdelay(20);
1146
1147 /* Disable Sync */
1148 tmp = INREG(ADPA);
1149 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1150 tmp |= ADPA_DPMS_D3;
1151 OUTREG(ADPA, tmp);
1152
1153 /* turn off pipe */
1154 tmp = INREG(pipe_conf_reg);
1155 tmp &= ~PIPECONF_ENABLE;
1156 OUTREG(pipe_conf_reg, tmp);
1157
1158 /* turn off PLL */
1159 tmp = INREG(dpll_reg);
1160 dpll_reg &= ~DPLL_VCO_ENABLE;
1161 OUTREG(dpll_reg, tmp);
1162
1163 /* Set PLL parameters */
1164 OUTREG(dpll_reg, *dpll & ~DPLL_VCO_ENABLE);
1165 OUTREG(fp0_reg, *fp0);
1166 OUTREG(fp1_reg, *fp1);
1167
1168 /* Set pipe parameters */
1169 OUTREG(hsync_reg, *hs);
1170 OUTREG(hblank_reg, *hb);
1171 OUTREG(htotal_reg, *ht);
1172 OUTREG(vsync_reg, *vs);
1173 OUTREG(vblank_reg, *vb);
1174 OUTREG(vtotal_reg, *vt);
1175 OUTREG(src_size_reg, *ss);
1176
1177 /* Set ADPA */
1178 OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1179
1180 /* Enable PLL */
1181 tmp = INREG(dpll_reg);
1182 tmp |= DPLL_VCO_ENABLE;
1183 OUTREG(dpll_reg, tmp);
1184
1185 /* Enable pipe */
1186 OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1187
1188 /* Enable sync */
1189 tmp = INREG(ADPA);
1190 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1191 tmp |= ADPA_DPMS_D0;
1192 OUTREG(ADPA, tmp);
1193
1194 /* setup display plane */
1195 OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1196 OUTREG(DSPASTRIDE, hw->disp_a_stride);
1197 OUTREG(DSPABASE, hw->disp_a_base);
1198
1199 /* Enable plane */
1200 if (!blank) {
1201 tmp = INREG(DSPACNTR);
1202 tmp |= DISPPLANE_PLANE_ENABLE;
1203 OUTREG(DSPACNTR, tmp);
1204 OUTREG(DSPABASE, hw->disp_a_base);
1205 }
1206
1207 return 0;
1208 }
1209
1210 static int
wait_ring(struct intelfb_info * dinfo,int n)1211 wait_ring(struct intelfb_info *dinfo, int n)
1212 {
1213 int i = 0;
1214 unsigned long end;
1215 u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1216
1217 #if 0
1218 DBG_MSG("wait_ring: %d\n", n);
1219 #endif
1220
1221 end = jiffies + (HZ * 3);
1222 while (dinfo->ring_space < n) {
1223 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1224 dinfo->ring_space = dinfo->ring_head -
1225 (dinfo->ring_tail + RING_MIN_FREE);
1226 if (dinfo->ring_space < 0)
1227 dinfo->ring_space += dinfo->ring_size;
1228 if (dinfo->ring_head != last_head) {
1229 end = jiffies + (HZ * 3);
1230 last_head = dinfo->ring_head;
1231 }
1232 i++;
1233 if (time_before(end, jiffies)) {
1234 WRN_MSG("space: %d wanted %d\n", dinfo->ring_space, n);
1235 WRN_MSG("lockup\n");
1236 break;
1237 }
1238 udelay(1);
1239 }
1240 return i;
1241 }
1242
1243 void
intelfbhw_do_sync(struct intelfb_info * dinfo)1244 intelfbhw_do_sync(struct intelfb_info *dinfo)
1245 {
1246 #if USE_SYNC_PAGE
1247 u32 newval;
1248 #endif
1249 u32 tmp;
1250 int i = 0;
1251
1252 #if VERBOSE > 0
1253 DBG_MSG("intelfbhw_do_sync\n");
1254 #endif
1255
1256 #if USE_SYNC_PAGE
1257 /*
1258 * Although doing MI_STORE_DWORD_IMM after the MI_FLUSH is supposed
1259 * to make sure everything is synchronised, there is still some
1260 * mis-ordering of operations when mixing 2D with direct CPU
1261 * writes to the framebuffer.
1262 */
1263 newval = readl(dinfo->syncpage_virt);
1264 newval++;
1265 #if VERBOSE > 0
1266 DBG_MSG("intelfbhw_do_sync: %d\n", newval);
1267 #endif
1268 START_RING(6);
1269 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE);
1270 OUT_RING(MI_NOOP);
1271 OUT_RING(MI_STORE_DWORD_IMM);
1272 OUT_RING(dinfo->syncpage_phys);
1273 OUT_RING(newval);
1274 OUT_RING(MI_NOOP);
1275 ADVANCE_RING();
1276 while ((tmp = readl(dinfo->syncpage_virt)) != newval && i < 10000) {
1277 i++;
1278 udelay(10);
1279 }
1280 if (tmp != newval) {
1281 DBG_MSG("intelfbhw_do_sync: STORE_DWORD_IMM returns %d "
1282 "instead of %d\n", tmp, newval);
1283 } else {
1284 #if VERBOSE > 1
1285 DBG_MSG("intelfbhw_do_sync: done in %d iterations\n", i);
1286 #endif
1287 }
1288 #else
1289 /*
1290 * Send a flush, then wait until the ring is empty. This is what
1291 * the XFree86 driver does, and actually it doesn't seem a lot worse
1292 * than the recommended method (both have problems).
1293 */
1294 START_RING(2);
1295 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE);
1296 OUT_RING(MI_NOOP);
1297 ADVANCE_RING();
1298 wait_ring(dinfo, dinfo->ring_size - RING_MIN_FREE);
1299 dinfo->ring_space = dinfo->ring_size - RING_MIN_FREE;
1300 #endif
1301 }
1302
1303 static void
refresh_ring(struct intelfb_info * dinfo)1304 refresh_ring(struct intelfb_info *dinfo)
1305 {
1306 DBG_MSG("refresh_ring\n");
1307
1308 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1309 dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1310 dinfo->ring_space = dinfo->ring_head -
1311 (dinfo->ring_tail + RING_MIN_FREE);
1312 if (dinfo->ring_space < 0)
1313 dinfo->ring_space += dinfo->ring_size;
1314 }
1315
1316 static void
reset_state(struct intelfb_info * dinfo)1317 reset_state(struct intelfb_info *dinfo)
1318 {
1319 int i;
1320 u32 tmp;
1321
1322 DBG_MSG("reset_state\n");
1323
1324 for (i = 0; i < FENCE_NUM; i++)
1325 OUTREG(FENCE + (i << 2), 0);
1326
1327 /* Flush the ring buffer if it's enabled. */
1328 tmp = INREG(PRI_RING_LENGTH);
1329 if (tmp & RING_ENABLE) {
1330 DBG_MSG("reset_state: ring was enabled\n");
1331 refresh_ring(dinfo);
1332 intelfbhw_do_sync(dinfo);
1333 DO_RING_IDLE();
1334 }
1335
1336 OUTREG(PRI_RING_LENGTH, 0);
1337 OUTREG(PRI_RING_HEAD, 0);
1338 OUTREG(PRI_RING_TAIL, 0);
1339 OUTREG(PRI_RING_START, 0);
1340 }
1341
1342 /* Stop the 2D engine, and turn off the ring buffer. */
1343 void
intelfbhw_2d_stop(struct intelfb_info * dinfo)1344 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1345 {
1346 DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1347 dinfo->ring_active);
1348
1349 if (!dinfo->accel)
1350 return;
1351
1352 dinfo->ring_active = 0;
1353 reset_state(dinfo);
1354 }
1355
1356 /*
1357 * Enable the ring buffer, and initialise the 2D engine.
1358 * It is assumed that the graphics engine has been stopped by previously
1359 * calling intelfb_2d_stop().
1360 */
1361 void
intelfbhw_2d_start(struct intelfb_info * dinfo)1362 intelfbhw_2d_start(struct intelfb_info *dinfo)
1363 {
1364 DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1365 dinfo->accel, dinfo->ring_active);
1366
1367 if (!dinfo->accel)
1368 return;
1369
1370 /* Initialise the primary ring buffer. */
1371 OUTREG(PRI_RING_LENGTH, 0);
1372 OUTREG(PRI_RING_TAIL, 0);
1373 OUTREG(PRI_RING_HEAD, 0);
1374
1375 OUTREG(PRI_RING_START, dinfo->ring_base_phys & RING_START_MASK);
1376 OUTREG(PRI_RING_LENGTH,
1377 ((dinfo->ring_size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1378 RING_NO_REPORT | RING_ENABLE);
1379 refresh_ring(dinfo);
1380 dinfo->ring_active = 1;
1381
1382 DBG_MSG("INSTPM was 0x%08x, setting to 0x%08x\n", INREG(INSTPM),
1383 0x1f << 16);
1384 OUTREG(INSTPM, 0x1f << 16);
1385 OUTREG(INSTPM, 0x1f << 16);
1386 }
1387
1388 /* 2D fillrect (solid fill or invert) */
1389 void
intelfbhw_do_fillrect(struct intelfb_info * dinfo,u32 x,u32 y,u32 w,u32 h,u32 color,u32 pitch,u32 bpp,u32 rop)1390 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1391 u32 color, u32 pitch, u32 bpp, u32 rop)
1392 {
1393 u32 br00, br09, br13, br14, br16;
1394
1395 #if VERBOSE > 1
1396 DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1397 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1398 #endif
1399
1400 br00 = COLOR_BLT_CMD;
1401 br09 = dinfo->fb_offset + (y * pitch + x * (bpp / 8));
1402 br13 = (rop << ROP_SHIFT) | pitch;
1403 br14 = (h << HEIGHT_SHIFT) | ((w * bpp / 8) << WIDTH_SHIFT);
1404 br16 = color;
1405
1406 switch (bpp) {
1407 case 8:
1408 br13 |= COLOR_DEPTH_8;
1409 break;
1410 case 16:
1411 br13 |= COLOR_DEPTH_16;
1412 break;
1413 case 32:
1414 br13 |= COLOR_DEPTH_32;
1415 br00 |= WRITE_ALPHA | WRITE_RGB;
1416 break;
1417 }
1418
1419 START_RING(6);
1420 OUT_RING(br00);
1421 OUT_RING(br13);
1422 OUT_RING(br14);
1423 OUT_RING(br09);
1424 OUT_RING(br16);
1425 OUT_RING(MI_NOOP);
1426 ADVANCE_RING();
1427 }
1428
1429 void
intelfbhw_do_bitblt(struct intelfb_info * dinfo,u32 curx,u32 cury,u32 dstx,u32 dsty,u32 w,u32 h,u32 pitch,u32 bpp)1430 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1431 u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1432 {
1433 u32 br00, br09, br11, br12, br13, br22, br23, br26;
1434
1435 #if VERBOSE > 0
1436 DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1437 curx, cury, dstx, dsty, w, h, pitch, bpp);
1438 #endif
1439
1440 br00 = XY_SRC_COPY_BLT_CMD;
1441 br09 = dinfo->fb_offset;
1442 br11 = (pitch << PITCH_SHIFT);
1443 br12 = dinfo->fb_offset;
1444 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1445 br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1446 br23 = ((dstx + w) << WIDTH_SHIFT) |
1447 ((dsty + h) << HEIGHT_SHIFT);
1448 br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1449
1450 switch (bpp) {
1451 case 8:
1452 br13 |= COLOR_DEPTH_8;
1453 break;
1454 case 16:
1455 br13 |= COLOR_DEPTH_16;
1456 break;
1457 case 32:
1458 br13 |= COLOR_DEPTH_32;
1459 br00 |= WRITE_ALPHA | WRITE_RGB;
1460 break;
1461 }
1462
1463 START_RING(8);
1464 OUT_RING(br00);
1465 OUT_RING(br13);
1466 OUT_RING(br22);
1467 OUT_RING(br23);
1468 OUT_RING(br09);
1469 OUT_RING(br26);
1470 OUT_RING(br11);
1471 OUT_RING(br12);
1472 ADVANCE_RING();
1473 }
1474
1475 int
intelfbhw_do_drawglyph(struct intelfb_info * dinfo,u32 fg,u32 bg,u32 w,u32 h,u8 * cdat,u32 x,u32 y,u32 pitch,u32 bpp)1476 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w, u32 h,
1477 u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1478 {
1479 int i, n = 0, fw_bytes, bytes_per_src_line;
1480 int nbytes, ndwords, pad, tmp;
1481 u16 *wcdat;
1482 u32 *dwcdat;
1483 u32 br00, br09, br13, br18, br19, br22, br23;
1484
1485 #if 0
1486 DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1487 #endif
1488
1489 /* Support fonts up to 32 pixels wide. */
1490 if (w > 32)
1491 return 0;
1492
1493 /* Number of bytes required for each cdat scanline. */
1494 fw_bytes = ROUND_UP_TO(w, 8) / 8;
1495
1496 /* Src scanlines are word (16-bit) padded. */
1497 bytes_per_src_line = ROUND_UP_TO(fw_bytes, 2);
1498
1499 /* Total bytes of padded scanline data to write out. */
1500 nbytes = h * bytes_per_src_line;
1501
1502 /*
1503 * Check if the glyph data exceeds the immediate mode limit.
1504 * It would take a large font (1K pixels) to hit this limit.
1505 */
1506 if (nbytes > MAX_MONO_IMM_SIZE)
1507 return 0;
1508
1509 /* Src data is packaged a dword (32-bit) at a time. */
1510 ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1511
1512 /* Ring has to be padded to a quad word. */
1513 pad = ndwords % 2;
1514
1515 /* For easy reference of the glyph data in different sized chunks. */
1516 wcdat = (u16 *)cdat;
1517 dwcdat = (u32 *)cdat;
1518
1519 tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1520 br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1521 br09 = dinfo->fb_offset;
1522 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1523 br18 = bg;
1524 br19 = fg;
1525 br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1526 br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1527
1528 switch (bpp) {
1529 case 8:
1530 br13 |= COLOR_DEPTH_8;
1531 break;
1532 case 16:
1533 br13 |= COLOR_DEPTH_16;
1534 break;
1535 case 32:
1536 br13 |= COLOR_DEPTH_32;
1537 br00 |= WRITE_ALPHA | WRITE_RGB;
1538 break;
1539 }
1540
1541 #if 0
1542 DBG_MSG("ndwords + pad is %d, pad is %d\n", ndwords + pad, pad);
1543 #endif
1544 START_RING(ndwords + pad);
1545 OUT_RING(br00);
1546 OUT_RING(br13);
1547 OUT_RING(br22);
1548 OUT_RING(br23);
1549 OUT_RING(br09);
1550 OUT_RING(br18);
1551 OUT_RING(br19);
1552 i = h;
1553 switch (fw_bytes) {
1554 case 1:
1555 while (i >= 2) {
1556 OUT_RING(cdat[0] | cdat[1] << 16);
1557 cdat +=2;
1558 i -= 2;
1559 n++;
1560 }
1561 if (i) {
1562 OUT_RING(cdat[0]);
1563 n++;
1564 }
1565 break;
1566 case 2:
1567 while (i >= 2) {
1568 OUT_RING(wcdat[0] | wcdat[1] << 16);
1569 wcdat += 2;
1570 i -= 2;
1571 n++;
1572 }
1573 if (i) {
1574 OUT_RING(wcdat[0]);
1575 n++;
1576 }
1577 break;
1578 case 3:
1579 while (i) {
1580 OUT_RING(wcdat[0] | cdat[3] << 16);
1581 wcdat += 2;
1582 cdat += 4;
1583 i--;
1584 n++;
1585 }
1586 break;
1587 case 4:
1588 while(i) {
1589 OUT_RING(dwcdat[0]);
1590 i--;
1591 n++;
1592 }
1593 }
1594 if (pad) {
1595 OUT_RING(MI_NOOP);
1596 n++;
1597 }
1598 #if 0
1599 DBG_MSG("%d immediate bytes + pad\n", n);
1600 #endif
1601 ADVANCE_RING();
1602 return 1;
1603 }
1604
1605 /* HW cursor functions. */
1606 void
intelfbhw_cursor_init(struct intelfb_info * dinfo)1607 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1608 {
1609 u32 tmp;
1610
1611 DBG_MSG("intelfbhw_cursor_init\n");
1612
1613 if (!dinfo->cursor_base)
1614 return;
1615
1616 if (dinfo->mobile) {
1617 if (!dinfo->cursor_base_real)
1618 return;
1619 tmp = INREG(CURSOR_A_CONTROL);
1620 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1621 CURSOR_MEM_TYPE_LOCAL |
1622 (1 << CURSOR_PIPE_SELECT_SHIFT));
1623 tmp |= CURSOR_MODE_DISABLE;
1624 OUTREG(CURSOR_A_CONTROL, tmp);
1625 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor_base_real);
1626 } else {
1627 #if 0
1628 tmp = INREG(CURSOR_CONTROL);
1629 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1630 CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1631 #endif
1632 tmp = CURSOR_FORMAT_3C;
1633 OUTREG(CURSOR_CONTROL, tmp);
1634 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor_offset);
1635 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1636 (64 << CURSOR_SIZE_V_SHIFT);
1637 OUTREG(CURSOR_SIZE, tmp);
1638 }
1639 }
1640
1641 void
intelfbhw_cursor_hide(struct intelfb_info * dinfo)1642 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1643 {
1644 u32 tmp;
1645
1646 #if VERBOSE > 1
1647 DBG_MSG("intelfbhw_cursor_hide\n");
1648 #endif
1649
1650 if (!dinfo->cursor_base)
1651 return;
1652
1653 dinfo->cursor.enabled = 0;
1654 dinfo->cursor.on = 0;
1655 if (dinfo->mobile) {
1656 if (!dinfo->cursor_base_real)
1657 return;
1658 tmp = INREG(CURSOR_A_CONTROL);
1659 tmp &= ~CURSOR_MODE_MASK;
1660 tmp |= CURSOR_MODE_DISABLE;
1661 OUTREG(CURSOR_A_CONTROL, tmp);
1662 /* Flush changes */
1663 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor_base_real);
1664 } else {
1665 tmp = INREG(CURSOR_CONTROL);
1666 tmp &= ~CURSOR_ENABLE;
1667 OUTREG(CURSOR_CONTROL, tmp);
1668 }
1669 }
1670
1671 void
intelfbhw_cursor_show(struct intelfb_info * dinfo)1672 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1673 {
1674 u32 tmp;
1675
1676 #if VERBOSE > 1
1677 DBG_MSG("intelfbhw_cursor_show\n");
1678 #endif
1679
1680 if (!dinfo->cursor_base)
1681 return;
1682
1683 dinfo->cursor.on = 1;
1684 dinfo->cursor.enabled = 1;
1685
1686 if (dinfo->cursor.blanked)
1687 return;
1688
1689 if (dinfo->mobile) {
1690 if (!dinfo->cursor_base_real)
1691 return;
1692 tmp = INREG(CURSOR_A_CONTROL);
1693 tmp &= ~CURSOR_MODE_MASK;
1694 tmp |= CURSOR_MODE_64_4C_AX;
1695 OUTREG(CURSOR_A_CONTROL, tmp);
1696 /* Flush changes */
1697 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor_base_real);
1698 } else {
1699 tmp = INREG(CURSOR_CONTROL);
1700 tmp |= CURSOR_ENABLE;
1701 OUTREG(CURSOR_CONTROL, tmp);
1702 }
1703 }
1704
1705 void
intelfbhw_cursor_setpos(struct intelfb_info * dinfo,int x,int y)1706 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1707 {
1708 u32 tmp;
1709
1710 #if VERBOSE > 1
1711 DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1712 #endif
1713
1714 /*
1715 * Sets the position. The coordinates are assumed to already
1716 * have any offset adjusted. Assume that the cursor is never
1717 * completely off-screen, and that x, y are always >= 0.
1718 */
1719
1720 if (!dinfo->cursor_base)
1721 return;
1722
1723 tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1724 ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1725 OUTREG(CURSOR_A_POSITION, tmp);
1726 }
1727
1728 void
intelfbhw_cursor_setcolor(struct intelfb_info * dinfo,u32 bg,u32 fg)1729 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1730 {
1731 #if VERBOSE > 1
1732 DBG_MSG("intelfbhw_cursor_setcolor\n");
1733 #endif
1734
1735 if (!dinfo->cursor_base)
1736 return;
1737
1738 OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1739 OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1740 OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1741 OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1742 }
1743
1744 void
intelfbhw_cursor_load(struct intelfb_info * dinfo,struct display * disp)1745 intelfbhw_cursor_load(struct intelfb_info *dinfo, struct display *disp)
1746 {
1747 u32 xline, mline;
1748 int i;
1749
1750 DBG_MSG("intelfbhw_cursor_load\n");
1751
1752 if (!dinfo->cursor_base)
1753 return;
1754
1755 intelfb_create_cursor_shape(dinfo, disp);
1756 xline = (1 << dinfo->cursor.w) - 1;
1757 mline = ~xline;
1758 for (i = 0; i < dinfo->cursor.u; i++) {
1759 writel(~0, dinfo->cursor_base + i * 16);
1760 writel(~0, dinfo->cursor_base + i * 16 + 4);
1761 writel(0, dinfo->cursor_base + i * 16 + 8);
1762 writel(0, dinfo->cursor_base + i * 16 + 12);
1763 }
1764 for (; i < dinfo->cursor.d; i++) {
1765 writel(mline, dinfo->cursor_base + i * 16);
1766 writel(~0, dinfo->cursor_base + i * 16 + 4);
1767 writel(xline, dinfo->cursor_base + i * 16 + 8);
1768 writel(0, dinfo->cursor_base + i * 16 + 12);
1769 }
1770 for (; i < 64; i++) {
1771 writel(~0, dinfo->cursor_base + i * 16);
1772 writel(~0, dinfo->cursor_base + i * 16 + 4);
1773 writel(0, dinfo->cursor_base + i * 16 + 8);
1774 writel(0, dinfo->cursor_base + i * 16 + 12);
1775 }
1776 }
1777
1778
1779