1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drv.h"
33 #include "i915_drm.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
ring_space(struct intel_ring_buffer * ring)37 static inline int ring_space(struct intel_ring_buffer *ring)
38 {
39 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
40 if (space < 0)
41 space += ring->size;
42 return space;
43 }
44
i915_gem_get_seqno(struct drm_device * dev)45 static u32 i915_gem_get_seqno(struct drm_device *dev)
46 {
47 drm_i915_private_t *dev_priv = dev->dev_private;
48 u32 seqno;
49
50 seqno = dev_priv->next_seqno;
51
52 /* reserve 0 for non-seqno */
53 if (++dev_priv->next_seqno == 0)
54 dev_priv->next_seqno = 1;
55
56 return seqno;
57 }
58
59 static int
render_ring_flush(struct intel_ring_buffer * ring,u32 invalidate_domains,u32 flush_domains)60 render_ring_flush(struct intel_ring_buffer *ring,
61 u32 invalidate_domains,
62 u32 flush_domains)
63 {
64 struct drm_device *dev = ring->dev;
65 u32 cmd;
66 int ret;
67
68 /*
69 * read/write caches:
70 *
71 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
72 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
73 * also flushed at 2d versus 3d pipeline switches.
74 *
75 * read-only caches:
76 *
77 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
78 * MI_READ_FLUSH is set, and is always flushed on 965.
79 *
80 * I915_GEM_DOMAIN_COMMAND may not exist?
81 *
82 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
83 * invalidated when MI_EXE_FLUSH is set.
84 *
85 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
86 * invalidated with every MI_FLUSH.
87 *
88 * TLBs:
89 *
90 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
91 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
92 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
93 * are flushed at any MI_FLUSH.
94 */
95
96 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
97 if ((invalidate_domains|flush_domains) &
98 I915_GEM_DOMAIN_RENDER)
99 cmd &= ~MI_NO_WRITE_FLUSH;
100 if (INTEL_INFO(dev)->gen < 4) {
101 /*
102 * On the 965, the sampler cache always gets flushed
103 * and this bit is reserved.
104 */
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
107 }
108 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
109 cmd |= MI_EXE_FLUSH;
110
111 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
112 (IS_G4X(dev) || IS_GEN5(dev)))
113 cmd |= MI_INVALIDATE_ISP;
114
115 ret = intel_ring_begin(ring, 2);
116 if (ret)
117 return ret;
118
119 intel_ring_emit(ring, cmd);
120 intel_ring_emit(ring, MI_NOOP);
121 intel_ring_advance(ring);
122
123 return 0;
124 }
125
ring_write_tail(struct intel_ring_buffer * ring,u32 value)126 static void ring_write_tail(struct intel_ring_buffer *ring,
127 u32 value)
128 {
129 drm_i915_private_t *dev_priv = ring->dev->dev_private;
130 I915_WRITE_TAIL(ring, value);
131 }
132
intel_ring_get_active_head(struct intel_ring_buffer * ring)133 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
134 {
135 drm_i915_private_t *dev_priv = ring->dev->dev_private;
136 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
137 RING_ACTHD(ring->mmio_base) : ACTHD;
138
139 return I915_READ(acthd_reg);
140 }
141
init_ring_common(struct intel_ring_buffer * ring)142 static int init_ring_common(struct intel_ring_buffer *ring)
143 {
144 drm_i915_private_t *dev_priv = ring->dev->dev_private;
145 struct drm_i915_gem_object *obj = ring->obj;
146 u32 head;
147
148 /* Stop the ring if it's running. */
149 I915_WRITE_CTL(ring, 0);
150 I915_WRITE_HEAD(ring, 0);
151 ring->write_tail(ring, 0);
152
153 /* Initialize the ring. */
154 I915_WRITE_START(ring, obj->gtt_offset);
155 head = I915_READ_HEAD(ring) & HEAD_ADDR;
156
157 /* G45 ring initialization fails to reset head to zero */
158 if (head != 0) {
159 DRM_DEBUG_KMS("%s head not reset to zero "
160 "ctl %08x head %08x tail %08x start %08x\n",
161 ring->name,
162 I915_READ_CTL(ring),
163 I915_READ_HEAD(ring),
164 I915_READ_TAIL(ring),
165 I915_READ_START(ring));
166
167 I915_WRITE_HEAD(ring, 0);
168
169 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
170 DRM_ERROR("failed to set %s head to zero "
171 "ctl %08x head %08x tail %08x start %08x\n",
172 ring->name,
173 I915_READ_CTL(ring),
174 I915_READ_HEAD(ring),
175 I915_READ_TAIL(ring),
176 I915_READ_START(ring));
177 }
178 }
179
180 I915_WRITE_CTL(ring,
181 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
182 | RING_REPORT_64K | RING_VALID);
183
184 /* If the head is still not zero, the ring is dead */
185 if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
186 I915_READ_START(ring) != obj->gtt_offset ||
187 (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
188 DRM_ERROR("%s initialization failed "
189 "ctl %08x head %08x tail %08x start %08x\n",
190 ring->name,
191 I915_READ_CTL(ring),
192 I915_READ_HEAD(ring),
193 I915_READ_TAIL(ring),
194 I915_READ_START(ring));
195 return -EIO;
196 }
197
198 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
199 i915_kernel_lost_context(ring->dev);
200 else {
201 ring->head = I915_READ_HEAD(ring);
202 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
203 ring->space = ring_space(ring);
204 }
205
206 return 0;
207 }
208
209 /*
210 * 965+ support PIPE_CONTROL commands, which provide finer grained control
211 * over cache flushing.
212 */
213 struct pipe_control {
214 struct drm_i915_gem_object *obj;
215 volatile u32 *cpu_page;
216 u32 gtt_offset;
217 };
218
219 static int
init_pipe_control(struct intel_ring_buffer * ring)220 init_pipe_control(struct intel_ring_buffer *ring)
221 {
222 struct pipe_control *pc;
223 struct drm_i915_gem_object *obj;
224 int ret;
225
226 if (ring->private)
227 return 0;
228
229 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
230 if (!pc)
231 return -ENOMEM;
232
233 obj = i915_gem_alloc_object(ring->dev, 4096);
234 if (obj == NULL) {
235 DRM_ERROR("Failed to allocate seqno page\n");
236 ret = -ENOMEM;
237 goto err;
238 }
239 obj->agp_type = AGP_USER_CACHED_MEMORY;
240
241 ret = i915_gem_object_pin(obj, 4096, true);
242 if (ret)
243 goto err_unref;
244
245 pc->gtt_offset = obj->gtt_offset;
246 pc->cpu_page = kmap(obj->pages[0]);
247 if (pc->cpu_page == NULL)
248 goto err_unpin;
249
250 pc->obj = obj;
251 ring->private = pc;
252 return 0;
253
254 err_unpin:
255 i915_gem_object_unpin(obj);
256 err_unref:
257 drm_gem_object_unreference(&obj->base);
258 err:
259 kfree(pc);
260 return ret;
261 }
262
263 static void
cleanup_pipe_control(struct intel_ring_buffer * ring)264 cleanup_pipe_control(struct intel_ring_buffer *ring)
265 {
266 struct pipe_control *pc = ring->private;
267 struct drm_i915_gem_object *obj;
268
269 if (!ring->private)
270 return;
271
272 obj = pc->obj;
273 kunmap(obj->pages[0]);
274 i915_gem_object_unpin(obj);
275 drm_gem_object_unreference(&obj->base);
276
277 kfree(pc);
278 ring->private = NULL;
279 }
280
init_render_ring(struct intel_ring_buffer * ring)281 static int init_render_ring(struct intel_ring_buffer *ring)
282 {
283 struct drm_device *dev = ring->dev;
284 struct drm_i915_private *dev_priv = dev->dev_private;
285 int ret = init_ring_common(ring);
286
287 if (INTEL_INFO(dev)->gen > 3) {
288 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
289 if (IS_GEN6(dev))
290 mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
291 I915_WRITE(MI_MODE, mode);
292 }
293
294 if (INTEL_INFO(dev)->gen >= 6) {
295 } else if (IS_GEN5(dev)) {
296 ret = init_pipe_control(ring);
297 if (ret)
298 return ret;
299 }
300
301 return ret;
302 }
303
render_ring_cleanup(struct intel_ring_buffer * ring)304 static void render_ring_cleanup(struct intel_ring_buffer *ring)
305 {
306 if (!ring->private)
307 return;
308
309 cleanup_pipe_control(ring);
310 }
311
312 static void
update_semaphore(struct intel_ring_buffer * ring,int i,u32 seqno)313 update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno)
314 {
315 struct drm_device *dev = ring->dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
317 int id;
318
319 /*
320 * cs -> 1 = vcs, 0 = bcs
321 * vcs -> 1 = bcs, 0 = cs,
322 * bcs -> 1 = cs, 0 = vcs.
323 */
324 id = ring - dev_priv->ring;
325 id += 2 - i;
326 id %= 3;
327
328 intel_ring_emit(ring,
329 MI_SEMAPHORE_MBOX |
330 MI_SEMAPHORE_REGISTER |
331 MI_SEMAPHORE_UPDATE);
332 intel_ring_emit(ring, seqno);
333 intel_ring_emit(ring,
334 RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i);
335 }
336
337 static int
gen6_add_request(struct intel_ring_buffer * ring,u32 * result)338 gen6_add_request(struct intel_ring_buffer *ring,
339 u32 *result)
340 {
341 u32 seqno;
342 int ret;
343
344 ret = intel_ring_begin(ring, 10);
345 if (ret)
346 return ret;
347
348 seqno = i915_gem_get_seqno(ring->dev);
349 update_semaphore(ring, 0, seqno);
350 update_semaphore(ring, 1, seqno);
351
352 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
353 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
354 intel_ring_emit(ring, seqno);
355 intel_ring_emit(ring, MI_USER_INTERRUPT);
356 intel_ring_advance(ring);
357
358 *result = seqno;
359 return 0;
360 }
361
362 int
intel_ring_sync(struct intel_ring_buffer * ring,struct intel_ring_buffer * to,u32 seqno)363 intel_ring_sync(struct intel_ring_buffer *ring,
364 struct intel_ring_buffer *to,
365 u32 seqno)
366 {
367 int ret;
368
369 ret = intel_ring_begin(ring, 4);
370 if (ret)
371 return ret;
372
373 intel_ring_emit(ring,
374 MI_SEMAPHORE_MBOX |
375 MI_SEMAPHORE_REGISTER |
376 intel_ring_sync_index(ring, to) << 17 |
377 MI_SEMAPHORE_COMPARE);
378 intel_ring_emit(ring, seqno);
379 intel_ring_emit(ring, 0);
380 intel_ring_emit(ring, MI_NOOP);
381 intel_ring_advance(ring);
382
383 return 0;
384 }
385
386 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
387 do { \
388 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
389 PIPE_CONTROL_DEPTH_STALL | 2); \
390 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
391 intel_ring_emit(ring__, 0); \
392 intel_ring_emit(ring__, 0); \
393 } while (0)
394
395 static int
pc_render_add_request(struct intel_ring_buffer * ring,u32 * result)396 pc_render_add_request(struct intel_ring_buffer *ring,
397 u32 *result)
398 {
399 struct drm_device *dev = ring->dev;
400 u32 seqno = i915_gem_get_seqno(dev);
401 struct pipe_control *pc = ring->private;
402 u32 scratch_addr = pc->gtt_offset + 128;
403 int ret;
404
405 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
406 * incoherent with writes to memory, i.e. completely fubar,
407 * so we need to use PIPE_NOTIFY instead.
408 *
409 * However, we also need to workaround the qword write
410 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
411 * memory before requesting an interrupt.
412 */
413 ret = intel_ring_begin(ring, 32);
414 if (ret)
415 return ret;
416
417 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
418 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
419 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
420 intel_ring_emit(ring, seqno);
421 intel_ring_emit(ring, 0);
422 PIPE_CONTROL_FLUSH(ring, scratch_addr);
423 scratch_addr += 128; /* write to separate cachelines */
424 PIPE_CONTROL_FLUSH(ring, scratch_addr);
425 scratch_addr += 128;
426 PIPE_CONTROL_FLUSH(ring, scratch_addr);
427 scratch_addr += 128;
428 PIPE_CONTROL_FLUSH(ring, scratch_addr);
429 scratch_addr += 128;
430 PIPE_CONTROL_FLUSH(ring, scratch_addr);
431 scratch_addr += 128;
432 PIPE_CONTROL_FLUSH(ring, scratch_addr);
433 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
434 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
435 PIPE_CONTROL_NOTIFY);
436 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
437 intel_ring_emit(ring, seqno);
438 intel_ring_emit(ring, 0);
439 intel_ring_advance(ring);
440
441 *result = seqno;
442 return 0;
443 }
444
445 static int
render_ring_add_request(struct intel_ring_buffer * ring,u32 * result)446 render_ring_add_request(struct intel_ring_buffer *ring,
447 u32 *result)
448 {
449 struct drm_device *dev = ring->dev;
450 u32 seqno = i915_gem_get_seqno(dev);
451 int ret;
452
453 ret = intel_ring_begin(ring, 4);
454 if (ret)
455 return ret;
456
457 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
458 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
459 intel_ring_emit(ring, seqno);
460 intel_ring_emit(ring, MI_USER_INTERRUPT);
461 intel_ring_advance(ring);
462
463 *result = seqno;
464 return 0;
465 }
466
467 static u32
ring_get_seqno(struct intel_ring_buffer * ring)468 ring_get_seqno(struct intel_ring_buffer *ring)
469 {
470 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
471 }
472
473 static u32
pc_render_get_seqno(struct intel_ring_buffer * ring)474 pc_render_get_seqno(struct intel_ring_buffer *ring)
475 {
476 struct pipe_control *pc = ring->private;
477 return pc->cpu_page[0];
478 }
479
480 static void
ironlake_enable_irq(drm_i915_private_t * dev_priv,u32 mask)481 ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
482 {
483 dev_priv->gt_irq_mask &= ~mask;
484 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
485 POSTING_READ(GTIMR);
486 }
487
488 static void
ironlake_disable_irq(drm_i915_private_t * dev_priv,u32 mask)489 ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
490 {
491 dev_priv->gt_irq_mask |= mask;
492 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
493 POSTING_READ(GTIMR);
494 }
495
496 static void
i915_enable_irq(drm_i915_private_t * dev_priv,u32 mask)497 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
498 {
499 dev_priv->irq_mask &= ~mask;
500 I915_WRITE(IMR, dev_priv->irq_mask);
501 POSTING_READ(IMR);
502 }
503
504 static void
i915_disable_irq(drm_i915_private_t * dev_priv,u32 mask)505 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
506 {
507 dev_priv->irq_mask |= mask;
508 I915_WRITE(IMR, dev_priv->irq_mask);
509 POSTING_READ(IMR);
510 }
511
512 static bool
render_ring_get_irq(struct intel_ring_buffer * ring)513 render_ring_get_irq(struct intel_ring_buffer *ring)
514 {
515 struct drm_device *dev = ring->dev;
516 drm_i915_private_t *dev_priv = dev->dev_private;
517
518 if (!dev->irq_enabled)
519 return false;
520
521 spin_lock(&ring->irq_lock);
522 if (ring->irq_refcount++ == 0) {
523 if (HAS_PCH_SPLIT(dev))
524 ironlake_enable_irq(dev_priv,
525 GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
526 else
527 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
528 }
529 spin_unlock(&ring->irq_lock);
530
531 return true;
532 }
533
534 static void
render_ring_put_irq(struct intel_ring_buffer * ring)535 render_ring_put_irq(struct intel_ring_buffer *ring)
536 {
537 struct drm_device *dev = ring->dev;
538 drm_i915_private_t *dev_priv = dev->dev_private;
539
540 spin_lock(&ring->irq_lock);
541 if (--ring->irq_refcount == 0) {
542 if (HAS_PCH_SPLIT(dev))
543 ironlake_disable_irq(dev_priv,
544 GT_USER_INTERRUPT |
545 GT_PIPE_NOTIFY);
546 else
547 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
548 }
549 spin_unlock(&ring->irq_lock);
550 }
551
intel_ring_setup_status_page(struct intel_ring_buffer * ring)552 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
553 {
554 drm_i915_private_t *dev_priv = ring->dev->dev_private;
555 u32 mmio = IS_GEN6(ring->dev) ?
556 RING_HWS_PGA_GEN6(ring->mmio_base) :
557 RING_HWS_PGA(ring->mmio_base);
558 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
559 POSTING_READ(mmio);
560 }
561
562 static int
bsd_ring_flush(struct intel_ring_buffer * ring,u32 invalidate_domains,u32 flush_domains)563 bsd_ring_flush(struct intel_ring_buffer *ring,
564 u32 invalidate_domains,
565 u32 flush_domains)
566 {
567 int ret;
568
569 ret = intel_ring_begin(ring, 2);
570 if (ret)
571 return ret;
572
573 intel_ring_emit(ring, MI_FLUSH);
574 intel_ring_emit(ring, MI_NOOP);
575 intel_ring_advance(ring);
576 return 0;
577 }
578
579 static int
ring_add_request(struct intel_ring_buffer * ring,u32 * result)580 ring_add_request(struct intel_ring_buffer *ring,
581 u32 *result)
582 {
583 u32 seqno;
584 int ret;
585
586 ret = intel_ring_begin(ring, 4);
587 if (ret)
588 return ret;
589
590 seqno = i915_gem_get_seqno(ring->dev);
591
592 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
593 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
594 intel_ring_emit(ring, seqno);
595 intel_ring_emit(ring, MI_USER_INTERRUPT);
596 intel_ring_advance(ring);
597
598 *result = seqno;
599 return 0;
600 }
601
602 static bool
ring_get_irq(struct intel_ring_buffer * ring,u32 flag)603 ring_get_irq(struct intel_ring_buffer *ring, u32 flag)
604 {
605 struct drm_device *dev = ring->dev;
606 drm_i915_private_t *dev_priv = dev->dev_private;
607
608 if (!dev->irq_enabled)
609 return false;
610
611 spin_lock(&ring->irq_lock);
612 if (ring->irq_refcount++ == 0)
613 ironlake_enable_irq(dev_priv, flag);
614 spin_unlock(&ring->irq_lock);
615
616 return true;
617 }
618
619 static void
ring_put_irq(struct intel_ring_buffer * ring,u32 flag)620 ring_put_irq(struct intel_ring_buffer *ring, u32 flag)
621 {
622 struct drm_device *dev = ring->dev;
623 drm_i915_private_t *dev_priv = dev->dev_private;
624
625 spin_lock(&ring->irq_lock);
626 if (--ring->irq_refcount == 0)
627 ironlake_disable_irq(dev_priv, flag);
628 spin_unlock(&ring->irq_lock);
629 }
630
631 static bool
gen6_ring_get_irq(struct intel_ring_buffer * ring,u32 gflag,u32 rflag)632 gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
633 {
634 struct drm_device *dev = ring->dev;
635 drm_i915_private_t *dev_priv = dev->dev_private;
636
637 if (!dev->irq_enabled)
638 return false;
639
640 spin_lock(&ring->irq_lock);
641 if (ring->irq_refcount++ == 0) {
642 ring->irq_mask &= ~rflag;
643 I915_WRITE_IMR(ring, ring->irq_mask);
644 ironlake_enable_irq(dev_priv, gflag);
645 }
646 spin_unlock(&ring->irq_lock);
647
648 return true;
649 }
650
651 static void
gen6_ring_put_irq(struct intel_ring_buffer * ring,u32 gflag,u32 rflag)652 gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
653 {
654 struct drm_device *dev = ring->dev;
655 drm_i915_private_t *dev_priv = dev->dev_private;
656
657 spin_lock(&ring->irq_lock);
658 if (--ring->irq_refcount == 0) {
659 ring->irq_mask |= rflag;
660 I915_WRITE_IMR(ring, ring->irq_mask);
661 ironlake_disable_irq(dev_priv, gflag);
662 }
663 spin_unlock(&ring->irq_lock);
664 }
665
666 static bool
bsd_ring_get_irq(struct intel_ring_buffer * ring)667 bsd_ring_get_irq(struct intel_ring_buffer *ring)
668 {
669 return ring_get_irq(ring, GT_BSD_USER_INTERRUPT);
670 }
671 static void
bsd_ring_put_irq(struct intel_ring_buffer * ring)672 bsd_ring_put_irq(struct intel_ring_buffer *ring)
673 {
674 ring_put_irq(ring, GT_BSD_USER_INTERRUPT);
675 }
676
677 static int
ring_dispatch_execbuffer(struct intel_ring_buffer * ring,u32 offset,u32 length)678 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
679 {
680 int ret;
681
682 ret = intel_ring_begin(ring, 2);
683 if (ret)
684 return ret;
685
686 intel_ring_emit(ring,
687 MI_BATCH_BUFFER_START | (2 << 6) |
688 MI_BATCH_NON_SECURE_I965);
689 intel_ring_emit(ring, offset);
690 intel_ring_advance(ring);
691
692 return 0;
693 }
694
695 static int
render_ring_dispatch_execbuffer(struct intel_ring_buffer * ring,u32 offset,u32 len)696 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
697 u32 offset, u32 len)
698 {
699 struct drm_device *dev = ring->dev;
700 int ret;
701
702 if (IS_I830(dev) || IS_845G(dev)) {
703 ret = intel_ring_begin(ring, 4);
704 if (ret)
705 return ret;
706
707 intel_ring_emit(ring, MI_BATCH_BUFFER);
708 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
709 intel_ring_emit(ring, offset + len - 8);
710 intel_ring_emit(ring, 0);
711 } else {
712 ret = intel_ring_begin(ring, 2);
713 if (ret)
714 return ret;
715
716 if (INTEL_INFO(dev)->gen >= 4) {
717 intel_ring_emit(ring,
718 MI_BATCH_BUFFER_START | (2 << 6) |
719 MI_BATCH_NON_SECURE_I965);
720 intel_ring_emit(ring, offset);
721 } else {
722 intel_ring_emit(ring,
723 MI_BATCH_BUFFER_START | (2 << 6));
724 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
725 }
726 }
727 intel_ring_advance(ring);
728
729 return 0;
730 }
731
cleanup_status_page(struct intel_ring_buffer * ring)732 static void cleanup_status_page(struct intel_ring_buffer *ring)
733 {
734 drm_i915_private_t *dev_priv = ring->dev->dev_private;
735 struct drm_i915_gem_object *obj;
736
737 obj = ring->status_page.obj;
738 if (obj == NULL)
739 return;
740
741 kunmap(obj->pages[0]);
742 i915_gem_object_unpin(obj);
743 drm_gem_object_unreference(&obj->base);
744 ring->status_page.obj = NULL;
745
746 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
747 }
748
init_status_page(struct intel_ring_buffer * ring)749 static int init_status_page(struct intel_ring_buffer *ring)
750 {
751 struct drm_device *dev = ring->dev;
752 drm_i915_private_t *dev_priv = dev->dev_private;
753 struct drm_i915_gem_object *obj;
754 int ret;
755
756 obj = i915_gem_alloc_object(dev, 4096);
757 if (obj == NULL) {
758 DRM_ERROR("Failed to allocate status page\n");
759 ret = -ENOMEM;
760 goto err;
761 }
762 obj->agp_type = AGP_USER_CACHED_MEMORY;
763
764 ret = i915_gem_object_pin(obj, 4096, true);
765 if (ret != 0) {
766 goto err_unref;
767 }
768
769 ring->status_page.gfx_addr = obj->gtt_offset;
770 ring->status_page.page_addr = kmap(obj->pages[0]);
771 if (ring->status_page.page_addr == NULL) {
772 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
773 goto err_unpin;
774 }
775 ring->status_page.obj = obj;
776 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
777
778 intel_ring_setup_status_page(ring);
779 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
780 ring->name, ring->status_page.gfx_addr);
781
782 return 0;
783
784 err_unpin:
785 i915_gem_object_unpin(obj);
786 err_unref:
787 drm_gem_object_unreference(&obj->base);
788 err:
789 return ret;
790 }
791
intel_init_ring_buffer(struct drm_device * dev,struct intel_ring_buffer * ring)792 int intel_init_ring_buffer(struct drm_device *dev,
793 struct intel_ring_buffer *ring)
794 {
795 struct drm_i915_gem_object *obj;
796 int ret;
797
798 ring->dev = dev;
799 INIT_LIST_HEAD(&ring->active_list);
800 INIT_LIST_HEAD(&ring->request_list);
801 INIT_LIST_HEAD(&ring->gpu_write_list);
802
803 spin_lock_init(&ring->irq_lock);
804 ring->irq_mask = ~0;
805
806 if (I915_NEED_GFX_HWS(dev)) {
807 ret = init_status_page(ring);
808 if (ret)
809 return ret;
810 }
811
812 obj = i915_gem_alloc_object(dev, ring->size);
813 if (obj == NULL) {
814 DRM_ERROR("Failed to allocate ringbuffer\n");
815 ret = -ENOMEM;
816 goto err_hws;
817 }
818
819 ring->obj = obj;
820
821 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
822 if (ret)
823 goto err_unref;
824
825 ring->map.size = ring->size;
826 ring->map.offset = dev->agp->base + obj->gtt_offset;
827 ring->map.type = 0;
828 ring->map.flags = 0;
829 ring->map.mtrr = 0;
830
831 drm_core_ioremap_wc(&ring->map, dev);
832 if (ring->map.handle == NULL) {
833 DRM_ERROR("Failed to map ringbuffer.\n");
834 ret = -EINVAL;
835 goto err_unpin;
836 }
837
838 ring->virtual_start = ring->map.handle;
839 ret = ring->init(ring);
840 if (ret)
841 goto err_unmap;
842
843 /* Workaround an erratum on the i830 which causes a hang if
844 * the TAIL pointer points to within the last 2 cachelines
845 * of the buffer.
846 */
847 ring->effective_size = ring->size;
848 if (IS_I830(ring->dev))
849 ring->effective_size -= 128;
850
851 return 0;
852
853 err_unmap:
854 drm_core_ioremapfree(&ring->map, dev);
855 err_unpin:
856 i915_gem_object_unpin(obj);
857 err_unref:
858 drm_gem_object_unreference(&obj->base);
859 ring->obj = NULL;
860 err_hws:
861 cleanup_status_page(ring);
862 return ret;
863 }
864
intel_cleanup_ring_buffer(struct intel_ring_buffer * ring)865 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
866 {
867 struct drm_i915_private *dev_priv;
868 int ret;
869
870 if (ring->obj == NULL)
871 return;
872
873 /* Disable the ring buffer. The ring must be idle at this point */
874 dev_priv = ring->dev->dev_private;
875 ret = intel_wait_ring_buffer(ring, ring->size - 8);
876 if (ret)
877 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
878 ring->name, ret);
879
880 I915_WRITE_CTL(ring, 0);
881
882 drm_core_ioremapfree(&ring->map, ring->dev);
883
884 i915_gem_object_unpin(ring->obj);
885 drm_gem_object_unreference(&ring->obj->base);
886 ring->obj = NULL;
887
888 if (ring->cleanup)
889 ring->cleanup(ring);
890
891 cleanup_status_page(ring);
892 }
893
intel_wrap_ring_buffer(struct intel_ring_buffer * ring)894 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
895 {
896 unsigned int *virt;
897 int rem = ring->size - ring->tail;
898
899 if (ring->space < rem) {
900 int ret = intel_wait_ring_buffer(ring, rem);
901 if (ret)
902 return ret;
903 }
904
905 virt = (unsigned int *)(ring->virtual_start + ring->tail);
906 rem /= 8;
907 while (rem--) {
908 *virt++ = MI_NOOP;
909 *virt++ = MI_NOOP;
910 }
911
912 ring->tail = 0;
913 ring->space = ring_space(ring);
914
915 return 0;
916 }
917
intel_wait_ring_buffer(struct intel_ring_buffer * ring,int n)918 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
919 {
920 struct drm_device *dev = ring->dev;
921 struct drm_i915_private *dev_priv = dev->dev_private;
922 unsigned long end;
923 u32 head;
924
925 /* If the reported head position has wrapped or hasn't advanced,
926 * fallback to the slow and accurate path.
927 */
928 head = intel_read_status_page(ring, 4);
929 if (head > ring->head) {
930 ring->head = head;
931 ring->space = ring_space(ring);
932 if (ring->space >= n)
933 return 0;
934 }
935
936 trace_i915_ring_wait_begin(ring);
937 end = jiffies + 3 * HZ;
938 do {
939 ring->head = I915_READ_HEAD(ring);
940 ring->space = ring_space(ring);
941 if (ring->space >= n) {
942 trace_i915_ring_wait_end(ring);
943 return 0;
944 }
945
946 if (dev->primary->master) {
947 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
948 if (master_priv->sarea_priv)
949 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
950 }
951
952 msleep(1);
953 if (atomic_read(&dev_priv->mm.wedged))
954 return -EAGAIN;
955 } while (!time_after(jiffies, end));
956 trace_i915_ring_wait_end(ring);
957 return -EBUSY;
958 }
959
intel_ring_begin(struct intel_ring_buffer * ring,int num_dwords)960 int intel_ring_begin(struct intel_ring_buffer *ring,
961 int num_dwords)
962 {
963 struct drm_i915_private *dev_priv = ring->dev->dev_private;
964 int n = 4*num_dwords;
965 int ret;
966
967 if (unlikely(atomic_read(&dev_priv->mm.wedged)))
968 return -EIO;
969
970 if (unlikely(ring->tail + n > ring->effective_size)) {
971 ret = intel_wrap_ring_buffer(ring);
972 if (unlikely(ret))
973 return ret;
974 }
975
976 if (unlikely(ring->space < n)) {
977 ret = intel_wait_ring_buffer(ring, n);
978 if (unlikely(ret))
979 return ret;
980 }
981
982 ring->space -= n;
983 return 0;
984 }
985
intel_ring_advance(struct intel_ring_buffer * ring)986 void intel_ring_advance(struct intel_ring_buffer *ring)
987 {
988 ring->tail &= ring->size - 1;
989 ring->write_tail(ring, ring->tail);
990 }
991
992 static const struct intel_ring_buffer render_ring = {
993 .name = "render ring",
994 .id = RING_RENDER,
995 .mmio_base = RENDER_RING_BASE,
996 .size = 32 * PAGE_SIZE,
997 .init = init_render_ring,
998 .write_tail = ring_write_tail,
999 .flush = render_ring_flush,
1000 .add_request = render_ring_add_request,
1001 .get_seqno = ring_get_seqno,
1002 .irq_get = render_ring_get_irq,
1003 .irq_put = render_ring_put_irq,
1004 .dispatch_execbuffer = render_ring_dispatch_execbuffer,
1005 .cleanup = render_ring_cleanup,
1006 };
1007
1008 /* ring buffer for bit-stream decoder */
1009
1010 static const struct intel_ring_buffer bsd_ring = {
1011 .name = "bsd ring",
1012 .id = RING_BSD,
1013 .mmio_base = BSD_RING_BASE,
1014 .size = 32 * PAGE_SIZE,
1015 .init = init_ring_common,
1016 .write_tail = ring_write_tail,
1017 .flush = bsd_ring_flush,
1018 .add_request = ring_add_request,
1019 .get_seqno = ring_get_seqno,
1020 .irq_get = bsd_ring_get_irq,
1021 .irq_put = bsd_ring_put_irq,
1022 .dispatch_execbuffer = ring_dispatch_execbuffer,
1023 };
1024
1025
gen6_bsd_ring_write_tail(struct intel_ring_buffer * ring,u32 value)1026 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1027 u32 value)
1028 {
1029 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1030
1031 /* Every tail move must follow the sequence below */
1032 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1033 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1034 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1035 I915_WRITE(GEN6_BSD_RNCID, 0x0);
1036
1037 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1038 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1039 50))
1040 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1041
1042 I915_WRITE_TAIL(ring, value);
1043 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1044 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1045 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1046 }
1047
gen6_ring_flush(struct intel_ring_buffer * ring,u32 invalidate,u32 flush)1048 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1049 u32 invalidate, u32 flush)
1050 {
1051 uint32_t cmd;
1052 int ret;
1053
1054 ret = intel_ring_begin(ring, 4);
1055 if (ret)
1056 return ret;
1057
1058 cmd = MI_FLUSH_DW;
1059 if (invalidate & I915_GEM_GPU_DOMAINS)
1060 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1061 intel_ring_emit(ring, cmd);
1062 intel_ring_emit(ring, 0);
1063 intel_ring_emit(ring, 0);
1064 intel_ring_emit(ring, MI_NOOP);
1065 intel_ring_advance(ring);
1066 return 0;
1067 }
1068
1069 static int
gen6_ring_dispatch_execbuffer(struct intel_ring_buffer * ring,u32 offset,u32 len)1070 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1071 u32 offset, u32 len)
1072 {
1073 int ret;
1074
1075 ret = intel_ring_begin(ring, 2);
1076 if (ret)
1077 return ret;
1078
1079 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1080 /* bit0-7 is the length on GEN6+ */
1081 intel_ring_emit(ring, offset);
1082 intel_ring_advance(ring);
1083
1084 return 0;
1085 }
1086
1087 static bool
gen6_render_ring_get_irq(struct intel_ring_buffer * ring)1088 gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
1089 {
1090 return gen6_ring_get_irq(ring,
1091 GT_USER_INTERRUPT,
1092 GEN6_RENDER_USER_INTERRUPT);
1093 }
1094
1095 static void
gen6_render_ring_put_irq(struct intel_ring_buffer * ring)1096 gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
1097 {
1098 return gen6_ring_put_irq(ring,
1099 GT_USER_INTERRUPT,
1100 GEN6_RENDER_USER_INTERRUPT);
1101 }
1102
1103 static bool
gen6_bsd_ring_get_irq(struct intel_ring_buffer * ring)1104 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1105 {
1106 return gen6_ring_get_irq(ring,
1107 GT_GEN6_BSD_USER_INTERRUPT,
1108 GEN6_BSD_USER_INTERRUPT);
1109 }
1110
1111 static void
gen6_bsd_ring_put_irq(struct intel_ring_buffer * ring)1112 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1113 {
1114 return gen6_ring_put_irq(ring,
1115 GT_GEN6_BSD_USER_INTERRUPT,
1116 GEN6_BSD_USER_INTERRUPT);
1117 }
1118
1119 /* ring buffer for Video Codec for Gen6+ */
1120 static const struct intel_ring_buffer gen6_bsd_ring = {
1121 .name = "gen6 bsd ring",
1122 .id = RING_BSD,
1123 .mmio_base = GEN6_BSD_RING_BASE,
1124 .size = 32 * PAGE_SIZE,
1125 .init = init_ring_common,
1126 .write_tail = gen6_bsd_ring_write_tail,
1127 .flush = gen6_ring_flush,
1128 .add_request = gen6_add_request,
1129 .get_seqno = ring_get_seqno,
1130 .irq_get = gen6_bsd_ring_get_irq,
1131 .irq_put = gen6_bsd_ring_put_irq,
1132 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
1133 };
1134
1135 /* Blitter support (SandyBridge+) */
1136
1137 static bool
blt_ring_get_irq(struct intel_ring_buffer * ring)1138 blt_ring_get_irq(struct intel_ring_buffer *ring)
1139 {
1140 return gen6_ring_get_irq(ring,
1141 GT_BLT_USER_INTERRUPT,
1142 GEN6_BLITTER_USER_INTERRUPT);
1143 }
1144
1145 static void
blt_ring_put_irq(struct intel_ring_buffer * ring)1146 blt_ring_put_irq(struct intel_ring_buffer *ring)
1147 {
1148 gen6_ring_put_irq(ring,
1149 GT_BLT_USER_INTERRUPT,
1150 GEN6_BLITTER_USER_INTERRUPT);
1151 }
1152
1153
1154 /* Workaround for some stepping of SNB,
1155 * each time when BLT engine ring tail moved,
1156 * the first command in the ring to be parsed
1157 * should be MI_BATCH_BUFFER_START
1158 */
1159 #define NEED_BLT_WORKAROUND(dev) \
1160 (IS_GEN6(dev) && (dev->pdev->revision < 8))
1161
1162 static inline struct drm_i915_gem_object *
to_blt_workaround(struct intel_ring_buffer * ring)1163 to_blt_workaround(struct intel_ring_buffer *ring)
1164 {
1165 return ring->private;
1166 }
1167
blt_ring_init(struct intel_ring_buffer * ring)1168 static int blt_ring_init(struct intel_ring_buffer *ring)
1169 {
1170 if (NEED_BLT_WORKAROUND(ring->dev)) {
1171 struct drm_i915_gem_object *obj;
1172 u32 *ptr;
1173 int ret;
1174
1175 obj = i915_gem_alloc_object(ring->dev, 4096);
1176 if (obj == NULL)
1177 return -ENOMEM;
1178
1179 ret = i915_gem_object_pin(obj, 4096, true);
1180 if (ret) {
1181 drm_gem_object_unreference(&obj->base);
1182 return ret;
1183 }
1184
1185 ptr = kmap(obj->pages[0]);
1186 *ptr++ = MI_BATCH_BUFFER_END;
1187 *ptr++ = MI_NOOP;
1188 kunmap(obj->pages[0]);
1189
1190 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1191 if (ret) {
1192 i915_gem_object_unpin(obj);
1193 drm_gem_object_unreference(&obj->base);
1194 return ret;
1195 }
1196
1197 ring->private = obj;
1198 }
1199
1200 return init_ring_common(ring);
1201 }
1202
blt_ring_begin(struct intel_ring_buffer * ring,int num_dwords)1203 static int blt_ring_begin(struct intel_ring_buffer *ring,
1204 int num_dwords)
1205 {
1206 if (ring->private) {
1207 int ret = intel_ring_begin(ring, num_dwords+2);
1208 if (ret)
1209 return ret;
1210
1211 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
1212 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
1213
1214 return 0;
1215 } else
1216 return intel_ring_begin(ring, 4);
1217 }
1218
blt_ring_flush(struct intel_ring_buffer * ring,u32 invalidate,u32 flush)1219 static int blt_ring_flush(struct intel_ring_buffer *ring,
1220 u32 invalidate, u32 flush)
1221 {
1222 uint32_t cmd;
1223 int ret;
1224
1225 ret = blt_ring_begin(ring, 4);
1226 if (ret)
1227 return ret;
1228
1229 cmd = MI_FLUSH_DW;
1230 if (invalidate & I915_GEM_DOMAIN_RENDER)
1231 cmd |= MI_INVALIDATE_TLB;
1232 intel_ring_emit(ring, cmd);
1233 intel_ring_emit(ring, 0);
1234 intel_ring_emit(ring, 0);
1235 intel_ring_emit(ring, MI_NOOP);
1236 intel_ring_advance(ring);
1237 return 0;
1238 }
1239
blt_ring_cleanup(struct intel_ring_buffer * ring)1240 static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1241 {
1242 if (!ring->private)
1243 return;
1244
1245 i915_gem_object_unpin(ring->private);
1246 drm_gem_object_unreference(ring->private);
1247 ring->private = NULL;
1248 }
1249
1250 static const struct intel_ring_buffer gen6_blt_ring = {
1251 .name = "blt ring",
1252 .id = RING_BLT,
1253 .mmio_base = BLT_RING_BASE,
1254 .size = 32 * PAGE_SIZE,
1255 .init = blt_ring_init,
1256 .write_tail = ring_write_tail,
1257 .flush = blt_ring_flush,
1258 .add_request = gen6_add_request,
1259 .get_seqno = ring_get_seqno,
1260 .irq_get = blt_ring_get_irq,
1261 .irq_put = blt_ring_put_irq,
1262 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
1263 .cleanup = blt_ring_cleanup,
1264 };
1265
intel_init_render_ring_buffer(struct drm_device * dev)1266 int intel_init_render_ring_buffer(struct drm_device *dev)
1267 {
1268 drm_i915_private_t *dev_priv = dev->dev_private;
1269 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1270
1271 *ring = render_ring;
1272 if (INTEL_INFO(dev)->gen >= 6) {
1273 ring->add_request = gen6_add_request;
1274 ring->irq_get = gen6_render_ring_get_irq;
1275 ring->irq_put = gen6_render_ring_put_irq;
1276 } else if (IS_GEN5(dev)) {
1277 ring->add_request = pc_render_add_request;
1278 ring->get_seqno = pc_render_get_seqno;
1279 }
1280
1281 if (!I915_NEED_GFX_HWS(dev)) {
1282 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1283 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1284 }
1285
1286 return intel_init_ring_buffer(dev, ring);
1287 }
1288
intel_render_ring_init_dri(struct drm_device * dev,u64 start,u32 size)1289 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1290 {
1291 drm_i915_private_t *dev_priv = dev->dev_private;
1292 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1293
1294 *ring = render_ring;
1295 if (INTEL_INFO(dev)->gen >= 6) {
1296 ring->add_request = gen6_add_request;
1297 ring->irq_get = gen6_render_ring_get_irq;
1298 ring->irq_put = gen6_render_ring_put_irq;
1299 } else if (IS_GEN5(dev)) {
1300 ring->add_request = pc_render_add_request;
1301 ring->get_seqno = pc_render_get_seqno;
1302 }
1303
1304 ring->dev = dev;
1305 INIT_LIST_HEAD(&ring->active_list);
1306 INIT_LIST_HEAD(&ring->request_list);
1307 INIT_LIST_HEAD(&ring->gpu_write_list);
1308
1309 ring->size = size;
1310 ring->effective_size = ring->size;
1311 if (IS_I830(ring->dev))
1312 ring->effective_size -= 128;
1313
1314 ring->map.offset = start;
1315 ring->map.size = size;
1316 ring->map.type = 0;
1317 ring->map.flags = 0;
1318 ring->map.mtrr = 0;
1319
1320 drm_core_ioremap_wc(&ring->map, dev);
1321 if (ring->map.handle == NULL) {
1322 DRM_ERROR("can not ioremap virtual address for"
1323 " ring buffer\n");
1324 return -ENOMEM;
1325 }
1326
1327 ring->virtual_start = (void __force __iomem *)ring->map.handle;
1328 return 0;
1329 }
1330
intel_init_bsd_ring_buffer(struct drm_device * dev)1331 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1332 {
1333 drm_i915_private_t *dev_priv = dev->dev_private;
1334 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1335
1336 if (IS_GEN6(dev))
1337 *ring = gen6_bsd_ring;
1338 else
1339 *ring = bsd_ring;
1340
1341 return intel_init_ring_buffer(dev, ring);
1342 }
1343
intel_init_blt_ring_buffer(struct drm_device * dev)1344 int intel_init_blt_ring_buffer(struct drm_device *dev)
1345 {
1346 drm_i915_private_t *dev_priv = dev->dev_private;
1347 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1348
1349 *ring = gen6_blt_ring;
1350
1351 return intel_init_ring_buffer(dev, ring);
1352 }
1353