Searched defs:intel_vgpu_primary_plane_format (Results 1 – 1 of 1) sorted by relevance
106 struct intel_vgpu_primary_plane_format { struct107 u8 enabled; /* plane is enabled */108 u32 tiled; /* tiling mode: linear, X-tiled, Y tiled, etc */109 u8 bpp; /* bits per pixel */110 u32 hw_format; /* format field in the PRI_CTL register */111 u32 drm_format; /* format in DRM definition */112 u32 base; /* framebuffer base in graphics memory */113 u64 base_gpa;114 u32 x_offset; /* in pixels */115 u32 y_offset; /* in lines */[all …]