1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2016-2019 Intel Corporation
4  */
5 
6 #include <linux/string_helpers.h>
7 
8 #include "gt/intel_gt.h"
9 #include "gt/intel_gt_print.h"
10 #include "gt/intel_reset.h"
11 #include "intel_gsc_fw.h"
12 #include "intel_gsc_uc.h"
13 #include "intel_guc.h"
14 #include "intel_guc_ads.h"
15 #include "intel_guc_print.h"
16 #include "intel_guc_submission.h"
17 #include "gt/intel_rps.h"
18 #include "intel_uc.h"
19 
20 #include "i915_drv.h"
21 #include "i915_hwmon.h"
22 
23 static const struct intel_uc_ops uc_ops_off;
24 static const struct intel_uc_ops uc_ops_on;
25 
uc_expand_default_options(struct intel_uc * uc)26 static void uc_expand_default_options(struct intel_uc *uc)
27 {
28 	struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
29 
30 	if (i915->params.enable_guc != -1)
31 		return;
32 
33 	/* Don't enable GuC/HuC on pre-Gen12 */
34 	if (GRAPHICS_VER(i915) < 12) {
35 		i915->params.enable_guc = 0;
36 		return;
37 	}
38 
39 	/* Don't enable GuC/HuC on older Gen12 platforms */
40 	if (IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) {
41 		i915->params.enable_guc = 0;
42 		return;
43 	}
44 
45 	/* Intermediate platforms are HuC authentication only */
46 	if (IS_ALDERLAKE_S(i915) && !IS_RAPTORLAKE_S(i915)) {
47 		i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
48 		return;
49 	}
50 
51 	/* Default: enable HuC authentication and GuC submission */
52 	i915->params.enable_guc = ENABLE_GUC_LOAD_HUC | ENABLE_GUC_SUBMISSION;
53 
54 	/* XEHPSDV and PVC do not use HuC */
55 	if (IS_XEHPSDV(i915) || IS_PONTEVECCHIO(i915))
56 		i915->params.enable_guc &= ~ENABLE_GUC_LOAD_HUC;
57 }
58 
59 /* Reset GuC providing us with fresh state for both GuC and HuC.
60  */
__intel_uc_reset_hw(struct intel_uc * uc)61 static int __intel_uc_reset_hw(struct intel_uc *uc)
62 {
63 	struct intel_gt *gt = uc_to_gt(uc);
64 	int ret;
65 	u32 guc_status;
66 
67 	ret = i915_inject_probe_error(gt->i915, -ENXIO);
68 	if (ret)
69 		return ret;
70 
71 	ret = intel_reset_guc(gt);
72 	if (ret) {
73 		gt_err(gt, "Failed to reset GuC, ret = %d\n", ret);
74 		return ret;
75 	}
76 
77 	guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
78 	gt_WARN(gt, !(guc_status & GS_MIA_IN_RESET),
79 		"GuC status: 0x%x, MIA core expected to be in reset\n",
80 		guc_status);
81 
82 	return ret;
83 }
84 
__confirm_options(struct intel_uc * uc)85 static void __confirm_options(struct intel_uc *uc)
86 {
87 	struct intel_gt *gt = uc_to_gt(uc);
88 	struct drm_i915_private *i915 = gt->i915;
89 
90 	gt_dbg(gt, "enable_guc=%d (guc:%s submission:%s huc:%s slpc:%s)\n",
91 	       i915->params.enable_guc,
92 	       str_yes_no(intel_uc_wants_guc(uc)),
93 	       str_yes_no(intel_uc_wants_guc_submission(uc)),
94 	       str_yes_no(intel_uc_wants_huc(uc)),
95 	       str_yes_no(intel_uc_wants_guc_slpc(uc)));
96 
97 	if (i915->params.enable_guc == 0) {
98 		GEM_BUG_ON(intel_uc_wants_guc(uc));
99 		GEM_BUG_ON(intel_uc_wants_guc_submission(uc));
100 		GEM_BUG_ON(intel_uc_wants_huc(uc));
101 		GEM_BUG_ON(intel_uc_wants_guc_slpc(uc));
102 		return;
103 	}
104 
105 	if (!intel_uc_supports_guc(uc))
106 		gt_info(gt,  "Incompatible option enable_guc=%d - %s\n",
107 			i915->params.enable_guc, "GuC is not supported!");
108 
109 	if (i915->params.enable_guc & ENABLE_GUC_LOAD_HUC &&
110 	    !intel_uc_supports_huc(uc))
111 		gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
112 			i915->params.enable_guc, "HuC is not supported!");
113 
114 	if (i915->params.enable_guc & ENABLE_GUC_SUBMISSION &&
115 	    !intel_uc_supports_guc_submission(uc))
116 		gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
117 			i915->params.enable_guc, "GuC submission is N/A");
118 
119 	if (i915->params.enable_guc & ~ENABLE_GUC_MASK)
120 		gt_info(gt, "Incompatible option enable_guc=%d - %s\n",
121 			i915->params.enable_guc, "undocumented flag");
122 }
123 
intel_uc_init_early(struct intel_uc * uc)124 void intel_uc_init_early(struct intel_uc *uc)
125 {
126 	uc_expand_default_options(uc);
127 
128 	intel_guc_init_early(&uc->guc);
129 	intel_huc_init_early(&uc->huc);
130 	intel_gsc_uc_init_early(&uc->gsc);
131 
132 	__confirm_options(uc);
133 
134 	if (intel_uc_wants_guc(uc))
135 		uc->ops = &uc_ops_on;
136 	else
137 		uc->ops = &uc_ops_off;
138 }
139 
intel_uc_init_late(struct intel_uc * uc)140 void intel_uc_init_late(struct intel_uc *uc)
141 {
142 	intel_guc_init_late(&uc->guc);
143 	intel_gsc_uc_load_start(&uc->gsc);
144 }
145 
intel_uc_driver_late_release(struct intel_uc * uc)146 void intel_uc_driver_late_release(struct intel_uc *uc)
147 {
148 }
149 
150 /**
151  * intel_uc_init_mmio - setup uC MMIO access
152  * @uc: the intel_uc structure
153  *
154  * Setup minimal state necessary for MMIO accesses later in the
155  * initialization sequence.
156  */
intel_uc_init_mmio(struct intel_uc * uc)157 void intel_uc_init_mmio(struct intel_uc *uc)
158 {
159 	intel_guc_init_send_regs(&uc->guc);
160 }
161 
__uc_capture_load_err_log(struct intel_uc * uc)162 static void __uc_capture_load_err_log(struct intel_uc *uc)
163 {
164 	struct intel_guc *guc = &uc->guc;
165 
166 	if (guc->log.vma && !uc->load_err_log)
167 		uc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
168 }
169 
__uc_free_load_err_log(struct intel_uc * uc)170 static void __uc_free_load_err_log(struct intel_uc *uc)
171 {
172 	struct drm_i915_gem_object *log = fetch_and_zero(&uc->load_err_log);
173 
174 	if (log)
175 		i915_gem_object_put(log);
176 }
177 
intel_uc_driver_remove(struct intel_uc * uc)178 void intel_uc_driver_remove(struct intel_uc *uc)
179 {
180 	intel_uc_fini_hw(uc);
181 	intel_uc_fini(uc);
182 	__uc_free_load_err_log(uc);
183 }
184 
185 /*
186  * Events triggered while CT buffers are disabled are logged in the SCRATCH_15
187  * register using the same bits used in the CT message payload. Since our
188  * communication channel with guc is turned off at this point, we can save the
189  * message and handle it after we turn it back on.
190  */
guc_clear_mmio_msg(struct intel_guc * guc)191 static void guc_clear_mmio_msg(struct intel_guc *guc)
192 {
193 	intel_uncore_write(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15), 0);
194 }
195 
guc_get_mmio_msg(struct intel_guc * guc)196 static void guc_get_mmio_msg(struct intel_guc *guc)
197 {
198 	u32 val;
199 
200 	spin_lock_irq(&guc->irq_lock);
201 
202 	val = intel_uncore_read(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15));
203 	guc->mmio_msg |= val & guc->msg_enabled_mask;
204 
205 	/*
206 	 * clear all events, including the ones we're not currently servicing,
207 	 * to make sure we don't try to process a stale message if we enable
208 	 * handling of more events later.
209 	 */
210 	guc_clear_mmio_msg(guc);
211 
212 	spin_unlock_irq(&guc->irq_lock);
213 }
214 
guc_handle_mmio_msg(struct intel_guc * guc)215 static void guc_handle_mmio_msg(struct intel_guc *guc)
216 {
217 	/* we need communication to be enabled to reply to GuC */
218 	GEM_BUG_ON(!intel_guc_ct_enabled(&guc->ct));
219 
220 	spin_lock_irq(&guc->irq_lock);
221 	if (guc->mmio_msg) {
222 		intel_guc_to_host_process_recv_msg(guc, &guc->mmio_msg, 1);
223 		guc->mmio_msg = 0;
224 	}
225 	spin_unlock_irq(&guc->irq_lock);
226 }
227 
guc_enable_communication(struct intel_guc * guc)228 static int guc_enable_communication(struct intel_guc *guc)
229 {
230 	struct intel_gt *gt = guc_to_gt(guc);
231 	struct drm_i915_private *i915 = gt->i915;
232 	int ret;
233 
234 	GEM_BUG_ON(intel_guc_ct_enabled(&guc->ct));
235 
236 	ret = i915_inject_probe_error(i915, -ENXIO);
237 	if (ret)
238 		return ret;
239 
240 	ret = intel_guc_ct_enable(&guc->ct);
241 	if (ret)
242 		return ret;
243 
244 	/* check for mmio messages received before/during the CT enable */
245 	guc_get_mmio_msg(guc);
246 	guc_handle_mmio_msg(guc);
247 
248 	intel_guc_enable_interrupts(guc);
249 
250 	/* check for CT messages received before we enabled interrupts */
251 	spin_lock_irq(gt->irq_lock);
252 	intel_guc_ct_event_handler(&guc->ct);
253 	spin_unlock_irq(gt->irq_lock);
254 
255 	guc_dbg(guc, "communication enabled\n");
256 
257 	return 0;
258 }
259 
guc_disable_communication(struct intel_guc * guc)260 static void guc_disable_communication(struct intel_guc *guc)
261 {
262 	/*
263 	 * Events generated during or after CT disable are logged by guc in
264 	 * via mmio. Make sure the register is clear before disabling CT since
265 	 * all events we cared about have already been processed via CT.
266 	 */
267 	guc_clear_mmio_msg(guc);
268 
269 	intel_guc_disable_interrupts(guc);
270 
271 	intel_guc_ct_disable(&guc->ct);
272 
273 	/*
274 	 * Check for messages received during/after the CT disable. We do not
275 	 * expect any messages to have arrived via CT between the interrupt
276 	 * disable and the CT disable because GuC should've been idle until we
277 	 * triggered the CT disable protocol.
278 	 */
279 	guc_get_mmio_msg(guc);
280 
281 	guc_dbg(guc, "communication disabled\n");
282 }
283 
__uc_fetch_firmwares(struct intel_uc * uc)284 static void __uc_fetch_firmwares(struct intel_uc *uc)
285 {
286 	struct intel_gt *gt = uc_to_gt(uc);
287 	int err;
288 
289 	GEM_BUG_ON(!intel_uc_wants_guc(uc));
290 
291 	err = intel_uc_fw_fetch(&uc->guc.fw);
292 	if (err) {
293 		/* Make sure we transition out of transient "SELECTED" state */
294 		if (intel_uc_wants_huc(uc)) {
295 			gt_dbg(gt, "Failed to fetch GuC fw (%pe) disabling HuC\n", ERR_PTR(err));
296 			intel_uc_fw_change_status(&uc->huc.fw,
297 						  INTEL_UC_FIRMWARE_ERROR);
298 		}
299 
300 		if (intel_uc_wants_gsc_uc(uc)) {
301 			gt_dbg(gt, "Failed to fetch GuC fw (%pe) disabling GSC\n", ERR_PTR(err));
302 			intel_uc_fw_change_status(&uc->gsc.fw,
303 						  INTEL_UC_FIRMWARE_ERROR);
304 		}
305 
306 		return;
307 	}
308 
309 	if (intel_uc_wants_huc(uc))
310 		intel_uc_fw_fetch(&uc->huc.fw);
311 
312 	if (intel_uc_wants_gsc_uc(uc))
313 		intel_uc_fw_fetch(&uc->gsc.fw);
314 }
315 
__uc_cleanup_firmwares(struct intel_uc * uc)316 static void __uc_cleanup_firmwares(struct intel_uc *uc)
317 {
318 	intel_uc_fw_cleanup_fetch(&uc->gsc.fw);
319 	intel_uc_fw_cleanup_fetch(&uc->huc.fw);
320 	intel_uc_fw_cleanup_fetch(&uc->guc.fw);
321 }
322 
__uc_init(struct intel_uc * uc)323 static int __uc_init(struct intel_uc *uc)
324 {
325 	struct intel_guc *guc = &uc->guc;
326 	struct intel_huc *huc = &uc->huc;
327 	int ret;
328 
329 	GEM_BUG_ON(!intel_uc_wants_guc(uc));
330 
331 	if (!intel_uc_uses_guc(uc))
332 		return 0;
333 
334 	if (i915_inject_probe_failure(uc_to_gt(uc)->i915))
335 		return -ENOMEM;
336 
337 	ret = intel_guc_init(guc);
338 	if (ret)
339 		return ret;
340 
341 	if (intel_uc_uses_huc(uc))
342 		intel_huc_init(huc);
343 
344 	if (intel_uc_uses_gsc_uc(uc))
345 		intel_gsc_uc_init(&uc->gsc);
346 
347 	return 0;
348 }
349 
__uc_fini(struct intel_uc * uc)350 static void __uc_fini(struct intel_uc *uc)
351 {
352 	intel_gsc_uc_fini(&uc->gsc);
353 	intel_huc_fini(&uc->huc);
354 	intel_guc_fini(&uc->guc);
355 }
356 
__uc_sanitize(struct intel_uc * uc)357 static int __uc_sanitize(struct intel_uc *uc)
358 {
359 	struct intel_guc *guc = &uc->guc;
360 	struct intel_huc *huc = &uc->huc;
361 
362 	GEM_BUG_ON(!intel_uc_supports_guc(uc));
363 
364 	intel_huc_sanitize(huc);
365 	intel_guc_sanitize(guc);
366 
367 	return __intel_uc_reset_hw(uc);
368 }
369 
370 /* Initialize and verify the uC regs related to uC positioning in WOPCM */
uc_init_wopcm(struct intel_uc * uc)371 static int uc_init_wopcm(struct intel_uc *uc)
372 {
373 	struct intel_gt *gt = uc_to_gt(uc);
374 	struct intel_uncore *uncore = gt->uncore;
375 	u32 base = intel_wopcm_guc_base(&gt->wopcm);
376 	u32 size = intel_wopcm_guc_size(&gt->wopcm);
377 	u32 huc_agent = intel_uc_uses_huc(uc) ? HUC_LOADING_AGENT_GUC : 0;
378 	u32 mask;
379 	int err;
380 
381 	if (unlikely(!base || !size)) {
382 		gt_probe_error(gt, "Unsuccessful WOPCM partitioning\n");
383 		return -E2BIG;
384 	}
385 
386 	GEM_BUG_ON(!intel_uc_supports_guc(uc));
387 	GEM_BUG_ON(!(base & GUC_WOPCM_OFFSET_MASK));
388 	GEM_BUG_ON(base & ~GUC_WOPCM_OFFSET_MASK);
389 	GEM_BUG_ON(!(size & GUC_WOPCM_SIZE_MASK));
390 	GEM_BUG_ON(size & ~GUC_WOPCM_SIZE_MASK);
391 
392 	err = i915_inject_probe_error(gt->i915, -ENXIO);
393 	if (err)
394 		return err;
395 
396 	mask = GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED;
397 	err = intel_uncore_write_and_verify(uncore, GUC_WOPCM_SIZE, size, mask,
398 					    size | GUC_WOPCM_SIZE_LOCKED);
399 	if (err)
400 		goto err_out;
401 
402 	mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
403 	err = intel_uncore_write_and_verify(uncore, DMA_GUC_WOPCM_OFFSET,
404 					    base | huc_agent, mask,
405 					    base | huc_agent |
406 					    GUC_WOPCM_OFFSET_VALID);
407 	if (err)
408 		goto err_out;
409 
410 	return 0;
411 
412 err_out:
413 	gt_probe_error(gt, "Failed to init uC WOPCM registers!\n");
414 	gt_probe_error(gt, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
415 		       i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET),
416 		       intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
417 	gt_probe_error(gt, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
418 		       i915_mmio_reg_offset(GUC_WOPCM_SIZE),
419 		       intel_uncore_read(uncore, GUC_WOPCM_SIZE));
420 
421 	return err;
422 }
423 
uc_is_wopcm_locked(struct intel_uc * uc)424 static bool uc_is_wopcm_locked(struct intel_uc *uc)
425 {
426 	struct intel_gt *gt = uc_to_gt(uc);
427 	struct intel_uncore *uncore = gt->uncore;
428 
429 	return (intel_uncore_read(uncore, GUC_WOPCM_SIZE) & GUC_WOPCM_SIZE_LOCKED) ||
430 	       (intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET) & GUC_WOPCM_OFFSET_VALID);
431 }
432 
__uc_check_hw(struct intel_uc * uc)433 static int __uc_check_hw(struct intel_uc *uc)
434 {
435 	if (uc->fw_table_invalid)
436 		return -EIO;
437 
438 	if (!intel_uc_supports_guc(uc))
439 		return 0;
440 
441 	/*
442 	 * We can silently continue without GuC only if it was never enabled
443 	 * before on this system after reboot, otherwise we risk GPU hangs.
444 	 * To check if GuC was loaded before we look at WOPCM registers.
445 	 */
446 	if (uc_is_wopcm_locked(uc))
447 		return -EIO;
448 
449 	return 0;
450 }
451 
print_fw_ver(struct intel_gt * gt,struct intel_uc_fw * fw)452 static void print_fw_ver(struct intel_gt *gt, struct intel_uc_fw *fw)
453 {
454 	gt_info(gt, "%s firmware %s version %u.%u.%u\n",
455 		intel_uc_fw_type_repr(fw->type), fw->file_selected.path,
456 		fw->file_selected.ver.major,
457 		fw->file_selected.ver.minor,
458 		fw->file_selected.ver.patch);
459 }
460 
__uc_init_hw(struct intel_uc * uc)461 static int __uc_init_hw(struct intel_uc *uc)
462 {
463 	struct intel_gt *gt = uc_to_gt(uc);
464 	struct drm_i915_private *i915 = gt->i915;
465 	struct intel_guc *guc = &uc->guc;
466 	struct intel_huc *huc = &uc->huc;
467 	int ret, attempts;
468 	bool pl1en = false;
469 
470 	GEM_BUG_ON(!intel_uc_supports_guc(uc));
471 	GEM_BUG_ON(!intel_uc_wants_guc(uc));
472 
473 	print_fw_ver(gt, &guc->fw);
474 
475 	if (intel_uc_uses_huc(uc))
476 		print_fw_ver(gt, &huc->fw);
477 
478 	if (!intel_uc_fw_is_loadable(&guc->fw)) {
479 		ret = __uc_check_hw(uc) ||
480 		      intel_uc_fw_is_overridden(&guc->fw) ||
481 		      intel_uc_wants_guc_submission(uc) ?
482 		      intel_uc_fw_status_to_error(guc->fw.status) : 0;
483 		goto err_out;
484 	}
485 
486 	ret = uc_init_wopcm(uc);
487 	if (ret)
488 		goto err_out;
489 
490 	intel_guc_reset_interrupts(guc);
491 
492 	/* WaEnableuKernelHeaderValidFix:skl */
493 	/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
494 	if (GRAPHICS_VER(i915) == 9)
495 		attempts = 3;
496 	else
497 		attempts = 1;
498 
499 	/* Disable a potentially low PL1 power limit to allow freq to be raised */
500 	i915_hwmon_power_max_disable(gt->i915, &pl1en);
501 
502 	intel_rps_raise_unslice(&uc_to_gt(uc)->rps);
503 
504 	while (attempts--) {
505 		/*
506 		 * Always reset the GuC just before (re)loading, so
507 		 * that the state and timing are fairly predictable
508 		 */
509 		ret = __uc_sanitize(uc);
510 		if (ret)
511 			goto err_rps;
512 
513 		intel_huc_fw_upload(huc);
514 		intel_guc_ads_reset(guc);
515 		intel_guc_write_params(guc);
516 		ret = intel_guc_fw_upload(guc);
517 		if (ret == 0)
518 			break;
519 
520 		gt_dbg(gt, "GuC fw load failed (%pe) will reset and retry %d more time(s)\n",
521 		       ERR_PTR(ret), attempts);
522 	}
523 
524 	/* Did we succeded or run out of retries? */
525 	if (ret)
526 		goto err_log_capture;
527 
528 	ret = guc_enable_communication(guc);
529 	if (ret)
530 		goto err_log_capture;
531 
532 	/*
533 	 * GSC-loaded HuC is authenticated by the GSC, so we don't need to
534 	 * trigger the auth here. However, given that the HuC loaded this way
535 	 * survive GT reset, we still need to update our SW bookkeeping to make
536 	 * sure it reflects the correct HW status.
537 	 */
538 	if (intel_huc_is_loaded_by_gsc(huc))
539 		intel_huc_update_auth_status(huc);
540 	else
541 		intel_huc_auth(huc, INTEL_HUC_AUTH_BY_GUC);
542 
543 	if (intel_uc_uses_guc_submission(uc)) {
544 		ret = intel_guc_submission_enable(guc);
545 		if (ret)
546 			goto err_log_capture;
547 	}
548 
549 	if (intel_uc_uses_guc_slpc(uc)) {
550 		ret = intel_guc_slpc_enable(&guc->slpc);
551 		if (ret)
552 			goto err_submission;
553 	} else {
554 		/* Restore GT back to RPn for non-SLPC path */
555 		intel_rps_lower_unslice(&uc_to_gt(uc)->rps);
556 	}
557 
558 	i915_hwmon_power_max_restore(gt->i915, pl1en);
559 
560 	guc_info(guc, "submission %s\n", str_enabled_disabled(intel_uc_uses_guc_submission(uc)));
561 	guc_info(guc, "SLPC %s\n", str_enabled_disabled(intel_uc_uses_guc_slpc(uc)));
562 
563 	return 0;
564 
565 	/*
566 	 * We've failed to load the firmware :(
567 	 */
568 err_submission:
569 	intel_guc_submission_disable(guc);
570 err_log_capture:
571 	__uc_capture_load_err_log(uc);
572 err_rps:
573 	/* Return GT back to RPn */
574 	intel_rps_lower_unslice(&uc_to_gt(uc)->rps);
575 
576 	i915_hwmon_power_max_restore(gt->i915, pl1en);
577 err_out:
578 	__uc_sanitize(uc);
579 
580 	if (!ret) {
581 		gt_notice(gt, "GuC is uninitialized\n");
582 		/* We want to run without GuC submission */
583 		return 0;
584 	}
585 
586 	gt_probe_error(gt, "GuC initialization failed %pe\n", ERR_PTR(ret));
587 
588 	/* We want to keep KMS alive */
589 	return -EIO;
590 }
591 
__uc_fini_hw(struct intel_uc * uc)592 static void __uc_fini_hw(struct intel_uc *uc)
593 {
594 	struct intel_guc *guc = &uc->guc;
595 
596 	if (!intel_guc_is_fw_running(guc))
597 		return;
598 
599 	if (intel_uc_uses_guc_submission(uc))
600 		intel_guc_submission_disable(guc);
601 
602 	__uc_sanitize(uc);
603 }
604 
605 /**
606  * intel_uc_reset_prepare - Prepare for reset
607  * @uc: the intel_uc structure
608  *
609  * Preparing for full gpu reset.
610  */
intel_uc_reset_prepare(struct intel_uc * uc)611 void intel_uc_reset_prepare(struct intel_uc *uc)
612 {
613 	struct intel_guc *guc = &uc->guc;
614 
615 	uc->reset_in_progress = true;
616 
617 	/* Nothing to do if GuC isn't supported */
618 	if (!intel_uc_supports_guc(uc))
619 		return;
620 
621 	/* Firmware expected to be running when this function is called */
622 	if (!intel_guc_is_ready(guc))
623 		goto sanitize;
624 
625 	if (intel_uc_uses_guc_submission(uc))
626 		intel_guc_submission_reset_prepare(guc);
627 
628 sanitize:
629 	__uc_sanitize(uc);
630 }
631 
intel_uc_reset(struct intel_uc * uc,intel_engine_mask_t stalled)632 void intel_uc_reset(struct intel_uc *uc, intel_engine_mask_t stalled)
633 {
634 	struct intel_guc *guc = &uc->guc;
635 
636 	/* Firmware can not be running when this function is called  */
637 	if (intel_uc_uses_guc_submission(uc))
638 		intel_guc_submission_reset(guc, stalled);
639 }
640 
intel_uc_reset_finish(struct intel_uc * uc)641 void intel_uc_reset_finish(struct intel_uc *uc)
642 {
643 	struct intel_guc *guc = &uc->guc;
644 
645 	uc->reset_in_progress = false;
646 
647 	/* Firmware expected to be running when this function is called */
648 	if (intel_guc_is_fw_running(guc) && intel_uc_uses_guc_submission(uc))
649 		intel_guc_submission_reset_finish(guc);
650 }
651 
intel_uc_cancel_requests(struct intel_uc * uc)652 void intel_uc_cancel_requests(struct intel_uc *uc)
653 {
654 	struct intel_guc *guc = &uc->guc;
655 
656 	/* Firmware can not be running when this function is called  */
657 	if (intel_uc_uses_guc_submission(uc))
658 		intel_guc_submission_cancel_requests(guc);
659 }
660 
intel_uc_runtime_suspend(struct intel_uc * uc)661 void intel_uc_runtime_suspend(struct intel_uc *uc)
662 {
663 	struct intel_guc *guc = &uc->guc;
664 
665 	if (!intel_guc_is_ready(guc)) {
666 		guc->interrupts.enabled = false;
667 		return;
668 	}
669 
670 	/*
671 	 * Wait for any outstanding CTB before tearing down communication /w the
672 	 * GuC.
673 	 */
674 #define OUTSTANDING_CTB_TIMEOUT_PERIOD	(HZ / 5)
675 	intel_guc_wait_for_pending_msg(guc, &guc->outstanding_submission_g2h,
676 				       false, OUTSTANDING_CTB_TIMEOUT_PERIOD);
677 	GEM_WARN_ON(atomic_read(&guc->outstanding_submission_g2h));
678 
679 	guc_disable_communication(guc);
680 }
681 
intel_uc_suspend(struct intel_uc * uc)682 void intel_uc_suspend(struct intel_uc *uc)
683 {
684 	struct intel_guc *guc = &uc->guc;
685 	intel_wakeref_t wakeref;
686 	int err;
687 
688 	/* flush the GSC worker */
689 	intel_gsc_uc_flush_work(&uc->gsc);
690 
691 	if (!intel_guc_is_ready(guc)) {
692 		guc->interrupts.enabled = false;
693 		return;
694 	}
695 
696 	with_intel_runtime_pm(&uc_to_gt(uc)->i915->runtime_pm, wakeref) {
697 		err = intel_guc_suspend(guc);
698 		if (err)
699 			guc_dbg(guc, "Failed to suspend, %pe", ERR_PTR(err));
700 	}
701 }
702 
__uc_resume_mappings(struct intel_uc * uc)703 static void __uc_resume_mappings(struct intel_uc *uc)
704 {
705 	intel_uc_fw_resume_mapping(&uc->guc.fw);
706 	intel_uc_fw_resume_mapping(&uc->huc.fw);
707 }
708 
__uc_resume(struct intel_uc * uc,bool enable_communication)709 static int __uc_resume(struct intel_uc *uc, bool enable_communication)
710 {
711 	struct intel_guc *guc = &uc->guc;
712 	struct intel_gt *gt = guc_to_gt(guc);
713 	int err;
714 
715 	if (!intel_guc_is_fw_running(guc))
716 		return 0;
717 
718 	/* Make sure we enable communication if and only if it's disabled */
719 	GEM_BUG_ON(enable_communication == intel_guc_ct_enabled(&guc->ct));
720 
721 	if (enable_communication)
722 		guc_enable_communication(guc);
723 
724 	/* If we are only resuming GuC communication but not reloading
725 	 * GuC, we need to ensure the ARAT timer interrupt is enabled
726 	 * again. In case of GuC reload, it is enabled during SLPC enable.
727 	 */
728 	if (enable_communication && intel_uc_uses_guc_slpc(uc))
729 		intel_guc_pm_intrmsk_enable(gt);
730 
731 	err = intel_guc_resume(guc);
732 	if (err) {
733 		guc_dbg(guc, "Failed to resume, %pe", ERR_PTR(err));
734 		return err;
735 	}
736 
737 	intel_gsc_uc_resume(&uc->gsc);
738 
739 	return 0;
740 }
741 
intel_uc_resume(struct intel_uc * uc)742 int intel_uc_resume(struct intel_uc *uc)
743 {
744 	/*
745 	 * When coming out of S3/S4 we sanitize and re-init the HW, so
746 	 * communication is already re-enabled at this point.
747 	 */
748 	return __uc_resume(uc, false);
749 }
750 
intel_uc_runtime_resume(struct intel_uc * uc)751 int intel_uc_runtime_resume(struct intel_uc *uc)
752 {
753 	/*
754 	 * During runtime resume we don't sanitize, so we need to re-init
755 	 * communication as well.
756 	 */
757 	return __uc_resume(uc, true);
758 }
759 
760 static const struct intel_uc_ops uc_ops_off = {
761 	.init_hw = __uc_check_hw,
762 	.fini = __uc_fini, /* to clean-up the init_early initialization */
763 };
764 
765 static const struct intel_uc_ops uc_ops_on = {
766 	.sanitize = __uc_sanitize,
767 
768 	.init_fw = __uc_fetch_firmwares,
769 	.fini_fw = __uc_cleanup_firmwares,
770 
771 	.init = __uc_init,
772 	.fini = __uc_fini,
773 
774 	.init_hw = __uc_init_hw,
775 	.fini_hw = __uc_fini_hw,
776 
777 	.resume_mappings = __uc_resume_mappings,
778 };
779