1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2019 Intel Corporation
4  */
5 
6 #include <linux/util_macros.h>
7 
8 #include "intel_ddi.h"
9 #include "intel_ddi_buf_trans.h"
10 #include "intel_de.h"
11 #include "intel_display_types.h"
12 #include "intel_snps_phy.h"
13 #include "intel_snps_phy_regs.h"
14 
15 /**
16  * DOC: Synopsis PHY support
17  *
18  * Synopsis PHYs are primarily programmed by looking up magic register values
19  * in tables rather than calculating the necessary values at runtime.
20  *
21  * Of special note is that the SNPS PHYs include a dedicated port PLL, known as
22  * an "MPLLB."  The MPLLB replaces the shared DPLL functionality used on other
23  * platforms and must be programming directly during the modeset sequence
24  * since it is not handled by the shared DPLL framework as on other platforms.
25  */
26 
intel_snps_phy_wait_for_calibration(struct drm_i915_private * i915)27 void intel_snps_phy_wait_for_calibration(struct drm_i915_private *i915)
28 {
29 	enum phy phy;
30 
31 	for_each_phy_masked(phy, ~0) {
32 		if (!intel_phy_is_snps(i915, phy))
33 			continue;
34 
35 		/*
36 		 * If calibration does not complete successfully, we'll remember
37 		 * which phy was affected and skip setup of the corresponding
38 		 * output later.
39 		 */
40 		if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy),
41 					    DG2_PHY_DP_TX_ACK_MASK, 25))
42 			i915->snps_phy_failed_calibration |= BIT(phy);
43 	}
44 }
45 
intel_snps_phy_update_psr_power_state(struct drm_i915_private * dev_priv,enum phy phy,bool enable)46 void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv,
47 					   enum phy phy, bool enable)
48 {
49 	u32 val;
50 
51 	if (!intel_phy_is_snps(dev_priv, phy))
52 		return;
53 
54 	val = REG_FIELD_PREP(SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR,
55 			     enable ? 2 : 3);
56 	intel_uncore_rmw(&dev_priv->uncore, SNPS_PHY_TX_REQ(phy),
57 			 SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val);
58 }
59 
intel_snps_phy_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)60 void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
61 				      const struct intel_crtc_state *crtc_state)
62 {
63 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
64 	const struct intel_ddi_buf_trans *trans;
65 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
66 	int n_entries, ln;
67 
68 	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
69 	if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
70 		return;
71 
72 	for (ln = 0; ln < 4; ln++) {
73 		int level = intel_ddi_level(encoder, crtc_state, ln);
74 		u32 val = 0;
75 
76 		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing);
77 		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.pre_cursor);
78 		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.post_cursor);
79 
80 		intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), val);
81 	}
82 }
83 
84 /*
85  * Basic DP link rates with 100 MHz reference clock.
86  */
87 
88 static const struct intel_mpllb_state dg2_dp_rbr_100 = {
89 	.clock = 162000,
90 	.ref_control =
91 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
92 	.mpllb_cp =
93 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
94 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
95 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
96 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
97 	.mpllb_div =
98 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
99 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
100 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
101 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
102 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
103 	.mpllb_div2 =
104 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
105 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226),
106 	.mpllb_fracn1 =
107 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
108 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
109 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
110 	.mpllb_fracn2 =
111 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
112 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3),
113 };
114 
115 static const struct intel_mpllb_state dg2_dp_hbr1_100 = {
116 	.clock = 270000,
117 	.ref_control =
118 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
119 	.mpllb_cp =
120 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
121 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
122 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
123 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
124 	.mpllb_div =
125 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
126 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
127 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
128 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
129 	.mpllb_div2 =
130 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
131 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184),
132 	.mpllb_fracn1 =
133 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
134 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
135 };
136 
137 static const struct intel_mpllb_state dg2_dp_hbr2_100 = {
138 	.clock = 540000,
139 	.ref_control =
140 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
141 	.mpllb_cp =
142 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
143 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
144 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
145 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
146 	.mpllb_div =
147 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
148 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
149 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
150 	.mpllb_div2 =
151 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
152 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184),
153 	.mpllb_fracn1 =
154 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
155 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
156 };
157 
158 static const struct intel_mpllb_state dg2_dp_hbr3_100 = {
159 	.clock = 810000,
160 	.ref_control =
161 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
162 	.mpllb_cp =
163 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
164 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |
165 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
166 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
167 	.mpllb_div =
168 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
169 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
170 	.mpllb_div2 =
171 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
172 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 292),
173 	.mpllb_fracn1 =
174 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
175 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
176 };
177 
178 static const struct intel_mpllb_state dg2_dp_uhbr10_100 = {
179 	.clock = 1000000,
180 	.ref_control =
181 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
182 	.mpllb_cp =
183 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
184 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 21) |
185 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
186 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
187 	.mpllb_div =
188 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
189 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
190 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
191 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
192 		REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
193 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
194 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) |
195 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
196 	.mpllb_div2 =
197 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
198 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 368),
199 	.mpllb_fracn1 =
200 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
201 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
202 
203 	/*
204 	 * SSC will be enabled, DP UHBR has a minimum SSC requirement.
205 	 */
206 	.mpllb_sscen =
207 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
208 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 58982),
209 	.mpllb_sscstep =
210 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 76101),
211 };
212 
213 static const struct intel_mpllb_state dg2_dp_uhbr13_100 = {
214 	.clock = 1350000,
215 	.ref_control =
216 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
217 	.mpllb_cp =
218 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
219 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 45) |
220 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
221 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
222 	.mpllb_div =
223 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
224 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
225 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
226 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
227 		REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
228 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
229 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3),
230 	.mpllb_div2 =
231 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
232 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 508),
233 	.mpllb_fracn1 =
234 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
235 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
236 
237 	/*
238 	 * SSC will be enabled, DP UHBR has a minimum SSC requirement.
239 	 */
240 	.mpllb_sscen =
241 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
242 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 79626),
243 	.mpllb_sscstep =
244 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 102737),
245 };
246 
247 static const struct intel_mpllb_state * const dg2_dp_100_tables[] = {
248 	&dg2_dp_rbr_100,
249 	&dg2_dp_hbr1_100,
250 	&dg2_dp_hbr2_100,
251 	&dg2_dp_hbr3_100,
252 	&dg2_dp_uhbr10_100,
253 	&dg2_dp_uhbr13_100,
254 	NULL,
255 };
256 
257 /*
258  * eDP link rates with 100 MHz reference clock.
259  */
260 
261 static const struct intel_mpllb_state dg2_edp_r216 = {
262 	.clock = 216000,
263 	.ref_control =
264 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
265 	.mpllb_cp =
266 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
267 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |
268 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
269 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
270 	.mpllb_div =
271 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
272 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
273 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
274 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
275 	.mpllb_div2 =
276 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
277 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312),
278 	.mpllb_fracn1 =
279 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
280 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
281 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
282 	.mpllb_fracn2 =
283 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
284 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4),
285 	.mpllb_sscen =
286 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
287 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961),
288 	.mpllb_sscstep =
289 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752),
290 };
291 
292 static const struct intel_mpllb_state dg2_edp_r243 = {
293 	.clock = 243000,
294 	.ref_control =
295 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
296 	.mpllb_cp =
297 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
298 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
299 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
300 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
301 	.mpllb_div =
302 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
303 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
304 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
305 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
306 	.mpllb_div2 =
307 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
308 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 356),
309 	.mpllb_fracn1 =
310 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
311 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
312 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
313 	.mpllb_fracn2 =
314 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
315 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
316 	.mpllb_sscen =
317 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
318 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 57331),
319 	.mpllb_sscstep =
320 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 73971),
321 };
322 
323 static const struct intel_mpllb_state dg2_edp_r324 = {
324 	.clock = 324000,
325 	.ref_control =
326 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
327 	.mpllb_cp =
328 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
329 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
330 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
331 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
332 	.mpllb_div =
333 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
334 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
335 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
336 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
337 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
338 	.mpllb_div2 =
339 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
340 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226),
341 	.mpllb_fracn1 =
342 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
343 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
344 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
345 	.mpllb_fracn2 =
346 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
347 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3),
348 	.mpllb_sscen =
349 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
350 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 38221),
351 	.mpllb_sscstep =
352 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 49314),
353 };
354 
355 static const struct intel_mpllb_state dg2_edp_r432 = {
356 	.clock = 432000,
357 	.ref_control =
358 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
359 	.mpllb_cp =
360 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
361 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |
362 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
363 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
364 	.mpllb_div =
365 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
366 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
367 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
368 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
369 	.mpllb_div2 =
370 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
371 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312),
372 	.mpllb_fracn1 =
373 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
374 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
375 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
376 	.mpllb_fracn2 =
377 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
378 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4),
379 	.mpllb_sscen =
380 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
381 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961),
382 	.mpllb_sscstep =
383 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752),
384 };
385 
386 static const struct intel_mpllb_state * const dg2_edp_tables[] = {
387 	&dg2_dp_rbr_100,
388 	&dg2_edp_r216,
389 	&dg2_edp_r243,
390 	&dg2_dp_hbr1_100,
391 	&dg2_edp_r324,
392 	&dg2_edp_r432,
393 	&dg2_dp_hbr2_100,
394 	&dg2_dp_hbr3_100,
395 	NULL,
396 };
397 
398 /*
399  * HDMI link rates with 100 MHz reference clock.
400  */
401 
402 static const struct intel_mpllb_state dg2_hdmi_25_175 = {
403 	.clock = 25175,
404 	.ref_control =
405 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
406 	.mpllb_cp =
407 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
408 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
409 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
410 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
411 	.mpllb_div =
412 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
413 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
414 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
415 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
416 	.mpllb_div2 =
417 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
418 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) |
419 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
420 	.mpllb_fracn1 =
421 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
422 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
423 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 143),
424 	.mpllb_fracn2 =
425 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36663) |
426 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 71),
427 	.mpllb_sscen =
428 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
429 };
430 
431 static const struct intel_mpllb_state dg2_hdmi_27_0 = {
432 	.clock = 27000,
433 	.ref_control =
434 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
435 	.mpllb_cp =
436 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
437 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
438 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
439 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
440 	.mpllb_div =
441 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
442 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
443 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
444 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
445 	.mpllb_div2 =
446 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
447 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) |
448 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
449 	.mpllb_fracn1 =
450 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
451 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
452 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
453 	.mpllb_fracn2 =
454 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
455 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
456 	.mpllb_sscen =
457 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
458 };
459 
460 static const struct intel_mpllb_state dg2_hdmi_74_25 = {
461 	.clock = 74250,
462 	.ref_control =
463 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
464 	.mpllb_cp =
465 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
466 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
467 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
468 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
469 	.mpllb_div =
470 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
471 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
472 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
473 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
474 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
475 	.mpllb_div2 =
476 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
477 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
478 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
479 	.mpllb_fracn1 =
480 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
481 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
482 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
483 	.mpllb_fracn2 =
484 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
485 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
486 	.mpllb_sscen =
487 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
488 };
489 
490 static const struct intel_mpllb_state dg2_hdmi_148_5 = {
491 	.clock = 148500,
492 	.ref_control =
493 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
494 	.mpllb_cp =
495 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
496 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
497 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
498 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
499 	.mpllb_div =
500 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
501 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
502 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
503 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
504 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
505 	.mpllb_div2 =
506 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
507 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
508 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
509 	.mpllb_fracn1 =
510 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
511 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
512 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
513 	.mpllb_fracn2 =
514 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
515 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
516 	.mpllb_sscen =
517 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
518 };
519 
520 /* values in the below table are calculted using the algo */
521 static const struct intel_mpllb_state dg2_hdmi_25200 = {
522 	.clock = 25200,
523 	.ref_control =
524 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
525 	.mpllb_cp =
526 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
527 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
528 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
529 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
530 	.mpllb_div =
531 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
532 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
533 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
534 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
535 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
536 	.mpllb_div2 =
537 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
538 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) |
539 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
540 	.mpllb_fracn1 =
541 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
542 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
543 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
544 	.mpllb_fracn2 =
545 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 41943) |
546 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2621),
547 	.mpllb_sscen =
548 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
549 };
550 
551 static const struct intel_mpllb_state dg2_hdmi_27027 = {
552 	.clock = 27027,
553 	.ref_control =
554 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
555 	.mpllb_cp =
556 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
557 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
558 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
559 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
560 	.mpllb_div =
561 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
562 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
563 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
564 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
565 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
566 	.mpllb_div2 =
567 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
568 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) |
569 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
570 	.mpllb_fracn1 =
571 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
572 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
573 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
574 	.mpllb_fracn2 =
575 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 31876) |
576 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 46555),
577 	.mpllb_sscen =
578 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
579 };
580 
581 static const struct intel_mpllb_state dg2_hdmi_28320 = {
582 	.clock = 28320,
583 	.ref_control =
584 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
585 	.mpllb_cp =
586 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
587 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
588 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
589 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
590 	.mpllb_div =
591 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
592 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
593 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
594 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
595 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
596 	.mpllb_div2 =
597 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
598 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 148) |
599 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
600 	.mpllb_fracn1 =
601 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
602 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
603 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
604 	.mpllb_fracn2 =
605 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40894) |
606 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 30408),
607 	.mpllb_sscen =
608 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
609 };
610 
611 static const struct intel_mpllb_state dg2_hdmi_30240 = {
612 	.clock = 30240,
613 	.ref_control =
614 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
615 	.mpllb_cp =
616 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
617 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
618 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
619 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
620 	.mpllb_div =
621 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
622 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
623 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
624 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
625 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
626 	.mpllb_div2 =
627 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
628 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 160) |
629 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
630 	.mpllb_fracn1 =
631 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
632 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
633 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
634 	.mpllb_fracn2 =
635 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 50331) |
636 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 42466),
637 	.mpllb_sscen =
638 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
639 };
640 
641 static const struct intel_mpllb_state dg2_hdmi_31500 = {
642 	.clock = 31500,
643 	.ref_control =
644 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
645 	.mpllb_cp =
646 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
647 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
648 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
649 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
650 	.mpllb_div =
651 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
652 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
653 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
654 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
655 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
656 	.mpllb_div2 =
657 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
658 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 68) |
659 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
660 	.mpllb_fracn1 =
661 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
662 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
663 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
664 	.mpllb_fracn2 =
665 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
666 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
667 	.mpllb_sscen =
668 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
669 };
670 
671 static const struct intel_mpllb_state dg2_hdmi_36000 = {
672 	.clock = 36000,
673 	.ref_control =
674 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
675 	.mpllb_cp =
676 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
677 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
678 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
679 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
680 	.mpllb_div =
681 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
682 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
683 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
684 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
685 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
686 	.mpllb_div2 =
687 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
688 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 82) |
689 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
690 	.mpllb_fracn1 =
691 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
692 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
693 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
694 	.mpllb_fracn2 =
695 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
696 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320),
697 	.mpllb_sscen =
698 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
699 };
700 
701 static const struct intel_mpllb_state dg2_hdmi_40000 = {
702 	.clock = 40000,
703 	.ref_control =
704 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
705 	.mpllb_cp =
706 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
707 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
708 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
709 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
710 	.mpllb_div =
711 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
712 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
713 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
714 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
715 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
716 	.mpllb_div2 =
717 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
718 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 96) |
719 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
720 	.mpllb_fracn1 =
721 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
722 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
723 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
724 	.mpllb_fracn2 =
725 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
726 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
727 	.mpllb_sscen =
728 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
729 };
730 
731 static const struct intel_mpllb_state dg2_hdmi_49500 = {
732 	.clock = 49500,
733 	.ref_control =
734 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
735 	.mpllb_cp =
736 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
737 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
738 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
739 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
740 	.mpllb_div =
741 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
742 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
743 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
744 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
745 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1),
746 	.mpllb_div2 =
747 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
748 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 126) |
749 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
750 	.mpllb_fracn1 =
751 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
752 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
753 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
754 	.mpllb_fracn2 =
755 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |
756 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
757 	.mpllb_sscen =
758 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
759 };
760 
761 static const struct intel_mpllb_state dg2_hdmi_50000 = {
762 	.clock = 50000,
763 	.ref_control =
764 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
765 	.mpllb_cp =
766 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
767 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
768 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
769 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
770 	.mpllb_div =
771 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
772 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
773 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
774 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
775 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1),
776 	.mpllb_div2 =
777 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
778 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) |
779 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
780 	.mpllb_fracn1 =
781 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
782 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
783 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
784 	.mpllb_fracn2 =
785 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
786 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
787 	.mpllb_sscen =
788 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
789 };
790 
791 static const struct intel_mpllb_state dg2_hdmi_57284 = {
792 	.clock = 57284,
793 	.ref_control =
794 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
795 	.mpllb_cp =
796 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
797 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
798 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
799 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
800 	.mpllb_div =
801 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
802 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
803 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
804 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
805 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
806 	.mpllb_div2 =
807 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
808 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 150) |
809 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
810 	.mpllb_fracn1 =
811 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
812 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
813 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
814 	.mpllb_fracn2 =
815 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 42886) |
816 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 49701),
817 	.mpllb_sscen =
818 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
819 };
820 
821 static const struct intel_mpllb_state dg2_hdmi_58000 = {
822 	.clock = 58000,
823 	.ref_control =
824 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
825 	.mpllb_cp =
826 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
827 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
828 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
829 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
830 	.mpllb_div =
831 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
832 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
833 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
834 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
835 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
836 	.mpllb_div2 =
837 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
838 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 152) |
839 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
840 	.mpllb_fracn1 =
841 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
842 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
843 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
844 	.mpllb_fracn2 =
845 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
846 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
847 	.mpllb_sscen =
848 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
849 };
850 
851 static const struct intel_mpllb_state dg2_hdmi_65000 = {
852 	.clock = 65000,
853 	.ref_control =
854 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
855 	.mpllb_cp =
856 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
857 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
858 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
859 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
860 	.mpllb_div =
861 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
862 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
863 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
864 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
865 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
866 	.mpllb_div2 =
867 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
868 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 72) |
869 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
870 	.mpllb_fracn1 =
871 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
872 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
873 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
874 	.mpllb_fracn2 =
875 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
876 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
877 	.mpllb_sscen =
878 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
879 };
880 
881 static const struct intel_mpllb_state dg2_hdmi_71000 = {
882 	.clock = 71000,
883 	.ref_control =
884 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
885 	.mpllb_cp =
886 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
887 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
888 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
889 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
890 	.mpllb_div =
891 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
892 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
893 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
894 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
895 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
896 	.mpllb_div2 =
897 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
898 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 80) |
899 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
900 	.mpllb_fracn1 =
901 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
902 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
903 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
904 	.mpllb_fracn2 =
905 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
906 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
907 	.mpllb_sscen =
908 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
909 };
910 
911 static const struct intel_mpllb_state dg2_hdmi_74176 = {
912 	.clock = 74176,
913 	.ref_control =
914 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
915 	.mpllb_cp =
916 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
917 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
918 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
919 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
920 	.mpllb_div =
921 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
922 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
923 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
924 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
925 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
926 	.mpllb_div2 =
927 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
928 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
929 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
930 	.mpllb_fracn1 =
931 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
932 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
933 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
934 	.mpllb_fracn2 =
935 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22334) |
936 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 43829),
937 	.mpllb_sscen =
938 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
939 };
940 
941 static const struct intel_mpllb_state dg2_hdmi_75000 = {
942 	.clock = 75000,
943 	.ref_control =
944 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
945 	.mpllb_cp =
946 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
947 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
948 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
949 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
950 	.mpllb_div =
951 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
952 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
953 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
954 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
955 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
956 	.mpllb_div2 =
957 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
958 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 88) |
959 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
960 	.mpllb_fracn1 =
961 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
962 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
963 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
964 	.mpllb_fracn2 =
965 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
966 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
967 	.mpllb_sscen =
968 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
969 };
970 
971 static const struct intel_mpllb_state dg2_hdmi_78750 = {
972 	.clock = 78750,
973 	.ref_control =
974 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
975 	.mpllb_cp =
976 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
977 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
978 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
979 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
980 	.mpllb_div =
981 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
982 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
983 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
984 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
985 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
986 	.mpllb_div2 =
987 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
988 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 94) |
989 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
990 	.mpllb_fracn1 =
991 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
992 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
993 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
994 	.mpllb_fracn2 =
995 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
996 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
997 	.mpllb_sscen =
998 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
999 };
1000 
1001 static const struct intel_mpllb_state dg2_hdmi_85500 = {
1002 	.clock = 85500,
1003 	.ref_control =
1004 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1005 	.mpllb_cp =
1006 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1007 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1008 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1009 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1010 	.mpllb_div =
1011 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1012 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
1013 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1014 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1015 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
1016 	.mpllb_div2 =
1017 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1018 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 104) |
1019 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1020 	.mpllb_fracn1 =
1021 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1022 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1023 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1024 	.mpllb_fracn2 =
1025 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
1026 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
1027 	.mpllb_sscen =
1028 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1029 };
1030 
1031 static const struct intel_mpllb_state dg2_hdmi_88750 = {
1032 	.clock = 88750,
1033 	.ref_control =
1034 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1035 	.mpllb_cp =
1036 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
1037 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
1038 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1039 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1040 	.mpllb_div =
1041 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1042 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
1043 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
1044 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1045 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1),
1046 	.mpllb_div2 =
1047 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1048 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 110) |
1049 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1050 	.mpllb_fracn1 =
1051 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1052 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
1053 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1054 	.mpllb_fracn2 =
1055 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
1056 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
1057 	.mpllb_sscen =
1058 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1059 };
1060 
1061 static const struct intel_mpllb_state dg2_hdmi_106500 = {
1062 	.clock = 106500,
1063 	.ref_control =
1064 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1065 	.mpllb_cp =
1066 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1067 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1068 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1069 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1070 	.mpllb_div =
1071 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1072 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
1073 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1074 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1075 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
1076 	.mpllb_div2 =
1077 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1078 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 138) |
1079 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1080 	.mpllb_fracn1 =
1081 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1082 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1083 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1084 	.mpllb_fracn2 =
1085 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |
1086 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
1087 	.mpllb_sscen =
1088 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1089 };
1090 
1091 static const struct intel_mpllb_state dg2_hdmi_108000 = {
1092 	.clock = 108000,
1093 	.ref_control =
1094 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1095 	.mpllb_cp =
1096 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1097 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1098 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1099 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1100 	.mpllb_div =
1101 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1102 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
1103 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1104 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1105 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
1106 	.mpllb_div2 =
1107 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1108 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) |
1109 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1110 	.mpllb_fracn1 =
1111 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1112 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1113 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1114 	.mpllb_fracn2 =
1115 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
1116 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
1117 	.mpllb_sscen =
1118 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1119 };
1120 
1121 static const struct intel_mpllb_state dg2_hdmi_115500 = {
1122 	.clock = 115500,
1123 	.ref_control =
1124 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1125 	.mpllb_cp =
1126 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1127 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1128 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1129 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1130 	.mpllb_div =
1131 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1132 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
1133 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1134 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1135 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
1136 	.mpllb_div2 =
1137 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1138 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 152) |
1139 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1140 	.mpllb_fracn1 =
1141 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1142 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1143 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1144 	.mpllb_fracn2 =
1145 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
1146 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
1147 	.mpllb_sscen =
1148 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1149 };
1150 
1151 static const struct intel_mpllb_state dg2_hdmi_119000 = {
1152 	.clock = 119000,
1153 	.ref_control =
1154 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1155 	.mpllb_cp =
1156 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1157 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1158 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1159 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1160 	.mpllb_div =
1161 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1162 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
1163 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1164 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1165 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
1166 	.mpllb_div2 =
1167 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1168 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 158) |
1169 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1170 	.mpllb_fracn1 =
1171 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1172 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1173 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1174 	.mpllb_fracn2 =
1175 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |
1176 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
1177 	.mpllb_sscen =
1178 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1179 };
1180 
1181 static const struct intel_mpllb_state dg2_hdmi_135000 = {
1182 	.clock = 135000,
1183 	.ref_control =
1184 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1185 	.mpllb_cp =
1186 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
1187 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
1188 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1189 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1190 	.mpllb_div =
1191 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1192 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1193 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
1194 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1195 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1196 	.mpllb_div2 =
1197 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1198 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 76) |
1199 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1200 	.mpllb_fracn1 =
1201 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1202 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
1203 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1204 	.mpllb_fracn2 =
1205 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
1206 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
1207 	.mpllb_sscen =
1208 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1209 };
1210 
1211 static const struct intel_mpllb_state dg2_hdmi_138500 = {
1212 	.clock = 138500,
1213 	.ref_control =
1214 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1215 	.mpllb_cp =
1216 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1217 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1218 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1219 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1220 	.mpllb_div =
1221 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1222 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1223 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1224 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1225 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1226 	.mpllb_div2 =
1227 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1228 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 78) |
1229 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1230 	.mpllb_fracn1 =
1231 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1232 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1233 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1234 	.mpllb_fracn2 =
1235 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
1236 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
1237 	.mpllb_sscen =
1238 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1239 };
1240 
1241 static const struct intel_mpllb_state dg2_hdmi_147160 = {
1242 	.clock = 147160,
1243 	.ref_control =
1244 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1245 	.mpllb_cp =
1246 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1247 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1248 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1249 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1250 	.mpllb_div =
1251 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1252 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1253 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1254 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1255 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1256 	.mpllb_div2 =
1257 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1258 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 84) |
1259 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1260 	.mpllb_fracn1 =
1261 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1262 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1263 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1264 	.mpllb_fracn2 =
1265 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 56623) |
1266 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 6815),
1267 	.mpllb_sscen =
1268 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1269 };
1270 
1271 static const struct intel_mpllb_state dg2_hdmi_148352 = {
1272 	.clock = 148352,
1273 	.ref_control =
1274 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1275 	.mpllb_cp =
1276 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1277 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1278 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1279 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1280 	.mpllb_div =
1281 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1282 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1283 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1284 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1285 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1286 	.mpllb_div2 =
1287 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1288 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
1289 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1290 	.mpllb_fracn1 =
1291 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1292 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1293 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1294 	.mpllb_fracn2 =
1295 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22334) |
1296 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 43829),
1297 	.mpllb_sscen =
1298 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1299 };
1300 
1301 static const struct intel_mpllb_state dg2_hdmi_154000 = {
1302 	.clock = 154000,
1303 	.ref_control =
1304 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1305 	.mpllb_cp =
1306 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1307 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 13) |
1308 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1309 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1310 	.mpllb_div =
1311 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1312 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1313 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1314 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1315 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
1316 	.mpllb_div2 =
1317 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1318 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 90) |
1319 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1320 	.mpllb_fracn1 =
1321 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1322 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1323 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1324 	.mpllb_fracn2 =
1325 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
1326 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320),
1327 	.mpllb_sscen =
1328 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1329 };
1330 
1331 static const struct intel_mpllb_state dg2_hdmi_162000 = {
1332 	.clock = 162000,
1333 	.ref_control =
1334 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1335 	.mpllb_cp =
1336 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1337 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1338 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1339 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1340 	.mpllb_div =
1341 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1342 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1343 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1344 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1345 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
1346 	.mpllb_div2 =
1347 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1348 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 96) |
1349 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1350 	.mpllb_fracn1 =
1351 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1352 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1353 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1354 	.mpllb_fracn2 =
1355 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
1356 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
1357 	.mpllb_sscen =
1358 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1359 };
1360 
1361 static const struct intel_mpllb_state dg2_hdmi_209800 = {
1362 	.clock = 209800,
1363 	.ref_control =
1364 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1365 	.mpllb_cp =
1366 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
1367 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1368 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1369 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1370 	.mpllb_div =
1371 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1372 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1373 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1374 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1375 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
1376 	.mpllb_div2 =
1377 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1378 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 134) |
1379 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1380 	.mpllb_fracn1 =
1381 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1382 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1383 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1384 	.mpllb_fracn2 =
1385 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 60293) |
1386 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 7864),
1387 	.mpllb_sscen =
1388 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1389 };
1390 
1391 static const struct intel_mpllb_state dg2_hdmi_262750 = {
1392 	.clock = 262750,
1393 	.ref_control =
1394 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1395 	.mpllb_cp =
1396 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
1397 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1398 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1399 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1400 	.mpllb_div =
1401 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1402 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
1403 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1404 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1405 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1406 	.mpllb_div2 =
1407 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1408 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 72) |
1409 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1410 	.mpllb_fracn1 =
1411 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1412 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1413 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1414 	.mpllb_fracn2 =
1415 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36044) |
1416 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
1417 	.mpllb_sscen =
1418 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1419 };
1420 
1421 static const struct intel_mpllb_state dg2_hdmi_268500 = {
1422 	.clock = 268500,
1423 	.ref_control =
1424 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1425 	.mpllb_cp =
1426 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
1427 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1428 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1429 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1430 	.mpllb_div =
1431 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1432 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
1433 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1434 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1435 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1436 	.mpllb_div2 =
1437 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1438 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 74) |
1439 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1440 	.mpllb_fracn1 =
1441 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1442 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1443 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1444 	.mpllb_fracn2 =
1445 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 45875) |
1446 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
1447 	.mpllb_sscen =
1448 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1449 };
1450 
1451 static const struct intel_mpllb_state dg2_hdmi_296703 = {
1452 	.clock = 296703,
1453 	.ref_control =
1454 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1455 	.mpllb_cp =
1456 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1457 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1458 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1459 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1460 	.mpllb_div =
1461 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1462 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
1463 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1464 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1465 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1466 	.mpllb_div2 =
1467 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1468 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
1469 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1470 	.mpllb_fracn1 =
1471 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1472 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1473 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1474 	.mpllb_fracn2 =
1475 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22321) |
1476 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 36804),
1477 	.mpllb_sscen =
1478 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1479 };
1480 
1481 static const struct intel_mpllb_state dg2_hdmi_241500 = {
1482 	.clock = 241500,
1483 	.ref_control =
1484 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1485 	.mpllb_cp =
1486 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1487 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1488 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1489 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1490 	.mpllb_div =
1491 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1492 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1493 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1494 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1495 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
1496 	.mpllb_div2 =
1497 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1498 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 160) |
1499 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1500 	.mpllb_fracn1 =
1501 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1502 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1503 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1504 	.mpllb_fracn2 =
1505 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
1506 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320),
1507 	.mpllb_sscen =
1508 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1509 };
1510 
1511 static const struct intel_mpllb_state dg2_hdmi_497750 = {
1512 	.clock = 497750,
1513 	.ref_control =
1514 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1515 	.mpllb_cp =
1516 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1517 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
1518 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1519 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1520 	.mpllb_div =
1521 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1522 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
1523 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1524 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1525 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
1526 	.mpllb_div2 =
1527 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1528 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 166) |
1529 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1530 	.mpllb_fracn1 =
1531 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1532 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1533 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1534 	.mpllb_fracn2 =
1535 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36044) |
1536 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
1537 	.mpllb_sscen =
1538 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1539 };
1540 
1541 static const struct intel_mpllb_state dg2_hdmi_592000 = {
1542 	.clock = 592000,
1543 	.ref_control =
1544 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1545 	.mpllb_cp =
1546 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1547 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1548 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1549 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1550 	.mpllb_div =
1551 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1552 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 0) |
1553 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1554 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1555 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1556 	.mpllb_div2 =
1557 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1558 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
1559 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1560 	.mpllb_fracn1 =
1561 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1562 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1563 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1564 	.mpllb_fracn2 =
1565 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |
1566 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
1567 	.mpllb_sscen =
1568 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1569 };
1570 
1571 static const struct intel_mpllb_state dg2_hdmi_593407 = {
1572 	.clock = 593407,
1573 	.ref_control =
1574 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1575 	.mpllb_cp =
1576 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1577 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1578 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1579 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1580 	.mpllb_div =
1581 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1582 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 0) |
1583 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1584 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1585 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1586 	.mpllb_div2 =
1587 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1588 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
1589 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1590 	.mpllb_fracn1 =
1591 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1592 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1593 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1594 	.mpllb_fracn2 =
1595 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22328) |
1596 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 7549),
1597 	.mpllb_sscen =
1598 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1599 };
1600 
1601 static const struct intel_mpllb_state dg2_hdmi_297 = {
1602 	.clock = 297000,
1603 	.ref_control =
1604 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1605 	.mpllb_cp =
1606 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1607 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1608 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1609 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1610 	.mpllb_div =
1611 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1612 		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
1613 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1614 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1615 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1616 	.mpllb_div2 =
1617 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1618 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
1619 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1620 	.mpllb_fracn1 =
1621 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1622 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1623 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1624 	.mpllb_fracn2 =
1625 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
1626 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
1627 	.mpllb_sscen =
1628 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1629 };
1630 
1631 static const struct intel_mpllb_state dg2_hdmi_594 = {
1632 	.clock = 594000,
1633 	.ref_control =
1634 		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1635 	.mpllb_cp =
1636 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
1637 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
1638 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1639 		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1640 	.mpllb_div =
1641 		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1642 		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1643 		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1644 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1645 	.mpllb_div2 =
1646 		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1647 		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
1648 		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1649 	.mpllb_fracn1 =
1650 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1651 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1652 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
1653 	.mpllb_fracn2 =
1654 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
1655 		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
1656 	.mpllb_sscen =
1657 		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1658 };
1659 
1660 static const struct intel_mpllb_state * const dg2_hdmi_tables[] = {
1661 	&dg2_hdmi_25_175,
1662 	&dg2_hdmi_27_0,
1663 	&dg2_hdmi_74_25,
1664 	&dg2_hdmi_148_5,
1665 	&dg2_hdmi_297,
1666 	&dg2_hdmi_594,
1667 	&dg2_hdmi_25200,
1668 	&dg2_hdmi_27027,
1669 	&dg2_hdmi_28320,
1670 	&dg2_hdmi_30240,
1671 	&dg2_hdmi_31500,
1672 	&dg2_hdmi_36000,
1673 	&dg2_hdmi_40000,
1674 	&dg2_hdmi_49500,
1675 	&dg2_hdmi_50000,
1676 	&dg2_hdmi_57284,
1677 	&dg2_hdmi_58000,
1678 	&dg2_hdmi_65000,
1679 	&dg2_hdmi_71000,
1680 	&dg2_hdmi_74176,
1681 	&dg2_hdmi_75000,
1682 	&dg2_hdmi_78750,
1683 	&dg2_hdmi_85500,
1684 	&dg2_hdmi_88750,
1685 	&dg2_hdmi_106500,
1686 	&dg2_hdmi_108000,
1687 	&dg2_hdmi_115500,
1688 	&dg2_hdmi_119000,
1689 	&dg2_hdmi_135000,
1690 	&dg2_hdmi_138500,
1691 	&dg2_hdmi_147160,
1692 	&dg2_hdmi_148352,
1693 	&dg2_hdmi_154000,
1694 	&dg2_hdmi_162000,
1695 	&dg2_hdmi_209800,
1696 	&dg2_hdmi_241500,
1697 	&dg2_hdmi_262750,
1698 	&dg2_hdmi_268500,
1699 	&dg2_hdmi_296703,
1700 	&dg2_hdmi_497750,
1701 	&dg2_hdmi_592000,
1702 	&dg2_hdmi_593407,
1703 	NULL,
1704 };
1705 
1706 static const struct intel_mpllb_state * const *
intel_mpllb_tables_get(struct intel_crtc_state * crtc_state,struct intel_encoder * encoder)1707 intel_mpllb_tables_get(struct intel_crtc_state *crtc_state,
1708 		       struct intel_encoder *encoder)
1709 {
1710 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
1711 		return dg2_edp_tables;
1712 	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
1713 		return dg2_dp_100_tables;
1714 	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1715 		return dg2_hdmi_tables;
1716 	}
1717 
1718 	MISSING_CASE(encoder->type);
1719 	return NULL;
1720 }
1721 
intel_mpllb_calc_state(struct intel_crtc_state * crtc_state,struct intel_encoder * encoder)1722 int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
1723 			   struct intel_encoder *encoder)
1724 {
1725 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1726 	const struct intel_mpllb_state * const *tables;
1727 	int i;
1728 
1729 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1730 		if (intel_snps_phy_check_hdmi_link_rate(crtc_state->port_clock)
1731 		    != MODE_OK) {
1732 			/*
1733 			 * FIXME: Can only support fixed HDMI frequencies
1734 			 * until we have a proper algorithm under a valid
1735 			 * license.
1736 			 */
1737 			drm_dbg_kms(&i915->drm, "Can't support HDMI link rate %d\n",
1738 				    crtc_state->port_clock);
1739 			return -EINVAL;
1740 		}
1741 	}
1742 
1743 	tables = intel_mpllb_tables_get(crtc_state, encoder);
1744 	if (!tables)
1745 		return -EINVAL;
1746 
1747 	for (i = 0; tables[i]; i++) {
1748 		if (crtc_state->port_clock == tables[i]->clock) {
1749 			crtc_state->mpllb_state = *tables[i];
1750 			return 0;
1751 		}
1752 	}
1753 
1754 	return -EINVAL;
1755 }
1756 
intel_mpllb_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1757 void intel_mpllb_enable(struct intel_encoder *encoder,
1758 			const struct intel_crtc_state *crtc_state)
1759 {
1760 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1761 	const struct intel_mpllb_state *pll_state = &crtc_state->mpllb_state;
1762 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1763 	i915_reg_t enable_reg = (phy <= PHY_D ?
1764 				 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
1765 
1766 	/*
1767 	 * 3. Software programs the following PLL registers for the desired
1768 	 * frequency.
1769 	 */
1770 	intel_de_write(dev_priv, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp);
1771 	intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div);
1772 	intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2);
1773 	intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen);
1774 	intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep);
1775 	intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1);
1776 	intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2);
1777 
1778 	/*
1779 	 * 4. If the frequency will result in a change to the voltage
1780 	 * requirement, follow the Display Voltage Frequency Switching -
1781 	 * Sequence Before Frequency Change.
1782 	 *
1783 	 * We handle this step in bxt_set_cdclk().
1784 	 */
1785 
1786 	/* 5. Software sets DPLL_ENABLE [PLL Enable] to "1". */
1787 	intel_uncore_rmw(&dev_priv->uncore, enable_reg, 0, PLL_ENABLE);
1788 
1789 	/*
1790 	 * 9. Software sets SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "1". This
1791 	 * will keep the PLL running during the DDI lane programming and any
1792 	 * typeC DP cable disconnect. Do not set the force before enabling the
1793 	 * PLL because that will start the PLL before it has sampled the
1794 	 * divider values.
1795 	 */
1796 	intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy),
1797 		       pll_state->mpllb_div | SNPS_PHY_MPLLB_FORCE_EN);
1798 
1799 	/*
1800 	 * 10. Software polls on register DPLL_ENABLE [PLL Lock] to confirm PLL
1801 	 * is locked at new settings. This register bit is sampling PHY
1802 	 * dp_mpllb_state interface signal.
1803 	 */
1804 	if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 5))
1805 		drm_dbg_kms(&dev_priv->drm, "Port %c PLL not locked\n", phy_name(phy));
1806 
1807 	/*
1808 	 * 11. If the frequency will result in a change to the voltage
1809 	 * requirement, follow the Display Voltage Frequency Switching -
1810 	 * Sequence After Frequency Change.
1811 	 *
1812 	 * We handle this step in bxt_set_cdclk().
1813 	 */
1814 }
1815 
intel_mpllb_disable(struct intel_encoder * encoder)1816 void intel_mpllb_disable(struct intel_encoder *encoder)
1817 {
1818 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1819 	enum phy phy = intel_port_to_phy(i915, encoder->port);
1820 	i915_reg_t enable_reg = (phy <= PHY_D ?
1821 				 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
1822 
1823 	/*
1824 	 * 1. If the frequency will result in a change to the voltage
1825 	 * requirement, follow the Display Voltage Frequency Switching -
1826 	 * Sequence Before Frequency Change.
1827 	 *
1828 	 * We handle this step in bxt_set_cdclk().
1829 	 */
1830 
1831 	/* 2. Software programs DPLL_ENABLE [PLL Enable] to "0" */
1832 	intel_uncore_rmw(&i915->uncore, enable_reg, PLL_ENABLE, 0);
1833 
1834 	/*
1835 	 * 4. Software programs SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "0".
1836 	 * This will allow the PLL to stop running.
1837 	 */
1838 	intel_uncore_rmw(&i915->uncore, SNPS_PHY_MPLLB_DIV(phy),
1839 			 SNPS_PHY_MPLLB_FORCE_EN, 0);
1840 
1841 	/*
1842 	 * 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment
1843 	 * (dp_txX_ack) that the new transmitter setting request is completed.
1844 	 */
1845 	if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 5))
1846 		drm_err(&i915->drm, "Port %c PLL not locked\n", phy_name(phy));
1847 
1848 	/*
1849 	 * 6. If the frequency will result in a change to the voltage
1850 	 * requirement, follow the Display Voltage Frequency Switching -
1851 	 * Sequence After Frequency Change.
1852 	 *
1853 	 * We handle this step in bxt_set_cdclk().
1854 	 */
1855 }
1856 
intel_mpllb_calc_port_clock(struct intel_encoder * encoder,const struct intel_mpllb_state * pll_state)1857 int intel_mpllb_calc_port_clock(struct intel_encoder *encoder,
1858 				const struct intel_mpllb_state *pll_state)
1859 {
1860 	unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
1861 	unsigned int multiplier, tx_clk_div, refclk;
1862 	bool frac_en;
1863 
1864 	if (0)
1865 		refclk = 38400;
1866 	else
1867 		refclk = 100000;
1868 
1869 	refclk >>= REG_FIELD_GET(SNPS_PHY_MPLLB_REF_CLK_DIV, pll_state->mpllb_div2) - 1;
1870 
1871 	frac_en = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_EN, pll_state->mpllb_fracn1);
1872 
1873 	if (frac_en) {
1874 		frac_quot = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_QUOT, pll_state->mpllb_fracn2);
1875 		frac_rem = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_REM, pll_state->mpllb_fracn2);
1876 		frac_den = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_DEN, pll_state->mpllb_fracn1);
1877 	}
1878 
1879 	multiplier = REG_FIELD_GET(SNPS_PHY_MPLLB_MULTIPLIER, pll_state->mpllb_div2) / 2 + 16;
1880 
1881 	tx_clk_div = REG_FIELD_GET(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_state->mpllb_div);
1882 
1883 	return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
1884 				     DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
1885 				     10 << (tx_clk_div + 16));
1886 }
1887 
intel_mpllb_readout_hw_state(struct intel_encoder * encoder,struct intel_mpllb_state * pll_state)1888 void intel_mpllb_readout_hw_state(struct intel_encoder *encoder,
1889 				  struct intel_mpllb_state *pll_state)
1890 {
1891 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1892 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1893 
1894 	pll_state->mpllb_cp = intel_de_read(dev_priv, SNPS_PHY_MPLLB_CP(phy));
1895 	pll_state->mpllb_div = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV(phy));
1896 	pll_state->mpllb_div2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV2(phy));
1897 	pll_state->mpllb_sscen = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy));
1898 	pll_state->mpllb_sscstep = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy));
1899 	pll_state->mpllb_fracn1 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy));
1900 	pll_state->mpllb_fracn2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy));
1901 
1902 	/*
1903 	 * REF_CONTROL is under firmware control and never programmed by the
1904 	 * driver; we read it only for sanity checking purposes.  The bspec
1905 	 * only tells us the expected value for one field in this register,
1906 	 * so we'll only read out those specific bits here.
1907 	 */
1908 	pll_state->ref_control = intel_de_read(dev_priv, SNPS_PHY_REF_CONTROL(phy)) &
1909 		SNPS_PHY_REF_CONTROL_REF_RANGE;
1910 
1911 	/*
1912 	 * MPLLB_DIV is programmed twice, once with the software-computed
1913 	 * state, then again with the MPLLB_FORCE_EN bit added.  Drop that
1914 	 * extra bit during readout so that we return the actual expected
1915 	 * software state.
1916 	 */
1917 	pll_state->mpllb_div &= ~SNPS_PHY_MPLLB_FORCE_EN;
1918 }
1919 
intel_snps_phy_check_hdmi_link_rate(int clock)1920 int intel_snps_phy_check_hdmi_link_rate(int clock)
1921 {
1922 	const struct intel_mpllb_state * const *tables = dg2_hdmi_tables;
1923 	int i;
1924 
1925 	for (i = 0; tables[i]; i++) {
1926 		if (clock == tables[i]->clock)
1927 			return MODE_OK;
1928 	}
1929 
1930 	return MODE_CLOCK_RANGE;
1931 }
1932 
intel_mpllb_state_verify(struct intel_atomic_state * state,struct intel_crtc_state * new_crtc_state)1933 void intel_mpllb_state_verify(struct intel_atomic_state *state,
1934 			      struct intel_crtc_state *new_crtc_state)
1935 {
1936 	struct drm_i915_private *i915 = to_i915(state->base.dev);
1937 	struct intel_mpllb_state mpllb_hw_state = { 0 };
1938 	struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state;
1939 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1940 	struct intel_encoder *encoder;
1941 
1942 	if (!IS_DG2(i915))
1943 		return;
1944 
1945 	if (!new_crtc_state->hw.active)
1946 		return;
1947 
1948 	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
1949 	intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state);
1950 
1951 #define MPLLB_CHECK(__name)						\
1952 	I915_STATE_WARN(mpllb_sw_state->__name != mpllb_hw_state.__name,	\
1953 			"[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \
1954 			crtc->base.base.id, crtc->base.name,		\
1955 			__stringify(__name),				\
1956 			mpllb_sw_state->__name, mpllb_hw_state.__name)
1957 
1958 	MPLLB_CHECK(mpllb_cp);
1959 	MPLLB_CHECK(mpllb_div);
1960 	MPLLB_CHECK(mpllb_div2);
1961 	MPLLB_CHECK(mpllb_fracn1);
1962 	MPLLB_CHECK(mpllb_fracn2);
1963 	MPLLB_CHECK(mpllb_sscen);
1964 	MPLLB_CHECK(mpllb_sscstep);
1965 
1966 	/*
1967 	 * ref_control is handled by the hardware/firemware and never
1968 	 * programmed by the software, but the proper values are supplied
1969 	 * in the bspec for verification purposes.
1970 	 */
1971 	MPLLB_CHECK(ref_control);
1972 
1973 #undef MPLLB_CHECK
1974 }
1975